Rev. 1.4 6/12 Copyright © 2012 by Silicon Laboratories Si8660/61/62/63
Si8660/61/62/63
LOW POWER SIX-CHANNEL DIGITAL ISOLATOR
Features
Applications
Safety Regulatory Approvals
Description
Silicon Lab's family of ultra-low-power digital isolators are CMOS devices
offering substantial data rate, propagation delay, power, size, reliability, and
external BOM advantages over legacy isolation technologies. The operating
parameters of these products remain stable across wide temperature ranges
and throughout device service life for ease of design and highly uniform
performance. All device versions have Schmitt trigger inputs for high noise
immunity and only require VDD bypass capacitors.
Data rates up to 150 Mbps are supported, and all devices achieve propagation
delays of less than 10 ns. Ordering options include a choice of isolation ratings
(3.75 and 5 kV) and a selectable fail-safe operating mode to control the default
output state during power loss. All products >1 kVRMS are safety certified by
UL, CSA, and VDE, and products in wide-body packages support reinforced
insulation withstanding up to 5 kVRMS.
High-speed operation
DC to 150 Mbps
No start-up initialization required
Wide Operating Supply Voltage
2.5–5.5 V
Up to 5000 VRMS isolation
60-year life at rated working voltage
High electromagnetic immunity
Ultra low power (typical)
5 V Operation
1.6 mA per channel at 1 Mbps
5.5 mA per channel at 100 Mbps
2.5 V Operation
1.5 mA per channel at 1 Mbps
3.5 mA per channel at 100 Mbps
Schmitt trigger inputs
Selectable fail-safe mode
Default high or low output
(ordering option)
Precise timing (typical)
10 ns propagation delay
1.5 ns pulse width distortion
0.5 ns channel-channel skew
2 ns propagation delay skew
5 ns minimum pulse width
Transient Immunity 50 kV/µs
AEC-Q100 qualification
Wide temperature range
–40 to 125 °C
RoHS-compliant packages
SOIC-16 wide body
SOIC-16 narrow body
Industrial automation systems
Medical electronics
Hybrid electric vehicles
Isolated switch mode supplies
Isolated ADC, DAC
Motor control
Power inverters
Communication systems
UL 1577 recognized
Up to 5000 VRMS for 1 minute
CSA component notice 5A approval
IEC 60950-1, 61010-1, 60601-1
(reinforced insulation)
VDE certification conformity
IEC 60747-5-2
(VDE0884 Part 2)
EN60950-1
(reinforced insulation)
Ordering Information:
See page 2 6.
2 Rev. 1.4
Si8660/61/62/63
Rev. 1.4 3
Si8660/61/62/63
TABLE OF CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.1. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.2. Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.3. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3.4. Fail-Safe Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
6. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
7. Land Pattern: 16-Pin Wide-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
8. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
9. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
10. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
10.1. Si866x Top Marking (16-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . .33
10.2. Top Marking Explanation (16-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . . . . .33
10.3. Si866x Top Marking (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . .34
10.4. Top Marking Explanation (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . .34
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
4 Rev. 1.4
Si8660/61/62/63
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Symbol Test Condition Min Typ Max Unit
Ambient Operating Temperature* TA150 Mbps , 15 pF, 5 V –40 25 125 °C
Supply Voltage VDD1 2.5 — 5.5 V
VDD2 2.5 — 5.5 V
*Note: The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels,
and supply voltage.
Table 2. Electrical Characteristics
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA=–40 to 125ºC)
Parameter Symbol Test Condition Min Typ Max Unit
VDD Undervoltage Threshold VDDUV+ VDD1, VDD2 rising 1.95 2.24 2.375 V
VDD Undervoltage Threshold V D DUV– VDD1, VDD2 falling 1.88 2.16 2.325 V
VDD Negative-Going
Lockout Hysteresis VDDHYS 50 70 95 mV
Positive-Going Input Threshold VT+ All inputs rising 1.4 1.67 1.9 V
Negative-Going
Input Threshold VT– All inputs falling 1.0 1.23 1.4 V
Input Hysteres is VHYS 0.38 0.44 0.50 V
High Level Input Voltage VIH 2.0 — — V
Low Level Input Voltage VIL ——0.8V
High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 –0.4 4.8 — V
Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V
Input Leakag e Curr en t IL——±10µA
Output Impedance1ZO—50—
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measu re d between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.4 5
Si8660/61/62/63
DC Supply Current (All inputs 0 V or at Supply)
Si8660Bx, Ex
VDD1
VDD2
VDD1
VDD2
VI= 0(Bx), 1(Ex)
VI= 0(Bx), 1(Ex)
VI= 1(Bx), 0(Ex)
VI= 1(Bx), 0(Ex)
—
—
—
—
1.2
3.5
8.8
3.7
1.9
5.3
12.3
5.6
mA
Si8661Bx, Ex
VDD1
VDD2
VDD1
VDD2
VI= 0(Bx), 1(Ex)
VI= 0(Bx), 1(Ex)
VI= 1(Bx), 0(Ex)
VI= 1(Bx), 0(Ex)
—
—
—
—
1.7
3.4
7.9
4.8
2.7
5.1
11.1
7.2
mA
Si8662Bx, Ex
VDD1
VDD2
VDD1
VDD2
VI= 0(Bx), 1(Ex)
VI= 0(Bx), 1(Ex)
VI= 1(Bx), 0(Ex)
VI= 1(Bx), 0(Ex)
—
—
—
—
2.2
3.0
7.5
5.6
3.3
4.5
10.5
8.4
mA
Si8663Bx, Ex
VDD1
VDD2
VDD1
VDD2
VI= 0(Bx), 1(Ex)
VI= 0(Bx), 1(Ex)
VI= 1(Bx), 0(Ex)
VI= 1(Bx), 0(Ex)
—
—
—
—
2.6
2.6
6.5
6.5
3.9
3.9
9.1
9.1
mA
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8660Bx, Ex
VDD1
VDD2
—
—5.0
4.2 7.0
5.9 mA
Si8661Bx, Ex
VDD1
VDD2
—
—4.9
4.6 6.9
6.4 mA
Si8662Bx, Ex
VDD1
VDD2
—
—5.1
4.7 7.1
6.6 mA
Si8663Bx, Ex
VDD1
VDD2
—
—4.9
4.9 6.8
6.8 mA
Table 2. Electrical Characteristics (Continued)
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA=–40 to 125ºC)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measu re d between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
6 Rev. 1.4
Si8660/61/62/63
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8660Bx, Ex
VDD1
VDD2
—
—5.0
5.9 7.0
8.3 mA
Si8661Bx, Ex
VDD1
VDD2
—
—5.2
6.1 7.3
8.5 mA
Si8662Bx, Ex
VDD1
VDD2
—
—5.6
5.9 7.9
8.2 mA
Si8663Bx, Ex
VDD1
VDD2
—
—5.7
5.7 8.0
8.0 mA
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8660Bx, Ex
VDD1
VDD2
—
—5.0
26.2 7.0
34.1 mA
Si8661Bx, Ex
VDD1
VDD2
—
—8.8
23 11.8
29.8 mA
Si8662Bx, Ex
VDD1
VDD2
—
—12.8
19.4 16.6
25.2 mA
Si8663Bx, Ex
VDD1
VDD2
—
—16.4
16.4 21.3
21.3 mA
Table 2. Electrical Characteristics (Continued)
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA=–40 to 125ºC)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measu re d between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.4 7
Si8660/61/62/63
Figure 1. Propagation Delay Timing
Timing Characteristics
Si866xBx, Ex
Maximum Data Rate 0 — 150 Mbps
Minimum Pulse Width — — 5.0 ns
Propagation Delay tPHL, tPLH See Figure 1 5.0 8.0 13 ns
Pulse Width Distortion
|tPLH - tPHL|PWD See Figure 1 — 0.2 4.5 ns
Propagation Delay Skew2tPSK(P-P) —2.04.5ns
Channel-Channel Skew tPSK —0.42.5ns
All Models
Output Rise Time trCL=15pF
See Figure 1 —2.5 4.0 ns
Output Fall Time tfCL=15pF
See Figure 1 —2.5 4.0 ns
Peak Eye Diagram Jitter tJIT(PK) See Figure 6 — 350 — ps
Common Mode
Transient Immunity CMTI VI=V
DD or 0 V 35 50 — kV/µs
Startup Time3tSU —1540µs
Table 2. Electrical Characteristics (Continued)
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA=–40 to 125ºC)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measu re d between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Typical
Input tPLH tPHL
Typical
Output trtf
90%
10%
90%
10%
1.4 V
1.4 V
8 Rev. 1.4
Si8660/61/62/63
Table 3. Electrical Characteristics
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA= –40 to 125 ºC)
Parameter Symbol Test Condition Min Typ Max Unit
VDD Undervoltage Threshold VDDUV+ VDD1, VDD2 rising 1.95 2.24 2.375 V
VDD Undervoltage Threshold VDDUV– VDD1, VDD2 falling 1.88 2.16 2.325 V
VDD Negative-Going Lockout
Hysteresis VDDHYS 50 70 95 mV
Positive-Going Input Threshold VT+ All inputs rising 1.4 1.67 1.9 V
Negative-Going Input Threshold VT– All inputs falling 1 .0 1.23 1.4 V
Input Hysteresis VHYS 0.38 0.44 0.50 V
High Level Input Voltage VIH 2.0 — — V
Low Level Input Voltage VIL ——0.8V
High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 –0.4 3.1 — V
Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V
Input Leakage Current IL——±10µA
Output Impedance1ZO—50—
DC Supply Current (All inputs 0 V or at supply)
Si8660Bx, Ex
VDD1
VDD2
VDD1
VDD2
VI=0(Bx), 1(Ex)
VI=0(Bx), 1(Ex)
VI=1(Bx), 0(Ex)
VI=1(Bx), 0(Ex)
—
—
—
—
1.2
3.5
8.8
3.7
1.9
5.3
12.3
5.6
mA
Si8661Bx, Ex
VDD1
VDD2
VDD1
VDD2
VI=0(Bx), 1(Ex)
VI=0(Bx), 1(Ex)
VI=1(Bx), 0(Ex)
VI=1(Bx), 0(Ex)
—
—
—
—
1.7
3.4
7.9
4.8
2.7
5.1
11.1
7.2
mA
Si8662Bx, Ex
VDD1
VDD2
VDD1
VDD2
VI=0(Bx), 1(Ex)
VI=0(Bx), 1(Ex)
VI=1(Bx), 0(Ex)
VI=1(Bx), 0(Ex)
—
—
—
—
2.2
3.0
7.5
5.6
3.3
4.5
10.5
8.4
mA
Si8663Bx, Ex
VDD1
VDD2
VDD1
VDD2
VI=0(Bx), 1(Ex)
VI=0(Bx), 1(Ex)
VI=1(Bx), 0(Ex)
VI=1(Bx), 0(Ex)
—
—
—
—
2.6
2.6
6.5
6.5
3.9
3.9
9.1
9.1
mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, outpu t pins should be approp riately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.4 9
Si8660/61/62/63
1 Mbps Supply Current (All input s = 500 kHz square wave, CI = 15 pF on all outputs)
Si8660Bx, Ex
VDD1
VDD2
—
—5.0
4.2 7.0
5.9 mA
Si8661Bx, Ex
VDD1
VDD2
—
—4.9
4.6 6.9
6.4 mA
Si8662Bx, Ex
VDD1
VDD2
—
—5.1
4.7 7.1
6.6 mA
Si8663Bx, Ex
VDD1
VDD2
—
—4.9
4.9 6.8
6.8 mA
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8660Bx, Ex
VDD1
VDD2
—
—5.0
5.0 7.0
7.0 mA
Si8661Bx, Ex
VDD1
VDD2
—
—5.0
5.3 7.0
7.4 mA
Si8662Bx, Ex
VDD1
VDD2
—
—5.3
5.2 7.4
7.3 mA
Si8663Bx, Ex
VDD1
VDD2
—
—5.2
5.2 7.3
7.3 mA
Table 3. Electrical Characteristics (Continued)
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA= –40 to 125 ºC)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, outpu t pins should be approp riately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
10 Rev. 1.4
Si8660/61/62/63
100 Mbps Supply Current (All inputs = 50 MHz square wav e, CI = 15 pF on all outputs)
Si8660Bx, Ex
VDD1
VDD2
—
—5.0
18.3 7.0
23.8 mA
Si8661Bx, Ex
VDD1
VDD2
—
—7.4
16.4 9.9
21.3 mA
Si8662Bx, Ex
VDD1
VDD2
—
—10
14.1 13
18.3 mA
Si8663Bx, Ex
VDD1
VDD2
—
—12.3
12.3 15.9
15.9 mA
Timing Characteristics
Si866xBx, Ex
Maximum Data Rate 0 — 150 Mb ps
Minimum Pulse Width — — 5.0 ns
Propagation Delay tPHL, tPLH See Figure 1 5.0 8.0 13 ns
Pulse Width Distortion
|tPLH - tPHL|PWD See Figure 1 — 0.2 4.5 ns
Propagation Delay Skew2tPSK(P-P) —2.04.5ns
Channel-Channel Skew tPSK —0.42.5ns
All Models
Output Rise Time trCL=15pF
See Figure 1 —2.5 4.0 ns
Output Fall Time tfCL=15pF
See Figure 1 —2.5 4.0 ns
Peak Eye Diagram Jitter tJIT(PK) See Figure 6 — 350 — ps
Common Mode Transient
Immunity CMTI VI=V
DD or 0 V 35 50 — kV/µs
Startup Time3tSU —1540µs
Table 3. Electrical Characteristics (Continued)
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA= –40 to 125 ºC)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, outpu t pins should be approp riately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.4 11
Si8660/61/62/63
Table 4. Electrical Characteristics
(VDD1 =2.5V ±5%, V
DD2 = 2.5 V ±5%, TA= –40 to 125 ºC)
Parameter Symbol Test Condition Min Typ Max Unit
VDD Undervoltage Threshold VDDUV+ VDD1, VDD2 rising 1.95 2.24 2.375 V
VDD Undervoltage Threshold VDDUV– VDD1, VDD2 falling 1.88 2.16 2.325 V
VDD Negative-Going Lockout
Hysteresis VDDHYS 50 70 95 mV
Positive-Going Input Threshold VT+ All inputs rising 1.4 1.67 1.9 V
Negative-Going Input Threshold VT– All inputs falling 1.0 1.23 1.4 V
Input Hysteresis VHYS 0.38 0.44 0.50 V
High Level Input Voltage VIH 2.0 — — V
Low Level Input Voltage VIL ——0.8V
High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 –0.4 2.3 — V
Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V
Input Leakage Current IL——±10µA
Output Impedance1ZO—50—
DC Supply Current (All inputs 0 V or at supply)
Si8660Bx, Ex
VDD1
VDD2
VDD1
VDD2
VI= 0(Bx), 1(Ex)
VI= 0(Bx), 1(Ex)
VI= 1(Bx), 0(Ex)
VI= 1(Bx), 0(Ex)
—
—
—
—
1.2
3.5
8.8
3.7
1.9
5.3
12.3
5.6
mA
Si8661Bx, Ex
VDD1
VDD2
VDD1
VDD2
VI= 0(Bx), 1(Ex)
VI= 0(Bx), 1(Ex)
VI= 1(Bx), 0(Ex)
VI= 1(Bx), 0(Ex)
—
—
—
—
1.7
3.4
7.9
4.8
2.7
5.1
11.1
7.2
mA
Si8662Bx, Ex
VDD1
VDD2
VDD1
VDD2
VI= 0(Bx), 1(Ex)
VI= 0(Bx), 1(Ex)
VI= 1(Bx), 0(Ex)
VI= 1(Bx), 0(Ex)
—
—
—
—
2.2
3.0
7.5
5.6
3.3
4.5
10.5
8.4
mA
Si8663Bx, Ex
VDD1
VDD2
VDD1
VDD2
VI= 0(Bx), 1(Ex)
VI= 0(Bx), 1(Ex)
VI= 1(Bx), 0(Ex)
VI= 1(Bx), 0(Ex)
—
—
—
—
2.6
2.6
6.5
6.5
3.9
3.9
9.1
9.1
mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the
same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
12 Rev. 1.4
Si8660/61/62/63
1 Mbps Supply Current (All input s = 500 kHz square wave, CI = 15 pF on all outputs)
Si8660Bx, Ex
VDD1
VDD2
—
—5.0
4.2 7.0
5.9 mA
Si8661Bx, Ex
VDD1
VDD2
—
—4.9
4.6 6.9
6.4 mA
Si8662Bx, Ex
VDD1
VDD2
—
—5.1
4.7 7.1
6.6 mA
Si8663Bx, Ex
VDD1
VDD2
—
—4.9
4.9 6.8
6.8 mA
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8660Bx, Ex
VDD1
VDD2
—
—5.0
4.6 7.0
6.4 mA
Si8661Bx, Ex
VDD1
VDD2
—
—5.0
4.9 6.9
6.9 mA
Si8662Bx, Ex
VDD1
VDD2
—
—5.2
4.9 7.2
6.9 mA
Si8663Bx, Ex
VDD1
VDD2
—
—5.0
5.0 7.0
7.0 mA
Table 4. Electrical Characteristics (Continued)
(VDD1 =2.5V ±5%, V
DD2 = 2.5 V ±5%, TA= –40 to 125 ºC)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the
same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.4 13
Si8660/61/62/63
100 Mbps Supply Current (All inputs = 50 MHz square wav e, CI = 15 pF on all outputs)
Si8660Bx, Ex
VDD1
VDD2
—
—5.0
14.7 7.0
19.1 mA
Si8661Bx, Ex
VDD1
VDD2
—
—6.7
13.4 9.1
17.4 mA
Si8662Bx, Ex
VDD1
VDD2
—
—8.7
11.7 11.3
15.2 mA
Si8663Bx, Ex
VDD1
VDD2
—
—10.3
10.3 13.4
13.4 mA
Timing Characteristics
Si866xBx, Ex
Maximum Data Rate 0 — 150 Mbps
Minimum Pulse Width — — 5.0 ns
Propagation Delay tPHL, tPLH See Figure 1 5.0 8.0 14 ns
Pulse Width Distortion
|tPLH - tPHL|PWD See Figure 1 — 0.2 5.0 ns
Propagation Delay Skew2tPSK(P-P) —2.05.0ns
Channel-Channel Skew tPSK —0.42.5ns
All Models
Output Rise Time trCL=15pF
See Figure 1 —2.5 4.0 ns
Output Fall Time tfCL=15pF
See Figure 1 —2.5 4.0 ns
Peak Eye Diagram Jitter tJIT(PK) See Figure 6 — 350 — ps
Common Mode
Transient Immunity CMTI VI=V
DD or 0 V 35 50 — kV/µs
Startup Time3tSU —1540µs
Table 4. Electrical Characteristics (Continued)
(VDD1 =2.5V ±5%, V
DD2 = 2.5 V ±5%, TA= –40 to 125 ºC)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the
same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
14 Rev. 1.4
Si8660/61/62/63
Table 5. Regulatory Information*
CSA
The Si866x is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
61010-1: Up to 600 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic ins ulation working volt-
age.
60601-1: Up to 125 VRMS reinforced insulation working voltage; up to 380 VRMS basic insulation working voltage.
VDE
The Si866x is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001.
60747-5-2: Up to 1200 Vpeak for basic insulation working voltage.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic ins ulation working volt-
age.
UL
The Si866x is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 5000 V RMS isolation voltage for basic protection.
*Note: Regu latory Certifications apply to 3.75 kVRMS rated devices which are production tested to 4.5 kV RMS for 1 sec.
Regulatory Certifications apply to 5.0 kVRMS rated devices which are production tested to 6.0 kVRMS for 1 sec.
For more information, see "5. Ordering Guide" on page 26.
Table 6. Insulation and Safety-Related Specifications
Parameter Symbol Test
Condition
Value Unit
WB
SOIC-16 NB
SOIC-16
Nominal Air Gap (Clearance)1L(IO1) 8.0 4.9 mm
Nominal External Tracking
(Creepage)1L(IO2) 8.0 4.01 mm
Minimum Internal Gap
(Internal Clearance) 0.014 0.011 mm
Tracking Resistance
(Proof Tracking Index) PTI IEC60112 600 600 VRMS
Erosion Depth ED 0.019 0.019 mm
Resistance (Input-Output)2RIO 1012 1012
Capacitance (Input-Output)2CIO f = 1 MHz 2.0 2.0 pF
Input Capacitance3CI4.0 4.0 pF
Notes:
1. The values in this table correspond to the nominal creepage and clearance values. VD E certifies the clearance and
creepage limits as 4.7 mm minimum for the NB SOIC-16 package and 8.5 mm minimum for the WB SOIC-16 package.
UL does not impose a clearance and creepage minimum for component-level certifications. CSA certifies the clearance
and creepage limits as 3.9 mm minimum for the NB SOIC-16 package and 7.6 mm minimum for the WB SOIC-16
package.
2. To determine resistance and capacitance, the Si86xx is converted into a 2-terminal device. Pins 1–8 are shorted
together to form the first terminal and pins 9–16 are shorted together to form the second terminal. The parameters are
then measured between these two terminals.
3. Measured from input pin to ground.
Rev. 1.4 15
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Table 7. IEC 60664-1 (VDE 0844 Part 2) Ratings
Parameter Test Conditions Specification
NB SOIC-16 WB SOIC-16
Basic Isolation Group Material Group I I
Installation Classification
Rated Mains Voltages < 150 VRMS I-IV I-IV
Rated Mains Voltages < 300 VRMS I-III I-IV
Rated Mains Voltages < 400 VRMS I-II I-III
Rated Mains Voltages < 600 VRMS I-II I-III
Table 8. IEC 60747-5-2 Insulation Characteristics for Si86xxxx*
Parameter Symbol Test Condition Characteristic Unit
WB
SOIC-16 NB SOIC-16
Maximum Working Insulation
Voltage VIORM 1200 630 Vpeak
Input to Output Test Voltage VPR
Method b1
(VIORM x1.875=V
PR, 100%
Production Test, tm= 1 sec,
Partial Discharge < 5 pC)
2250 1182
Transient Overvoltage VIOTM t = 60 sec 6000 6000 Vpeak
Pollution Degree
(DIN VDE 0110, Table 1) 22
Insulation Resistance at TS,
VIO =500V RS>109>109
*Note: Maintenance of the safety data is ensured by protective circuits. The Si86xxxx provides a climate classification of
40/125/21.
Table 9. IEC Safety Limiting Values1
Parameter Symbol Test Condition Min Typ Max Unit
WB SOIC-16 NB SOIC-16
Case Temperature TS—— 150 150 °C
Safety Input, Output,
or Supply Current ISJA =105°C/W
(NB SOIC-16),
VI=5.5V, T
J=150°C,
TA=25°C
——
220 215
mA
Device Power
Dissipation2PD—— 415 415 mW
Notes:
1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figures 2 and 3.
2. The Si86xx is tested with VDD1 = VDD2 = 5.5 V, TJ = 150 ºC, CL = 15 pF, input a 150 Mbps 50% duty cycle square
wave.
16 Rev. 1.4
Si8660/61/62/63
Figure 2. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
Figure 3. (NB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
Table 10. Thermal Characteristics
Parameter Symbol Test Condition WB SOIC-16 NB SOIC-16 Unit
IC Junction-to- Air T herm a l
Resistance JA 100 105 ºC/W
0 20015010050
500
400
200
100
0
Temperature (ºC)
Safety-Limiting Current (mA)
450
300
370
220
VDD1, VDD2 = 2.70 V
VDD1, VDD2 = 3.6 V
VDD1, VDD2 = 5.5 V
020015010050
500
400
200
100
0
Temperature (ºC)
Safety-Limiting Current (mA)
430
300
360
215
VDD1, VDD2 = 2.70 V
VDD1, VDD2 = 3.6 V
VDD1, VDD2 = 5.5 V
Rev. 1.4 17
Si8660/61/62/63
Table 11. Absolute Maximum Ratings1
Parameter Symbol Min Typ Max Unit
Storage Temperature2TSTG –65 — 150 °C
Ambient Temper a tur e Unde r Bia s TA–40 — 125 °C
Junction Temperature TJ——150°C
Supply Voltage VDD1, VDD2 –0.5 — 7.0 V
Input Voltage VI–0.5 — VDD + 0.5 V
Output Voltage VO–0.5 — VDD + 0.5 V
Output Current Drive Channel IO——10mA
Lead Solder Temperature (10 s) — — 260 °C
Maximum Isolation (Input to Output) (1 sec)
NB SOIC-16 — — 4500 VRMS
Maximum Isolation (Input to Output) (1 sec)
WB SOIC-16 — — 6500 VRMS
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to conditions as specified in the operational sections of this data sheet.
2. VDE certifies storage temperature from –40 to 150 °C.
18 Rev. 1.4
Si8660/61/62/63
2. Functional Description
2.1. Theory of Operation
The operation of an Si866x channel is analogous to that of an opto coupler, except an RF carrier is modulated
instead of light. This simple architecture provides a robust isolated data path and requires no special
considerations or initialization at start-up. A simplified block diagram for a single Si866x channel is shown in
Figure 4.
Figure 4. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier.
Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The
Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the
result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it
provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See
Figure 5 for more details.
Figure 5. Modulation Scheme
RF
OSCILLATOR
MODULATOR DEMODULATOR
A B
Semiconductor-
Based Isolation
Barrier
Transmitter Receiver
Input Signal
Output Signal
Modulation Signal