Copyright ANPEC Electronics Corp.
Rev. A.7 - Mar., 2011
APW7145
www.anpec.com.tw1
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
3A, 12V, Synchronous-Rectified Buck Converter
The APW7145 is a 3A synchronous-rectified Buck con-
verter with integrated 55mΩ power MOSFETs. The
APW7145, designed with a current-mode control scheme,
can convert wide input voltage of 4.3V to 14V to the output
voltage adjustable from 0.8V to VIN to provide excellent
output voltage regulation.
For high efficiency over all load current range, the
APW7145 is equipped with an automatic Skip/PWM mode
operation. At light load, the IC operates in the Skip mode,
which keeps a constant minimum inductor peak current,
to reduce switching losses. At heavy load, the IC works in
PWM mode, which inductor peak current is programmed
by the COMP voltage, to provide high efficiency and excel-
lent output voltage regulation.
The APW7145 is also equipped with power-on-reset, soft-
start, soft-stop, and whole protections (under-voltage,
over-voltage, over-temperature, and current-limit) into a
single package. In shutdown mode, the supply current
drops below 3µA.
This device, available SOP-8P and DFN4x4-8 packages,
provides a very compact system solution with minimal
external components and PCB area.
FeaturesGeneral Description
•Wide Input Voltage from 4.3V to 14V
•Output Current up to 3A
•Adjustable Output Voltage from 0.8V to VIN
- ±2% System Accuracy
•55mΩ Integrated Power MOSFETs
•High Efficiency up to 95%
- Automatic Skip/PWM Mode Operation
•Current-Mode Operation
- Easy Feedback Compensation
- Stable with Low ESR Output Capacitors
- Fast Load/Line Transient Response
•Power-On-Reset Monitoring
•Fixed 500kHz Switching Frequency in PWM Mode
•Built-In Digital Soft-Start and Soft-Stop
•Current-Limit Protection with Frequency Foldback
•123% Over-Voltage Protection
•Hiccup-Mode 50% Under-Voltage Protection
•Over-Temperature Protection
•<3µA Quiescent Current in Shutdown Mode
• SOP-8P and Compact 4mmx4mm DFN-8
(DFN4x4-8) Packages
•Lead Free and Green Devices Available
(RoHS Compliant)
Applications
•OLPC, UMPC
•Notebook Computer
• Handheld Portable Device
•Step-Down Converters Requiring High Efficiency
and 3A Output Current0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1 10
VIN=5V, VOUT=3.3V, L1=2.2µH
VIN=12V, VOUT=5V, L1=6.8µH
VIN=12V, VOUT=3.3V, L1=4.7µH
VIN=12V, VOUT=2V, L1=3.3µH
VIN=5V, VOUT=1.2V, L1=2.2µH
Copyright ANPEC Electronics Corp.
Rev. A.7 - Mar., 2011
APW7145
www.anpec.com.tw2
Ordering and Marking Information
Absolute Maximum Ratings (Note 1)
Symbol Parameter Rating Unit
VIN VIN Supply Voltage (VIN to AGND) -0.3 ~ 15 V
> 100ns -1 ~ VIN+1
VLX LX to GND Voltage < 100ns - 5 ~ VIN+5 V
PGND to AGND Voltage -0.3 ~ +0.3 V
EN to AGND Voltage -0.3 ~ VIN+0.3 V
FB, COMP to AGND Voltage -0.3 ~ 6 V
PD Power Dissipation Internally Limited W
Maximum Junction Temperature 150 oC
TSTG Storage Temperature -65 ~ 150 oC
TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 oC
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Pin Configuration
The Pin 7 must be connected to the Exposed Pad
NC
VIN
AGND
FB
1
2
3
4
PGND
LX
EN
COMP
8
7
6
5
9
LX
APW7145
SOP-8P
(Top View) DFN4x4-8
(Top View)
1
6
54
3
28
7PGND
EN
LX
COMP
VIN
FB
NC
AGND
APW7145
APW7145 Package Code
KA : SOP-8P QA: DFN4x4-8
Operating Ambient Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
Handling Code
Temperature Range
Package Code
Assembly Material
APW7145 KA : XXXXX - Date Code
APW7145
XXXXX
APW7145 QA : APW7145
XXXXX XXXXX - Date Code
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom-
mended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability
Copyright ANPEC Electronics Corp.
Rev. A.7 - Mar., 2011
APW7145
www.anpec.com.tw3
Symbol Parameter Range Unit
VIN VIN Supply Voltage 4.3 ~ 14 V
VOUT Converter Output Voltage 0.8 ~ VIN V
IOUT Converter Output Current 0 ~ 3 A
CIN Converter Input Capacitor (MLCC) 8 ~ 50 µF
Converter Output Capacitor 20 ~ 1000 µF
COUT Effective Series Resistance 0 ~ 60 mΩ
LOUT Converter Output Inductor 1 ~ 22 µH
Resistance of the Feedback Resistor connected from FB to GND 1 ~ 20 kΩ
TA Ambient Temperature -40 ~ 85 oC
TJ Junction Temperature -40 ~ 125 oC
Symbol Parameter Typical Value Unit
θJA Junction-to-Ambient Thermal Resistance in Free Air (Note 2) SOP-8P
DFN4x4-
8
50
65
oC/W
θJC Junction-to-Case Resistance in Free Air (Note 3)
SOP-8P
DFN4x4-
8
20
30
oC/W
Recommended Operating Conditions (Note 4)
Electrical Characteristics
Refer to the “Typical Application Circuits”. These specifications apply over VIN=12V, VOUT=3.3V and TA= -40 ~ 85°C, unless otherwise
specified. Typical values are at TA=25°C.
APW7145
Symbol Parameter Test Conditions Min. Typ. Max.
Unit
SUPPLY CURRENT
IVIN VIN Supply Current V
FB = VREF +50mV, VEN=3V, LX=NC - 0.5 1.5 mA
IVIN_SD VIN Shutdown Supply Current V
EN = 0V - - 3 µA
POWER-ON-RESET (POR) VOLTAGE THRESHOLD
VIN POR Voltage Threshold V
IN rising 3.9 4.1 4.3 V
VIN POR Hysteresis - 0.5 - V
REFERENCE VOLTAGE
VREF Reference Voltage Regulated on FB pin - 0.8 - V
T
J = 25oC, IOUT=10mA, VIN=12V -1.0 - +1.0
Output Voltage Accuracy I
OUT=10mA~3A, VIN=4.75~14V -2.0 - +2.0 %
Line Regulation V
IN = 4.75V to 14V - +0.02
- %/V
Load Regulation IOUT = 0.5A ~ 3A - -0.04
- %/A
Thermal Characteristics
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
Note 3: The case temperature is measured at the center of the exposed pad on the underside of the SOP-8P and DFN4x4-8 packages.
Note 4: Refer to the Typical Application Circuits.
Copyright ANPEC Electronics Corp.
Rev. A.7 - Mar., 2011
APW7145
www.anpec.com.tw4
Electrical Characteristics (Cont.)
Refer to the “Typical Application Circuits”. These specifications apply over VIN=12V, VOUT=3.3V and TA= -40 ~ 85°C, unless otherwise
specified. Typical values are at TA=25°C.
APW7145
Symbol Parameter Test Conditions Min. Typ. Max.
Unit
OSCILLATOR AND DUTY CYCLE
FOSC Oscillator Frequency T
J = -40 ~ 125oC, VIN = 4.75 ~ 14V
450 500 550 kHz
Foldback Frequency V
OUT = 0V - 80 - kHz
Maximum Converter’s Duty - 99 - %
TON_MIN Minimum Pulse Width of LX - 150 - ns
CURRENT-MODE PWM CONVERTER
Gm Error Amplifier Transconductance V
FB=VREF±50mV - 200 - µA/V
Error Amplifier DC Gain COMP = NC - 80 - dB
Current-Sense to COMP Voltage
Transresistance - 0.1 - V/A
Between VIN and Exposed Pad,
VIN = 5V, TJ=25°C - 70 100
High-Side Switch Resistance Between VIN and Exposed Pad,
VIN = 12V, TJ=25°C - 55 80 mΩ
Between GND and Exposed Pad,
VIN = 5V, TJ=25°C - 55 100
Low-Side Switch Resistance Between GND and Exposed Pad,
VIN = 12V, TJ=25°C - 45 80 mΩ
PROTECTIONS
ILIM High-Side Switch Current-limit Peak Current 5 6.5 8 A
VTH_UV FB Under-Voltage Threshold V
FB falling 45 50 55 %
VTH_OV FB Over-Voltage Threshold V
FB rising 118 123 128 %
FB Under-Voltage Debounce - 1 - µs
TOTP Over-Temperature Trip Point - 150 - oC
Over-Temperature Hysteresis - 40 - oC
TD Dead-Time V
LX = -0.7V - 20 - ns
SOFT-START, SOFT-STOP, ENABLE, AND INPUT CURRENTS
TSS Soft-Start / Soft-Stop Interval 1.5 2 2.5 ms
EN Low Logic Level V
EN falling - - 0.5 V
EN High Logic Level V
EN rising 2.1 - - V
High-side Switch Leakage Current
V
EN = 0V, VLX = 0V - - 2 µA
IFB FB Pin Input Current -100 - +100
nA
IEN EN Pin Input Current V
EN = 0V ~ VIN -100 - +100
nA
Copyright ANPEC Electronics Corp.
Rev. A.7 - Mar., 2011
APW7145
www.anpec.com.tw5
Typical Operating Characteristics
VIN Input Current vs. Supply Voltage
Supply Voltage, VIN (V)
VIN Input Current, IVIN (mA)
Current Limit Level (Peak Current)
vs. Junction Temperature
Junction Temperature, TJ (oC)
Output Voltage vs. Supply Voltage
Supply Voltage, VIN (V)
Output Current vs. Efficiency Output Current vs. Output Voltage
Output Current, IOUT (A)Output Current, IOUT (A)
Output Voltage, VOUT (V)
Efficiency (%)
Output Voltage, VOUT (V)
Current Limit Level, ILIM (A)
Reference Voltage, VREF (V)
Junction Temperature, TJ (oC)
Reference Voltage vs. Junction Temperature
0.784
0.788
0.792
0.796
0.800
0.804
0.808
0.812
0.816
-50 -25 025 50 75 100 125 150
3.2
3.22
3.24
3.26
3.28
3.3
3.32
3.34
3.36
3.38
3.4
46810 12 14
IOUT=500mA
(Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=4.7µH)
0.0
0.5
1.0
1.5
2.0
0 2 4 6 8 10 12 14
VFB=0.85V
5.5
6
6.5
7
7.5
7
-40 -20 020 40 60 80 100 120 140
3.2
3.22
3.24
3.26
3.28
3.3
3.32
3.34
3.36
3.38
3.4
0 1 2 3
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1 10
VIN=5V, VOUT=3.3V, L1=2.2µH
VIN=12V, VOUT=5V, L1=6.8µH
VIN=12V, VOUT=3.3V, L1=4.7µH
VIN=12V, VOUT=2V, L1=3.3µH
VIN=5V, VOUT=1.2V, L1=2.2µH
Copyright ANPEC Electronics Corp.
Rev. A.7 - Mar., 2011
APW7145
www.anpec.com.tw6
Typical Operating Characteristics (Cont.)
Oscillator Frequency vs.
Junction Temperature
Oscillator Frequency, FOSC (kHz)
Junction Temperature, TJ (oC)
(Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=4.7µH)
450
460
470
480
490
500
510
520
530
540
550
-50 -25 0 25 50 75 100 125 150
Copyright ANPEC Electronics Corp.
Rev. A.7 - Mar., 2011
APW7145
www.anpec.com.tw7
EnableShutdown
VEN
VOUT
IL1
CH1 : VEN , 5V/div
CH3 : IL1, 2A/div
Time : 100µs/div
CH2 : VOUT , 2V/div
1
2
3
IOUT=3A
CH1 : VEN , 5V/div
CH3 : IL1 , 2A/div
Time : 1ms/div
CH2 : VOUT , 2V/div
1
2
3
VEN
VOUT
IL1
IOUT=3A
Power OnPower Off
CH1 : VIN , 5V/div
CH2 : VOUT , 2V/div
Time : 1ms/div
1
2
3
CH3 : IL1 , 2A/div
VIN
VOUT
IL1
IOUT=3A
CH1 : VIN , 5V/div
CH2 : VOUT , 2V/div
Time : 10ms/div
CH3 : IL1 , 2A/div
1
2
3
VIN
VOUT
IL1
IOUT=3A
Operating Waveforms
(Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=4.7µH)
Copyright ANPEC Electronics Corp.
Rev. A.7 - Mar., 2011
APW7145
www.anpec.com.tw8
Operating Waveforms (Cont.)
Load Transient Response Load Transient Response
(Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=4.7µH)
CH1 : VOUT , 100mV/div
CH2 : IL1 , 2A/div
Time : 100µs/div
IL1
VOUT
1
2
IOUT= 0.5A-> 3A ->0.5A
IOUT rising/falling time=10µs
VOUT
IL1
CH1 : VOUT , 200mV/div
CH2 : IL1 , 2A/div
Time : 100µs/div
1
2
IOUT= 50mA-> 3A ->50mA
IOUT rising/falling time=10µs
Short CurrentShort Circuit
CH1 : VLX , 10V/div
CH2 : VOUT , 2V/div
CH3 : IL1 , 5A/div
Time : 20µs/div
IOUT =3~7A
VLx
VOUT
IL1
1
2
3
1
2
3
VLX
VOUT
IL1
CH1 : VLX , 5V/div
CH2 : VOUT , 200mV/div
CH3 : IL1 , 5A/div
Time : 5ms/div
VOUT is shorted to GND by a short wire
Copyright ANPEC Electronics Corp.
Rev. A.7 - Mar., 2011
APW7145
www.anpec.com.tw9
Operating Waveforms (Cont.)
Line Transient
(Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=4.7µH)
VIN
VOUT
IL1
CH1 : VIN , 5V/div
CH2 : VOUT , 50mV/div (Voffset=3.3V)
Time : 100µs/div
1
2
3
CH3 : IL1 , 2A/div
VIN= 5~12V VIN rising/falling time=20µs
Switching WaveformSwitching Waveform
CH1 : VLX , 5V/div
CH2 : IL1 , 2A/div
Time : 1µs/div
IL1
VLX
IOUT=0.2A
1
2
CH1 : VLX , 5V/div
CH2 : IL1 , 2A/div
Time : 1µs/div
VLX
IL1
IOUT=3A
1
2
Over-Voltage Protection
VIN
VOUT
IL1
1
2
4
3
VLX
IOUT=-1A
CH1 : VIN , 5V/div
CH2 : VOUT , 2V/div
CH4 : IL1 , 5A/div
Time : 20µs/div
CH3 : VLX , 5V/div
Copyright ANPEC Electronics Corp.
Rev. A.7 - Mar., 2011
APW7145
www.anpec.com.tw10
Pin Description
PIN
NO. NAME FUNCTION
1 NC No Connection.
2 VIN
Power Input. VIN supplies the power (4.3V to 14V) to the control circuitry, gate drivers
and step-down converter switches. Connecting a ceramic bypass capacitor and a
suitably large capacitor between VIN and both of AGND and PGND to eliminate
switching noise and voltage ripple on the input to the IC.
3 AGND Ground of MOSFET Gate Drivers and Control Circuitry.
4 FB Output Feedback Input. The APW7145 senses the feedback voltage via FB and
regulates the voltage at 0.8V. Connecting FB with a resistor-divider from the converter’s
output sets the output voltage from 0.8V to VIN.
5 COMP Output of the error amplifier. Connecting a series RC network from COMP to GND to
compensate the regulation control loop. In some cases, an additional capacitor from
COMP to GND is required.
6 EN Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn
on the regulator, drive it low to turn it off. Connecting this pin to VIN if it is not used.
7 LX Power Switching Output. LX is the junction of the high-side and low-side power
MOSFETs to supply power to the output LC filter.
8 PGND Power Ground of the APW7145, which is the source of the N-channel power MOSFET.
Connect this pin to the system ground with lowest impedance.
9
(Exposed Pad) LX
Power Switching Output. LX is the Drain of the P-channel MOSFET to supply power to
the output. The Exposed Pad provides current with lower impedance than the Pin 7.
Connecting the pad to output LC filter via a top-layer thermal pad on PCBs. The PCB will
be a heat sink of the IC.
Block Diagram
LX
Gate
Control
VREF
Soft-Start /
Soft-Stop
and
Fault Logic
Error
Amplifier
FB
Inhibit
50%VREF UVP
PGND
POR
Soft-Start /
Soft-Stop
Power-On-
Reset
VIN
VIN
Current Sense
Amplifier
EN
COMP
OVP
123%VREF
Oscillator
500kHz
Slope
Compensation
Current
Compartor
VIN
Over-
Temperature
Protection
Zero-Crossing
Comparator
Current
Limit
FB
UG
LG
Gate
Driver
Gate
Driver
AGND
Gm
Enable/
Shutdown
Copyright ANPEC Electronics Corp.
Rev. A.7 - Mar., 2011
APW7145
www.anpec.com.tw11
Typical Application Circuit
1. 4.3~14V Single Power Input Step-down Converter (with a Ceramic Output Capacitor)
LX
EN
6
VIN
2
AGND
3
COMP
5
9
U1
APW7145
FB 4
VOUT
L1
3A
VIN
C1
LX 7
Enable
Shutdown
PGND 8C2
R1
±1%
R2
±1% C4
(±30%, Optional)
R3
(±5%)
C3
(±30%)
a. Cost-effective Feedback Compensation (C4 is no connection)
VIN(V) VOUT(V) L1(µF) C2(µF) C2 ESR(mΩ)R1(kΩ)R2(kΩ)R3(kΩ)C3(pF)
12 5 6.8 22 563.0 12 33.0 820
12 5 6.8 44 363.0 12 68.0 820
12 3.3 4.7 22 546.9 15 27.0 1000
12 3.3 4.7 44 346.9 15 56.0 1000
12 2 3.3 22 530.0 20 18.0 1800
12 2 3.3 44 330.0 20 33.0 1800
12 1.8 3.3 22 518.8 15 15.0 1800
12 1.8 3.3 44 318.8 15 30.0 1800
53.3 2.2 22 546.9 15 27.0 470
53.3 2.2 44 346.9 15 56.0 470
51.8 2.2 22 525.0 20 15.0 820
51.8 2.2 44 325.0 20 30.0 820
51.5 2.2 22 521.9 25 12.0 1000
51.5 2.2 44 321.9 25 24.0 1000
51.2 2.2 22 57.5 15 10.0 1200
51.2 2.2 44 37.5 15 20.0 1200
Copyright ANPEC Electronics Corp.
Rev. A.7 - Mar., 2011
APW7145
www.anpec.com.tw12
2. +12V Single Power Input Step-down Converter (with an Electrolytic Output Capacitor)
Typical Application Circuit (Cont.)
LX
EN
6
VIN
AGND
COMP
5
9
U1
APW7145
FB 4
L1
4.7µH /3A
VIN
12V
C1
2.2µF
LX 7
Enable
Shutdown
PGND 8C2
470µF
(ESR=30mΩ)
R1
46.9K
1%
R2
15K
1%
R3
100K
C3
1000pF
C5
470µF
VOUT
3.3V/3A
2
3
b. Fast-Transient-Response Feedback Compensation (C4 is connected)
VIN(V) VOUT(V) L1(µH) C2(µF)C2 ESR(mΩ)R1(kΩ)R2(kΩ)R3(kΩ)C3(pF) C4(pF)
12 5 6.8 22 5 63.0 12 43 680.0 27
12 5 6.8 44 3 63.0 12 82 680.0 27
12 3.3 4.7 22 5 46.9 15 27 1000.0 27
12 3.3 4.7 44 3 46.9 15 56 1000.0 27
12 2 3.3 22 5 30.0 20 18 1800.0 27
12 2 3.3 44 3 30.0 20 33 1800.0 27
12 1.8 3.3 22 5 18.8 15 15 1800.0 33
12 1.8 3.3 44 3 18.8 15 30 1800.0 33
53.3 2.2 22 5 46.9 15 27 470.0 27
53.3 2.2 44 3 46.9 15 56 470.0 27
51.8 2.2 22 5 25.0 20 15 820.0 56
51.8 2.2 44 3 25.0 20 30 820.0 56
51.5 2.2 22 5 22 25 12 1000 56
51.5 2.2 44 3 22 25 24 1000 56
51.2 2.2 22 5 7.5 15 10 1200 180
51.2 2.2 44 3 7.5 15 20 1200 270
Copyright ANPEC Electronics Corp.
Rev. A.7 - Mar., 2011
APW7145
www.anpec.com.tw13
Function Description
VIN Power-On-Reset (POR)
The APW7145 keeps monitoring the voltage on the VIN
pin to prevent wrong logic operations which may occur
when VIN voltage is not high enough for the internal con-
trol circuitry to operate. The VIN POR has a rising thresh-
old of 4.1V (typical) with 0.5V of hysteresis.
During start-up, the VIN voltage must exceed the enable
voltage threshold. Then, the IC starts a start-up process
and ramps up the output voltage to the voltage target.
Digital Soft-Start
The APW7145 has a built-in digital soft-start to control the
rise rate of the output voltage and limit the input current
surge during start-up. During soft-start, an internal voltage
ramp (VRAMP), connected to one of the positive inputs of
the error amplifier, rises up from 0V to 0.95V to replace the
reference voltage (0.8V) until the voltage ramp reaches
the reference voltage.
During soft-start without output over-voltage, the APW7145
converter’s sinking capability is disabled until the output
voltage reaches the voltage target.
Digital Soft-Stop
At the moment of shutdown controlled by EN signal, un-
der-voltage event, or over-temperature protection, the
APW7145 initiates a digital soft-stop process to discharge
the output voltage in the output capacitors. Certainly, the
load current also discharges the output voltage.
During soft-stop, the internal voltage ramp (VRAMP) falls
down from 0.95V to 0V to replace the reference voltage.
Therefore, the output voltage falls down slowly at light load.
After the soft-stop interval elapses, the soft-stop process
ends and the the IC turns on the low-side power MOSFET.
Output Under-Voltage Protection (UVP)
In the operational process, if a short-circuit occurs, the
output voltage will drop quickly. Before the current-limit
circuit responds, the output voltage will fall out of the re-
quired regulation range. The under-voltage continually
monitors the FB voltage after soft-start is completed. If a
load step is strong enough to pull the output voltage lower
than the under-voltage threshold, the IC shuts down
converter’s output.
The under-voltage threshold is 50% of the nominal out-
put voltage. The undervoltage comparator has a built-in
2µs noise filter to prevent the chips from wrong UVP shut-
down caused by noise. The under-voltage protection
works in a hiccup mode without latched shutdown. The
IC will initiate a new soft-start process at the end of the
preceding delay.
Over-Voltage Protection (OVP)
The over-voltage function monitors the output voltage by
FB pin. When the FB voltage increase over 123% of the
reference voltage due to the high-side MOSFET failure,
or for other reasons, the over-voltage protection compara-
tor will force the low-side MOSFET gate driver high. This
action actively pulls down the output voltage and eventu-
ally attempts to blow the internal bonding wires. As soon
as the output voltage is within regulation, the OVP com-
parator is disengaged. The chip will restore its normal
operation. This OVP scheme only clamps the voltage over-
shoot and does not invert the output voltage when other-
wise activated with a continuously high output from low-
side MOSFET driver - a common problem for OVP
schemes with a latch.
Over-Temperature Protection (OTP)
The over-temperature circuit limits the junction tempera-
ture of the APW7145. When the junction temperature ex-
ceeds TJ = +150oC, a thermal sensor turns off the both
power MOSFETs, allowing the devices to cool. The ther-
mal sensor allows the converters to start a start-up pro-
cess and regulate the output voltage again after the junc-
tion temperature cools by 40oC. The OTP is designed
with a 40oC hysteresis to lower the average TJ during
continuous thermal overload conditions, increasing life-
time of the APW7145.
Enable/Shutdown
Driving EN to the ground initiates a soft-stop process
and then places the APW7145 in shutdown. When in
shutdown, after the soft-stop process is completed, the
internal power MOSFETs turns off, all internal circuitry
shuts down and the quiescent supply current reduces to
less than 3mA.
Copyright ANPEC Electronics Corp.
Rev. A.7 - Mar., 2011
APW7145
www.anpec.com.tw14
Function Description (Cont.)
Current-Limit Protection
The APW7145 monitors the output current, flowing through
the high-side power MOSFET, and limits the current peak
at current-limit level to prevent loads and the IC from dam-
ages during overload or short-circuit conditions.
Frequency Foldback
The foldback frequency is controlled by the FB voltage.
When the output is shortened to the ground, the frequency
of the oscillator will be reduced to 80kHz. This lower fre-
quency allows the inductor current to safely discharge,
thereby preventing current runaway. The oscillator’s fre-
quency will gradually increase to its designed rate when
the feedback voltage on FB again approaches 0.8V.
Copyright ANPEC Electronics Corp.
Rev. A.7 - Mar., 2011
APW7145
www.anpec.com.tw15
Application Information
(V) )
R2
R1
(10.8VOUT +⋅=
Setting Output Voltage
The regulated output voltage is determined by:
Suggested R2 is in the range from 1K to 20kΩ. For
portable applications, a 10K resistor is suggested for R2.
To prevent stray pickup, please locate resistors R1 and R2
close to APW7145.
Input Capacitor Selection
Use small ceramic capacitors for high frequency
decoupling and bulk capacitors to supply the surge cur-
rent needed each time the P-channel power MOSFET (Q1)
turns on. Place the small ceramic capacitors physically
close to the VIN and between the VIN and the GND.
The important parameters for the bulk input capacitor are
the voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and
current ratings above the maximum input voltage and larg-
est RMS current required by the circuit. The capacitor volt-
age rating should be at least 1.25 times greater than the
maximum input voltage and a voltage rating of 1.5 times is
a conservative guideline. The RMS current (IRMS) of the
bulk input capacitor is calculated as the following equation:
(A) D)-(1DI IOUTRMS ⋅⋅=
where D is the duty cycle of the power MOSFET.
For a through hole design, several electrolytic capacitors
may be needed. For surface mount designs, solid tanta-
lum capacitors can be used, but caution must be exer-
cised with regard to the capacitor surge current rating.
Figure 1. Converter Waveforms
Output Capacitor Selection
An output capacitor is required to filter the output and sup-
ply the load transient current. The filtering requirements
are the function of the switching frequency and the ripple
current (∆I). The output ripple is the sum of the voltages,
having phase shift, across the ESR, and the ideal output
capacitor. The peak-to-peak voltage of the ESR is calcu-
lated as the following equations:
........... (1)
........... (2)
L · FD)-(1 · V
IOSC
OUT
=∆
The peak-to-peak voltage of the ideal output capacitor is
calculated as the following equation:
VIN
VOUT
CIN
COUT
L
Q1
LX ESR
ILIOUT
IQ1
ICOUT
VIN
Q2
IOUT
VLX
T=1/FOSC
IL
IQ1
ICOUT
IOUT
I
I
DT
VOUT
VOUT
V
V
DIN
OUT
=
........... (3)
ESR.IVESR ⋅∆=
(V)
CF8I
VOUTOSC
COUT ⋅⋅ ∆
=∆........... (4)
For the applications using bulk capacitors, the ∆VCOUT is
much smaller than the VESR and can be ignored. Therefore,
the AC peak-to-peak output voltage (∆VOUT ) is shown as
below:
(V) ESRI VOUT ⋅∆=∆........... (5)
Copyright ANPEC Electronics Corp.
Rev. A.7 - Mar., 2011
APW7145
www.anpec.com.tw16
Application Information (Cont.)
Output Capacitor Selection (Cont.)
where
For the applications using ceramic capacitors, the VESR is
much smaller than the ∆VCOUT and can be ignored.
Therefore, the AC peak-to-peak output voltage (∆VOUT ) is
close to ∆VCOUT.
The load transient requirements are the function of the
slew rate (di/dt) and disengaged\the magnitude of the
transient load current. These requirements are generally
met with a mix of capacitors and careful layout. High fre-
quency capacitors initially supply the transient and slow
the current load rate seen by the bulk capacitors. The bulk
filter capacitor values are generally determined by the ESR
(Effective Series Resistance) and voltage rating require-
ments rather than actual capacitance requirements.
High frequency decoupling capacitors should be placed
as close to the power pins of the load as physically
possible. Be careful not to add inductance in the circuit
board wiring that could cancel the usefulness of these
low inductance components. An aluminum electrolytic
capacitor’s ESR value is related to the case size with lower
ESR available in larger case sizes. However, the Equiva-
lent Series Inductance (ESL) of these capacitors increases
with case size and can reduce the usefulness of the ca-
pacitor to high slew-rate transient loading.
Inductor Value Calculation
........... (6)
IN(MAX)IN V V=
The operating frequency and inductor selection are inter-
related in that higher operating frequencies permit the
use of a smaller inductor for the same amount of inductor
ripple current. However, this is at the expense of efficiency
due to an increase in MOSFET gate charge losses. The
equation (2) shows that the inductance value has a direct
effect on ripple current.
Accepting larger values of ripple current allows the use of
low inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ∆I ≤ 0.4 ⋅ IOUT(MAX). Please be no-
ticed that the maximum ripple current occurs at the maxi-
mum input voltage. The minimum inductance of the in-
ductor is calculated by using the following equation:
Layout Consideration
In high power switching regulator, a correct layout is im-
portant to ensure proper operation of the regulator. In
general, interconnecting impedance should be minimized
by using short and wide printed circuit traces. Signal and
power grounds are to be kept separating and finally com-
bined using ground plane construction or single point
grounding. Figure 2 illustrates the layout, with bold lines
indicating high current paths. Components along the bold
lines should be placed close together. Below is a check-
list for your layout:
1. Firstly, to initial the layout by placing the power
components. Orient the power circuitry to achieve a
clean power flow path. If possible, make all the con-
nections on one side of the PCB with wide and copper
filled areas.
Figure 2. Current Path Diagram
1.2
V· L · 500000 )V-(V · V
IN
OUTINOUT ≤
(H)
V· 600000 )V-(V · V
LIN
OUTINOUT
≥
2. In Figure 2, the loops with same color bold lines con-
duct high slew rate current. These interconnecting im-
pedances should be minimized by using wide and short
printed circuit traces.
VOUT
LX
EN
6
VIN
2
AGND
3
COMP
5
9
U1
APW7145
FB 4
C3
R3 R1
LX 7
PGND 8
R2
L 1
C2Load
C1
+
VIN
-
Feedback
Divider
C4(Optional)
Compensation
Network
1
NC
+
-
Copyright ANPEC Electronics Corp.
Rev. A.7 - Mar., 2011
APW7145
www.anpec.com.tw17
Layout Consideration (Cont.)
4. Place the decoupling ceramic capacitor C1 near the
VIN as close as possible. Use a wide power ground
plane to connect the C1 and C2 to provide a low imped-
ance path between the components for large and high
slew rate current.
Figure 3. Recommended Layout Diagram
3. Keep the sensitive small signal nodes (FB and COMP)
away from switching nodes (LX or others) on the PCB.
Therefore, place the feedback divider and the feedback
compensation network close to the IC to avoid switch-
ing noise. Connect the ground of feedback divider di-
rectly to the AGND pin of the IC using a dedicated ground
trace.
Application Information (Cont.)
Ground
SOP-8P
C1
L1
VIN
APW7145
VOUT
VLX
Ground
1
2
3
4
For dissipating heat
5
6
7
8
C2
Ground
DFN4x4
C1
L1
VIN
APW7145
VOUT
VLX
Ground
1
2
3
4
For dissipating heat
5
6
7
8
C2
Copyright ANPEC Electronics Corp.
Rev. A.7 - Mar., 2011
APW7145
www.anpec.com.tw18
Package Information
SOP-8P
THERMAL
PAD
D
D1
E2
E1
E
eb
A2
A
A1
VIEW AL
0.25
GAUGE PLANE
SEATING PLANE
θ
Note : 1. Followed from JEDEC MS-012 BA.
2. Dimension "D" does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side .
3. Dimension "E" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
0.020
0.010
0.020
0.050
0.006
0.063
MAX.
0.40L
θ0oC
E
e
h
E1
0.25
D
c
b
0.17
0.31
0.016
1.27
8oC0oC8oC
0.50
1.27 BSC
0.51
0.25
0.050 BSC
0.010
0.012
0.007
MILLIMETERS
MIN.
S
Y
M
B
O
L
A1
A2
A
0.00
1.25
SOP-8P
MAX.
0.15
1.60
MIN.
0.000
0.049
INCHES
D1 2.50 0.098
2.00 0.079E2
3.50
3.00
0.138
0.118
4.80 5.00 0.189 0.197
3.80 4.00 0.150 0.157
5.80 6.20 0.228 0.244
h X 45o
c
SEE VIEW A
-T- SEATING PLANE < 4 mils
Copyright ANPEC Electronics Corp.
Rev. A.7 - Mar., 2011
APW7145
www.anpec.com.tw19
Package Information
DFN4x4-8A
b
A1
A3
Pin 1
D
E
Pin 1 Corner
E2
D2
e
LK
S
Y
M
B
O
LMIN. MAX.
1.00
0.00
0.25 0.35
3.10 3.30
0.05
2.40
A
A1
b
D
D2
E
E2
e
L
MILLIMETERS
A3 0.20 REF
DFN4x4-8
0.40 0.60
2.60
0.008 REF
MIN. MAX.
INCHES
0.039
0.000
0.010 0.014
0.122 0.130
0.094
0.016 0.024
0.80
0.102
0.031
0.002
0.80 BSC 0.031 BSC
0.20 0.008
K
3.90 4.10 0.154 0.161
3.90 4.10 0.154 0.161
Note : 1. Followed from JEDEC MO-229 VGGB.
Copyright ANPEC Electronics Corp.
Rev. A.7 - Mar., 2011
APW7145
www.anpec.com.tw20
Application
A H T1 C d D W E1 F
330.0±2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±0.30
1.75±0.10
5.5±0.05
P0 P1 P2 D0 D1 T A0 B0 K0
SOP-8P
4.0±0.10
8.0±0.10
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
6.40±0.20
5.20±0.20
2.10±0.20
Application
A H T1 C d D W E1 F
330.0±2.00
50 MIN.
12.4+2.00
-
0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±0.30
1.75±0.10
5.5±0.05
P0 P1 P2 D0 D1 T A0 B0 K0
DFN4x4-8
4.0±0.10
8.0±0.10
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
4.30±0.20
4.30±0.20
1.30±0.20
(mm)
Devices Per Unit
Carrier Tape & Reel Dimensions
Package Type Unit Quantity
SOP-8P Tape & Reel 2500
DFN4x4-8 Tape & Reel 3000
A
E1
A
B
W
F
T
P0
OD0
BA0
P2
K0
B0
SECTION B-B
SECTION A-A
OD1
P1
H
T1
A
d
Copyright ANPEC Electronics Corp.
Rev. A.7 - Mar., 2011
APW7145
www.anpec.com.tw21
Taping Direction Information
USER DIRECTION OF FEED
USER DIRECTION OF FEED
SOP-8P
DFN4x4-8
Copyright ANPEC Electronics Corp.
Rev. A.7 - Mar., 2011
APW7145
www.anpec.com.tw22
Classification Profile
Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
Average ramp-up rate
(Tsmax to TP) 3 °C/second max. 3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL) 183 °C
60-150 seconds 217 °C
60-150 seconds
Peak package body Temperature
(Tp)* See Classification Temp in table 1 See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc) 20** seconds 30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max. 6 °C/second max.
Time 25°C to peak temperature 6 minutes max. 8 minutes max.
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Classification Reflow Profiles
Copyright ANPEC Electronics Corp.
Rev. A.7 - Mar., 2011
APW7145
www.anpec.com.tw23
Classification Reflow Profiles (Cont.)
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness Volume mm3
<350 Volume mm3
≥350
<2.5 mm 235 °C 220 °C
≥2.5 mm 220 °C 220 °C
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness Volume mm3
<350 Volume mm3
350-2000 Volume mm3
>2000
<1.6 mm 260 °C 260 °C 260 °C
1.6 mm – 2.5 mm 260 °C 250 °C 245 °C
≥2.5 mm 250 °C 245 °C 245 °C
Test item Method Description
SOLDERABILITY JESD-22, B102 5 Sec, 245°C
HOLT JESD-22, A108 1000 Hrs, Bias @ Tj=125°C
PCT JESD-22, A102 168 Hrs, 100%RH, 2atm, 121°C
TCT JESD-22, A104 500 Cycles, -65°C~150°C
HBM MIL-STD-883-3015.7 VHBM≧2KV
MM JESD-22, A115 VMM≧200V
Latch-Up JESD 78 10ms, 1tr≧100mA
Reliability Test Program
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
