A SILAS FEATURES Z84C00 Z80 CPU with Z84C30 CTC, 284C4x SIO, CGC, Watch Dog Timer{WDT). In addition, Z84C15 and Z84015 have Z84C20 PIO. High speed operation 6, 10 MHz @ 16 MHz operation for Z84C 15 only. @ Low power consumption in four operation modes: 41 MA Typ. (Run mode) 6 mA Typ. (idle1 mode) 60 pA Typ. (Idie2 mode) 0.5 pA Typ. (Stop mode) Wide operational voltage range (5V 10%). m TTL/CMOS compatible. m 284013 features: - Z84C00 Z80 CPU - On-chip two channel SIO (Z80 SiO). - On-chip four channel Counter Timer Controller (Z80 CTC). - Built-in Clock Generator Controlier (CGC). PRODUCT SPECIFICATION 284013/015 284013/Z84015 IPC INTELLIGENT PERIPHERAL CONTROLLER - Built-in Watch Dog Timer (WDT). - Noise filter to CLK/TRG inputs of the CTC. - 84-pin PLCC package. 284015 features: m - All 284013 features, plus on-chip two 8-bit ports (Z80 PIQ) and 100-pin QFP package. 284C 13/Z84C 15 enhancements to 284013/Z84015: m - Power-on reset. - Addition of two chip select pins. - 32-bit CRC for Channel A of SIO. - Wait state generator. - Simplified EV mode selection. - Schmitt-trigger inputs to transmit and receive clocks of the SIO. - Crystal divide-by-one mode. - 100-pin VOFP (Z284C15 only) GENERAL DESCRIPTION The Intelligent Peripheral Controller (IPC) is a series of highly superintegrated devices with four versions. The Z84C13 and the 784C15 are upward compatible versions of the 784013 and the 2784015. The 284015 is a CMOS 8-bit microprocessor integrated with the CTC, SIO, CGC, WDT and the PlOintoa single 100-pin Quad Flat Pack(QFP) package. The 284013 is the 784015 without PIO, and is housed in a 84-pin PLCC package. The Z84C13 is the. 284013 with enhancements and the Z84C 15 is the 284015 with enhancements. These high-end superintegrated in- telligent peripheral controllers are targeted for a broad range of applications ranging from error correcting mo- dems to enhancement/cost reductions of existing hard- ware using Z80-based discrete peripherals. Figures 1 and 2 show the difference between the Z84013/015 and the 2840 13/Z84C 15. Hereinafter, use the word IPC on the description covering all versions (784C 13/284C 15 and Z84013/Z84015). Use Z84C13/C15 on the description that applies only to the Z84C 13. and Z84C 15, and use Z84013/015 on the descrip- tion that applies only to the Z84013 and 284015. 293284013 284015 cpu CGC CPU CGC CcTc cic PIO Figure 1. Z84013/015 Version 284013 284015 CPU CGC CPU CGC SiO. =WDT SIO. WDT CTC cTc PIO Enhancement Enhancement Figure 2. Z84C13/C15 Version ser Ttetrte >> > > > o- NN Oo = NOOO OOOO BUSREQ MAT 8 2 9 BaeaaRESS DO OOO oo 75 284013 284013 84-PIN PLCC (Top View) 74 x UUUUUUUUUUUUUUU UU UU ISYNCA (18 RXDA (J IRXCA (J ge Mxca XDA CJ MTRA CI IRTSA (CI CTSA MCDA CI "iso Cs vec Cla *1cs1 MCOB CI * ICT for the Z840 = o IRTSB (J TRB CI oB C4 mea C4 wRXCB ictsB Co Axos isYNCR Cy Figure 3. Z84013/Z84C13 Pin-out Assignments . XTALI vss MWOTOUT fel NC NM ATRF MIPRDYB Note: Power connections follow Conventional d 11s below Connection | Circuit | Device Power Voc | Yoo Ground GND | VogCLK/TRG2 CLK/TRGI CLK/TRGO D7 D3 D2 O1 vec A1S Ai4 A13 Al2 Alt A10 CLI/TRG3 ZC/TO3 Zc/TO2 2C/T01 /RFSH ZC/TOO MWDTOUT tE1 /BUSREQ 5 zod J3us aESSnEE se 100-Pin VQFP Z84C15 (Only) BRDY /BSTB PB? PB6 EX@ePgsgohs bare = 29 a Z84C15 Pin-out Assignments PAG PAS PA4 PB4 PBS PB2 PBI PA3 PA2 PAt PBO MWIRDYB ISYNCB RXDB IRXCB (TXCB TXDB /OTRB ARTSB iCTSB fOCDE KSI voc CSO /DCDA ICTSA ARTSA /OTRA TXDA ITXCA IRXCA RXDA ISYNCA MUIRDYVA PAO 295Aft Al2 A13 At4 Ais vec 00 01 02 D3 D4 DS D6 07 CLI/TRGO @eee2z a CLKTRGI M CLITRG2 A CLK/TRG3 R Zeros Al zerroe ~ zorro1 IRFSH Zerroo Mi MDTOUT (RESET te! RUSREQ Ico puss ATRE WR 284015 oureur RD 284015 EV NORQ 100-PIN QFP XTAL2 VSS XTALI MALT Mi ANT BRDY ARDY /BSTB /ASTB PB? PA? PRG PAG PBS PAS PB4 PM PB3 PA3 PB2 PA2 PBI PAI PBO PAD MIRDYB MIIRDYA /SYNCB the 284015 * ICT for Figure 4. 284015/Z84C15 Pin-out Assignments PIN DEFINITIONS The pin assignment for each device is shown in Figures 3_ that applies to both 784C 13/Z84013 or Z84C15/7B4015. and 4. Following is the description on each pin. For the Otherwise, C13 for 784C13, C15 for 284C15, 013 for description and the pin number, if stated as x13 or x15, 284013 and 015 for Z84015.CPU SIGNALS Pin Name AO-A15 Pin Number 16-1(x13), 6-1, 100-91(x15) Input/Output, 3-State vO Function 16-bit address bus. Specifies /O and memory addresses to be accessed. During the refresh period, addresses for refreshing are output. The bus is an input when the external master is accessing the on-chip peripherals. DO-D7 83-76(x13), 89-82(x15) VO 8-bit bidirectional data bus. When the on-chip CPU is accessing on-chip peripherals, these lines are set to output and hold the data to/from on-chip peripherals. : /RD 30(x13), 14(x15) 1/0 Read signal. CPU read signal for accepting data from memory or I/O devices. When an external master is accessing the on-chip peripherals, it is an input signal. 20(x13), 13(x15) 1/0 Write Signal. This signal is output when data, to be stored in a specified memory or peripheral LSI, is on the MPU data bus. When an external master is accessing the on-chip peripherals, it is an input signal. /MREQ 23(x13), 17(x15) /O, 3-State Memory request signal. When an effective ad- dress for memory access is on the address bus, O is output. When an external master is accessing the on-chip peripherals, it is an tri- state signal. AORQ 21(x13), 15(x15) VO I/O request signal. When addresses for I/O are on the lower 8 bits (A7-AO) of the addres$s bus in the I/O operation, 0 is output. In addition, the {ORQ signal is output with the (M1 signal at the time of interrupt acknowledge cycle to inform peripheral LSI of the state of the interrupt response vector is when put on the data bus. When an external master is accessing the on- chip peripherals, itis an input signal. | iM1 17(x13), 8(x15) VO Machine cycle 1. AMREQ and 0 are putput together in the operation code fetch cydle. /M1 is output for every opcode fetch when a two byte opcode is executed. in the maskable interrupt acknowledge cycle, this signal is output together with /AORQ. !tis 3-stated in EV mode. 297CPU SIGNALS (Continued) Pin Name Pin Number Input/Output, 3-State Function /RFSH 26(x13), 7(x15) Out, 3-State The refresh signal. When the dynamic memory refresh address is on the low order byte of the - address bus, /RFSH is active along with /MREQ signal. This pin is 3-stated in EV mode. ANT 25(X13), 19(x15) Open drain Maskable interrupt request signal. Interrupt is generated by peripheral LSI. This signal is accepted if the interrupt enable Flip-Flop (IFF) is set to 1. The /INT signal of on-chip peripherals is internally wired - OR without pull-up resistors and requires external pull-up. Also, interrupts from on-chip peripherals go out from this pin. JNM} 56(x13), 63(x15) In : Non-maskable interrupt request signal. This interrupt request has a higher priority than the maskable interrupt request and does not rely upon the state of the interrupt enable Flip-Flop (IFF). [HALT 31(x13), 81(x15) Out, 3-State Halt signal. Indicates that the CPU has executed a HALT instruction. This signal is 3-stated in EV mode. : /BUSREQ 18(x13), 10(x15) In BUS request signal. /BUSREQ requests place- ment of the address bus, data bus, /MREQ, AORQ, /RD and /WR signals into the high impedance state. (BUSREQ is normally wired- OR and a pull-up resistor is externally connected. /BUSACK 2x13), 12(x15) Out (013/015), Bus Acknowledge signal. In response to Out/3-State /BUSREQ signal, /BUSACK informs a peripheral (C13/C 15) LSI that the address bus, data bus, /MREQ, AORQ, /RD and (WR signals have been placed in the high impedance state. Note: For the Z84013/015 the /BUSACK signal will not be 3-stated during EV mode. For the Z84C.13/C 15 the /BUSACK will be 3-stated during EV mode. WAIT 19x13), 11(x15) in(013/015), Wait signal. (WAIT informs the CPU that VO(C13/C 15) specified memory or peripheral is not reacly for data transfer. As long as WAIT signal is active, MPU is continuously kept in the wait state. Note: For the Z84C 13/C 15, the WAIT pin becomes an output to bring out on-chip wait state generator during the EV mode. 298CPU SIGNALS (Continued) Pin Name Pin Number Input/Output, 3-State Function A7RF 55(x13), 70(x15) Out 1-bit auxiliary address bus. Output is the same as bit-7 (A7) of the address bus. However, during a refresh cycle, this pin outputs the address which is the most significant bit of the 8-bit refresh address signal linked to the low order 7 bits of the address bus. CTC SIGNALS Pin Name Pin Number input/Output, 3-State Function CLK/TRGO- = 75-72(x13), 81-78(x15) In External clock/trigger input. These four CLK/ CLK/TRG3 TRG pins correspond to four Counter/Timer Channels. In the counter mode, each active edge will cause the downcounter to decrement by one. In timer mode, an active edge wii start the timer. It is program selectable whether the active edge is rising or falling. ZC/TOO - 68-71(x13), 74-77(x15) Out Zero count/timer out signal. in either timer or ZC/TO3 counter mode, pulses are output when the down-counter has reached zero. SIO SIGNALS Pin Name Pin Number Input/Output, 3-State Function IWARDYA, 32,54(x13), 30,52(x15) Out Wait/Ready signal A and Wait/Ready signal IWI/RDYB B. Used as /WAIT or /READY depending upon ! SIO programming. When programmed ag WAIT they go active at 0, alerting the CPU that addressed memory or I/O devices are not ready by requesting the CPU to wait. When programmed as /READY, they are active.at 0 which determines when a peripheral device associated with a DMA port is for read/write data. ISYNCA, 33,53(x13), 31,51(x15) 1/0 Synchronous signals.In asynchronous /SYNCB receive mode, they act as /CTS and /CDC. In external sync mode, these signals act as inputs. In internal sync mode, they act as outputs. RxDA, RxDB -3.4,52(x13), 32,50(x15) In Serial receive data signal.SIO SIGNALS (Continued) Pin Name Pin Number Input/Output, 3-State Function IRxCA, /RxXCB 35,51(x13), 33,49(x15) In Receive clock signal. In the asynchronous mode, the receive clocks can be 1, 16, 32, or 64 times the data transfer rate. ITxCA, /TxCB 36,50(x13), 34,48(x15) In Transmitter clock signal. In the asynchronous mode, the transmitter clocks can be 1, 16, 32, or 64 times the data transfer rate. TXDA, TxDB 37,49(x13), 35,47(x15) Out Serial transmit data signal. /OTRA, /OTRB 38,48(x13), 36.46(x15) Out Data terminal ready signal. When ready, these signals go active to enable the terminal transmitter. When not ready they go inactive to disable the transfer from the terminal. IRTSA, /RTSB 39,47(x13), 37,45(x15) Out Request to send signal. "0" when transmitting serial data. They are active when enabling their receivers to transmit data. ICTSA, ICTSB 40,46(x13), 38,44(x15) In Clear to send signal. When O", after trangmit- ting these signals the modem is ready to receive serial data. When ready, these signats go active fo enable terminal transmitter. When not ready, these signals go inactive to disable transfer from the terminal. /DCDA, 41 ,45(x13), 39,43(x15) In Data carrier detect signal. When 0, serial /OCDB data can be received. These signals are active to enable receivers to transmit. SYSTEM CONTROL SIGNALS Pin Name Pin Number Input/Output, 3-State Function IEl 60(x13), 72(x15) in Interrupt enable input signal. IEI is used with the IEO to form a priority daisy chain when there is more than one interrupt-driven peripheral. IEO 59(x13), 71(x15) Out The interrupt enabie output signal. in the daisy chain interrupt control, EO controls the interrupt of external peripherals. [EO is active when IEI is 1 and the CPU is not servicing an interrupt from the on-chip peripherals. /CSO 42(C 13), 40(C 15) Out Chip Select 0. Used to access external (C13/C 15 only) memory or I/O devices. This pin has been assigned to ICT pin on Z84013/015. This signal is decoded only from A15-A12 without control signals. Refer to Functional Description on-chip select signals for further explanation.SYSTEM CONTROL SIGNALS (Continued) Pin Name Pin Number Input/Output, 3-State Function iCSs1 40(x13), 42(x15) Out Chip Select 1. Used to access external (C13/C 15 only) memory or I/O devices. This pin has been assigned to ICT pin on 284013/015. This signal is decoded only from A15-A12 without control signais. Refer to Functional Description on-chip select signals for further explanation. MWOTOUT 61(x13), 73(x15) Out(013/015), Watch Dog Timer Output signal. Output pulse Open Drain(C13/C15) width depends on the externatly connected pin. /RESET 28(x13), 9(x15) Input(013/015), Reset signal. /RESET signal is used for 1/0 (Open Drain) initializing MPU and other devices in the system. (C13/C 15) Also used to return from the steady state in the STOP or IDLE modes. Note: For the 784013/Z84015 the /RESET must be kept in active state for a period of at least three system clock cycies. Note: For the Z84C 13/Z84C 15, during the power-up sequence, the (RESET becomes an Open drain output and the Z84C 13/C 15 will drive this pinto 0" for 25 to 75 msec after the power supply passes through approx. 2.2V and then reverts to input. If it receives the (RESET signal after! power-on sequence, it will drive (RESET pin for 16-processor clock cycles depending on the status of Reset Output Disable bit in Misc Control Register. If this Reset output is disabled, it must be kept in active state for a period of at least three system clock cycles. Note, that if using Z84C 13/C15 in a 284013 015 socket, modification may be required on the reset circuit since this pin is pure input pin on the Z84013/015. Also, the (RESET pin dotsn't have internal pull-up resistors and therefore requires extemal pull-ups. For more details on the device, please refer to Functional Description." XTAL1 63(x13), 65(x15) In Crystal oscillator connecting terminal. A parallel resonant crystal is recommended. If externa! clock source is used as an input to the OGC unit, supply clock goes into this terminal. If external clock is supply to CLKIN pin (without CGC unit), this terminal must be connected to O" or 1. XTAL2 63(x13), 66(x15) Out Crystal oscillator connecting terminal. CLKIN 67(x13), 69(x15) _(n Single-phase System Clock Input. CLKOUT 66(x13), 68(x15) Out Single-phase clock output from on-chip Clock : Generator/Controller. EV 58(x13), 67(x15) In Evaluator signal. When 1 is applied to this pin, IPC is put in Evaluation mode. Note: For the Z84013/015, together with /BUSREQ, the EV signal puts the IPC into the evaluation mode. When this signal becomes active, |the status of (M1, /HALT and /RFSH change to input. When using Z84013/015 as an evaluator chip, the CPU is electrically disconnected after one machine cycle is executed with the EV signal "1" and the (BUSREQ signal "0". It follows the instructions from the other CPU (of ICE). Upon receiving /(BUSREQ; A15- AO, /(MREQ, AORQ, /RD and WR are changed to input and D7-D0 changes its direction. (BUSACK is NOT 3-stated so it should be discomected by an extemally connected circuit. For details, please refer to Functional Description on EV mode. 301SYSTEM CONTROL SIGNALS (Continued) Note: For the Z84C 13/C 15, to access on-chi IRD and (WR are changed to input; D7-D0 c to 1. Also, /BUSACK is 3-stated. For details, please refer to hanges its direction; p resources from the CPU (e.g., ICE CPU), the CPU is electrically disconnected; A15-A0, /MREQ, /IORQ, M1, {HALT and /RFSH are put into the high impedance state when the EV pin is set Functional Description on EV mode. Pin Name Pin Number Input/Output, 3-State Function ICT 42,44(013), 40,42(015), Out Test pins. Used in the open state. Not with C13/C15 NC 24,27,57,65(x13), Not connected. Not with x15 VCC 43,84(x13), 41.90(x15) Power Supply +5 Volts VSS 22, 62(x13), 16,64(x15) Power Supply 0 Voits PIO SIGNALS (for the Z84x15 only) Pin Name Pin Number Input/Output, 3-State Function /ASTB 21(x15) In Port A strobe pulse from a peripheral device. The signal is used as the handshake between Port A and external circuits. The meaning of this signal depends on the mode of operation selected for Port A (see PIO Basic Timing). /BSTB 61(x15) In Port B strobe pulse from a peripheral device. This signalis used as the handshake between Port B and external circuits. The meaning of this signal is the same as /ASTB, except when Port A is in mode 2 (see PIO Basic Timing). ARDY 20(x15) Out Register A ready signal. Used as the handshake between Port A and external circuits. Themeaning of this signal depends on the mode of operation selected for Port A (see PIO Basic Timing). BRDY 62(x15) Out Register B ready signal. Used as the handshake between PortB and external circuits. The meaning of this signal is the same as ARDY except when Port A is in mode 2 (see PIO Basic Timing). PA7-PAO 22-29(x15) V/O, 3-State Port A data signals. Used for data transfer between Port A and external circuits. PB7-PBO 53-60(x15) 1/O, 3-State Port B data signals. Used for transfer between Port B and external circuits. 302The following pins have different functions between 013/015 and C13/C15 Pin Name Pin # X13 Pin # X15 Function /RESET 28 9 Functionality is different. WAIT 19 15 Functionality. is different. EV 58 67 Functionality is different. MWDTOUT 61 73 Push-pull output on Z84013/015, Open drain on 284 C13/C15 ICT 40, 42 42, 40 (Test pin) on Z84013/015; /CSO and /CS1 on Z84C 13/15. TxCA, TxCB, 35, 36, 50,51 33, 34, 48,49 On Z84C13/15; these signals have Schmitt-triggered inputs. RxCA and RxCB /BUSACK 29 12 In EV mode, 3-stated on Z84C 13/15; remains active on 284013/015. FUNCTIONAL DESCRIPTION Figure 5(a) shows the functional block diagram of the 284013/015 and Figure 5(b) shows the functional block diagram of the Z84C 13/C 15. As described earlier, the only difference between the Z84x13 and the 784x15 is the PIO not being available on the 784x13. Functionalfy, the on-chip SIO, PIO (not available on Z84x 13), CTC, and the Z80 CPU are the same as the discrete devices. Therefore, for detailed description of each indi- vidual unit, refer to the Product Specification/Technical Manual of each discrete product. The following subsections describe each individual func- tional unit of the IPC. 2Z84C00/01 Logic Unit The CPU provides all the capabilities and pins of the Zilog 280 CPU. This allows 100% software compatibility with existing Z80 software. in addition, it has the pin called A7RF to extend ORAM refresh address to 8-bits. Refer to Z84C01 Z80 CPU with CGC Product Specification. 284C20 Parallel Input/Output Logic Unit (284x15 Only) This logic unit provides both TTL- and CMOS- compatible interfaces between peripheral devices and a CPU through the use of two &-bit parallel ports (Figure 6). The CPU configures the togic to interface toa wide range of periph- eral devices with no external logic. Typical devices that are compatible with this interface are keyboards, printers, and EPROM/PAL programmers. The parallel ports (designated Port A and Port B) are byte wide and completely compatible with the Z84C20 PIO. These two ports have several modes of operation; input, output, bi-directional, or bit control mode. Each port has two handshake signals (RDY and /STB) which are used to control data transfers. The RDY (ready) indicates that the portis ready for data transfer while /STB (strobe) is aninput to the port that indicates when data transfer has occurred. Each of the ports can be programmed to interrupt the CPU upon the occurrence of specified status conditions, and generate unique interrupt vectors when the CPU responds (for more information on the operation of this portion of the logic, please refer to the Z84C20 PIO Product Specifica- tion and Technical Manual). Z84C30 Counter/Timer Logic Unit This logic unit provides the user with four individual 8-bit Counter/Timer Channels that are compatible with the 2Z84C30 CTC (Figure 7). The Counter/Timers can be pro- grammed by the CPU for a broad range of counting and timing applications. Typical applications include event counting, interrupt and interval counting, and serial baud rate clock generation. Each of the Counter/Timer Channels, designated Chan- nels 0-3, have an 8-bit prescaler (when used in timer mode) and its own 8-bit counter to provide a wide'range of count resolution. Each of the channels have their own Clock/Trigger input to quantify the counting process and an output to indicate zero crossing/limeout conditions. With only one interrupt vector programmed into the logic unit, each channel can generate a unique interrupt vector in response to the interrupt acknowledge cycle. 303RESET zcrTo, -ZC10 CLK/TRG, -CLI/TRG PA PB XTALI XTAL2 (M1 ARALTCLKOUT CLKIN EV BUSREQ /BUSACK Controller ac wi a Q oO wi Q D_ AMI (RESET 1E1 WR RSH 7 1o WATCH DOG TIMER AND REGISTERS o- CLK #F0 DECODER DECODER MM1-/RESET MS1,MS2 BO Ag Ag Figure 5(a). Block Diagram for 84013/015 IPCXTALt XTAL2 Mi MALT CUXOUT CLKIN EV /BUSREQ /BUSACK ff 4 {if CLK Power wet MAT MALT jp MREC n Ms2 Mt Mi RESET NMI Mt a o [convaor mn CLK RESET ANT Conta J" CPU mRESET + by i MRESET INT Nt WAIT 2-0 STATE it a7 GENERATOR 2GMTO, -20/10 4 CLK 4y 45 ip oO WA MESH } sit IRFSH CLXTAG, -CLTRG 0% = WR . 3 O = IPD cTc m7 - FO *RESET baal .---- (CTSA iB 4 ---. CDA J | MATSA IEO M1 +4 [( pall os w qe CuK D,- D (RD AORQ be WIRDYA 2 Q JRESET ae /SYNCA cs 9 1 RXDA 144] eH aT IRXCA - H]TXCA = Mi _ a 18 sio TxDA = 1E0 La TXDB bd ee WE ++_| A1XcB. a +] axce 1a CLK OL! -" RXDB iASTB {co NT 9 un Jam /SYNCB -e- /WIRDYE ARDY <4 ti }e1 iA 0-0. PAG: PA, < 077 < | _ hen Lr iAtsa Pa. PB PIS a ATSB o 7 (zucis 1 0C0B ONLY) ot J = ~ BRODY < p,- 0, Mt RESET fet AWA URESH mwotour STB cLK Hy F c ATE ce beter WATCH DOG - ui wi mn TIMER | ics0 cw fe HE Q | _ AND REGISTERS |e st a & SEE it 1EO BAO a SEF MI-RESET MS1MS2 A 8 A As Figure 5(b). Block Diagram for 84C13/C15 IPC 305Internal Control Data Logic N Port of Control A AN vo } Handshake L$ 7 Bus Peripheral BUS er ral { Data Vo K Intemal Bus Interface 7 8 Control Data Port ij or Control B \/Z Y vo } Handshake Interrupt _ Control ie {interrupt Control Lines Figure 6. PIO Block Diagram N Internal Control Logic a N\ cru Data t ANT 7 Bus K Hianal a interrupt iE <4 rae Control il }t IEO Counter/ [2 zoo oN Timer V| Logic K 4 cLKTRG JRESET Figure 7. CTC Block Diagram Z84C4x Serial VO Logic Unit This logic unit provides the user with two separate multi- protocol serial i/O channels that are completely compat- ible with the 284C4x SIO. Their basic functions as serial-to- parallel and parallel-to-serial converters can be pro- grammed by a CPU for a broad range of serial communi- cations applications. Each channel, designated Channel A and Channel B, is capable of supporting all common asynchronous and synchronous protocols (Monosync, Bisync, and SDLC/HDLC, byte or bit oriented - Figure 8). 284C13/C15 Only. As an enhancement tothe 784013/015, the Z84C13/C15 can handle a 32-bit CRC on Channel A and Schmitt-trigger inputs on the /TxC and /RxC pins of both channels. 306f--? | Serial Channel A Channel [*- J Data Control A {a} Channel and Status qf Clocks Registers aie- /SYNC rt = WAIT/READY < i Channel A Mod Conta K 7 Control or other and |___ Logic Status control Data _ Channel B ) bus LN] Control fe | Modem vO 2 and or other Control e( | staws [OS } contol - | Serial interrupt, ~4},_ interrupt Channel p* J Data Control .p] Control LK B q___.)_ Channel Lines 1g Logic / jat J Clocks | ew /SYNC WIRDY Channel B Control and Status Registers Figure 8. SIO Block Diagram Watch Dog Timer (WDT) Logic Unit This logic unit has been superintegrated into the IPC. It detects an operation error, caused by the program run- away, and returns to normal operation. Figure 9, shows the block diagram of the WDT. Upon Power-On Reset, this unit is enabled. if WDT is not required, but WWDTOUT is con- nected to /RESET or any other circuit, it has to be disabled. During the power-down mode of operation (either DLE1/ 2 or Stop), the Watch Dog Timer is halted. WDT Output (WDTOUT pin). When the WDT is used, the "0" level signal is output from the WDTOUT pin after a duration of time specified in the WDTP or in the WOTMR. The output pulse width is one of the following, depending on the WWDTOUT pin connection. @ The /WDTOUT is connected to the (RESET pin: The 0 level is pulsed for 5TcC (System clock cycles). = The WDTOUT is connected to a pin other than the /RESET pin: The 0 tevet is kept until the Watch Dog timer is cleared by software, or reset by /RESET pin. CGC Logic Unit. The IPC has CGC (Clock Generator/ Controller) unit. This unit is identical to the one with the 284C01 and the Z84C50, and supports power-down modes of operation. The output from this unit is on the pin called CLKOUT, and is not connected to the system clock inter- nally. The CLKIN pin is the system clock input. The user can connect CLKOUT to CLKIN to utilize this CGC unit, or supply external clock from CLKIN pin. The CGC unit allows crystal input (XTAL1, XTAL2) or External Clock input on the XTAL1 pin. It has clock divide- by-two circuits and generates a half-speed clock to the input. 2Z84C13/C15. The power-down modes of the IPC vary depending upon whether the system clock is fed from the CGC unit (tie CLKOUT to CLKIN) or the external clock source on the CLKIN pin. They also have divide-by-one Mode. If the clock is supplied by this CGC unit, all of the modes in halt state are available. When external clock is provided on the CLKIN pin, XTAL1 is not left open (tied to O" or 1") to avoid meta-stable conditions to minimize power consumption. 307MWDTOUT #FO gs WDTP Enable (Bits 6 and 5) __pu! eT ETAT AA o 22-Stage Binary Counter Q (WDTCLK) _*"|_ for Watch Dog Timer FF R $ RESET RESET RESET > | eH Ware -__~+- WDTE 28 JL B1H WRITE Watch Dog Timer Command Watch DogTimer Register #F1 (WDTCR) Master Register #FO (WDTMR) ft ft Internal Data Bus Figure 9. Block Diagram of Watch Dog Timer 284013/015 Only. If the system clock is provided on the Z84C13/C15. Clock output is the same, or half, of the CLKIN pin, none of the power-down mode (exceptRUN external frequency. mode) is supported. 284C13/C15 Only. If the system clock is provided on the Z84X13/X15 CLKIN pin, only the IDLE2 mode is applicable. In this mode, if the HALT instruction is executed, internal clock to the CTC is kept on Continue, but the clock to the other components (CPU, PIO, SIO and Watch Dog Timer) are XTAL1 TL stopped. The divide-by-two circuit of the CGC unit can be Cry = 33pF skipped by programming bit D4 of the WOTMR (see Ol Y Programming section). Upon Power-on Reset, it comes XTAL2 I up in divide by two mode. System Clock Generation V The IPC has a built-in oscillator circuit and the required clock can be easily generated by connecting a crystal to the external terminals (XTAL1, XTAL2). Clock output is the same frequency as half the speed of the crystal fre- Figure 10. Circuit Configuration For Crystal quency. Example of oscillator connections are shown in Figure 10. 308Recommended characteristics of the crystal and the val- ues for the capacitor are as follows (the values will change with crystal frequency). Type of crystal: Fundamental, paraflel type crystal (AT cut is recommended). Frequency tolerance: Application dependent. CL, Load capacitance: Approximately 22pf (acceptable range is 20-30pf). Rs, equivalent-series resistance: < 150 ohms. @ Drive level: 1OmW (for < 10MHz crystal); 5mW (for = 10MHz crystal). = 33pF. Power-On Reset Logic Unit (284C13/C15 Only) The Z84C13/C 15 has the enhanced feature of a Power-on Reset Circuit. During the power-up sequence, the open- drain gate of the on-chip power-on Reset circuit drives /RESET pin to "0" for 25 to 75 msec after the power supply passes through approx. 2.2V. After the termination of the Power-on Reset cycle, the open-drain gate of the on-chip Power-on Reset circuit stops to drive the /RESET pin. It is required to have external pull-up register on the (RESET pin. = C,=C if it receives /RESET input from outside after the power-on sequence and while the Reset Output Disable bit in Misc Control Register is cleared to O", it will drive the ARESET pin for 16-processor clock cycles from the falling edge of the external (RESET input. Otherwise, the /RESET pin must be kept in the active state for a period of at least 3 system clock cycles. If there are power-on reset circuits outside of this device, Grive this pin with OPEN-DRAIN type gates with pull-up resisters because /RESET signal is driven low for the period mentioned above during the Power-on sequence. If the external Power-on Reset circuit has push-pull type drivers and they drive the /RESET pin to 1 during that period, it may cause damage. In particular, when using Z84C13/C 15 in the Z84013/015 socket, modification may be required on the external reset circuit. Wait State Generator Unit (Z84C13/C15 Only) The 284C 13/C 15 has the enhanced feature of a Wait State Generator circuit. Itis capable of generating /WAIT signals tothe CPU internally. The status of the External /WAIT input line is sampled after the insertion of software wait states, except for the wait state's insertion of Interrupt Daisy Chain Wait (for this cycle, insertion of a wait state is not simple). The Wait State Control Register can be prograrnmed to generate multiple Wait states during different CPU cycles listed as follows. Memory Wait and Opcode wait. The Wait State Generator can put 0 to 3 wait states in memory accesses. Addition- ally, one added wait state can be inserted during an /M1 (Opcode fetch) cycle, because /M1 cycles timing require- ment is tighter than memory ReadMtite cycles. It gener- ates wait states to the Memory Access in a specified address range, which is programmed in the Memory Wait Boundary Register. /O Wait. The Wait State generator can put 0, 2, 4 or 6 wait States in I/O accesses. Regardless of the programming of this field, no I/O wait states are inserted fora accesses to on- chip peripherals. Interrupt Vector Wait. During Interrupt acknowledge cycie, the Wait State Generator can insert one wait state after /IORQ goes active, to extend the time between /IORQ fall to vector fetch by CPU. It allows a slow vector response device. interrupt Daisy Chain Wait and RETI sequence extension. During Interrupt acknowledge cycle, the Wait State Gen- erator can insert 0, 2, 4 or 6 wait states between /M1 falling to ORQ falling edge, to extend the time required to settle daisy chain. This allows a longer daisy chain. Also, this field controls the number of wait states inserted during RET! (Return From Interrupt) cycle. If specified to insert 4 or 6 wait states during Interrupt Acknowledge cycle, Wait State Generator also inserts wait states during RETI fetch sequence. This sequence is generated with two op-code fetch cycles (Op-code is EDh followed by 4Dh). It inserts 2or 4 wait states, respectively, if op-code followed by EDh is 4Dh. One wait state if the following op-code is not 4Dh. Chip Select Signals (284C13/C15 Only) . The Z84C13/C15 has an enhanced feature of adding two chip select(/CSO, /CS1) pins. Both signals are originally IC test pins (ICT) on the 284013/015. The boundary value for each Chip Select Signal is 4 bits wide, and compare with A15-A12 of the address. Each Chip Select Signal goes active when: /CSO: (D3-D0 of CSBR) 2 A15-A12 20 /CS1: (D7-D4 of CSBR) 2 A15-A12 > (D3-D0 of CsBR) (Where CSBR is the contents of Chip Select Boundary Register.) There is also a separate /CS enable bit. /CSOis enabled on power-up with a boundary value of F causing /C'SO to go active for all memory accesses. /CS1 is disabled on 309power-up, and boundary address is undefined. These features are controlled via the 1/O control registers located at I/O address EEh and EFh. Note that a glitch may be observed on these pins because address decode logic is decoding only A15-A12, without any control signals. For more detail, please refer to the Programming section. Other functional features (784C13/C15 Only) For more system design flexibility, the Z84C 13/C 15 has the following unique features. These features are controlled by MCR (Misc. Control Register) which is indirectly accessed via the System Control Register Pointer (SCRP, {/O ad- dress EEh), and System Control Data Port (SCDP, I/O address EFh). For more details, please refer to the Pro- gramming" section. = Clock Divide-by-one option = Reset Output Disable = 32-bit CRC Generation/Checking Clock Divide-by-One Option. This feature is programmed through Bit D4 of MCR. Upon Power-On reset, the Clock from on-chip CGC is passed through a divide-by-two circuit. By setting this bit to one, the divide-by-two circuit is bypassed so the clock on the CLKOUT pin is equal to Xtal input. If the clock is applied to the CLKIN pin from external clock source, the status of this bitis ignored. Upon Power-on Reset, it is cleared to 0. For details, please refer to Programming section. Reset Output Disable. This feature is programmed by Bit D3 of MCR. If this bit is cleared to 0, The /RESET pin becomes Open-drain output and is driven to "0" for 16- Clock cycles from the falling edge of RESET input. This feature is for the cases where /RESET is used to get out from the HALT state. If this bit is set to one, the on-chip _ Feset circuit will not drive /RESET pin. 32-bit CRC Generation/Checking. This feature is pro- grammed by Bit D2 of MCR. By setting this bit to one, Channel A of SIO is set to use the 32-bit CRC generator/ checker instead of the original 16-bit CRC generator/ checker in synchronous communication modes. The poly- nomial to be used in this mode is the one for the protocols such as V.42, and is (X32 + X26 + X234 X22 4 X16 4 X12 +X114X10+X84X74X54X44X24X4 1). Upon Power- on Reset, this bit is cleared to 0. Evaluation Mode The IPC has a built evaluation (or development) mode feature which allows the users to utilize standard Z80 development systems conveniently. This mode virtually replaces the on-chip 780 CPU with the external CPU. In this mode, the on-chip CPU is electrically disconnected from internal bus and all 3-state signals (A15-0, D7-0, /MREQ, /IORQ, /RD, WR, /HALT, /M1 and /RESH; for C13/ C15, /BUSREQ as well) are tri-stated, or changed to input. This allows the development system CPU to take over and use the internal I/O registers of the IPC exactly as if the CPU was on-chip. 284013/015 Only. When this signal is active,the /M1, /HALT and /RFSH pins are put in the high-impedance State. In using the Z84013/015 as an evaluator chip, the CPU is electrically disconnected (put in high-impedance State) after one machine cycle is executed with the EV signal being 1" and the /BUSREQ signal being 0. Then, on-chip resources can be accessed from the outside. /BUSACK is disconnected by an externally connected circuit. 284C13/C15 Only. If the EV pinis tied to Vcc on Power-up, the Z84C13/C15 enters into an evaluation mode. In this mode, the internal CPU is immediately disconnected from the internal bus and ail 3-state signals mentioned above are tri-stated, or changed to input. Note that the WAIT pin became the OUTPUT pin in EV mode, and the Wait State Generator generates wait states only as programmed. if the target application board has a separate wait state generator, modification of the target may be required. IBUSACK is 3-stated in this mode. The 284C13/C15 behaves similarly to the situation where in regular operation, the /BUSREQ signal is asserted by an external master causing all 3-state signals to be tri-stated by the 284C13/C15 during T1 of the following machine cycle. The /BUSREQ approach was not used for the evaluation mode to avoid significant external circuitry to work around the time period before the external CPU uses the bus for 284C13/C15 accesses. PROGRAMMING V/O address assignment The IPC s on-chip peripherals {/O addresses are listed in Table 1. They are fully decoded from A7-A0 and have no image. The registers with 784C13/C 15 located at I/O Ad- dress EEh and EFh are the registers to contro! enhanced features to Z84013/015, and not assigned on Z84C013/ O15. 310Table 1. O Control Register Address Address Device Channel! Register 10h CTC Cho Control Register 11h CTC _ Chit Control Register 12h CTC Ch2 Control Register 13h CTC Ch3 Control Register 18h SiO Ch. A Data Register 19h SIO Ch.A Control Register 1Ah SIO Ch. B Data Register 1Bh silo Ch. B Control Register 1Ch PIO Port A Data Register (Not with Z84x13) 1iDh PIO Port A Command Register (Not with 784x13) 1Eh PIO Port B Data Register (Not with Z84x13) 1Fh PIO Port B Command Register (Not with 784x13) FOh Watch-Dog Timer Master Register (WDTMR) Fih Watch-Dog Timer Control Register (WDTCR) F4h Interrupt Priority Register EEh System Control Register Pointer (SCRP) (Not with Z84013/015) EFh System Control Data Port (SCDP) (Not with 784013/015) Through SCRP and SCDP Control Register 00 - Wait State Control : register (WCR) Control Register 01 - Memory Wait state Boundary Register (MWBR) Control Register 02 - Chip Select Boundary Register (CSBR) Control Register 03 - Misc. Control Register (MCR) PIO REGISTERS For more detailed information, please refer to the PIO Technical Manual. These registers are not in the Z84x13. v7 [ve vs Jv [v3 [ve [vi J v0) Interrupt Vector Word : L_ identifies Into The PIO logic unit is designed to work with the 780 CPU in Ue. at interrupt Mode 2. The interrupt word must be programmed Vector if interrupts are used. Bit DO must be a zero (Figure 11). Figure 11. PIO Interrupt Vector Word 311Mode Control Word Selects the port operating mode. This wordis required and is written at any time (Figure 12). PPE TTT eee Controt Word Don't Care Mode Select 0.0 MODE O 0 1 MODE! 10 MODE 2 11 MODES Figure 12. PIO Mode Control Word VO Register Control Word When Mode 3 is selected, the Mode Control Word is followed by the I/O Register Contro! Word. This word configures the I/O register, which defines which port lines are inputs or outputs. A 1 indicates input while a O" indicates output. This word is required when in Mode 3 (Figure 13). vO isis[Te[ef Te] LT pacer 1 Sets Bit to Input Figure 13. /O Register Control! Word Interrupt Control Word In Mode 3 operation, handshake signals are not used. Interrupts are generated as a logic function of the input signal levels. The Interrupt Control Word sets the Jogic conditions and the logic levels required for generating an interrupt. Two logic conditions or functions are available: AND (if all input bits change to the active level, an interrupt is triggered), OR (if any one of the input bits change to the active logic level, an interrupt is triggered). The user can program which input bits are to be considered as part of 312 this logic function. Bit D6 sets the logic function, bit 5 sets the logic level, and bit D4 specifies a mask control word to follow (Figure 14). MSK 07 0o ey el Pet TT] Kdentifies Interrupt Control Word 1 = Mask Follows [1] 1 = Active High 1 = And Function Ire 1 = Interrupt Function Enable [2] Note: [?] Regardless of the operating mode, setting Bit D4 = 1 causes any pending interrupts to be cleared. [2] The port interrupt is not enabled until the interrupt function enable is followed by an active AA1. Figure 14. Interrupt Control Word Mask Control Word This word sets the mask control register, thus allowing any unused bits to be masked off. If any bits are to be masked, then bit D4 of the interrupt Control Word is set. When bit D4 of the interrupt Control Word is set, then the next word programmed is the Mask Control Word. To mask an input bit, the corresponding Mask Control Word bit ig a 1" (Figure 15). }o7 Jos [05 [04 [oe [oe fox Poo] | MBO-MB7 Mask Bits. A Bit is Monitored for an Interrupt if it s Defined as an Input and the Mask Bit is Set to 0. Figure 15. Mask Control Word interrupt Disable Word This word can be used to enable or disable a port's interrupts without changing the rest of the port's interrupt conditions (Figure 16).PrP peTeT TT scree Disable Word Don't Care 07 =01 pt Disable D7 = 4 Interrupt Enable Figure 16. Interrupt Disable Word CTC CONTROL REGISTERS For more detailed information, refer to the CTC Technical Manual. Channel Control Word This word sets the operating modes and parameters as described below. Bit DO is a 1 to indicate that this is a Control Word (Figure 17). 97 ] 06] 0s |o4 D9} 02 Jos foo] CLIK/TRG Edge Selection 0 Selects Falling Edge 1 Selects Rising Edge Prescaler Value * 1 = Value of 256 0 = Value of 16 Mode 0 Selects Timer Mode 1 Selects Counter Mode Inter 1 Enables Interrupt Disables Interrupt * Timer Mode Only Figure 17. CTC Channel Contro! Word Bit D7. interrupt Enable. This bit enables the interrupt iogic so that an internal INT can be generated at zero count. Interrupts are programmed in either mode and may be enabled or disabled at any time. Bit D6. Mode Bit. This bit selects either Timer Mode or Counter Mode. Bit D5. Prescalor Factor. This bit setects the prescalor factor for use in the timer mode. Either divide-by-16 or divide-by-256 is available. Bit D4. Clock/Trigger Edge Selector. This bit selects the active edge of the CLK/TRG input pulses. Bit D3. Timer Trigger. This bit selects the trigger mode for timer operation. Either automatic or external triggermay be selected. Bit D2. Time Constant. This bit indicates that the next word programmed is time constant data for the downcounter. Bit D1. Software Reset. Writing 1 to this bit indicates a software reset operation, which stops counting activities until another time constant word is written. Time Constant Word Before a channel starts counting, it must receive a time constant word. The time constant value is anywhere be- tween 1 and 256, with 0 being accepted as a countof 256 (Figure 18). p76] 05 ]o] 09 [2] os [oo = Tc2 TCe3 TC4 TCS TC6 Tc? Figure 18. CTC Time Constant Word Interrupt Vector Word If one or more of the CTC channels have interrupt enabled, then the Interrupt Vector Word must be programmed. Only the five most significant bits of this word are programmed, and bit DO must be 0. Bits D2-D1 are autonvatically modified by the CTC channels when it responds with an interrupt vector (Figure 19). 313[or Jos] 05] 54 [os] o2fos [oo] L_ = interrupt Vector Word 1 = Control Word weee Channel identifier {Automatically inserted by CTC) 0 0 Channel 0 0 1=Channel 1 1 O=Channel 2 1 1=Channei 3 Supplied By User Figure 19. CTC Interrupt Vector Word SiO REGISTERS For more detailed information, refer to the SIO Technical Manual. . . Read Registers. The SIO channel B contains three read registers while channel A contains only two that are read to obtain status information. To read the contents ofa register (rather than RRO), the program must first write a pointer to WRO in exactly the same manner as a write operation. The next I/O read cycle will place the contents of the selected read registers onto the data bus (Figure 20a, b, c). Read Register 0 [07] 96] os [o]o2 2] 01 Poo] | L_ Rx Character Available INT Pending (Ch. A Only) Tx Buffer Empty pcb Sync/Hunt cts * Tx Underrun/EOM * Used With "Exteral/Status Interrupt" Modes Figure 20a. SIO Read Register 0 L_ All Sent 1Fled Bit 1 Fleld Bitin in Previous Second Previous Byte Byte 0 o 3 0 0 4 o 0 5 * 1 o 6 1 0 7 1 0 8 1 1 8 0 2 8 Parity Error Rx Overrun Error nrc CRC/Framing Error End of Frame (SDLC) e Residue data for eight Fix bits/character programmed t Used with special receive condition mode Figure 20b. SIO Read Register 1 Read Register 2 (Channel B Only) or | ps} os [os [oe [oe ox Joo iL, v2t < V3 Interrupt V4 Vector V5 v6 V7 t Variable if "Status Affects Vector is programmed Figure 20c. SIO Read Register 2 Write Registers. The SIO Channel B contains eight write registers while Channel A contains only seven that are programmed to configure the operating mode character- istics of each channel. With the exception of WRO, pro- gramming the write registers is a two step operation. The firstoperation is a pointer written to WRO which points to the selected register. The second operation is the actual control word thatis written into the register to configure the S!O channel (Figure 21). 314Wrhe Register 0 Write Register t oz} os | 04 [os] v2 f+ [oo }o7 ] 6] 0s [04] 02] 02] foo] | | | L_ EXT INT Enable 0 0 O Register 0d 0 1 Register 1 Tx INT Enable 0 1 @ Register 2 Oo 1 14 Register 3 Status Affects Vector 1 0 O Register 4 (Ch. B only) 1 0 1 Registers 1 1 0 Register 6 0 0 Rx INT Disable 1 1 1 Register 7 0 1 Rx INT On First Character 1 0 INT On Ai Rx Characters (Parity Affects Vector) 0 0 O Nu Code 161 ve On Ali Rx Characters (Parity Does Not Affect 0 1 Send Abort (SDLC) ) 0 1 O Reset EXT/STATUS Interrupts 0 1 1 Channel Reset MaliReady on R/T 1 0 Enable INT on Next Rx Character 1 1 Reset TxINT Pending MaitReady Function 1 1 0 Error Reset Naltr Enable 1 1. 1 Retum from INT (Ch. A Only) jeady En: * Or on special condition 0 Null Code 0 1 Reset Rx CRC Checker 1 0 Reset Tx CRC Generator 1 1 Reset Tx Underrun/EOM Latch Write Register 3 Pr [oe oes] os] =] Joo] Write Register 2 (Channel B Cnt | = { Rx Enable Jo7 | 0s] 5 [o+} 02 v2 [0+ [oo] Syne Character Load Inhibit | Address Search Mode (SDLC) Rx CRC Enable Enter Hunt Phase Interrupt Auto & Vector S&SEESRE ESS =-=o0 Oo a g Figure 21. SIO Write Registers 315| L_ Parity Enable Parity Everv/Odd 0 0 Sync Modes Enable 1 1 Stop Bit/Character 1 0 1 1/2 Stop Bits/Character 1 1+ 2 Stop Bits/Character 8 Bi Sync Character 16 Bit Sync Character SDLC Mode (01111110 Flag) External Sync Mode ~-=o0 -Oo-0 -300 -O-0 a o SS Syne BR 1 Sync Bi 2 Sync Bk 3 * Sync BA 4 Sync Bk 5 Sync BR 6 Sync Ba 7 * Also SDLC Address Field Write Register 5 [07 ]06 | os [+ [os Joe [or Joo] [- Tx CRC Enable RTS FSDLC/CRC 16 Tx Enable Send Break 0 x5 Bits (Or Less)/Character 1 Tx 7 Bikts/Character 1 Tx 6 Bits/Character 1 1) Tx 8 Bits/Character Le f)}f} Write Register 7 Jo? } 0s [05 | o] 02 [oe [os [oo] Sync Bit 8 Sync Bit 9 Sync Bit 10 Syne Bitt1 Sync Bit 12 Syne Bit 13 Sync Bit 14 Syne Bit 15 - * For SDLC It must be programmed to "Ot 111110" for flag recognition Figure 21. SIO Write Registers (Continued) WATCH DOG CONTROL REGISTERS There are two registers to control Watch Dog Timer opera- tions. These are Watch Dog Timer Master Register (WDTMR; YO Address FOh) and the WOT Command Register (WDTCR; 1/O Address F1h). Watch Dog Timer Logic has a double key structure to prevent the WDT disabling error, which may lead to the WDT operation to stop due to program runaway. Programming the WDT follows this procedure. Also, these registers program the power-down mode of operation. The Second key is needed when turning off the Watch Dog Timer. Enabling the WDT. The WDT is enabled by setting the WDT Enable Bit (D7:WDTE) to "1" and the WDT Pericdlic field (D5,D6:WDTP) to the desired time period. These com- mand bits are in the Watch Dog Timer Master Register (WDTMR; I/O Address FOh). Disabling the WDT. The WDT is disabled by clearing WDT Enable bit (WDTE) in the WOTMR to 0 followed by writing Bih to the WOT Command Register (WDTCR; t/O Ad- dress Fth). 316Clearing the WDT. The WDT can be cleared by writing AEh into the WDOTCR. Watch Dog Timer Master Register (WDTMR;V/O address FOh). This register controls the activities of the Watch Dog Timer and selects power-down mode of operation (Figure 22). WDTMR (Read/Write) sysfs fafsfofs ts] (Value on Power-on Reset) | ~ Lo Should be "011 HALT Mode (HALTM) 0 0-IDLE1 Mode 0 1-IDLE2 Mode 1 0-STOP Mode 1 1-RUN Mode WOT Periodic Field (WDTP) 0 0-Periodis (ToS x 216) 0 1- Period is (ToC x 218) 1 0-Perlodis (TcC x 220) 1 1-Petiodis (ToC x 222) Watch Dog Timer Enable (WDTE) 1 = Enable 0 = Disable Figure 22. Watch Dog Timer Master Register Bit D7. Watch Dog Timer Enable(WDTE). This bit controls the activities of Watch Dog Timer. The WDT can be enabled by setting this bit to 1". To disable WDT, write O to this bit followed by writing B1h in the WOT Command Register. Watch Dog Timer Logic has a double key Structure to prevent the WDT disabling error, which may lead to the WDT operation to stop, due to program run- away. Upon Power-on reset, this bit is set to "1" and the WDT is enabled. Bit D6-D5. WDT Periodic field (WDTP). This two bit field determines the desired time period. Upon Power-on reset, this field sets to"11". 00 - Period is (TcC * 2%) 01 - Period is (TcC * 2") 10 - Period is (TcC * 2) 11 - Period is (TcC * 2) Bit D4-D3. HALT mode (HALTM). This two bit field speci- fies one of four power-down modes. To change this field, write DBh to the WOT command register, followed by a write to this register. For detailed descriptions of this field, please refer to the section Mode of operations. Upon Power-on Reset, this field is set to 11, which specifies RUN mode." 00 - IDLE 1 Mode 01 - IDLE 2 Mode 10 - STOP Mode 11 - RUN Mode Bit D2-D0. Reserved. These three bits are reserved and should always be programmed as 011. A read to these bit returns 011. Watch Dog Timer Command Register (WDTCR; VO ad- Gress F th). In conjunction with the WOTMR, this register works as a Second key for the Watch Dog Timer. This register is write only (Figure 23). Write Bth after clearing WDTE to 0 - Disable WDT. Write 4Eh - Clear WDT. Write DBh followed by a write to HALTM - Change Power-down mode. WOTCR (Write Only) 07] pe] 05 ]o] os [oe] os [oo] ~ So _ _ oS o _ (Bh) - Disable WDT (After Clearing WDTE) (4Eh) - Clear WOT (DBh) - Change HALT Mode {Followed by setting HALTM) Figure 23. Watch Dog Timer Command Register 317INTERRUPT PRIORITY REGISTER (INTPR; 1/O address F4h) This register (write only) is provided to determine the interrupt priority for the CTC, SIO and the PIO (Figure 24). IPR (Write Only) D7 Bo DDT ToT oT] cate onronron es | | | ZB4X15 2B4X13 Dp Dy Dy Hihtow High-Low 0 CTC-SIO-PIO CTC-SIO 1 SIOCTC-PIO SsIO-CcTC CTC-PIO-SIO Reserved I ou4400 =4904-00 Figure 24. interrupt Priority Register Bit D7-D3. Unused Bit D2-D0. This field specifies the order of the interrupt daisy chain. Upon Power-on Reset, this field is set to 000". 284015 284613 High - Low High - Low 000 CTC-SIO-PIO CTC-SIO 001 SIO-CTC-PIO SIO-CTC 010 CTC-PIO-SIO Reserved on PIO-SIO-CTC Reserved 100 PIO-CTC-SIO Reserved 101 SIO-PIO-CTC Reserved 110 Reserved Reserved 111 Reserved Reserved REGISTERS FOR SYSTEM CONFIGURATION (The following registers are not available on Z84013/015.) There are four indirectly accessible registers to determine System configuration with the 784C13/C15. These indi- rectly accessible registers are: Wait State Control Register (WCR, Control Register 00h), Memory Wait Boundary Register (MWBR, Control Register 01h), Chip Select Bound- ary Register (CSBR, Control Register 02h) and Misc. Control Register (MCR, Control Register 03h). To access these registers, Z84C 13/C 15 writes register number to be accessed" to the System Control Register Pointer (SCRP, I/O address EEh), and then accesses the target register through the System Control Data Port (SCDP, I/O address EFh). The pointer which writes into SCRP is kept until modified. System Control Register Pointer (SCRP, /O address EEh) This register stores the pointer to access System Control Registers (WCR, MWBR, CSBR and MCR). This register is Read/Write and it holds the pointer value until modified. Upon Power-on Reset, all bits are cleared to zero. The pointer value, other than 00h to 03h is reserved and is not written. Upon Power-on Reset, this register is set to "00h" (Figure 25). SCRP (Read/Write) 07 DO ToT ToT ef oJ] ] vate sore: en hey (00h) Point to WCR (01h) Point to MWBR (02h) Point to CSBR (03h) Point to MGR e000 e000 ocao oooe e000 eocoo +-=00 4+on0 Figure 25. System Control Register Pointer System Control Data Port (SCDP, V/O address EFh) This register is to access WCR, MWBR, CSBR and MCR (Figure 26). SCOP (Read Write) 07 Do LT pete tengo Pointed by SCPR Figure 26. System Control Data Port Wait State Control Register (WCR, Control Register 00h) This register can be accessed through SCDP with the pointer value 00h in SCRP (Figure 27). To maintain com- patibility with the Z84013/015, the Z84C13/C 15 inserts the maximum number of wait states (set all bits of this register to one) for fifteen (M1 cycles after Powr-on Reset. It automatically clears the contents of this register (move to no-wait state insertion) on the trailing edge of the 16th /M1 signal uniess software has programmed a value. ff auto- matic wait state insertion is needed, the wait state is programmed within this time period. A read to WCR during this period will return FFh, unless programmed. 318Do LELEETTET] 1 16 - AA1 Cycles After Power-on Reset Unless Programmed see } LL soe vo No Wak State 0 1 1 0 1 Two Walt States Four Wait States 1 Six Wak States Wait 0 0 No Walt State 0 1 One Wait State 1 1 Two Wak States 1 Three Wak States Op-code Fetch Extension 0: No Additional Wait On =eem== interupt Vector Wat | 0: No Wait +: One Wait State upt Daisy Chain Wak interrupt RETI Acknowledge Cycle Cycle O OWakState 0 Walt State 0 1 2WaiStaws 0 Wait Sta 1 0 4Wak States 2 Wait States 11 @WakStates 4 Walt States Figure 27. Wait State Control Register This register has the following fields: Bit 7-6. Interrupt Daisy Chain Wait. This 2-bit field specifies the number of wait states to be inserted during an Interrupt Daisy Chain settle period of the Interrupt Acknowledge cycle, which is/lORQ falls after the settling period from /M1 going active "0". Also, this field controls the number of wait States inserted during the RETI (Return From Interrupt) cycle. If specified to insert 4 or 6 wait states during interrupt Acknowledge cycle, the Waitstate generator also inserts wait states during RETI fetch sequence. This se- quence is formed with two op-code fetch cycles (Op-code is EDh followed by 4Dh). It inserts 1 wait state if op-code followed by EDh is NOT 4Dh, and inserts 2 or 4 wait states, respectively, if the following op-code is 4Dh. Interrupt Acknowledge RETI cycle 00 - No Wait states No Wait states 01 - 2 Wait states No Wait states 10 - 4 Wait states 2 Wait states 11 - 6 Wait states 4 Wait states For fifteen /M1 cycles from Power-on Reset, bits 7-6 are set to 11 . They clear to 00" on the trailing edge of the 16th /M1 signal unless programmed. Bit 5. Interrupt Vector Wait. While this bit is set to one, the wait state generator inserts one wait state after the AORQ signal goes active during the Interrupt acknowledge cycle. This gives more time for the vector read cycle. While this bit is cleared to zero, no wait state is inserted (standard timing). For fifteen (M1 cycles from Power-on Reset, this bit is set to 1", then cleared to 0 on the trailing edge of the 16th /M1 signal, unless programmed. Bit 4. Opcode Fetch Extension. If this bit is set to 1, one additional wait state is inserted during the Op-code fetch cycle in addition to the number of wait states programmed in the Memory Wait field. For fifteen (M1 cycles from Power- on Reset, this bit is set to 1, then cleared to 0 on the trailing edge of the 16th /M1 signal, unless programmed. Bit 3-2. Memory Wait States. This 2-bit field specifies the number of wait states to be inserted during memory Read/ Write transactions. 00 - No Wait states 01 - 1 Wait states 10 - 2 Wait states 11-3 Wait states For fifteen (M1 cycles from Power-on Reset, these bits are set to 11, then cleared to 00 on the trailing edge of the16th /M1 signal, unless programmed. . Bit 1-0. /O Wait states. This 2-bit field specifies the fumber of wait states to be inserted during {/O transactions. 00 - No Wait states 01 - 2 Wait states 10 - 4 Wait states 11 - 6 Wait states For fifteen (M1 cycles from Power-on Reset, these bits are set to 11, then cleared to 00" on the trailing adge of the 16th /M1 signal, unless programmed. For the actesses to the on-chip 1/O registers, no Wait states are inserted regardless of the programming of this field. Memory Wait Boundary Register (MWBR, Control Register 01h) This register specifies the address range to insert memory wait states. When accessed memory addresses are within this range, the Memory Wait State generator inserts Memory Wait States specified in the Memory Wait field of WCR (Figure 28). 319MWEBR (Read/Write) D7 Do LT fT PoP of 0] 0] cae on power-on Rosey Specifies Address (A15-A12) for Memory Wak Ingertion eras Memory Wait High Boundary Specifies High Address (A15-A12) for Memory Wait Insertion Memory Walt Low Boundary Lower Figure 28. Memory Wait Boundary Register Bit D7-D4. Memory Wait High Boundary. This field speci- fies A15-A12 of the upper address boundary for Memory Wait. Bit D3-D0. Memory Wait Low Boundary. This field specifies A15-12 of the lower address boundary for Memory Wait. Memory Wait states are inserted for the address range: (D7-D4 of MWBR) 2 A15-A12 2 (D3-D0 of MWBR) This register is set to FOh on Power-on Reset, which specifies the address range for Memory Wait as O000h to FFFFh". Chip Select Boundary Register (CSBR, Controt Register 02h) . This register specifies the address range for each chip select signal. When accessed memory addresses are within this range, chip setect signals are active (Figure 29). CSBR (Read/Write) D7 - po xLxpxpxpi papaya (Value on Power-on Reset) CSO Boundary (A15-A12 <) /CS1 Boundary (A15-A12 < and > /CSO Boundary) Figure 29. Chip Select Boundary Register D7-D4. /CS1 Boundary Address. These bits specify the boundary address range for /CS1. The bit values are ignored on power-up as the /CS1 enable bitis off. The /CS1 is asserted if the address lines A15-12 have an address value greater than the programmed value for /CSO, and less than or equal to the programmed value in these bits. D3-D0. /CSO Boundary Address. These bits specify the boundary address range for /CSO. /CSO is asserted if the address lines A15-12 have an address value less than or equal to the programmed boundary vatue. Tha /CSO en- able bitin the MCR must be setto 1. Upon Power-up reset, these bits come up as all 1's so that /CSO is asserted for all addresses. Chip Select signals are active for the address range: /CSO: (D3-D0 of CSBR) > A15-A12>0 ICS1: (D7-D4 of CSBR) > A15-A12 > (D3-D0 of CSBR) This register is set to xxxx1111b on Power-on Reset, which specifies the address range of /CSO for *0000h to FFFFh" (all Memory location) and /CS1 undefined. Misc Controt Register (MCR, Controt Register 03h) This register specifies miscellaneous options on this de- vice (Figure 30). MCR (Read/Write) D7 po fofofofofofo]o]s {Value on Power-on Reset} Figure 30. Misc Control Register CSO Enable 0 = Disable 1 = Enable CS1 Enable 0 = Disable 1 = Enable 92-Bk CRC Enable 0 = Disable 1 = Enable Reset Output Diesbie 0 = Reset Output Is Enabled 1 = Reset Output fs Disabled Should Program as 000 Bit D7-D5. Reserved. These three bits are reserved and are always programmed as O00. Bit D4. Clock Divide-by-one option. O"-Disable, 1"-en- able. On-chip CGC unit has divide-by-two circuil. By Setting this bit toone, this circuit is bypassed and CLKOUT is equal to X'tal oscillator frequency (or external clack input on the XTAL1 pin). This bit has no effect when the on-chip CGC unit is not in use and the external system clock is fed from CLKIN pin. Upon Power-on Reset, this bit is cleared to 0 and the clock is divided by two.Bit D3. Reset Output Disable. O"-Reset output is enabled, 1-Reset output is disabled. This bit controls the /RESET signal andis driven out when reset input is used to take the 284C13/C15 out of the Halt state. The reset pulse is driven out for 16-clock cycles from the falling edge of /RESET input, unless this bit is set. Upon Power-on reset, this bit is cleared to 0. Bit D2. 32-Bit CRC enable. O"-Normal mode (16-bit CRC) 1"-32-bit CRC generation/Checking is enabled on SIO Channel A. This bit determines if the 32-bit CRC feature is enabled on Channel A of the SIO. If this bit is O, the SIO is in anormal mode of operation. If this bitis set to 1 , anormal CRC generator/checker is replaced with a 32-bit CRC generator/checker. Upon Power-on Reset, this bit is clear to 0. Bit D1. /CS1 Enable. 0-Disable, 1"-Enable. This bit enables /CS1 output. While this bit is 0, /CS1 is forced to 1. While this bit is 1, /CS1 carries the address range specified in the CSBR. Upon Power-on Reset, this bit is cleared to 0. Bit DO. /CSO Enable. '0-Disable, 1'-Enable. This bit en- ables /CSO output. While this bit is 0, /CS1 pin is forced to 1. While this bit is 1, the (CSO carries address range specified in the CSBR. Upon Power-on Reset, this bit is set to1". Operation modes There are four kinds of operation modes available for the IPC in connection with clock generation: RUN Mode, IDLE 1/2 Modes and STOP Mode. The Operation mode is effective when the HALT instruction is executed. Restart of the MPU from the stopped state under IDLE 1/2 Mode or STOP mode is affected by input- ting either (RESET or interrupt (/NMI or INT). The mode selection of these power-down modes is made by pro- gramming the HALTM field (Bit D4-3) of WOTMR, Setting Halt Mode Duplicate control is provided to prevent the stopping of the WDT operation caused by the halt mode setting an error due to program runaway. As described in the program- ming section, changing the Halt Mode field of WDTMR is in two steps. First, write DBh to WDTCR followed bya write to the WOTMR with the value in HALTM. Table 2 has descriptions of each mode, and Table 3 has device status in the Halt state. Tabie 2. Power-down Modes (When using on-chip CGC unit; CLKOUT and CLKIN are tied together) : WDTMR Operation Mode Bit D4 Bit D3 Description at HALT State RUN Mode 1 1 The IPC continues the Operation and continuously supplies a clock to the outside. IDLE1 Mode 0 .0 The internal oscillators operation is continued. Clock output (CLKOUT) as well as internal clock to the CPU, PIO, SIO, CTC and the Watch Dog Timer is stopped at 0 level of T4 state in the halt instruction operation code fetch cycle. IDLE2 Mode 0 1 The internal oscillator and the CTCs operation continues and supplies Clock to the outside on the CLKOUT pin continuously. But the internal Clock to the CPU, PIO, SIO and the Watch Dog Timer is stopped at 0 level of T4 state in the halt instruction operation code fetch cycle. STOP Mode 1 0 All operations of the internal oscillator, clock (CLK) output, intarnal clock tothe CPU, PIO, CTC, SIO and the Watch Dog Timer are stopped at O" level of T4 state in the halt instruction operation code fetch cycle. 321Table 3. Device status in Halt state (When using on-chip CGC unit; CLKOUT and CLKIN are tied together) Mode CGC CPU CTC PIO SIO WDT CLKOUT IDLE1 O IDLE2 O STOP X RUN O Oxxx Oxo. Ox x x Oxxx Oxxx Oxo~x O: Operating X: Stop All of the operating modes listed here are valid with crystal input (Crystal connected between XTAL1/2 or external clock input on XTAL1). For the external clock on the CLKIN pin, only the IDLE2 and RUN modes are applicable. TIMING Basic Timing The basic timing is explained here with emphasis placed on the hait function relative to the clock generator. The following items are identical to those for the Z84C00. Refer to the data sheet for the 784C00. Operation code fetch cycle Memory ReadMrite operation = {nput/Output operation Bus request/acknowledge operation = Maskable interrupt request operation = Non-Maskable interrupt request operation Reset Operation Operation When HALT Instruction is Executed. When the CPU fetches a halt instruction in the operation code fetch cycle, /HALT goes active (Low) in synch with the falling edge of T4 state before the peripheral LS! and CPU stops the operation. After this, the system clock generation differs depending upon the operation mode (RLIN Mode, IDLE 1/2 Mode or STOP Mode). If the internal system clock is running, the CPU continues to execute NOP instruction even in the halt state. RUN Mode (HALTM = 11). Shown in Figure 31 is the basic timing when the halt instruction is executed in RUN Mode. MiCycle | | M1 Cycle |. M1 Cycle g T4 T1 T2 T3 T4 1 T2 3 cLKouT LI L (HALT 1 HALT OP-Code FetchCycle | NOP Execution | NOP Execution | Figure 31. Timing of RUN Mode (at Halt Instruction Command Execution)in RUN Mode, output from the CGC unit (CLKOUT) is not Stopped and the internal system clock (@) continues even after the halt instruction is executed. Therefore, until the halt state is released by the interrupt signal (/NMI or /INT) or (RESET signal, MPU continues to execute HALT instruc- tions (internally executing NOP instructions). IDLE1 Mode (HALTM=00). Shown in Figure 32 is the basic timing when the halt instruction is executed in IDLE 1 Mode. T4 CLKOUT | ] nt a o al Tk MPU Operation STOP Ss raton c ae Sf HALT te 3} Mi HALT Instruction Operation Code Fetch Cycle Figure 32. IDLE1 Mode Timing (At Halt Instruction Execution) intOLE 1 Mode, the internal oscillator continues to operate, but clock output (CLKOUT) is stopped at T4 Low state of HALT instruction execution. Then ail components in the MPU stop their operation. This mode is not supported CLKOUT when the CGC unit is inactive and the external clock is fed from CLKIN pin; CLKOUT should be connected ta CLKIN. IDLE2 Mode (HALTM=01). Shown in Figure 33 is the basic timing when the hait instruction is executed in IDLE? Mode. @ (intemal System Clock) Jb MHALT m1 SLOP, Pn GPU Operation STOP a a ifa a HALT Instruction Operation Code Fetch Cycle Figure 33. 1DLE2 Mode Timing (At Halt Instruction Execution) 323In IDLE2 Mode, the internal oscillator and clock output (CLKOUT) continue to operate. The internal system clock, fed from CLKIN to the components other than CTC is Stopped at the T4 Low state of HALT instruction execution. STOP Mode (HALTM=10). Shown in Figure 34 is the basic timing when the haltinstruction is executed in STOP Mode. Ti T2 T3 T4 CLKOUT j | i ] [ | | ] CLK Output STOP 2 (internal System | | i | | ] | kK MPU Operation STOP Clock) /HALT M1 a | F Code Fetch Cyclo HALT Instruction Operation Figure 34. STOP Mode Timing (At Halt Instruction. Execution) in STOP Mode, the on-chip CGC unit is stopped at T4 Low State of HALT instruction execution. Therefore, clock out- put (CLKOUT), operation of Watch Dog Timer, CPU, PIO, CTC, SIO are stopped. Release from Halt State. The halt state of the CPU is released when 0 is input to the /RESET signal and the MPU is reset or an interrupt request is accepted. An interrupt request signal is sampled at the leading edge of the last clock cycle (T4 state) of NOP instruction. In case of the maskabie interrupt, interrupt will be accepted by an active /INT signal (O" level). Also, the interrupt enable flip- flop is set to 1. The accepted interrupt process is started from the next cycle. Further, when the internal system clock is stopped (IDLE 1/ 2 Mode, STOP Mode), it is necessary first to restart the internal system clock. The internal system clock is re- Started when /RESET or interrupt signal (/NMI or /INT) is asserted. RUN Mode (HALTM=11). The halt release operation is enabled by interrupt request in RUN Mode (Figure 35). 324HALT Instruction Execution I CLKOUT NOP Instruction Execution | | Mi : T4 T1 T2 Ti T2 13 14 Ti T2 Interrupt Process aa lant 14 11 T2 1 T2 13 T4 T1 T2 (internal ~] rT] 1 r] 7] r] 1 1 1 r 1] [ System Clock) 1 MALT J M1 $ T LI mane 4. * CPU Intemal t Latch for NMI | M1 f | | { ' Interrupt Sample Timing Figure 35. Halt Release Operation Timing By Interrupt Request Signal in RUN Mode In RUN Mode the internal system clock is not stopped. If the interrupt signal is recognized on the rising clock edge of T4 of the continued NOP instruction, CPU will execute the interrupt process from the next cycle. The halt release resets CPU in RUN Mode (Figure 36). After reset, CPU will execute an instruction Starting from ad- dress OOOOH. However, in order to reset the CPU it is necessary tokeep /RESET signal at 0 for atleast 3 system clock cycles. (For Z84C13/C15: 3 clock cycles if Reset output is disabled.) In addition, if RESET signal becomes 1, after the dummy cycle for at least two T States, CPU executes an instruction from address OOOOH. 325HALT Instruction Execute Instruction Execution Address 0000H T4 Tt T2 " LE LI LAST LL LL - @ (Internal = System | | Sf | | | | | ] SS | | | ] | | [ | Clock) maar ng /RESET - GF | Figure 36. Halt Release Operation Timing By Reset in RUN Mode IDLE1 Mode (HALTM=00), IDLE2 Mode (HALTM=01). The halt release operation by interrupt signat in IDLE1 Mode is shown in Figure 37 (a) and in IDLE2 Mode in Figure 37 (b). 326| NOP Instruction Execution | 4 11 T2 3 4 v1 wer TL ig PLE LP LE LPL Latch for NMI (a) IDLE1 Mode = erupt Sampling Timing | NOP Command Execution | 14 1 T2 T3 v4 T1 wer TLPLOLEL LLL LL {internal son TL, Clock) HALT ] 3J i m1 4 | a I I 1 NMI if S$ ----------~-~ ~~ J___ 1* Mpu nema Latch for NMI s | ANT f ] ' | {f kL 1 interrupt Sampling Timing (b) IDLE2 Mode Figure 37. Halt Release Operation Timing By Interrupt Request Signal in IDLE1/2 Mode 327When receiving /NMI or /INT signals, the stopped internal system clock starts to feed. In IDLEt Mode, the !PC starts clock output on CLKOUT at the same time. The operation stop of CPU in IDLE2 mode is taking place at O" level during T4 state in the halt instruction op-code fetch cycle. Therefore, after being restarted by the inter- ruptsigna!, CPU executes one NOP instruction and samples an interrupt signai at the rise of T4 state during the execution of this NOP instruction, and executes the inter- tupt process from next cycle. T4 If no interrupt signal is accepted during the execution of the first NOP instruction after the internal system clock is restarted, CPU is not released from the halt state. It is placed in IDLE 1/2 Mode again at 0 level during T4 state of the NOP instruction, stopping the internal system clock. if (INT signal is not at O fevel at the rise of T4 state, no interrupt request is accepted. The halt release operation resets the IPC in ID_LE1 Mode (Figure 38a) and in IDLE2 Mode (Figure 38b). Execution Instruction from Address 0000H 1 T2 T3 oor TL yg FL LGPL LS Le (internal System Clock) LC eid Lt a | j LC. /RESET IL, mr Ls (a) IDLE1 Mode Execution Instruction from Address 0000H T4 11 T2 T3 LC a L { - j A (b) IDLE2 Mode Figure 38. Halt Release Operation Timing By Reset in IDLE1/2 ModeWhen /RESET signal at 0 level is input into the IPC, the internal system clock is restarted and the IPC will execute an instruction stored in address OOOOH. At time of (RESET signal input, it is necessary to take the same care as that in resetting the IPC in RUN Mode. {. . NOP Command Execution Halt release in STOP Mode (HALTM=1 0) by interrupt. The halt release operation by interrupt signal in STOP Mode is shown in Figure 39. | 4 T2 T3 4 v1 CLKOUT @ (internal System Clock) t I ' /HALT Lig a I ' I M1 Sf- SS i . L__| ! Le l 1 {f L NMI 1 t ~-f eee ee ee LLL 4. MPU intemal I Latch for NMI t { ANT ' | !l 1 t Interrupt Sampling Timing Figure 39. Halt Release Operation Timing By Interrupt Request Signal in STOP Mode When the tPC receives an interrupt signal, the internal oscillator is restarted. To obtain stabilized oscillation, CLKOUT (and the internal system clock) are started after a Start-up time of (2%+2.5) TcC (TcC: Clock Cycle) by the internal counter. CPU executes one NOP instruction after the internal sys- tem clock is restarted. At the same time, it samples an interrupt signal at the rise of T4 state during the execution of this NOP instruction. If the interrupt signal is accepted, CPU executes the interrupt process operation from the next cycle. During interrupt signal input, it is necessary to take the same care as the interrupt signal input in IDLE 1/2 Mode. Halt release in STOP Mode (HALTM=10) by /RESET. When /RESET at O" level is input into the IPC, the internal oscillator is restarted. However, the internal clock counter for warm-up does not operate. Therefore, the operation is not carried out properly due to unstable clock oscillation. Itis necessary to hold /RESET at O" level for sufficienttime. The halt release operation by the IPC resetting in STOP Mode is shown in Figure 40. 329Z84C13/C15 Only. The /RESET pulse is stretched to a minimum of 16 cycles and driven outof the Z84C13/C150n the /RESET pin if Reset output is enabled (bit D3 of MCR is cleared to 0"). Setting bit D3 disables the driving out of CLKOUT | | @ {Internal System Clock) MHALT __I Le 1 /RESET /RESET. The values in the contro! registers (WDTMR, SCRP, WCR, MWBR, CSBR and MCR) are initialized to the default value on /RESET. Executive Instruction from Address 0000H 1 T2 3 JU LU LLP Le LC oF 4 Figure 40. Halt Release Operation Timing By Reset in STOP Mode Start-up Time at Time of Restart (STOP Mode). When the MPU is released from the halt state by accepting an interrupt request, it executes an interrupt service routine. Therefore, when an interrupt request is accepted, it starts generating clock on the CLKOUT pin, after a start-up time, by the internat counter [(2%+2.5) TcC (TcC:Clock Cycle)]. This obtains a stabilized oscillation for operation. Further, in case of restart by the /RESET signal, the internal counter does not operate. Evaluation operation. Each of the CPU signals (A15-0, D7-0, /MREQ, /IORQ, /RD, WR, /HALT, /M1, /AFSH) can be 3-stated by activating the EV pin. The Z84C13/C15 enhances the counter part by eliminating the requirement of /BUSREQ to go active. Instruction set. The instruction setof the IPC is the same for the Z84CO0. For details, refer to the data sheet of the Z84C00 Technical Manual. AC TIMING The following section describes the timing of the IPC. The numbers appearing in the figures refer to the parameters on Table A - F. CPU Timing Parameters referenced in Figure 41 through Figure 48 appear in Table A. The IPCsCPU executes instructions by proceeding through the following specific sequence of operations: Memory read or write I/O device read or write Interrupt acknowledge The basic clock periodis referred to as a Time or Cycle and three or more T cycles make up a machine cycle (e.g., M1, M2 or M3). Machine cycles are extended either by the CPU automatically inserting one or more Wait states or by the insertion of one or more Wait states by the user. 330Instruction Op-code Fetch. The CPU places the contents of the Program Counter (PC) on the address bus at the start of the cycle (Figure 41). Approximately one-half clock cycle later, /MREQ goes active. When active, /RD indi- cates that the memory data can be enabled onto the CPU data bus. Ty T2 Tw Tg T4 \ \ PV J VAN Ly, wy, Ss 5 ! f t. ad A15-A0 PC REFRESH ADDR If- 0 +1@ : (1) | /MREQ / C 10 . J 14 /RD - WAIT 1 \ {t dds ft External Memory Data in /RFSH Figure 41. Instruction Op-code Fetch (See Table A) The CPU samples the /WAIT input with the falling edge of clock state T2. During clock states T3 and 14 of an M1 cycle, dynamic RAM refresh can occur while the CPU Starts decoding and executing the instruction. 331Memory Read or Write Cycles. Figure 42 shows the timing of memory read or write cycles other than an Op-code fetch (M1) cycle. The (MREQ and /RD signals function like the Op-code fetch cycle. in a memory write cycle, /MREQ also becomes active when the Address Bus is stable. The WR line is active when the Data Bus is stable, so thal it can be used directly as an R/W pulse to most semiconductor memories. Tw T3 A15-A0 x MREQ ad Valid Address # WAIT RD Read Operation _ D07-D0 Data In Write D7-DO Data Out Data Out }_ fC Figure 42. Memory Read or Write Cycle (See Table A) 332Input or Output Cycles. Figure 43 shows the timing foran When the CPUis accessing the on-chip I/O registers (PIO, 1/0 read or /O write operation. During I/O operations, the CTC, SIO and system control registers), the data from/to CPU automatically inserts a single Wait state (Ty,)- This these registers also appears on the data bus, or data bus extra Wait state allows sufficient time for an 1/0 port to is output during 1/0 cycle. decode the address from the port address lines. 4 Te Twa Tw T3 om . J \ St / | i J) A\ ~ ae ~*~ Or ad Valid Port Address ro f a 7 <@> ft / ) oot - +~}G) He (36) @r NN. f 7 dd . sor ott ; FE Valid Data @- S {f / | +- A7-A0 AORQ WAIT cr /RD External VO Read Operation 07-Do Data In \ (we VO Write Operation D7-Do Data tn M Internal Read D7-D0 Operation Data Out [C ~ ad wh __# ema + dd Output Valid Note: Twa = One wait cycle automatically inserted by CPU Figure 43. Input or Output Cycle (See Table A) 333interrupt Request/Acknowledge Cycle. The CPU samples the interrupt signal with the rising edge of the last clock cycle at the end of any instruction (Figure 44). When an interrupt is accepted, a special /M1 cycle is generated. During this /M1 cycle, /IORQ becomes active (instead of /MREQ) to indicate that the interrupting device can place an 8-bit vector on the data bus. The CPU automatically adds two Wait states to this cycle. NA NS ANS NS NS et @) -o A15-A0 yi PC AORQ WAIT >| @ 7 D7-Do A NOTE: 1}T 1) = Last state of any instruction cycle 2) Twa = Walt cycle automatically inserted by CPU Figure 44. interrupt Request/Acknowledge Cycle (See Table A) 334Non-Maskable interrupt Request Cycle. /NMI is sampledat the same time as the maskable interrupt input ANT, but has higher priority and cannot be disabled under software control. The subsequent timing is similar to that of anormal memory read operation except that data put on the bus by the memory is ignored. The CPU instead executes a restart (RST) operation and jumps to the /NMI service routine located at the address OO66H (Figure 45). Last M Cycle Mi Tu NY T2 3 14 Ts _ -NMI ~ SS eee se sss estes ses ~" L +09 fe A15-A0 PC mM x |@ Ft Or mi PK @ +| AO /MREQ f @ op. MD * Although /NMI is an asynchronous input, fo guarantee its being recognized on the following machine gre. mats fafing edge must occur no later than the rising edge of the clock cycle preceding the last state of any instruction cycle u) Figure 45. Non-Maskable Interrupt Request Operation (See Table A) 335Bus Request/Acknowledge Cycle. The CPU samples Peripheral access from an external bus master with the /BUSREQ with the rising edge of the last clock period of ising edge of the next clock pulse. At that time, any any machine cycle (Figure 46). If (BUSREQ is active, the &xternal device can take control of these fines, usually to CPU sels its address, data, and /MREQ to Inputs, and __lransfer data between memory and I/O devices. MORQ, /RD and MWR lines set to an input for on-chip Tim Tx Tx TX = S\ANIN\, / aw | /BUSREQ \ / \ ga + + @ /BUSACK ; A1S-A0 } f Floating vo por /MREQ -| > + AAD, WR - Floating HORQ, Mt , (HALT, /RFSH Notes: 1) TLyy = Last state of any M cycle 2) Tx = An arbitrary clock cycle used by requesting device Figure 46. BUS Request/Acknowledge Cycle (See Table A)Halt acknowledge cycle. Figure 47 shows the timing for Halt acknowledge cycle. M1 I Mt m1 Ta Ts Ta 1 Tp Clock MHALT Halt instruction Received : NMI * Although /NMIis an yach input, to gu its bei gnized on the fol cycle, /NMI's falling Ing J edge must occur no later than the rsing edge of the clock preceding the last state of any Instruction cycle (T, ). Figure 47. Halt Acknowledge (See Table A) Reset Cycle. /RESET must be active for at east three clock cycles for the CPU to properly acceptit. As long as /RESET remains active, the address and data buses float, and the control outputs are inactive. Once /RESET goes inactive, two internal T cycles are consumed before the CPU resumes normal processing operation. /RESET clears the PC register, so the first op-code fetch location is OOOOH (Figure 48). 284C13/C15 Only. If Reset output is disabled, /RESET must be active for at least three clock cycles for the CPU to properly acceptit. Otherwise, /RESET must be active for at least two clock cycles and the on-chip reset circuit extends /RESET signal to at least a minimum of 16-clock cycles. 337Clock RESET * Extemal PRESET Input * (RESET (Open drain) A15-A0 07-00 MREQ AORG /BUSACK HALT _ Mi - NY Tg J 7 _ A) , ~ 6s) ft. aE xy , rf Floating f LLLLL/ * 84C13/15 Only Reset Output is Enabled Figure 48. Reset Cycle (See Table A) 338CGC TIMING Parameters referenced in Figure 49 thru Figure 52 appear Figure 49 to Figure 52 shows the timing related CGC and in Table B. Power-On Reset circuit. 2.2V40.4V Vec JRESET MM Figure 49. Reset on Power-up (Applies only for Z84C13/C1 5) (See Table B) T4 Ty To T3 Clock } ANT i o m Pat A37: (2)- Figure 50. Clock Restart Timing by /INT, /NMI (STOP Mode) (See Table B) 339Clock wn L\/\/S\_ 4 11 To T3 Clock et L\ /\ /\L\S\I\. @) ANT \ NMI \ AS? (4) OS (a) Clock Restart Timing by /INT, /NMi (IDLE1/2 Mode) y CLKOUT rest (NY / (b) Clock Restart Timing by /RESET (IDLE 1/2 Mode) ' Figure 51. Clock Restart Timing (IDLE1/2 Mode) (See Table B)CLKOUT IXTALI reper LA \_ i (7) (2) Oe {b) CLKOUT Timing (a) XTAL1 Timing for External Clock Input Figure 52. Clock Timing (See Table B) On-chip peripheral access from External Bus master. The bus master is shown in Figure 53. This timing also applies timing for the on-chip !/O device access from the external _to the timing during EV mode of operation. 4 To T WA Ts Clock Address AORO 7RD Read Cycle 07-D0 Dd Witte to cTe, D7-D0 sO WR, fora Write to System Control Register D7-D0 SIO AWRIADY (WAIT Mode} sto sio Timing WRYARDY (Ready Mode) . (a) On-chip peripheral /O access from External Bus master (See Tables C and F) Figure 53. On-chip Peripheral Timing from External Bus master 341(b) Interrupt Acknowledge Cycle Timing for On-chip peripheral from External Bus master (See Table C) 2 Ts T, y tel Di AW. : ) @) c |EO x . ( (c) Op-code fetch Cycle Timing for On-chip peripheral from External Bus master (See Table C) Figure 53. On-chip Peripheral Timing from External Bus master (Continued) 342PO timing (Not applicable on Z84x13) Figure 54 shows the timing for on-chip PIO, = we 7 \ v bo(6 1+} Mode 0 q fOr -O~ Mode 1 x x Om io Mode 2 Z i. Mode 3 mx x @ i) ANT \ Figure 54. PIO Timing (See Table D) 343CTC Timing Figure 55 shows the timing for on-chip CTC. CLK/TRG Counter CLK/TRG Timer ZC/TO ANT [ A F \ Figure 55. Counter/Timer Timing (See Table E)SIO Timing Figure 56 shows the timing for on-chip SIO. CTS, /DCD, Sf N f 4 \ SYNC 1 @) 1 <1) mf \ 4 ~@) VI 4) (6) +O} ate O TxD mM WWT/ARDY \ ir \ (it) a a 8 (1) > @ _ (18) fO--0- . xX (18) MWWT/ARDY (19) ANT SYNC {Extemal J Syne Mode) } SYNC (Output Mode) I - Figure 56. SIO Timing (See Table F) 345Watch-Dog Timer Timing Figure 57 shows the timing for Watch-dog Timer. WWOTOUT \ _/ VIX [-t#- >) J Figure 57. Watch-dog Timer Timing (See Table H) PRECAUTIONS (1) To release the HALT state by /RESET signal in STOP Mode, hold the /RESET signal at 0 until the output from the internal oscillator stabilizes. Z84013/015 Only. To reset MPU, it is necessary to hold /RESET signal input at O level for at least three clocks. 284C13/C15 Only. If Reset output is disabled, /RESET must be active for at least three clock cycles for the CPU to properly accept it. Otherwise, the on-chip reset circuit extends /RESET signal to at least a minimum of 16-clock cycles. (2) Releasing the MPU from the HALT state by the interrupt signal in IDLE1/2 Mode and STOP Mode, depends upon the HALT state and the internal system clock. They will stop unless an interrupt signal is accepted during the execution of NOP instruction, even when the internal system clock is restarted by the interrupt signal input. In particular, care must be taken when /INT is used. Other precautions are identical to those for the Z84CO0. Refer to the data sheet for the Z84CO00. ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Voltage on Vcc with respect to Vss............ -0.3V to +7.0V Voltages on all inputs with respect to VSS oe ceee -0.3V to Vec+0.3V Operating Ambient Temperature 0c ces See Ordering Information Storage Temperature oo... cee -65 C to + 150 C Stresses greater than those listed under Absolute Maxi- mum Ratings may cause permanent damage to the de- vice. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.STANDARD TEST CONDITIONS The DC Characteristics and capacitance sections below apply for the following standard test conditions, unless otherwise noted. All voltages are referenced to GND (OV). Positive current flows into the referenced pin. Available operating temperature range is: E = -40C to 100C Voitage Supply Range: +4.50V < Vcc <+5.50V All AC parameters assume a load capacitance of 100 pf. Add 10 ns delay for each 50 pf increase in load up to a maximum of 150 pf for the data bus and 100 pf for address and control lines. AC timing measurements are referenced to 1.5 volts (except for clock, which is referenced to the 10% and 90% points). Maximum capacitive load for CLK is 125 pf. The Ordering Information section lists temperature ranges and product numbers. Package drawings are in the Pack- age Information section. Refer to the Literature List for additional documentation. +5V 21K From Output Under Test 100 pF 250 uA Figure 58. Standard Test Load CAPACITANCE Guaranteed by design and characterization Symbol Parameter Min Max Unit Coon Clock Capacitance 35 pF Cy, Input Capacitance 5 pF Cour Output Capacitance 15 pF 347DC CHARACTERISTICS Vog=5.0V + 10%, unless otherwise specified Symbol Parameter Min Max Unit Condition Vac Clock Output High Voltage Vo,0.6 V -2.0MA Vouc Clock Output Low Voltage 0.4 Vv +2.0MA Vatc Clock Input High Voltage Voe-0.6 Vv Vac Clock Input Low Voltage 0.4 Vv Ves input High Voltage 2.2 Voc v Vi Input Low Voltage -0.3 0.8 Vv Vo. Output Low Voltage 0.4 [5] Vv I, g=2-OmA Vou Output High Voltage 2.4 Vv lye 1 -6MA Vow Output High Voltage V,,0.8 [5] Vv loy=-250pA lees Power Supply Current Vog=5V XTALIN =10MHz 50 mA Vu Vo-0.2V XTALIN = 6MHz 30 mA V, =0.2V loca Power Supply Current (STOP Mode) 50 pA Veg=5V loos Power Supply Current (IDLE1 Mode) Vog=5V XTALIN =10MHz 6 mA Viy=Voo-0.2V XTALIN = 6MHz 4 mA V, =0.2V loca Power Supply Current (IDLE2 Mode) Vop=5V XTALIN =10MHz TBD [1] mA Vug=Voe-0-2V XTALIN = 6MHz TBD [1] mA V,=0.2V i Input Leakage Current -10 10 [4] pA Viy=0.4V to Veg lusy SYNC pin Leakage Current -40 10 pA Voyr=0.4V to Veg lo 3-state Output Leakage Current in Float -10 10 [2] BA Vour=0.4V tO Veg lowe Darlington Drive Current Voy= 1.5V (Port B and CTC ZC/TO) -1.5 mA REXT = 390 Ohms Notes: [1] Measurements made with outputs floating. [2] A15-A0, D7-D0, (MREQ, fORQ, (RD and (WR. {3] |... Standby Current is guaranteed when the /HALT pin is low in STOP mode. [4] All Pins except XTALI, where [=t25pA. [5] A15-A0, 07-Do, (MREQ, /ORQ, /RD, WR, HALT, (M1 and /BUSACK.AC CHARACTERISTICS Table A. CPU Timing (See Figure 41 to 48) Z84X1306 284X1310 284C1316* 7284X1506 Z84X1510 284C1516 No Symbol Parameter Min Max Min Max Min Max Unit Note 1 TeC Clock Cycle time 162** DC 100* OC 61 DC ns [At] 2 TwCh Clock Pulse Width (High) 65 DC 40 DC 20 DC ns [At} 3. Tw Clock Pulse Width (Low) 65 DC 40 oc 20 DC ns [At] 4 TI Clock Fall time 20 10 6 fs [At] 5 Te Clock Rise time 20 10 6 ns [Al] 6 TdCr{A) Address Valid from Clock Rise 90 65 55 ns 7 TdA(MREQH Address Valid to (MREQ Fall 35** 0** -15 ns 8 TdCf(MREQh Clock Fatt to /MREQ Fall Delay 70 55 40 ns 9 TdCr(MREQr) Clock Rise to /MREQ Rise Delay 70 55 40 ns 10 TwMREQh /MREQ Pulse Width (High) &* 30** 10 ns [A2] 11 TwMREQI /MREQ Pulse Width (Low) 132** 75** 25 ns [A2] 12 TdCf(MERQr) Clock Fall to /MREQ Rise Delay 70 55 40 ns 13 TdCK(RDA) Clock Fall to /RD Fall Delay 80 65 40 ns 14 TdCr(RDr) Clock Rise to /RD Rise Delay 70 55 40 ns 15 TsD(Cr Data Setup Time to Clock Rise 30 25 10 ns 16 ThD(RDr) Data Hold Time After /RD Rise 0 0 0 ns 17 TsWAIT(Cf) AT Setup Time to Clock Fall 60 20 rhs) ns 18 ThWAIT(Cf) WAIT Hold Time After Clock Fall 10 10 10 ns 19 TdCr(Mif) Clock Rise to /M1 Fall Delay 80 65 40 ns 20 TdCr(Min Clock Rise to /M1 Rise Delay 80 65 40 ns 21 TdCr(RFSHA Clock Rise to /RFSH Fall Delay 110 80 60 ns 22 TdCr(RFSHr) Clock Rise to /RFSH Rise Delay "100 80 60 ns 23 TdCf(RDr) Clock Fall to (RD Rise Delay 70 55 40 ns 24 = TdCr(ROf) Clock Rise to /RD Falt Delay 70 55 40 ns 25 TsD(Cf) Data Setup to Clock Fall During M2, M3, M4 or M5 Cycles 40 25 12 ns 26 TdA(IOROQA Address Stable Prior to AORQ Fall 107** 50** 0 ns 27 TdCr(lOROF) Clock Rise to /IORQ Fatt Delay 65 50 40 ns 28 TdCf(lORQr) Clock Fall to /LORQ Rise Delay 70 55 40 ns 29 TdD(WR) Data Stable Prior to (WR Fall 22** 40** -10 ns 30 TdCi(WRI) Clock Fall to (WR Fall Delay 70 55 40 ns 31 TwwR MWR Pulse Width 132** 75** 25 ns 32 TdCf(WRr) Clock Fal! to (WR Rise Delay 70 55 40 ns 33 TAD(WRAIO Data Stable Prior to (WR Fall -55** -10** -30 ns 34 TdCr(WRf) Clock Rise to /WR Fall Delay 60 50 40 ns 35 TdWRr(D) Data Stable from /WR Fall 30* 10** 0 0 ns 36 TdCf(HALT) Clock Fall to (HALT 0 or 1 260 90 70 ns 37 TwNMI /MNI pulse Width . 60 60 60 ns 38 TsBUSREQ(Cr) /BUSREQ Selup Time to Clock Rise 50 30 15 ns 39 ThBUSREQ(Cr) /BUSREQ Hold Time after Clock Rise 10 10 10 ns 40 TdCr(BUSACKA) Clock Rise to /BASACK Fall Delay 9 75 40 ns 349AC CHARACTERISTICS (Continued) Table A. CPU Timing (Continued) Z84X1306 284X1310 28401316" 284X1506 Z84X1510 28401516 No Symbol Parameter Min Max Min Max Min Max Unit Note 41 TdCKBUSACKr) Clock Fall to /BASACK Rise Delay 90 75 40 ns 42 TdCr(Dz) Clock Rise to Data Float Delay 80 65 40 ns 43 TdCr(CTz) Clock Rise to Control Outputs Float Delay (/MREQ, /HORQ, /RD and (WR) 70 65 40 ns 44 TdCr(Az) Clock Rise to Address Float Delay 80 75 40 ns 45 TdCTW(A) Address Hold Time from 35** 20** 0 ns /MREQ, AORO, /RD or (WR 46 TsRESET(Cr) TRESET to Clock Rise Setup Time 60 40 15 ns 47 THRESET(Cr) /RESET to Clock Rise Hold Time 10 10 10 ns 48 TsINT&(Cr /INT Fall to Clock Rise-Setup Time 70 50 15 ns 49 ThINTKCr) /INT Rise to Clock Rise Hold Time 10 10 10 ns 50 TdMif(tOROF) /M1 Fall to AORQ Fall Delay 359** 220** 100 ns 51 TdCi(lOROf) Clock Fall to /LORQ Fall Delay 70 55 45 ns 52 TdCf(iORQr) Clock Rise to /ORQ Rise Delay 70 55 45 ns 53 TdCf(D) Clock Fall to Data Valid Delay 130 110 15 ns 54 TRD&{(D) /RD Fall to Output Data Valid TBD 60 40 ns 55 TdiORQ(D) /IORQ Fali to Output Data Valid TBD 70 45 ns 56 TwRESET /RESET Pulse Width 013/015, or C13/C15 with RESET 3TcC 3TcC 3TcC ns Output Disabled 57 TwRESEToe /RESET Pulse Width RESET Output Enabled 2TcC 2TcC 2TcC ns 58 TwRESETdo /RESET Drive Duration RESET Output Enabled 16TcC 16TcC 16TcC ns 59 TwRESETpor /RESET drive duration on Power-On Sequence 10975 10 75 10 75 ms Notes: * 16 MHz Timings are preliminary and subject to change. Only C version * For clock period other than the minimum shown, calculate parameters using the formula on Table H. [A1] These parameters apply to the external Clock input on CLKIN pin. For the cases where external Clock is fed from XTAL1, please refer to Table B. [A2] For loading >= 50 pF, decrease width by 10 ns for each additional 50 pF. 350Table H. Footnote to Table A. Z84X1306 Z84X1310 Z84C1316* No Symbol Parameter 284X1506 Z84X1510 28401516 1 TcC TwCh + TwCl + TrC + TIC 7 TdA(MREQY) TwCh + TIC -50 -50 -A5 10 TwMREQh TwCh + TIC -20 -20 -20 11 TwMREQI TcC -30 -25 -25 26 TdA(IORQf) TcC -55 -50 -50 29 TdD(WRf) TcC -140 -60 -60 31 TwWR TcC -30 -25 -25 33 TdD(WRI) TwCl + TrC -140 -60 -60 35 TdWRr(D) TwCl + TrC -55 -40 -25 45 TdCTr(A) TwCl + TrC -50 -30 -30 50 TdM1f(IORQf) 2TcC + TwCh + TIC -50 -30 -30 351AC CHARACTERISTICS (Continued) Table B. CGC Timing (See Figure 49 to 52) Z84C 1306 28401310 284C1316* 28401506 78401510 284C1516 No Symbol Parameter Min = Max Min Max Min = Max Unit Note 1 TRST(INT)S Clock Restart Time by /INT (Typ)2"42.5TcC (Typ)2+2.5TcC (Typ)2"+2.5TcC ns (STOP Mode) 2 TRST(MNIJS Clock Restart Time by /NMI (Typ)2"+2.5TcC (Typ)2"+2 5TcC (Typ)2"42.5TcC ns ___ (STOP Mode) 3 TRST(INT)I Clock Restart Time by /INT 25tcT 2.51cT 2.51cT ns (IDLE Mode) . 4 TRST(Nmi)I Clock Restart Time by /NMI 251cT 2.50cT 2.51cT ns (IDLE Mode) 5 TRST(RESET)I Clock Restart Time by /RESET 1TcC 1TcC 1TeC ns (IDLE Mode) 6 TICLKOUT CLKOUT Rise Time 15 10 6 ns 7 TrCLKOUT CLKOUT Fall time 15 10 6 ns 8 TcX1 XTAL1 Cycle Time (for External Clock Input on XTAL 1) Divide-by-Two Mode 81 50 31 ns Divide-by-One Mode 162 100 61 ns 9 Twixt XTAL1 Low Pulse Width (for Extemal Clock Input on XTAL1) Divide-by-Two Mode 35 15 10 ns Divide-by-One Mode 65 40 25 ns 10 Twhxt XTAL1 High Pulse Width (for External Clock input on XTAL1) Divide-by-Two mode 35 15 10 ns " Divide-by-One mode 65 40 25 ns WoT XTAL1 Rise Time 25 25 15 ns {81) (for External Clock input on XTAL1) 12. OT XTAL1 Fall Time 25 25 15 ns (B1} (for External Clock Input on XTAL1) Note: [B1} If parameters 8 and 9 are not met, adjust parameters 11 and 12 to satisfy parameters 8 and 9. 352Table C. Timing for on-chip peripheral access from external bus master and daisy chain timing (See Figure 53(a)) 284C1306 Z84C1310 284C1316" 28401506 284C1510 284C1516 No Symbol Parameter Min Max Min Max Min Max Unit Note 1 TsA(RIf) Address Setup Time to /RD, /IORQ Fail 50 40 30 ns 2 TsRKCr) /RD, /IORO Rise to Clock Rise Setup 60 50 40 ns 3 Th Hold time for Specified Setup 15 15 10 ns 4 TdCr(D0) Clock Rise to Data out delay 100 80 60 ns 5 TdRir(D0z) /RD, AORQ Rise to Data Out Float Delay 75 60 50 ns 6 ThRDr(D) /M1, MD, (ORO Rise to Data Hold 15 . 40 15 30 20 ns {C1] 7 TsD(Cr) Data in to Clock Rise Setup Time 30 3 15 ns 8 TdlOf(D01) AORQ Fall to Data Out Delay 95 % 70 ns (INTACK cycle) 9 ThtOr(D) /OROQ Rise to Data Hold 15 15 10 ns 10 ThlOr{A) AORQ Rise to Address Hold 15 15 10 ns Tt TsWif(Cr) AORO, (WR setup time to Clock Rise 20 20 15 ns (C2] New parameter 12 ThWReACr) Clock Rise to ORO, (WR Rise hold time 0 0 0 ns {C2] 13 TsMif(Cr) /M1 Fall to Clock Rise Setup Time 40 40 15 ns 14 TsMir(Cf) /M1 Rise to Clock Rise Setup Time -15 -1 -10 ns (M1 cycle) 15 = TdMI1f(IEOf) = M1 Fall to 1E0 Fall delay (Interrupt Immediately Preceding 140 80 60 ns /M1 Fall) 20 = TACF(IEOr) Clock Fall to IEO Rise Delay 50 40 30 ns 21 += TAC{(IEOA) Clock Fall to IEO Rise Delay 90 75 50 ns Notes: {C1] For I/O write to PIO, CTC and SIO. [C2] For lO Write to system control registers. {C3] For daisy-chain timing, please refer to the note on Page 356. 353AC CHARACTERISTICS (Continued) Table D. PIO Timing (Z84x15 only) (See Figure 54) Z84C1506 28401510 284C1516* No Symbol Parameter Min Max Min Max Min Max Unit Note 1 TslOr(Cr) /IORQ Rise to Clock Fall Setup Time (To Activate RDY on Next Clock Cycle) 100 100 100 ns 2 TdCf(RDY1) Clock Fall to RDY Rise Delay 100 115 30 ns [D2] 3 TdCh(RDYA) Clock Fall to RDY Fall Delay 100 115 30 ns [D2] 4 TwSTB /STB Pulse Width 100 80 50 ns (D1] 5 TsSTBr(Cr) /STB Rise to Clock Fail Setup Time (To Activate RDY on Next Clock Cycle) 100 100 70 ns (D2} 6 TdlOr(PD) ORO Rise to Port Data Stable Delay (Mode 0) 140 120 100 ns (D2) 7 TsPD(STBr) Port Data to /STB Rise Setup Time (Mode 1) 140 75 30 ns 8 ThPD(STBr) Port Data to /STB Rise Hold Time (Mode 1) 15 15 15 ns 9 TdSTB(PD) /STB Fall to Port Data Stable (Mode 2) 150 120 30 ns (D2) 10 TdSTBr(PDz) /STB Rise to Port Data Float Delay (Mode 2) 140 120 50 ns 11. TAPD(INT#) Port Data Match to /INT Fall Delay (Mode 3) 250 200 40 ns 12. TdSTBr(INTf) _/STB Rise to /INT Fall Delay 290 220 75 ns Notes: [D1} For Mode 2: TwSTB >TsPOXSTB). [D2] Increase these values by 2 ns for 10 pF increase in loading up to 100 pF Max. Table E. CTC Timing (Figure 55) 284C1306 28401310 284C1316* Z84C 1506 284C1510 Z84C1516 No Symbol Parameter Min Max Min Max Min = Max Unit Note 1 TdCr{INTA Clock Rise to /INT Fall Delay (TcC+100) (TcC +80) (TcC+30) (E1} 2 TsCTR(Cc) CLK/TRG to Clock Rise Setup Time for immediate Count 90 90 40 ns (E2] 3 TsCTR(Ct) CLK/TRG to Clock Rise Setup Time for Enabling of 90 90 40 ns {Et} Prescalor on Following Clock Rise 4 TACTRINTA) = CLK/TRG to /INT Fall Delay TsCTR(C) Satisfied (1)+{3) (1)+(3) (1)4(3) ns {E2} TsCTR(C) not Satisfied Tc+(1}+(3) TeC-+{1)+(3) TeC+{1)+(3) ns {E2] 5 TcCiR CLK/TRG Cycle time (2TcC) DC (2TcC) OC (2TcC) DC ns (E3] 6 TwCTRh CLK/TRG Width (Low) 90 DC 90 DC 25 DC ns 7 TwCTRi CLK/TRG Width (High) 90 DC 90 DC 25 DC ns 8 TrCTR CLK/TRG Rise Time 30 30 15 ns 9 TfCTR CLK/TRG Fall Time 30 30 15 ns 10 TdCr(ZCr) Clock Rise to ZC/TO Rise Delay 80 80 25 ns 11 TdCh(ZCf) Clock Fall to 2C/TO Fall Delay 80 80 25 ns Notes: [E1] Timer Mode. [E2] Counter Mode. {E3] Counter Mode only; when using a cycle time less than 3TcC, parameter #2 must be met. 354Table F. SIO Timing (See Figures 53(a) and 56) oOOonN DD Cn ff G2 AD ww 28401306 284C1310 284C1316* 284C1506 284C1510 78401516 No Symbol Parameter Min Max Min Max Min Max Unit Note TwPh Pulse Width (High) 150 120 80 ns TwPI Pulse Width (Low) 150 120 80 ns TcTxC /TxC Cycle Time 250 200 120 ns {F1] TwIxCH /TxC Width (High) 85 80 5 ns TwIxCL . /TxC Width (Low) 85 80 55 ns TrTxC /TxC Rise Time 60 60 60 ns TATxC /1xC Fall Time 60 60 60 ns TdTxCi(TxD) {TxC Fall to TxD Delay 160 120 40 ns TdTxCf(w/RRf) /TxC Fall to W//RDY Fall Delay 5 9 5 9 5 8 TcC (Ready Mode) 10 TdT xCi(INTA /TxC Fall to /INT Fall Delay 5 9 5 9 5 9 TcC 11 TeRxC /RxC Cycle Time 250 200 120 ns [F1] 12 TwRxCh /RxC Width (High) 85 80 55 ns 13 TwRxCl /RxC Width (Low) 85 80 5 ns 14 TrRxC /RxC Rise Time 60 60 60 ns 5 TERxC /RxC Fatl Time 60 60 60 ns 16 TsRxD(RxCr) RxD to /RxC Rise Setup Time 0 0 0 ns (X1 Mode) 17 ThRxCr(RxD) /RxC Rise to RxD Hold Time 80 . 60 40 ns (Xt Mode) 18 TdRxCr(W/RRf) /RxC Rise to WW//RDY Fall Delay 10.13 10 13 10 = 13 TcC (Ready Mode) 19 TdRxCr(INTf) /RXC Rise to ANT Fall Delay 10 13 10 = 13 10 13 TeC 20 TdRxCr(SYNCf} /PXC Rise to SYNC Fail Delay 4 7 4 7 4 7 TcC (Output Modes) 21 TsSYNC{(RxCr) /SYNC Fall to RxC Rise Setup -100 -100 -100 ns [F2] (Extemal Sync Modes) 22 TdlOf(W/RRf) ANORQ Fall or Valid Address to 130 110 40 ns (F2] W//RDY Delay (Wait Mode) 23 TdCr(W/RRf) Clock Rise to (W//RDY Delay 85 85 40 ns [F2] (Ready Mode) . 24 TdCf(w/Rz) Clock Fall to (W//RDY Float Delay 90 80 40 ns {F2] (Wait Mode) Notes: [F 1] In all modes, the System Clock rate must be at least five times the maximum data rate. [F2] Parameters 22 to 24 are on Figure 53a. 355AC CHARACTERISTICS (Continued) Table G. Watch Dog Timer Timing (See Figure 57) 28401306 284C1310 284C1316* 28401506 28401510 Z84C1516 No Symbol Parameter Min Max Min Max Min Max = Units 1 TdC(WDTH) Clock Rise to (WDTOUT Fall Delay 160 160 160 ns 2 TdCr(WoTc) Clock Rise to (WDTOUT Rise Delay 165 165 160 ns 3 TcWOT MWOTOUT Cycle Time WDTP = 00 (Typ)2"TcC (Typ}2*TcC (Typ)2"*TcC ns WOTP =01 (Typ)2"tcC (Typ)2"TcC (Typ)2"TeC ns WDTP = 10 (Typ)2"TcC (Typ)2TcC (Typ)2"TcC ns WOTP =11 (Typ)2"TeC (Typ)}27TcC (Typ)22TcC ns Notes: * Inall modes, the System Clock rate must be at least five times the maximum data rate. RESET must be active a minimum of one complete clock cycle. [t] Units equat to System Clock Periods. [2] Units in nanoseconds (ns). Additional information for note [C3] Parameter #15, 16, 17 and 18 of Table C. These parame- [ ters are daisy-chain timing and calculated values, and input Device Device Device Output vary depending on the inside daisy-chain configuration, ct TT a ory ee we Butt | 1EO which is specified in the Interrupt Priority Register. Inside the IPC, the daisy chain can be figured as follows: Internal Daisy Chain Configuration 6 MHz 10 MHz 16 MHz* No Parameter Min Max Min Max Min Max Units 15 TdM1(IEQ) 160 100 100 ns 16 TsIEI(tO) (PIO at #3) 160 100 400 ns (CTC at #3) 160 100 , 100 ns (SIO at #3) 160 100 100 ns 17 TdIEKIEOF) 120 70 100 ns 18 TdIE((tEOr) 120 70 100 ns To calculate IPC daisy-chain timing, it can be treated as if there are Z80 PIO, CTC and SIO with Input buffer and took ahead circuit on the chain. Following are the calculation formulas: Parameter Table C, #15, /M1 falling to IEO delay TsM1(IEQ) = Max[TdM1(lO}#1, TdM1(10)#2, TdM1(1O)#3] + (look-ahead gate Detay) Parameter Table C, #16, IEI to HORQ falling setup time TSIEK!O) = THIE(IEO)#1 + TdIEI(IEO)#2 + TsIEI(IO)#3 + (Input Buffer delay) 356 Parameter Table C, #17, IEI falling to IEO falling delay TdIEN(IEOf) = Max{TdIEIK(IEOF)P!IO, ToalEI(IEOfCTC, TdlEI(IEOASIO] + (input Buffer delay) + (look-ahead gate Delay) ED decode) TdlEI(IEOr) = TdIEI(IEOr)PIO+ TdIEKIEONCTC + TdGIEI(IEOr)SIO + (Input Buffer delay) + (look-ahea Delay) Parameter Table C, #18, !E[ rising to |EO rising wept gate * Where TdIEI(IEO) is worse number between TdIEl(IEOr) and TdiEKIEOf)6MHz 10MHz 16MHz Min Max Min Max Min Max input Buffer Delay 10nS 10nS 10 nS Look ahead gate delay 10nS 10nS 10 nS 6MHz PIO part CTC part SIO part Min Max Min Max Min Max TdM1(IEO) 90nS 130nS 150nS TsIEK(IO) 90nS 100nS 70nS TdIENKIEOf) 100nS 90nS 50nS TdIE(IEOr) 130nS 90nS 50nS 10MHz PIO part CTC part S10 part Min Max Min Max Min Max TdMi1(IEO) 60nS 60nS 90nS TsiEI(IO) 50nS 70nS 50nS TdIEKIEOF) 50nS 50nS 30nS TdIEs(lEOr) 50nS 50nS 30nS Preliminary 16MHz* PIO part CTC part SIO part Min Max Min Max Min Max TdM1(IEO) 55nS 55nS 90nS TSIEI(IO) 45nS 65nS 45n$ TdlEKIEOF) 45nS 45nS 30n$ TdIEK(IEOr) 45nS 45nS 30n$ * Note: 16MHz is for C15 only. If using an interrupt from only a portion of the IPC, these numbers are smaller than the values shown above. For more details about the Z80 Daisy Chain Structure, please refer to the Application Note *Z780 Family Interrupt Structure included in the Z80 Data book. 357