R5F21365CNFA - Renesas Electronics

R01DS0018EJ0110 Rev.1.10 Page 1 of 59

Nov 02, 2010

R8C/36C Group

RENESAS MCU

Datasheet

1. Overview

1.1 Features

The R8C/36C Group of single-chip MCUs incorporates the R8C CPU core, employing sophisticated instructions

for a high level of efficiency. With 1 Mbyte of address space, and it is capable of executing instructions at high

speed. In addition, the CPU core boasts a multiplier for high-speed operation processing.

Power consumption is low, and th e supported operating modes allow additional power cont rol. These MCUs are

designed to maximize EMI/EMS performance.

Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of

system components.

The R8C/36C Group has data flash (1 KB × 4 blocks) wit h the background operation (BGO ) functi on.

1.1.1 Applications

Electronic household appli a nces, office equipment, audio equipment, consumer equipment, etc.

R01DS0018EJ0110

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R8C/36C Group 1. Overview

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Nov 02, 2010

1.1.2 Specifications

Tables 1.1 and 1.2 outline the Specifications for R8C/36C Group.

Table 1.1 Specifications for R8C/36C Group (1)

Item Function Specification

CPU Central processing

unit R8C CPU core

• Number of fundamental instructions: 89

• Minimum instruction execution time:

50 ns (f(XIN) = 20 MHz, VCC = 2.7 to 5.5 V)

200 ns (f(XIN) = 5 MHz, VCC = 1.8 to 5.5 V)

• Multiplier: 16 bits × 16 bits → 32 bits

• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bit s

• Operation mode: Single-chip mode (address space: 1 Mbyte)

Memory ROM, RAM,

Data flash Refer to Table 1.3 Product List for R8C/36C Group

Power Supply

Voltage

Detection

Voltage detection

circuit • Power-on reset

• Voltage detection 3 (detection level of voltage detection 0 and voltage

detection 1 selectable)

I/O Ports Programmable I/O

ports • Input-only: 1 pin

• CMOS I/O ports: 59, selectable pull- up resistor

• High current drive ports: 59

Clock Clock generation

circuits • 4 circuits: XIN clock oscillation circuit,

XCIN clock oscillation circuit (32 kHz),

High-speed on-chip oscillator (with frequency adjustment function),

Low-speed on-chip oscillator

• Oscillation stop detection: XIN clock oscillati on stop detection function

• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16

• Low power consumption modes:

S t andard operating mode (high-speed clock, low-speed clock, high-speed on-

chip oscillator, low-speed on-chip oscillator), wait mode, stop mode

Real-time clock (timer RE)

Interrupts • Interrupt Vectors: 69

• External: 9 sources (INT × 5, key input × 4)

• Priority levels: 7 levels

Watchdog Timer • 14 bits × 1 (with prescaler)

• Reset start selectable

• Low-speed on-chip oscillator for watchdog timer selectable

DTC (Data Transfer Controller) • 1 channel

• Activation sources: 39

• Transfer modes: 2 (normal mode, repeat mode)

Timer Timer RA 8 bits × 1 (with 8-bit prescaler)

Timer mode (period timer), pulse output mode (output level inverted every

period), event counter mode, pulse width measurement mode, pulse period

measurement mode

Timer RB 8 bits × 1 (with 8-bit prescaler)

T imer mode (period timer), programmable waveform generation mode (PWM

output), programma ble one-shot generation mode, programmable wait one-

shot generation mode

Timer RC 16 bits × 1 (w it h 4 ca pture/compare registe rs)

Timer mode (input capture function, output compare function), PWM mode

(output 3 pins), PWM2 mode (PWM output pin)

Timer RD 16 bits × 2 (w it h 4 ca pture/compare registe rs)

Timer mode (input capture function, output compare function), PWM mode

(output 6 pins), reset synchronous PWM mode (output three-phase

waveforms (6 pins), sawtooth wave modulation), complementary PWM mode

(output three-phase waveforms (6 pins), triangular wave modulation), PWM3

mode (PWM output 2 pins with fixed period)

R8C/36C Group 1. Overview

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Nov 02, 2010

Note:

1. Specify the D version if D version functions are to be used.

Table 1.2 Specifications for R8C/36C Group (2)

Item Function Specification

Timer Timer RE 8 bits × 1

Real-time clock mode (count seconds, minutes, hours, days of week), output

compare mode

Timer RF 16 bits × 1

Input capture mode (input capture circuit), output compare mode (output

compare circuit)

Timer RG 16 bits × 1 (w it h 2 ca pture/compare registe rs)

Timer mode (input capture function, output compare function), PWM mode

(output 1 pin), phase countin g mode (available automatic measurement for

the counts of 2-phase encoder)

Serial

Interface UART0, UART1 Clock synchronous serial I/O/U ART × 2 channel

UART2 Clock synchronous serial I/O, UART, I2C mode (I2C bus), multiprocessor

communica tion function

Synchronous Serial

Communication Unit (SSU) 1 (shared with I2C bus)

I2C bus 1 (shared with SSU)

LIN Module Hardware LIN: 1 (timer RA, UART0)

A/D Converter 10-bit resolution × 12 channels, includes sample and hold function, with sweep

mode

D/A Converter 8-bit resolution × 2 circuits

Comparator B 2 circuits

Flash Memory • Programming and erasure voltage: VCC = 2.7 to 5.5 V

• Programming and erasure endurance:10,000 times (data flash)

1,000 times (program ROM)

• Program security: ROM code protect, ID code check

• Debug functions: On-chip debug, on-board fla s h rewrite function

• Background operation (BGO) function (data flash)

Operating Frequency/Supply

Voltage f(XIN) = 20 MHz (VCC = 2.7 to 5.5 V)

f(XIN) = 5 MHz (VCC = 1.8 to 5.5 V)

Current consumption Typ. 7.0 mA (VCC = 5.0 V, f(XIN) = 20 MHz)

Typ. 3.5 mA (VCC = 3.0 V, f(XIN ) = 10 MHz)

Typ. 4.0 µA (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz))

Typ. 2.0 µA (VCC = 3.0 V, stop mode)

Operating Ambient Temperature −20 to 85°C (N version)

−40 to 85°C (D version) (1)

Package 64-pin LQFP

• Package code: PLQP0064KB-A (previous code: 64P6Q-A)

• Package code: PLQP0064GA-A (previous code: 64P6U-A)

64-pin TQFP

• Package code: PTQP0064LB-A

R8C/36C Group 1. Overview

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Nov 02, 2010

1.2 Product List

Tables 1.3 and 1.4 list Product List for R8C/36C Group. Figure 1.1 shows a Part Num ber, Memory Size, and

Package of R8C/36C Group.

(D): Under development

Note:

1. The user ROM is programmed before shipment.

Table 1.3 Product List for R8C/36C Group (1) Current of Nov 2010

Part No. ROM Capacity RAM

Capacity Package Type Remarks

Program

ROM Data flash

R5F21364CNFP 16 Kbytes 1 Kbyte × 4 1.5 Kbytes PLQP0064KB-A N version

R5F21365CNFP 24 Kbytes 1 Kbyte × 4 2 Kbytes PLQP0064KB-A

R5F21366CNFP 32 Kbytes 1 Kbyte × 4 2.5 Kbytes PLQP0064KB-A

R5F21367CNFP 48 Kbytes 1 Kbyte × 4 4 Kbytes PLQP0064KB-A

R5F21368CNFP 64 Kbytes 1 Kbyte × 4 6 Kbytes PLQP0064KB-A

R5F2136ACNFP 96 Kbytes 1 Kbyte × 4 8 Kbytes PLQP0064KB-A

R5F2136CCNFP 128 Kbytes 1 Kbyte × 4 10 Kbytes PLQP0064KB-A

R5F21364CNFA 16 Kbytes 1 Kbyte × 4 1. 5 Kbytes PLQP00 64 G A-A

R5F21365CNFA 24 Kbytes 1 Kbyte × 4 2 Kbytes PLQP0064GA-A

R5F21366CNFA 32 Kbytes 1 Kbyte × 4 2. 5 Kbytes PLQP00 64 G A-A

R5F21367CNFA 48 Kbytes 1 Kbyte × 4 4 Kbytes PLQP0064GA-A

R5F21368CNFA 64 Kbytes 1 Kbyte × 4 6 Kbytes PLQP0064GA-A

R5F2136ACNFA 96 Kbytes 1 Kbyte × 4 8 Kbytes PL QP 00 64 G A -A

R5F2136CCNFA 128 Kbytes 1 Kbyte × 4 10 Kbytes PLQP0064GA-A

R5F21364CNFB (D) 16 Kbytes 1 Kbyte × 4 1.5 Kbytes PTQP0064LB-A

R5F21365CNFB (D) 24 Kbytes 1 Kbyte × 4 2 Kbytes PTQP0064LB-A

R5F21366CNFB (D) 32 Kbytes 1 Kbyte × 4 2.5 Kbytes PTQP0064LB-A

R5F21367CNFB (D) 48 Kbytes 1 Kbyte × 4 4 Kbytes PTQP0064LB-A

R5F21368CNFB (D) 64 Kbytes 1 Kbyte × 4 6 Kbytes PTQP0064LB-A

R5F2136ACNFB (D) 96 Kbytes 1 Kbyte × 4 8 Kbytes PTQP0064LB-A

R5F2136CCNFB (D) 128 Kbytes 1 Kbyte × 4 10 Kbytes PTQP0064LB-A

R5F21364CNXXXFP 16 Kbytes 1 Kbyte × 4 1.5 Kbytes PLQP0064KB-A N version Factory

programming

product (1)

R5F21365CNXXXFP 24 Kbytes 1 Kbyte × 4 2 Kbytes PLQP0064KB-A

R5F21366CNXXXFP 32 Kbytes 1 Kbyte × 4 2.5 Kbytes PLQP0064KB- A

R5F21367CNXXXFP 48 Kbytes 1 Kbyte × 4 4 Kbytes PLQP0064KB-A

R5F21368CNXXXFP 64 Kbytes 1 Kbyte × 4 6 Kbytes PLQP0064KB-A

R5F2136ACNXXXFP 96 Kbytes 1 Kbyte × 4 8 Kbytes PLQP0064KB-A

R5F2136CCNXXXFP 128 Kbytes 1 Kbyte × 4 10 Kbytes PLQP0064KB-A

R5F21364CNXXXFA 16 Kbytes 1 Kbyte × 4 1.5 Kbytes PLQP0064GA-A

R5F21365CNXXXFA 24 Kbytes 1 Kbyte × 4 2 Kbytes PLQP0064GA-A

R5F21366CNXXXFA 32 Kbytes 1 Kbyte × 4 2.5 Kbytes PLQP0064GA-A

R5F21367CNXXXFA 48 Kbytes 1 Kbyte × 4 4 Kbytes PLQP0064GA-A

R5F21368CNXXXFA 64 Kbytes 1 Kbyte × 4 6 Kbytes PLQP0064GA-A

R5F2136ACNXXXFA 96 Kbytes 1 Kbyte × 4 8 Kbytes PLQP0064GA-A

R5F2136CCNXXXFA 128 Kbytes 1 Kbyte × 4 10 Kbytes PLQP0064GA-A

R5F21364CNXXXFB (D) 16 Kbytes 1 Kbyte × 4 1.5 Kbytes PTQP0064LB-A

R5F21365CNXXXFB (D) 24 Kbytes 1 Kbyte × 4 2 Kbytes PTQP0064LB-A

R5F21366CNXXXFB (D) 32 Kbytes 1 Kbyte × 4 2.5 Kbytes PTQP0064LB-A

R5F21367CNXXXFB (D) 48 Kbytes 1 Kbyte × 4 4 Kbytes PTQP0064LB-A

R5F21368CNXXXFB (D) 64 Kbytes 1 Kbyte × 4 6 Kbytes PTQP0064LB-A

R5F2136ACNXXXFB (D) 96 Kbytes 1 Kbyte × 4 8 Kbytes PTQP0064LB-A

R5F2136CCNXXXFB (D) 128 Kbytes 1 Kbyte × 4 10 Kbytes PTQP0064LB-A

R8C/36C Group 1. Overview

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Nov 02, 2010

(D): Under development

Note:

1. The user ROM is programmed before shipment.

Table 1.4 Product List for R8C/36C Group (2) Current of Nov 2010

Part No. ROM Capacity RAM

Capacity Package Type Remarks

Program

ROM Data flash

R5F21364CDFP 16 Kbytes 1 Kbyte × 4 1.5 Kbytes PLQP0064KB-A D version

R5F21365CDFP 24 Kbytes 1 Kbyte × 4 2 Kbytes PLQP0064KB-A

R5F21366CDFP 32 Kbytes 1 Kbyte × 4 2.5 Kbytes PLQP0064KB-A

R5F21367CDFP 48 Kbytes 1 Kbyte × 4 4 Kbytes PLQP0064KB-A

R5F21368CDFP 64 Kbytes 1 Kbyte × 4 6 Kbytes PLQP0064KB-A

R5F2136ACDFP 96 Kbytes 1 Kbyte × 4 8 Kbytes PLQP0064KB-A

R5F2136CCDFP 128 Kbytes 1 Kbyte × 4 10 Kbytes PLQP0064KB-A

R5F21364CDFA 16 Kbytes 1 Kbyte × 4 1. 5 Kbytes PLQP00 64 G A-A

R5F21365CDFA 24 Kbytes 1 Kbyte × 4 2 Kbytes PLQP0064GA-A

R5F21366CDFA 32 Kbytes 1 Kbyte × 4 2. 5 Kbytes PLQP00 64 G A-A

R5F21367CDFA 48 Kbytes 1 Kbyte × 4 4 Kbytes PLQP0064GA-A

R5F21368CDFA 64 Kbytes 1 Kbyte × 4 6 Kbytes PLQP0064GA-A

R5F2136ACDFA 96 Kbytes 1 Kbyte × 4 8 Kbytes PL QP 00 64 G A -A

R5F2136CCDFA 128 Kbytes 1 Kbyte × 4 10 Kbytes PLQP0064GA-A

R5F21364CDFB (D) 16 Kbytes 1 Kbyte × 4 1.5 Kbytes PTQP0064LB-A

R5F21365CDFB (D) 24 Kbytes 1 Kbyte × 4 2 Kbytes PTQP0064LB-A

R5F21366CDFB (D) 32 Kbytes 1 Kbyte × 4 2.5 Kbytes PTQP0064LB-A

R5F21367CDFB (D) 48 Kbytes 1 Kbyte × 4 4 Kbytes PTQP0064LB-A

R5F21368CDFB (D) 64 Kbytes 1 Kbyte × 4 6 Kbytes PTQP0064LB-A

R5F2136ACDFB (D) 96 Kbytes 1 Kbyte × 4 8 Kbytes PTQP0064LB-A

R5F2136CCDFB (D) 128 Kbytes 1 Kbyte × 4 10 Kbytes PTQP0064LB-A

R5F21364CDXXXFP 16 Kbytes 1 Kbyte × 4 1.5 Kbytes PLQP0064KB-A N version Factory

programming

product

R5F21365CDXXXFP 24 Kbytes 1 Kbyte × 4 2 Kbytes PLQP0064KB-A

R5F21366CDXXXFP 32 Kbytes 1 Kbyte × 4 2.5 Kbytes PLQP0064KB- A

R5F21367CDXXXFP 48 Kbytes 1 Kbyte × 4 4 Kbytes PLQP0064KB-A

R5F21368CDXXXFP 64 Kbytes 1 Kbyte × 4 6 Kbytes PLQP0064KB-A

R5F2136ACDXXXFP 96 Kbytes 1 Kbyte × 4 8 Kbytes PLQP0064KB-A

R5F2136CCDXXXFP 128 Kbytes 1 Kbyte × 4 10 Kbytes PLQP0064KB-A

R5F21364CDXXXFA 16 Kbytes 1 Kbyte × 4 1.5 Kbytes PLQP0064GA-A

R5F21365CDXXXFA 24 Kbytes 1 Kbyte × 4 2 Kbytes PLQP0064GA-A

R5F21366CDXXXFA 32 Kbytes 1 Kbyte × 4 2.5 Kbytes PLQP0064GA-A

R5F21367CDXXXFA 48 Kbytes 1 Kbyte × 4 4 Kbytes PLQP0064GA-A

R5F21368CDXXXFA 64 Kbytes 1 Kbyte × 4 6 Kbytes PLQP0064GA-A

R5F2136ACDXXXFA 96 Kbytes 1 Kbyte × 4 8 Kbytes PLQP0064GA-A

R5F2136CCDXXXFA 128 Kbytes 1 Kbyte × 4 10 Kbytes PLQP0064GA-A

R5F21364CDXXXFB (D) 16 Kbytes 1 Kbyte × 4 1.5 Kbytes PTQP0064LB-A

R5F21365CDXXXFB (D) 24 Kbytes 1 Kbyte × 4 2 Kbytes PTQP0064LB-A

R5F21366CDXXXFB (D) 32 Kbytes 1 Kbyte × 4 2.5 Kbytes PTQP0064LB-A

R5F21367CDXXXFB (D) 48 Kbytes 1 Kbyte × 4 4 Kbytes PTQP0064LB-A

R5F21368CDXXXFB (D) 64 Kbytes 1 Kbyte × 4 6 Kbytes PTQP0064LB-A

R5F2136ACDXXXFB (D) 96 Kbytes 1 Kbyte × 4 8 Kbytes PTQP0064LB-A

R5F2136CCDXXXFB (D) 128 Kbytes 1 Kbyte × 4 10 Kbytes PTQP0064LB-A

R8C/36C Group 1. Overview

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Nov 02, 2010

Figure 1.1 Part Number, Memory Size, and Package of R8C/36C Group

Part No. R 5 F 21 36 6 C N XXX FP

Package type:

FP: PLQP0064KB-A

FA: PLQP0064GA-A

FB: PTQP0064LB-A

ROM number

Classification

N: Operating ambient temperature −20°C to 85°C

D: Operating ambient temperature −40°C to 85°C

ROM capacity

4: 16 KB

5: 24 KB

6: 32 KB

7: 48 KB

8: 64 KB

A: 96 KB

C: 128 KB

R8C/36C Group

R8C/3x Serie s

Memory type

F: Flash memory

Renesas MCU

Renesas semiconductor

R8C/36C Group 1. Overview

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Nov 02, 2010

1.3 Block Diagram

Figure 1.2 shows a Block Diagram.

Figure 1.2 Block Diagram

D/A converter

(8 bits × 2)

R8C CPU core

System clock generation

circuit

XIN-XOUT

High-speed on-chip oscillator

Low-speed on-chip oscillator

XCIN-XCOUT

Memory

ROM (1)

RAM (2)

Multiplier

R0H R0L

R1H R2

R1L

USP

ISP

INTB

FLG

I/O ports

Notes:

1. ROM size v ari es wit h M CU t y pe .

2. RAM size varies with MCU type.

Timers

Timer RA (8 bits × 1)

Timer RB (8 bits × 1)

Timer RC (16 bits × 1)

Timer RD (16 bits × 2)

Timer RE (8 bits × 1)

Timer RF (16 bits × 1)

Timer RG (16 bits × 1)

UART or

clock synchronous serial I/O

(8 bits × 3)

I2C bus or SSU

(8 bits × 1)

Peripheral functions

Watchdog timer

(14 bits)

A/D converter

(10 bits × 12 channels)

LIN module

Comparat or B

Voltage detection circuit

DTC

Low-speed on-chip oscillator

for watch dog time r

Port P5

5 1

Port P4

Port P3

Port P0

Port P1

Port P2

Port P6

Port P8

R8C/36C Group 1. Overview

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Nov 02, 2010

1.4 Pin Assignment

Figure 1.3 shows Pin Assignment (Top View). Tables 1.5 and 1.6 outline the Pin Name Information by Pin Number .

Figure 1.3 Pin Assignment (Top View)

43 42 41 40 39 38 37 36

1 34567891011122

35 34 33

13 14 15 16

4445464748

R8C/36C Group

PLQP0064KB-A (64P6Q-A)

PLQP0064GA-A (64P6U-A)

PTQP0064LB-A

(Top view)

P0_7/AN0/DA1(/TRCIOC)

P0_6/AN1/DA0(/TRCIOD)

P0_5/AN2(/TRCIOB)

P0_4/AN3/TREO(/TRCIOB)

P0_3/AN4(/CLK1/TRCIOB)

P0_2/AN5(/RXD1/TRCIOA/TRCTRG)

P0_1/AN6(/TXD1/TRCIOA/TRCTRG)

P0_0/AN7(/TRCIOA/TRCTRG)

P6_4(/RXD1)

P6_3(/TXD1)

P6_2(/CLK1)

P6_1

P6_0(/TREO)

P5_7(/TRGIOB)

P5_6(/TRAO/TRGIOA)

P3_2(/INT1/INT2/TRAIO/TRGCLKB)

P8_4(/TRFO11)

P8_5(/TRFO12)

P8_6

P3_1(/TRBO)

P3_6(/INT1)

P2_0(/INT1/TRCIOB/TRDIOA0/TRDCLK)

P2_1(/TRCIOC/TRDIOC0)

P2_2(/TRCIOD/TRDIOB0)

P2_3(/TRDIOD0)

P2_4(/TRDIOA1)

P2_5(/TRDIOB1)

P2_6(/TRDIOC1)

P2_7(/TRDIOD1)

P3_3/IVCMP3/INT3/SCS(/CTS2/RTS2/TRCCLK)

P3_4/IVREF3/SSI(/RXD2/SCL2/TXD2/SDA2/TRCIOC)

P3_5/SCL/SSCK(/CLK2/TRCIOD)

P3_0(/TRAO/TRGCLKA)

P4_2/VREF

MODE

P4_3(/XCIN)

P4_4(/XCOUT)

RESET

P4_7/XOUT

VSS/AVSS

P4_6/XIN

VCC/AVCC

P5_4(/TRCIOD)

P5_3(/TRCIOC)

P5_2(/TRCIOB)

P5_1(/TRCIOA/TRCTRG)

P5_0(/TRCCLK)

P3_7/SDA/SSO/TRAO(/RXD2/SCL2/TXD2/SDA2)

P1_0/AN8/KI0(/TRCIOD)

P1_1/AN9/KI1(/TRCIOA/TRCTRG)

P1_2/AN10/KI2(/TRCIOB)

P1_3/AN11/KI3/TRBO(/TRCIOC)

P1_4(/TXD0/TRCCLK)

P1_5(/INT1/RXD0/TRAIO)

P1_6/IVREF1(/CLK0)

P1_7/IVCMP1/INT1(/TRAIO)

P4_5/ADTRG/INT0(/RXD2/SCL2)

P6_5/INT4(/CLK1/CLK2/TRCIOB)

P6_6/INT2(/TXD2/SDA2/TRCIOC)

P6_7(/INT3/TRCIOD)

P8_0(/TRFO00)

P8_1(/TRFO01)

P8_2(/TRFO02)

P8_3(/TRFI/TRFO10)

Notes:

1. Can be assigned to the pin in parentheses by a program.

2. P4_2 is an input-only pin.

3. Confirm the pin 1 position on th e package by referring to the pack age dime nsi ons.

R8C/36C Group 1. Overview

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Nov 02, 2010

Note:

1. Can be assigned to the pin in parentheses by a program.

Table 1.5 Pin Name Information by Pin Number (1)

Number Control Pin Port

I/O Pin Functions for Peripheral Mo dules

Interrupt Timer Serial

Interface SSU I2C

bus

A/D Converter,

D/A Converter,

Comparator B

1 P3_0 (TRAO/TRGCLKA)

2P4_2 VREF

3MODE

4(XCIN)P4_3

5(XCOUT)P4_4

6RESET

7XOUTP4_7

8 VSS/AVSS

9XINP4_6

10 VCC/AVCC

11 P5_4 (TRCIOD)

12 P5_3 (TRCIOC)

13 P5_2 (TRCIOB)

14 P5_1 (TRCIOA/TRCTRG)

15 P5_0 (TRCCLK)

16 P3_7 TRAO (TXD2/SDA2/

RXD2/SCL2) SSO SDA

17 P3_5 (TRCIOD) (CLK2) SSCK SCL

18 P3_4 (TRCIOC) (TXD2/SDA2/

RXD2/SCL2) SSI IVREF3

19 P3_3 INT3 (TRCCLK) (CTS2/RTS2)SCS IVCMP3

20 P2_7 (TRDIOD1)

21 P2_6 (TRDIOC1)

22 P2_5 (TRDIOB1)

23 P2_4 (TRDIOA1)

24 P2_3 (TRDIOD0)

25 P2_2 (TRCIOD/TRDIOB0)

26 P2_1 (TRCIOC/TRDIOC0)

27 P2_0 (INT1)(TRCIOB/TRDIOA0/

TRDCLK)

28 P3_6 (INT1)

29 P3_1 (TRBO)

30 P8_6

31 P8_5 (TRFO12)

32 P8_4 (TRFO11)

33 P8_3 (TRFI/TRFO10)

34 P8_2 (TRFO02)

35 P8_1 (TRFO01)

36 P8_0 (TRFO00)

37 P6_7 (INT3)(TRCIOD)

38 P6_6 INT2 (TRCIOC) (TXD2/SDA2)

39 P6_5 INT4 (TRCIOB) (CLK2/CLK1)

R8C/36C Group 1. Overview

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Nov 02, 2010

Note:

1. Can be assigned to the pin in parentheses by a program.

Table 1.6 Pin Name Information by Pin Number (2)

Number Control Pin Port

I/O Pin Functions for Peripheral Mo dules

Interrupt Timer Serial

Interface SSU I2C

bus

A/D Converter,

D/A Converter,

Comparator B

40 P4_5 INT0 (RXD2/SCL2) ADTRG

41 P1_7 INT1 (TRAIO) IVCMP1

42 P1_6 (CLK0) IVREF1

43 P1_5 (INT1) (TRAIO) (RXD0)

44 P1_4 (TRCCLK) (TXD0)

45 P1_3 KI3 TRBO

(/TRCIOC) AN11

46 P1_2 KI2 (TRCIOB) AN10

47 P1_1 KI1 (TRCIOA/TRCTRG) AN9

48 P1_0 KI0 (TRCIOD) AN8

49 P0_7 (TRCIOC) AN0/DA1

50 P0_6 (TRCIOD) AN1/DA0

51 P0_5 (TRCIOB) AN2

52 P0_4 TREO(/TRCIOB) AN3

53 P0_3 (TRCIOB) (CLK1) AN4

54 P0_2 (TRCIOA/TRCTRG) (RXD1) AN5

55 P0_1 (TRCIOA/TRCTRG) (TXD1) AN6

56 P0_0 (TRCIOA/TRCTRG) AN7

57 P6_4 (RXD1)

58 P6_3 (TXD1)

59 P6_2 (CLK1)

60 P6_1

61 P6_0 (TREO)

62 P5_7 (TRGIOB)

63 P5_6 (TRAO/TRGIOA)

64 P3_2 (INT1/

INT2)(TRAIO/TRGCLKB)

R8C/36C Group 1. Overview

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1.5 Pin Functions

Tables 1.7 and 1.8 list Pin Functions.

I: Input O: Output I/O: Input and output

Note:

1. Refer to the oscillator manufacturer for oscillation characteristics.

Table 1.7 Pin Functions (1)

Item Pin Name I/O Type Description

Power supply input VCC, VSS —Apply 1.8 to 5.5 V to the VCC pin.

Apply 0 V to the VSS pin.

Analog power

supply input AVCC, AVSS —Power supply for the A/D converter.

Connect a capacitor between AVCC and AVSS.

Reset input RESET IInput “L” on this pin resets the MCU.

MODE MODE I Connect this pin to VCC via a resistor.

XIN clock input XIN I These pins are provided for XIN clock generation circuit I/O.

Connect a ceramic resonator or a crystal oscillator between

the XIN and XOUT pins. (1)

To use an external clock, input it to the XOUT pin and leave

the XIN pin open.

XIN clock output XOUT

I/O

XCIN clock input XCIN I These pins are provided for XCIN clock generation circuit I/O.

Connect a crystal oscillator between the XCIN and XCOUT

pins. (1)

To use an external clock, input it to the XCIN pin and leave

the XCOUT pin open.

XCIN clock output XCOUT

INT interrupt input INT0 to INT4 IINT interrupt input pins.

Key input interrupt KI0 to KI3 IKey input interrupt input pins.

Timer RA TRAIO I/O Timer RA I/O pin.

TRAO O Timer RA output pin.

Timer RB TRBO O Timer RB output pin.

Timer RC TRCCLK I External clock input pin.

TRCTRG I External trigger input pin.

TRCIOA, TRCIOB,

TRCIOC, TRCIOD I/O Timer RC I/O pins.

Timer RD TRDIOA0, TRDIOA1,

TRDIOB0, TRDIOB1,

TRDIOC0, TRDIOC1,

TRDIOD0, TRDIOD1

I/O

Timer RD I/O pins.

TRDCLK I External clock input pin.

Timer RE TREO O Divided clock output pin.

Timer RF TRFO00, TRFO1 0,

TRFO01,TRFO11,

TRFO02,TRFO12 OTimer RF output pins.

TRFI I Timer RF input pin.

Timer RG TRGIOA, TRGIOB I/O Timer RG I/O ports.

TRGCLKA, TRGCLKB I External clock input pins.

Serial interface CLK0, CLK1, CLK2 I/O Transfer clock I/O pins.

RXD0, RXD1, RXD2 I Serial data input pins.

TXD0, TXD1, TXD2 O Serial data output pins.

CTS2 ITransmission control input pin.

RTS2 OReception control output pin.

SCL2 I/O I2C mode clock I/O pin.

SDA2 I/O I2C mode data I/O pin.

R8C/36C Group 1. Overview

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Nov 02, 2010

I: Input O: Output I/O: Input and output

Table 1.8 Pin Functions (2)

Item Pin Name I/O Type Description

SSU SSI I/O Data I/O pin.

SCS I/O Chip-select signal I/O pin.

SSCK I/O Clock I/O pin.

SSO I/O Data I/O pin.

I2C bus SCL I/O Clock I/O pin

SDA I/O Data I/O pin

Reference voltage

input VREF I Reference voltage input pin to A/D converter.

A/D converter AN0 to AN11 I Analog input pins to A/D converter.

ADTRG I AD external trigger input pin.

D/A converter DA0, DA1 O D/A converter output pins.

Comparator B IVCMP1, IVCMP3 I Comparator B analog voltage input pins.

IVREF1, IVREF3 I Comparator B reference voltage input pins.

I/O port P0_0 to P0_7,

P1_0 to P1_7,

P2_0 to P2_7,

P3_0 to P3_7,

P4_3 to P4_7,

P5_0 to P5_4,

P5_6, P5_7,

P6_0 to P6_7,

P8_0 to P8_6

I/O CMOS I/O ports. Each port has an I/O select direction

or output individually.

Any port set to input can be set to use a pull-up resistor or not

by a program.

Input port P4_2 I Input-only port.

R8C/36C Group 2. Central Processing Unit (CPU)

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Nov 02, 2010

2. Central Processing Unit (CPU)

Figure 2.1 shows the CPU Registers. Th e CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a

Figure 2.1 CPU Registers

b31 b15 b8b7 b0

Data registers (1)

Address registers (1)

R3 R0H (high-order of R0)

INTBHb15b19 b0

INTBL

FB Frame base register (1)

The 4 high order bits of INTB are INTBH and

the 16 low order bits of INTB are INTBL.

Interrupt table regist er

b19 b0

USP

Program counter

ISP

User stack pointer

Interrupt stack pointer

Static base regis ter

FLG Flag register

Carry flag

Debug flag

Zero flag

Sign flag

Overflow flag

Interrupt enable flag

Stack pointer select flag

Reserved bit

Processor interrupt priority level

Reserved bit

IPL DZSBOIU

b15 b0

b8 b7

Note:

1. These registers comprise a register bank. There are two register banks.

R1H (high-order of R1)

R0L (low-order of R0)

R1L (low-order of R1)

R8C/36C Group 2. Central Processing Unit (CPU)

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2.1 Data Registers (R0, R1, R2, and R3)

R0 is a 16-bit register for transfer, arithmetic, and logic op erations. The sam e applies to R1 to R3. R0 can be split

into high-order bits (R0H) and low-order bits (R0L) to be used separat ely as 8-bit dat a reg isters. R1H and R1L are

analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is

analogous to R2R0.

2.2 Address Registers (A0 and A1)

A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also

used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32-

bit address register (A1A0).

2.3 Frame Base Register (FB)

FB is a 16-bit register for FB relative addressing.

2.4 Interrupt Table Register (INTB)

INTB is a 20-bit register that indicates the starting address of an interrupt vector table.

2.5 Program Counter (PC)

PC is 20 bits wide and indicates the address of the next instruction to be executed.

2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)

The stack pointers (SP), USP and ISP, are each 16 bits wide. The U flag of FLG is used to switch between

USP and ISP.

2.7 Static Base Register (SB)

SB is a 16-bit register for SB relative addressing.

2.8 Flag Register (FLG)

FLG is an 11-bit register indicating the CPU state.

2.8.1 Carry Flag (C)

The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic un it.

2.8.2 Debug Flag (D)

The D flag is for debugging only. Set it to 0.

2.8.3 Zero Flag (Z)

The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.

2.8.4 Sign Flag (S)

The S flag is set to 1 when an arithmetic operation results in a negative valu e; otherwise to 0.

2.8.5 Register Bank Select Flag (B)

2.8.6 Overflow Flag (O)

The O flag is set to 1 when an operation results in an overflow; otherwise to 0.

R8C/36C Group 2. Central Processing Unit (CPU)

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Nov 02, 2010

2.8.7 Interrupt Enable Flag (I)

The I flag enables maskable interrupts.

Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0

when an interrupt request is acknowledged.

2.8.8 Stack Pointer Select Flag (U)

ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.

The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software

interrupt numbers 0 to 31 is executed.

2.8.9 Processor Interrupt Priority Leve l (IPL)

IPL is 3 bits wide and assigns processor interrupt prio rity levels from level 0 to level 7.

If a requested interrupt has higher priori ty than IPL, the interrupt is enabled.

2.8.10 Reserved Bit

If necessary, set to 0. When read, the content is undefined.

R8C/36C Group 3. Memory

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Nov 02, 2010

3. Memory

3.1 R8C/36C Group

Figure 3.1 is a Memory Map of R8C/36C Group. The R8C/36C Group has a 1-Mbyte address space from address es

00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address

0FFFFh. For example, a 64-Kbyte internal ROM area is allocated addresses 04000h to 13FFFh.

The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. The starting address of each interrupt

routine is stored here.

The internal ROM (data flash) is allocated addresses 03000h to 03FFFh.

The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 6-Kbyte internal

RAM area is allocated addresses 00400h to 01BFFh. The internal RAM is used not only for data storage but also as

a stack area when a subroutine is called or when an interrupt request is acknowledged.

Special function registers (SFRs) are allocated addresses 00000h to 002FFh and 02C00h to 02FFFh (the SFR areas

for the DTC and other modules). Peripheral function control registers are allocated here. All unallocated spaces

within the SFRs are reserved and cannot be accessed by users.

R8C/36C Group 3. Memory

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Nov 02, 2010

Figure 3.1 Memory Map of R8C/36C Group

0FFFFh

0FFDCh

Notes:

1. The data flash indicat es block A (1 Kbyte), block B (1 Kbyte), block C (1 Kbyt e), and block D (1 Kbyte).

2. The SFR areas for the DTC and other modules are allocated to addresses 02C00h t o 02FFFh.

3. The blank areas are reserved and cannot be accessed by use rs.

Internal RAM

Size Address 0XXXXh

1.5 Kbytes

2 Kbytes

2.5 Kbytes

4 Kbytes

6 Kbytes

8 Kbytes

10 Kbytes

009FFh

00BFFh

00DFFh

013FFh

01BFFh

023FFh

02BFFh

Part Number Internal ROM

Size Ad dr e s s 0Y YYY h

R5F21364CNFP, R5F21364CDFP, R5F21364CNFA,

R5F21364CDFA, R5F21364CNFB, R5F21364CDFB,

R5F21364CNXXXFP, R5F21364CDXXXFP,

R5F21364CNXXXFA, R5F21364CDXXXFA,

R5F21364CNXXXFB, R5F21364CDXXXFB

R5F21365CNFP, R5F21365CDFP, R5F21365CNFA,

R5F21365CDFA, R5F21365CNFB, R5F21365CDFB,

R5F21365CNXXXFP, R5F21365CDXXXFP,

R5F21365CNXXXFA, R5F21365CDXXXFA,

R5F21365CNXXXFB, R5F21365CDXXXFB

R5F21366CNFP, R5F21366CDFP, R5F21366CNFA,

R5F21366CDFA, R5F21366CNFB, R5F21366CDFB,

R5F21366CNXXXFP, R5F21366CDXXXFP,

R5F21366CNXXXFA, R5F21366CDXXXFA,

R5F21366CNXXXFB, R5F21366CDXXXFB

R5F21367CNFP, R5F21367CDFP, R5F21367CNFA,

R5F21367CDFA, R5F21367CNFB, R5F21367CDFB,

R5F21367CNXXXFP, R5F21367CDXXXFP,

R5F21367CNXXXFA, R5F21367CDXXXFA,

R5F21367CNXXXFB, R5F21367CDXXXFB

R5F21368CNFP, R5F21368CDFP, R5F21368CNFA,

R5F21368CDFA, R5F21368CNFB, R5F21368CDFB,

R5F21368CNXXXFP, R5F21368CDXXXFP,

R5F21368CNXXXFA, R5F21368CDXXXFA,

R5F21368CNXXXFB, R5F21368CDXXXFB

R5F2136ACNFP, R5F2136ACDFP, R5F2136ACNFA,

R5F2136ACDFA, R5F2136ACNFB, R5F2136ACDFB,

R5F2136ACNXXXFP, R5F2136ACDXXXFP,

R5F2136ACNXXXFA, R5F2136ACDXXXFA,

R5F2136ACNXXXFB, R5F2136ACDXXXFB

R5F2136CCNFP, R5F2136CCDFP, R5F2136CCNFA,

R5F2136CCDFA, R5F2136CCNFB, R5F2136CCDFB,

R5F2136CCNXXXFP, R5F2136CCDXXXFP,

R5F2136CCNXXXFA, R5F2136CCDXXXFA,

R5F2136CCNXXXFB, R5F2136CCDXXXFB

16 Kbytes

24 Kbytes

32 Kbytes

48 Kbytes

64 Kbytes

96 Kbytes

128 Kbytes

0C000h

0A000h

08000h

04000h

Address ZZZZZh

–

13FFFh

1BFFFh

23FFFh

FFFFFh

0FFFFh

0YYYYh

0XXXXh

00400h

002FFh

00000h

Internal ROM

(program ROM)

Internal RAM

SFR

(Refer to 4. Special Function

Regi sters ( SFRs))

02FFFh

02C00h SFR (2)

(Refer to 4. Special Function

Regi sters ( SFRs))

ZZZZZh

03FFFh

03000h Internal ROM

(data flash) (1)

Internal ROM

(program ROM)

Undefined instruction

Overflow

BRK instruction

Address match

Single step

Watchdog timer, oscillation stop detect ion, voltage monitor

Address break

(Reserved)

Reset

R8C/36C Group 4. Special Function Registers (SFRs)

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4. Special Function Registers (SFRs)

An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.12 list the special

function registers. Table 4.13 lists the ID Code Areas and Option Function Select Area.

Table 4.1 SFR Information (1) (1)

X: Undefined

Notes:

1. The blank areas are reserved and cannot be accessed by users.

2. The CWR bit in the RSTFR register is set to 0 after power-on and voltage monitor 0 reset. Hardwar e reset, software reset, or watchdog timer

reset does not affect this bit.

3. The CSPROINI bit in the OFS register is set to 0.

4. The LVDAS bit in the OFS register is set to 1.

5. The LVDAS bit in the OFS register is set to 0.

Address Register Symbol After Reset

0000h

0001h

0002h

0003h

0004h Processor Mode Register 0 PM0 00h

0005h Processor Mode Register 1 PM1 00h

0006h System Clock Control Register 0 CM0 00101000b

0007h System Clock Control Register 1 CM1 00100000b

0008h Module Standby Control Register MSTCR 00h

0009h System Clock Control Register 3 CM3 00h

000Ah Protect Register PRCR 00h

000Bh Reset Source Determination Register RSTFR 0XXXXXXXb (2)

000Ch Oscillation Stop Detection Register OCD 00000100b

000Dh Watchdog Ti mer Reset Register WDTR XXh

000Eh Watchdog Timer Start Register WDTS XXh

000Fh Watchdog Timer Control Register WDTC 00111111b

0010h

0011h

0012h

0013h

0014h

0015h High-Speed On-Chip Oscillator Control Register 7 FRA7 When shipping

0016h

0017h

0018h

0019h

001Ah

001Bh

001Ch Count Source Protect ion Mode Register CSPR 00h

10000000b (3)

001Dh

001Eh

001Fh

0020h

0021h

0022h

0023h High-Speed On-Chip Oscillator Control Register 0 FRA0 00h

0024h High-Speed On-Chip Oscillator Control Register 1 FRA1 When shipping

0025h High-Speed On-Chip Oscillator Control Register 2 FRA2 00h

0026h On-Chip Reference Voltage Control Register OCVREFCR 00h

0027h

0028h Clock Prescaler Reset Flag CPSRF 00h

0029h High-Speed On-Chip Oscillator Control Register 4 FRA4 When shipping

002Ah High-Speed On-Chip Oscillator Control Register 5 FRA5 When shipping

002Bh High-Speed On-Chip Oscillator Control Register 6 FRA6 When shipping

002Ch

002Dh

002Eh

002Fh High-Speed On-Chip Oscillator Control Register 3 FRA3 When shipping

0030h Voltage Monitor Circuit Cont rol Register CMPA 00h

0031h Voltage Monitor Circuit Edge Select Register VCAC 00h

0032h

0033h Voltage Detect Register 1 VCA1 00001000b

0034h Voltage Detect Register 2 VCA2 00h (4)

00100000b (5)

0035h

0036h Voltage Detection 1 Level Select Register VD1LS 00000111b

0037h

0038h Voltage Monitor 0 Circuit Control Register VW0C 1100X010b (4)

1100X011b (5)

0039h Voltage Monitor 1 Circuit Control Register VW1C 10001010b

R8C/36C Group 4. Special Function Registers (SFRs)

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Nov 02, 2010

Table 4.2 SFR Information (2) (1)

X: Undefined

Notes:

1. The blank areas are reserved and cannot be accessed by users.

2. Selectable by the IICSEL bit in the SSUIICSR register.

Address Register Symbol After Reset

003Ah Voltage Monitor 2 Circuit Control Register VW2C 10000010b

003Bh

003Ch

003Dh

003Eh

003Fh

0040h

0041h Flash Memory Ready Interrupt Control Regi ster FMRDYIC XXXXX000b

0042h

0043h

0044h

0045h

0046h INT4 Interrupt Control Register INT4IC XX00X000b

0047h Timer RC Interrupt Control Register TRCIC XXXXX000b

0048h Timer RD0 Interrupt Control Register TRD0IC XXXXX000b

0049h Timer RD1 Interrupt Control Register TRD1IC XXXXX000b

004Ah Timer RE Interrupt Control Register TREIC XXXXX000b

004Bh UART2 Transmit Interrupt Control Register S2TIC XXXXX000b

004Ch UART2 Receive Interrupt Control Register S2RIC XXXXX000b

004Dh Key Input In terrupt Control Register KUPIC XXXXX000b

004Eh A/D Conversion Interrupt Control Register ADIC XXXXX000b

004Fh SSU Interrupt Control Register/IIC bus Interrupt Control Register (2) SSUIC/IICIC XXXXX000b

0050h Timer RF Compare 1 Interrupt Control Register CMP1IC XXXXX000b

0051h UART0 Transmit Interrupt Control Regist er S0TIC XXXXX000b

0052h UART0 Receive Interrupt Control Register S0RIC XXXXX000b

0053h UART1 Transmit Interrupt Control Regist er S1TIC XXXXX000b

0054h UART1 Receive Interrupt Control Register S1RIC XXXXX000b

0055h INT2 Interrupt Control Register INT2IC XX00X000b

0056h Timer RA Interrupt Control Register TRAIC XXXXX000b

0057h

0058h Timer RB Interrupt Control Register TRBIC XXXXX000b

0059h INT1 Interrupt Control Register INT1IC XX00X000b

005Ah INT3 Interrupt Control Register INT3IC XX00X000b

005Bh Timer RF Interrupt Control Register TRFIC XXXXX000b

005Ch Timer RF Compare 0 Interrupt Control Register CMP0IC XXXXX000b

005Dh INT0 Interrupt Control Register INT0IC XX00X000b

005Eh UART2 Bus Collision Detect ion Interrupt Control Register U2BCNIC XXXXX000b

005Fh Timer RF Capture Interrupt Control Register CAPIC XXXXX000b

0060h

0061h

0062h

0063h

0064h

0065h

0066h

0067h

0068h

0069h

006Ah

006Bh Timer RG Interrupt Control Register TRGIC XXXXX000b

006Ch

006Dh

006Eh

006Fh

0070h

0071h

0072h Voltage Monitor 1 Interrupt Control Register VCMP1IC XXXXX000b

0073h Voltage Monitor 2 Interrupt Control Register VCMP2IC XXXXX000b

0074h

0075h

0076h

0077h

0078h

0079h

007Ah

007Bh

007Ch

007Dh

007Eh

007Fh

R8C/36C Group 4. Special Function Registers (SFRs)

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Nov 02, 2010

Table 4.3 SFR Information (3) (1)

X: Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

Address Register Symbol After Reset

0080h DTC Activation Control Register DTCTL 00h

0081h

0082h

0083h

0084h

0085h

0086h

0087h

0088h DTC Activation Enable Register 0 DTCEN0 00h

0089h DTC Activation Enable Register 1 DTCEN1 00h

008Ah DTC Activation Enable Register 2 DTCEN2 00h

008Bh DTC Activation Enable Register 3 DTCEN3 00h

008Ch DTC Activation Enable Register 4 DTCEN4 00h

008Dh DTC Activation Enable Register 5 DTCEN5 00h

008Eh DTC Activation Enable Register 6 DTCEN6 00h

008Fh

0090h Timer RF Register TRF 00h

00h0091h

0092h

0093h

0094h

0095h

0096h

0097h

0098h

0099h

009Ah Timer RF Control Register 0 TRFCR0 00h

009Bh Timer RF Control Register 1 TRFCR1 00h

009Ch Capture and Compa re 0 Re gister TRFM0 00h

00h009Dh

009Eh Compare 1 Register TRFM1 FFh

FFh009Fh

00A0h UART0 Transmit/Receive Mode Register U0MR 00h

00A1h UART0 Bit Rate Register U0BRG XXh

00A2h UART0 Transmit Buffer Register U0TB XXh

XXh00A3h

00A4h UART0 Transmit/Receive Control Register 0 U0C0 00001000b

00A5h UART0 Transmit/Receive Control Register 1 U0C1 00000010b

00A6h UART0 Receive Buffer Register U0RB XXh

XXh00A7h

00A8h UART2 Transmit/Receive Mode Register U2MR 00h

00A9h UART2 Bit Rate Register U2BRG XXh

00AAh UART2 Transmit Buffer Register U2TB XXh

XXh00ABh

00ACh UART2 Transmit/Receive Control Register 0 U2C0 00001000b

00ADh UART2 Transmit/Receive Control Register 1 U2C1 00000010b

00AEh UART2 Receive Buffer Register U2RB XXh

XXh00AFh

00B0h UART2 Digital Filter Function Select Register URXDF 00h

00B1h

00B2h

00B3h

00B4h

00B5h

00B6h

00B7h

00B8h

00B9h

00BAh

00BBh UART2 Special Mode Register 5 U2SMR5 00h

00BCh UART2 Special Mode Register 4 U2SMR4 00h

00BDh UART2 Special Mode Register 3 U2SMR3 000X0X0Xb

00BEh UART2 Special Mode Register 2 U2SMR2 X0000000b

00BFh UART2 Special Mode Register U2SMR X0000000b

R8C/36C Group 4. Special Function Registers (SFRs)

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Nov 02, 2010

Table 4.4 SFR Information (4) (1)

X: Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

Address Register Symbol After Reset

00C0h A/D Register 0 AD0 XXh

000000XXb

00C1h

00C2h A/D Register 1 AD1 XXh

000000XXb

00C3h

00C4h A/D Register 2 AD2 XXh

000000XXb

00C5h

00C6h A/D Register 3 AD3 XXh

000000XXb

00C7h

00C8h A/D Register 4 AD4 XXh

000000XXb

00C9h

00CAh A/D Register 5 AD5 XXh

000000XXb

00CBh

00CCh A/D Register 6 AD6 XXh

000000XXb

00CDh

00CEh A/D Register 7 AD7 XXh

000000XXb

00CFh

00D0h

00D1h

00D2h

00D3h

00D4h A/D Mode Register ADMOD 00h

00D5h A/D Input Select Register ADINSEL 11000000b

00D6h A/D Control Register 0 ADCON0 00h

00D7h A/D Control Register 1 ADCON1 00h

00D8h D/A0 Register DA0 00h

00D9h D/A1 Register DA1 00h

00DAh

00DBh

00DCh D/A Control Register DACON 00h

00DDh

00DEh

00DFh

00E0h Port P0 Register P0 XXh

00E1h Port P1 Register P1 XXh

00E2h Port P0 Direction Register PD0 00h

00E3h Port P1 Direction Register PD1 00h

00E4h Port P2 Register P2 XXh

00E5h Port P3 Regi st er P3 XXh

00E6h Port P2 Direction Register PD2 00h

00E7h Port P3 Direction Register PD3 00h

00E8h Port P4 Regi st er P4 XXh

00E9h Port P5 Register P5 XXh

00EAh Port P4 Direction Register PD4 00h

00EBh Port P5 Direction Register PD5 00h

00ECh Port P6 Register P6 XXh

00EDh

00EEh Port P6 Direction Register PD6 00h

00EFh

00F0h Port P8 Register P8 XXh

00F1h

00F2h Port P8 Direction Register PD8 00h

00F3h

00F4h

00F5h

00F6h

00F7h

00F8h

00F9h

00FAh

00FBh

00FCh

00FDh

00FEh

00FFh

R8C/36C Group 4. Special Function Registers (SFRs)

R01DS0018EJ0110 Rev.1.10 Page 22 of 59

Nov 02, 2010

Table 4.5 SFR Information (5) (1)

Note:

1. The blank areas are reserved and cannot be accessed by users.

Address Register Symbol After Reset

0100h Timer RA Control Register TRACR 00h

0101h Timer RA I/O Control Register TRAIOC 00h

0102h Timer RA Mode Register TRAMR 00h

0103h Timer RA Prescaler Register TRAPRE FFh

0104h Timer RA Register TRA FFh

0105h LIN Control Register 2 LINCR2 00h

0106h LIN Control Register LINCR 00h

0107h LIN Status Register LINST 00h

0108h Timer RB Control Register TRBCR 00h

0109h Timer RB One-Shot Control Register TRBOCR 00h

010Ah Timer RB I/O Control Register TRBIOC 00h

010Bh Timer RB Mode Register TRBMR 00h

010Ch Timer RB Prescaler Register TRBPRE FFh

010Dh Timer RB Secondary Register TRBSC FFh

010Eh Timer RB Primary Register TRBPR FFh

010Fh

0110h

0111h

0112h

0113h

0114h

0115h

0116h

0117h

0118h Timer RE Second Data Register / Counter Data Register TRESEC 00h

0119h Timer RE Minute Data Register / Compare Data Register TREMIN 00h

011Ah Timer RE Hour Data Register TREHR 00h

011Bh Timer RE Day of Week Data Register TREWK 00h

011Ch Timer RE Control Register 1 TRECR1 00h

011Dh Timer RE Control Register 2 TRECR2 00h

011Eh Timer RE Count Source Select Register TRECSR 00001000b

011Fh

0120h Timer RC Mode Register TRCMR 01001000b

0121h Timer RC Control Register 1 TRCCR1 00h

0122h Timer RC Interrupt Enable Register TRCIER 01110000b

0123h Timer RC Status Register TRCSR 01110000b

0124h Timer RC I/O Control Register 0 TRCIOR0 10001000b

0125h Timer RC I/O Control Register 1 TRCIOR1 10001000b

0126h Timer RC Counter TRC 00h

00h0127h

0128h Timer RC General Register A TRCGRA FFh

FFh0129h

012Ah Timer RC General Register B TRCGRB FFh

FFh012Bh

012Ch Timer RC General Register C TRCGRC FFh

FFh012Dh

012Eh Timer RC General Register D TRCGRD FFh

FFh012Fh

0130h Timer RC Control Register 2 TRCCR2 000110 00b

0131h Timer RC Digital Filter Function Select Register TRCDF 00h

0132h Timer RC Output Master Enable Register TRCOER 01111111b

0133h Timer RC Trigger Control Register TRCADCR 00h

0134h

0135h Timer RD Control Expansion Register TRDECR 00h

0136h Timer RD Trigger Control Register TRDADCR 00h

0137h Timer RD Start Register TRDSTR 11111100b

0138h Timer RD Mode Register TRDMR 00001110b

0139h Timer RD PWM Mode Register TRDPMR 100010 00b

013Ah Timer RD Function Control Register TRDFCR 10000000b

013Bh Timer RD Output Master Enable Register 1 TRDOER1 FFh

013Ch Timer RD Output Master Enable Register 2 TRDOER2 01111111b

013Dh Timer RD Output Control Register TRDOCR 00h

013Eh Timer RD Digital Filter Function Select Register 0 TRDDF0 00h

013Fh Timer RD Digital Filter Function Select Register 1 TRDDF1 00h

R8C/36C Group 4. Special Function Registers (SFRs)

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Nov 02, 2010

Table 4.6 SFR Information (6) (1)

X: Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

Address Register Symbol After Reset

0140h Timer RD Control Register 0 TRDCR0 00h

0141h Timer RD I/O Control Register A0 TRDIORA0 10001000b

0142h Timer RD I/O Control Register C0 TRDIORC0 10001000b

0143h Timer RD Status Register 0 TRDSR0 11100000b

0144h Timer RD Interrupt Enable Register 0 TRDIER0 11100000b

0145h Timer RD PWM Mode Output Level Control Register 0 TRDPOCR0 11111000b

0146h Timer RD Counter 0 TRD0 00h

00h

0147h

0148h Timer RD General Register A0 TRDGRA0 FFh

FFh

0149h

014Ah Timer RD General Register B0 TRDGRB0 FFh

FFh

014Bh

014Ch Timer RD General Register C0 TRDGRC0 FFh

FFh

014Dh

014Eh Timer RD General Register D0 TRDGRD0 FFh

FFh

014Fh

0150h Timer RD Control Register 1 TRDCR1 00h

0151h Timer RD I/O Control Register A1 TRDIORA1 10001000b

0152h Timer RD I/O Control Register C1 TRDIORC1 10001000b

0153h Timer RD Status Register 1 TRDSR1 11000000b

0154h Timer RD Interrupt Enable Register 1 TRDIER1 11100000b

0155h Timer RD PWM Mode Output Level Control Register 1 TRDPOCR1 11111000b

0156h Timer RD Counter 1 TRD1 00h

00h

0157h

0158h Timer RD General Register A1 TRDGRA1 FFh

FFh

0159h

015Ah Timer RD General Register B1 TRDGRB1 FFh

FFh

015Bh

015Ch Timer RD General Register C1 TRDGRC1 FFh

FFh

015Dh

015Eh Timer RD General Register D1 TRDGRD1 FFh

FFh

015Fh

0160h UART1 Transmit/Receive Mode Register U1MR 00h

0161h UART1 Bit Rate Register U1BRG XXh

0162h UART1 Transmit Buffer Register U1TB XXh

XXh

0163h

0164h UART1 Transmit/Receive Control Register 0 U1C0 00001000b

0165h UART1 Transmit/Receive Control Register 1 U1C1 00000010b

0166h UART1 Receive Buffer Register U1RB XXh

XXh

0167h

0168h

0169h

016Ah

016Bh

016Ch

016Dh

016Eh

016Fh

0170h Timer RG Mode Register TRGMR 01000000b

0171h Timer RG Count Control Register TRGCNTC 00h

0172h Timer RG Control Register TRGCR 10000000b

0173h Timer RG Interrupt Enable Register TRGIER 11110000b

0174h Timer RG Status Register TRGSR 11100000b

0175h Timer RG I/O Control Register TRGIOR 00h

0176h Timer RG Counter TRG 00h

00h

0177h

0178h Timer RG General Register A TRGGRA FFh

FFh

0179h

017Ah Timer RG General Register B TRGGRB FFh

FFh

017Bh

017Ch Timer RG General Register C TRGGRC FFh

FFh

017Dh

017Eh Timer RG General Register D TRGGRD FFh

FFh

017Fh

R8C/36C Group 4. Special Function Registers (SFRs)

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Nov 02, 2010

Table 4.7 SFR Information (7) (1)

X: Undefined

Notes:

1. The blank areas are reserved and cannot be accessed by users.

2. Selectable by the IICSEL bit in the SSUIICSR register.

Address Register Symbol After Reset

0180h Timer RA Pin Select Register TRASR 00h

0181h Timer RB/RC Pin Select Register TRBRCSR 00h

0182h Timer RC Pin Select Register 0 TRCPSR0 00h

0183h Timer RC Pin Select Register 1 TRCPSR1 00h

0184h Timer RD Pin Select Register 0 TRDPSR0 00h

0185h Timer RD Pin Select Register 1 TRDPSR1 00h

0186h Timer Pin Select Register TIMSR 00h

0187h Timer RF Output Control Register TRFOUT 00h

0188h UART0 Pin Select Register U0SR 00h

0189h UART1 Pin Select Register U1SR 00h

018Ah UART2 Pin Select Register 0 U2SR0 00h

018Bh UART2 Pin Select Register 1 U2SR1 00h

018Ch SSU/IIC Pin Select Register SSUIICSR 00h

018Dh

018Eh INT Interrupt Input Pin Select Register INTSR 00h

018Fh I/O Function Pin Select Register PINSR 00h

0190h

0191h

0192h

0193h SS Bit Counter Register SSBR 11111000b

0194h SS Transmit Data Register L / IIC bus Transmit Data Register (2) SSTDR / ICDRT FFh

0195h SS Transmit Data Register H (2) SSTDRH FFh

0196h SS Receive Data Register L / IIC bus Receive Data Register (2) SSRDR / ICDRR FFh

0197h SS Receive Data Register H (2) SSRDRH FFh

0198h SS Control Register H / IIC bus Control Register 1 (2) SSCRH / ICCR1 00h

0199h SS Control Register L / IIC bus Control Regist er 2 (2) SSCRL / ICCR2 01111101b

019Ah SS Mode Register / IIC bus Mode Register (2) SSMR / ICMR 00010000b / 00011000b

019Bh SS Enable Register / IIC bus Interrupt Enable Register (2) SSER / ICIER 00h

019Ch SS Status Register / IIC bus Status Register (2) SSSR / ICS R 00h / 0000X000b

019Dh SS Mode Register 2 / Slave Address Register (2) SSMR2 / SAR 00h

019Eh

019Fh

01A0h

01A1h

01A2h

01A3h

01A4h

01A5h

01A6h

01A7h

01A8h

01A9h

01AAh

01ABh

01ACh

01ADh

01AEh

01AFh

01B0h

01B1h

01B2h Flash Memory Status Register FST 10000X00b

01B3h

01B4h Flash Memory Control Register 0 FMR0 00h

01B5h Flash Memory Control Register 1 FMR1 00h

01B6h Flash Memory Control Register 2 FMR2 00h

01B7h

01B8h

01B9h

01BAh

01BBh

01BCh

01BDh

01BEh

01BFh

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Nov 02, 2010

Table 4.8 SFR Information (8) (1)

X: Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

Address Register Symbol After Reset

01C0h Address Match Interrupt Register 0 RMAD0 XXh

XXh

0000XXXXb

01C1h

01C2h

01C3h Address Match Interrupt Enable Register 0 AIER0 00h

01C4h Address Match Interrupt Register 1 RMAD1 XXh

XXh

0000XXXXb

01C5h

01C6h

01C7h Address Match Interrupt Enable Register 1 AIER1 00h

01C8h

01C9h

01CAh

01CBh

01CCh

01CDh

01CEh

01CFh

01D0h

01D1h

01D2h

01D3h

01D4h

01D5h

01D6h

01D7h

01D8h

01D9h

01DAh

01DBh

01DCh

01DDh

01DEh

01DFh

01E0h Pull-Up Control Register 0 PUR0 00h

01E1h Pull-Up Control Register 1 PUR1 00h

01E2h Pull-Up Control Register 2 PUR2 00h

01E3h

01E4h

01E5h

01E6h

01E7h

01E8h

01E9h

01EAh

01EBh

01ECh

01EDh

01EEh

01EFh

01F0h Port P1 Drive Capacity Control Register P1DRR 00h

01F1h Port P2 Drive Capacity Control Register P2DRR 00h

01F2h Drive Capacity Control Register 0 DRR0 00h

01F3h Drive Capacity Control Register 1 DRR1 00h

01F4h Drive Capacity Control Register 2 DRR2 00h

01F5h Input Threshold Control Register 0 VLT0 00h

01F6h Input Threshold Control Register 1 VLT1 00h

01F7h Input Threshold Control Register 2 VLT2 00h

01F8h Comparator B Control Register 0 INTCMP 00h

01F9h

01FAh External Input Enable Register 0 INTEN 00h

01FBh External Input Enable Register 1 INTEN1 00h

01FCh INT Input Filter Select Register 0 INTF 00h

01FDh INT Input Filter Select Register 1 INTF1 00h

01FEh Key Input Enable Register 0 KIEN 00h

01FFh

R8C/36C Group 4. Special Function Registers (SFRs)

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Nov 02, 2010

Table 4.9 SFR Information (9) (1)

X: Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

Address Register Symbol After Reset

2C00h DTC Transfer Vector Area XXh

2C01h DTC Transfer Vector Area XXh

2C02h DTC Transfer Vector Area XXh

2C03h DTC Transfer Vector Area XXh

2C04h DTC Transfer Vector Area XXh

2C05h DTC Transfer Vector Area XXh

2C06h DTC Transfer Vector Area XXh

2C07h DTC Transfer Vector Area XXh

2C08h DTC Transfer Vector Area XXh

2C09h DTC Transfer Vector Area XXh

2C0Ah DTC Transfer Vector Area XXh

: DTC Transfer Vector Area XXh

2C3Ah DTC Transfer Vector Area XXh

2C3Bh DTC Transfer Vector Area XXh

2C3Ch DTC Transfer Vector Area XXh

2C3Dh DTC Transfer Vector Area XXh

2C3Eh DTC Transfer Vector Area XXh

2C3Fh DTC Transfer Vector Area XXh

2C40h DTC Control Data 0 DTCD0 XXh

2C41h XXh

2C42h XXh

2C43h XXh

2C44h XXh

2C45h XXh

2C46h XXh

2C47h XXh

2C48h DTC Control Data 1 DTCD1 XXh

2C49h XXh

2C4Ah XXh

2C4Bh XXh

2C4Ch XXh

2C4Dh XXh

2C4Eh XXh

2C4Fh XXh

2C50h DTC Control Data 2 DTCD2 XXh

2C51h XXh

2C52h XXh

2C53h XXh

2C54h XXh

2C55h XXh

2C56h XXh

2C57h XXh

2C58h DTC Control Data 3 DTCD3 XXh

2C59h XXh

2C5Ah XXh

2C5Bh XXh

2C5Ch XXh

2C5Dh XXh

2C5Eh XXh

2C5Fh XXh

2C60h DTC Control Data 4 DTCD4 XXh

2C61h XXh

2C62h XXh

2C63h XXh

2C64h XXh

2C65h XXh

2C66h XXh

2C67h XXh

2C68h DTC Control Data 5 DTCD5 XXh

2C69h XXh

2C6Ah XXh

2C6Bh XXh

2C6Ch XXh

2C6Dh XXh

2C6Eh XXh

2C6Fh XXh

R8C/36C Group 4. Special Function Registers (SFRs)

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Nov 02, 2010

Table 4.10 SFR Information (10) (1)

X: Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

Address Register Symbol After Reset

2C70h DTC Control Data 6 DTCD6 XXh

2C71h XXh

2C72h XXh

2C73h XXh

2C74h XXh

2C75h XXh

2C76h XXh

2C77h XXh

2C78h DTC Control Data 7 DTCD7 XXh

2C79h XXh

2C7Ah XXh

2C7Bh XXh

2C7Ch XXh

2C7Dh XXh

2C7Eh XXh

2C7Fh XXh

2C80h DTC Control Data 8 DTCD8 XXh

2C81h XXh

2C82h XXh

2C83h XXh

2C84h XXh

2C85h XXh

2C86h XXh

2C87h XXh

2C88h DTC Control Data 9 DTCD9 XXh

2C89h XXh

2C8Ah XXh

2C8Bh XXh

2C8Ch XXh

2C8Dh XXh

2C8Eh XXh

2C8Fh XXh

2C90h DTC Control Data 10 DTCD10 XXh

2C91h XXh

2C92h XXh

2C93h XXh

2C94h XXh

2C95h XXh

2C96h XXh

2C97h XXh

2C98h DTC Control Data 11 DTCD11 XXh

2C99h XXh

2C9Ah XXh

2C9Bh XXh

2C9Ch XXh

2C9Dh XXh

2C9Eh XXh

2C9Fh XXh

2CA0h DTC Control Data 12 DTCD12 XXh

2CA1h XXh

2CA2h XXh

2CA3h XXh

2CA4h XXh

2CA5h XXh

2CA6h XXh

2CA7h XXh

2CA8h DTC Control Data 13 DTCD13 XXh

2CA9h XXh

2CAAh XXh

2CABh XXh

2CACh XXh

2CADh XXh

2CAEh XXh

2CAFh XXh

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Nov 02, 2010

Table 4.11 SFR Information (11) (1)

X: Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

Address Register Symbol After Reset

2CB0h DTC Control Data 14 DTCD14 XXh

2CB1h XXh

2CB2h XXh

2CB3h XXh

2CB4h XXh

2CB5h XXh

2CB6h XXh

2CB7h XXh

2CB8h DTC Control Data 15 DTCD15 XXh

2CB9h XXh

2CBAh XXh

2CBBh XXh

2CBCh XXh

2CBDh XXh

2CBEh XXh

2CBFh XXh

2CC0h DTC Control Data 16 DTCD16 XXh

2CC1h XXh

2CC2h XXh

2CC3h XXh

2CC4h XXh

2CC5h XXh

2CC6h XXh

2CC7h XXh

2CC8h DTC Control Data 17 DTCD17 XXh

2CC9h XXh

2CCAh XXh

2CCBh XXh

2CCCh XXh

2CCDh XXh

2CCEh XXh

2CCFh XXh

2CD0h DTC Control Data 18 DTCD18 XXh

2CD1h XXh

2CD2h XXh

2CD3h XXh

2CD4h XXh

2CD5h XXh

2CD6h XXh

2CD7h XXh

2CD8h DTC Control Data 19 DTCD19 XXh

2CD9h XXh

2CDAh XXh

2CDBh XXh

2CDCh XXh

2CDDh XXh

2CDEh XXh

2CDFh XXh

2CE0h DTC Control Data 20 DTCD20 XXh

2CE1h XXh

2CE2h XXh

2CE3h XXh

2CE4h XXh

2CE5h XXh

2CE6h XXh

2CE7h XXh

2CE8h DTC Control Data 21 DTCD21 XXh

2CE9h XXh

2CEAh XXh

2CEBh XXh

2CECh XXh

2CEDh XXh

2CEEh XXh

2CEFh XXh

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Nov 02, 2010

Table 4.12 SFR Information (12) (1)

X: Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

Table 4.13 ID Code Areas and Option Function Select Area

Notes:

1. The option function select area is allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program.

Do not write addition s to the option fu nctio n select are a. If the bl ock includin g t he opti on f unct ion sel ect a rea is erased , t he opt ion fun cti on select

area is set to FFh.

When blank products are shipped, th e option function select area is set to FFh. It is set to the wr itten value after written by the user.

When factory-programming products are shipped, the value of the option function select area is the value programmed by the user.

2. The ID code areas are allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program.

Do not write additions to the ID code areas. If the block including the ID code areas is erased, the ID code areas are set to FFh.

When blank products are shipped, th e ID code areas are set to FFh. They are set to the written value after written by the user.

When factory-programming products are shipped, the value of the ID code areas is the value programmed by the user.

Address Register Symbol After Reset

2CF0h DTC Control Data 22 DTCD22 XXh

2CF1h XXh

2CF2h XXh

2CF3h XXh

2CF4h XXh

2CF5h XXh

2CF6h XXh

2CF7h XXh

2CF8h DTC Control Data 23 DTCD23 XXh

2CF9h XXh

2CFAh XXh

2CFBh XXh

2CFCh XXh

2CFDh XXh

2CFEh XXh

2CFFh XXh

2D00h

2FFFh

Address Area Name Symbol After Reset

FFDBh Option Function Select Register 2 OFS2 (Note 1)

FFDFh ID1 (Note 2)

FFE3h ID2 (Note 2)

FFEBh ID3 (Note 2)

FFEFh ID4 (Note 2)

FFF3h ID5 (Note 2)

FFF7h ID6 (Note 2)

FFFBh ID7 (Note 2)

FFFFh O p tio n Func tio n Select Re gis te r OFS (Note 1)

R8C/36C Group 5. Electrical Characteristics

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Nov 02, 2010

5. Electrical Characteristics

Table 5.1 Absolute Maximum Ratings

Symbol Parameter Condition Rated Value Unit

VCC/AVCC Supply voltage −0.3 to 6.5 V

VIInput voltage −0.3 to VCC + 0.3 V

VOOutput voltage −0.3 to VCC + 0.3 V

PdPower dissipation −40°C ≤ Topr ≤ 85°C500mW

Topr Operating ambient temperature −20 to 85 (N version)/

−40 to 85 (D version) °C

Tstg Storage temperature −65 to 150 °C

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Nov 02, 2010

Notes:

1. VCC = 1.8 to 5.5 V and Topr = −20 to 85 °C (N version)/−40 to 85 °C (D version), unless otherwise specified.

2. The average output current indicates the average value of current measured during 100 ms.

3. fOCO40M can be used as the count source for timer RC, timer RD or timer RG in the r ange of VCC = 2.7 to 5.5 V.

Table 5.2 Recommended Operating Conditions (1)

Symbol Parameter Conditions Standard Unit

Min. Typ. Max.

VCC/AVCC Supply voltage 1.8 — 5.5 V

VSS/AVSS Supply voltage — 0 — V

VIH Input “H” voltage Other than CMOS input 0.8 VCC —VCC V

CMOS

input Input level

switching

function

(I/O port)

Input level selection:

0.35 VCC 4.0 V ≤ VCC ≤ 5.5 V 0.5 VCC —VCC V

2.7 V ≤ VCC < 4.0 V 0.55 VCC —VCC V

1.8 V ≤ VCC < 2.7 V 0.65 VCC —VCC V

Input level selection:

0.5 VCC 4.0 V ≤ VCC ≤ 5.5 V 0.65 VCC —VCC V

2.7 V ≤ VCC < 4.0 V 0.7 VCC —VCC V

1.8 V ≤ VCC < 2.7 V 0.8 VCC —VCC V

Input level selection:

0.7 VCC 4.0 V ≤ VCC ≤ 5.5 V 0.85 VCC —VCC V

2.7 V ≤ VCC < 4.0 V 0.85 VCC —VCC V

1.8 V ≤ VCC < 2.7 V 0.85 VCC —VCC V

External clock input (XOUT) 1.2 — VCC V

VIL Input “L” voltage Other than CMOS input 0 — 0.2 VCC V

CMOS

input Input level

switching

function

(I/O port)

Input level selection:

0.35 VCC 4.0 V ≤ VCC ≤ 5.5 V 0 — 0.2 VCC V

2.7 V ≤ VCC < 4.0 V 0 — 0.2 VCC V

1.8 V ≤ VCC < 2.7 V 0 — 0.2 VCC V

Input level selection:

0.5 VCC 4.0 V ≤ VCC ≤ 5.5 V 0 — 0.4 VCC V

2.7 V ≤ VCC < 4.0 V 0 — 0.3 VCC V

1.8 V ≤ VCC < 2.7 V 0 — 0.2 VCC V

Input level selection:

0.7 VCC 4.0 V ≤ VCC ≤ 5.5 V 0 — 0.55 VCC V

2.7 V ≤ VCC < 4.0 V 0 — 0.45 VCC V

1.8 V ≤ VCC < 2.7 V 0 — 0.35 VCC V

External clock input (XOUT) 0 — 0.4 V

IOH(sum) Peak sum output “H”

current Sum of all pins IOH(peak) ——−160 mA

IOH(sum) Average sum output “H”

current Sum of all pins IOH(avg) ——−80 mA

IOH(peak) Peak output “H” current Drive capacity Low — — −10 mA

Drive capacity High — — −40 mA

IOH(avg) Average output “H”

current Drive capacity Low — — −5mA

Drive capacity High — — −20 mA

IOL(sum) Peak sum output “L”

current Sum of all pins IOL(peak) — — 160 mA

IOL(sum) Average sum output “L”

current Sum of all pins IOL(avg) ——80mA

IOL(peak) Peak output “L” current Drive capacity Low — — 10 mA

Drive capacity High — — 40 mA

IOL(avg) Average output “L”

current Drive capacity Low — — 5 mA

Drive capacity High — — 20 mA

f(XIN) XIN clock input oscillation frequency 2.7 V ≤ VCC ≤ 5.5 V — — 20 MHz

1.8 V ≤ VCC < 2.7 V — — 5 MHz

f(XCIN) XCIN clock input oscillation frequency 1.8 V ≤ VCC ≤ 5.5 V — 32.768 50 kHz

fOCO40M When used as the count source for timer RC, timer RD or

timer RG (3) 2.7 V ≤ VCC ≤ 5.5 V 32 — 40 MHz

fOCO-F fOCO-F frequency 2.7 V ≤ VCC ≤ 5.5 V — — 20 MHz

1.8 V ≤ VCC < 2.7 V — — 5 MHz

— System clock frequency 2.7 V ≤ VCC ≤ 5.5 V — — 20 MHz

1.8 V ≤ VCC < 2.7 V — — 5 MHz

f(BCLK) CPU clock frequency 2.7 V ≤ VCC ≤ 5.5 V — — 20 MHz

1.8 V ≤ VCC < 2.7 V — — 5 MHz

R8C/36C Group 5. Electrical Characteristics

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Nov 02, 2010

Figure 5.1 Ports P0 to P6, P8 Timing Measurement Circuit

30 pF

R8C/36C Group 5. Electrical Characteristics

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Nov 02, 2010

Notes:

1. VCC/AVCC = Vref = 2.2 to 5.5 V, VSS = 0 V, and Topr = −20 to 85 °C (N version)/−40 to 85 °C (D version), unless otherwise

specified.

2. The A/D conversion result will be undefined in wait mode, stop mode, when the flash memory stops, and in low-current-

consumption mode. Do not perform A/D conversion in these states or transition to these states during A/D conversion.

3. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in

8-bit mode.

Table 5.3 A/D Converter Characteristics

Symbol Parameter Conditions Standard Unit

Min. Typ. Max.

— Resolution Vref = AVCC ——10Bit

— Absolute accuracy 10-bit mode Vref = AVCC = 5.0 V AN0 to AN7 input,

AN8 to AN11 input — — ±3 LSB

Vref = AVCC = 3.3 V AN0 to AN7 input,

AN8 to AN11 input — — ±5 LSB

Vref = AVCC = 3.0 V AN0 to AN7 input,

AN8 to AN11 input — — ±5 LSB

Vref = AVCC = 2.2 V AN0 to AN7 input,

AN8 to AN11 input — — ±5 LSB

8-bit mode Vref = AVCC = 5.0 V AN0 to AN7 input,

AN8 to AN11 input — — ±2 LSB

Vref = AVCC = 3.3 V AN0 to AN7 input,

AN8 to AN11 input — — ±2 LSB

Vref = AVCC = 3.0 V AN0 to AN7 input,

AN8 to AN11 input — — ±2 LSB

Vref = AVCC = 2.2 V AN0 to AN7 input,

AN8 to AN11 input — — ±2 LSB

φAD A/D conversion clock 4.0 V ≤ Vref = AVCC ≤ 5.5 V (2) 2—20MHz

3.2 V ≤ Vref = AVCC ≤ 5.5 V (2) 2—16MHz

2.7 V ≤ Vref = AVCC ≤ 5.5 V (2) 2—10MHz

2.2 V ≤ Vref = AVCC ≤ 5.5 V (2) 2—5MHz

— Tolerance level impedance — 3 — kΩ

tCONV Conversion time 10-bit mode Vref = AVCC = 5.0 V, φAD = 20 MHz 2.2 — — µs

8-bit mode Vref = AVCC = 5.0 V, φAD = 20 MHz 2.2 — — µs

tSAMP Sampling time φAD = 20 MHz 0.8 — — µs

IVref Vref current VCC = 5.0 V, XIN = f1 = φAD = 20 MHz — 45 — µA

Vref Reference voltage 2.2 — AVCC V

VIA Analog input voltage (3) 0—Vref V

OCVREF On-chip reference voltage 2 MHz ≤ φAD ≤ 4 MHz 1.19 1.34 1.49 V

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Nov 02, 2010

Notes:

1. VCC/AVCC = Vref = 2.7 to 5.5 V and Topr = −20 to 85 °C (N version)/−40 to 85 °C (D version), unless otherwise specified.

2. This applies when one D/A converter is used and the value of the DAi register (i = 0 or 1) for the unused D/A converter is 00h.

The resistor ladder of the A/D converter is not included.

Notes:

1. VCC = 2.7 to 5.5 V and Topr = −20 to 85 °C (N version)/−40 to 85 °C (D version), unless otherwise specified.

2. When the digital filter is disabled.

Table 5.4 D/A Converter Characteristics

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

— Resolution —— 8Bit

— Absolute accuracy — — 2.5 LSB

tsu Setup time —— 3µs

ROOutput resistor —6—kΩ

IVref Reference power input current (Note 2) — — 1.5 mA

Table 5.5 Comparator B Electrical Characteristics

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

Vref IVREF1, IVREF3 input reference voltage 0 — VCC − 1.4 V

VIIVCMP1, IVCMP3 input voltage −0.3 — VCC + 0.3 V

— Offset — 5 100 mV

tdComparator output delay time (2) VI = Vref ± 100 mV — 0.1 — µs

ICMP Comparator operating current VCC = 5.0 V — 17.5 — µA

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Nov 02, 2010

Notes:

1. VCC = 2.7 to 5.5 V and Topr = 0 to 60 °C, unless otherwise specified.

2. Definition of programming/erasure endurance

The programming and erasure endurance is defined on a per-block basis.

If the programming and erasure endurance is n (n = 1,000), each block can be erased n times. For example, if 1 ,024 1-byte

writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the

programming/erasure endurance still stands at one. However, the same address must not be programmed more than once

per erase operation (overwriting prohibited).

3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed.)

4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential

addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,

when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups

before erasing them all in one operation. It is also advisable to retain data on the erasure endurance of each block and limit

the number of erase operations to a certain number.

5. If an error occurs during block erase, attempt to execute the clear status register command , then execute the block erase

command at least three times until the erase error does not occur.

6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.

7. The data hold time includes time that the power supply is off or the clock is not supplied.

Table 5.6 Flash Memory (Program ROM) Electrical Characteristics

Symbol Parameter Conditions Standard Unit

Min. Typ. Max.

—Program/erase endurance (2) 1,000 (3) ——times

— Byte program time — 80 500 µs

— Block erase time — 0.3 — s

td(SR-SUS) Time delay from suspend request until

suspend — — 5 + CPU clock

× 3 cycles ms

— Interval from erase start/restart until

following suspend request 0— —µs

— Time from suspend until erase restart — — 30 + CPU clock

× 1 cycle µs

td(CMDRST

-READY) Time from when command is forcibly

stopped until reading is enabled — — 30 + CPU clock

× 1 cycle µs

— Program, erase voltage 2.7 — 5.5 V

— Read voltage 1.8 — 5.5 V

— Program, erase temperature 0 — 60 °C

—Data hold time (7) Ambient temperature = 55 °C20 — — year

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Nov 02, 2010

Notes:

1. VCC = 2.7 to 5.5 V and Topr = −20 to 85 °C (N version)/−40 to 85 °C (D version), unless otherwise specified.

2. Definition of programming/erasure endurance

The programming and erasure endurance is defined on a per-block basis.

If the programming and erasure endurance is n (n = 10,000), each block can be erased n times. For example, if 1,024 1-byte

writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the

programming/erasure endurance still stands at one. However, the same address must not be programmed more than once

per erase operation (overwriting prohibited).

3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed.)

4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential

addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,

when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups

before erasing them all in one operation. In addition, averaging the erasure endurance between blocks A to D can further

reduce the actual erasure endurance. It is also advisable to retain data on the erasure endurance of each block and limit the

number of erase operations to a certain number.

5. If an error occurs during block erase, attempt to execute the clear status register command , then execute the block erase

command at least three times until the erase error does not occur.

6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.

7. −40 °C for D version.

8. The data hold time includes time that the power supply is off or the clock is not supplied.

Figure 5.2 Time delay until Su sp end

Table 5.7 Flash Memory (Data flash Block A to Block D) Electrical Characteristics

Symbol Parameter Conditions Standard Unit

Min. Typ. Max.

—Program/erase endurance (2) 10,000 (3) ——times

— Byte program time

(program/erase endurance ≤ 1,000 times) — 160 1500 µs

— Byte program time

(program/erase endurance > 1,000 times) — 300 1500 µs

— Block erase time

(program/erase endurance ≤ 1,000 times) —0.2 1 s

— Block erase time

(program/erase endurance > 1,000 times) —0.3 1 s

td(SR-SUS) Time delay from suspend request until

suspend — — 5 + CPU clock

× 3 cycles ms

— Interval from erase start/restart until

following suspend request 0— — µs

— Time from suspend until erase restart — — 30 + CPU clock

× 1 cycle µs

td(CMDRST

-READY) Time from when command is forcibly

stopped until reading is enabled — — 30 + CPU clock

× 1 cycle µs

— Program, erase voltage 2.7 — 5.5 V

— Read voltage 1.8 — 5.5 V

— Program, erase temperature −20 (7) —85 °C

—Data hold time (8) Ambient temperature = 55 °C20 — — year

FST6 bit

Suspend request

(FMR21 bit)

Fixed time

td(SR-SUS)

Clock-dependent

time Access restart

FST6, FST7: Bit in FST register

FMR21: Bit in FMR2 register

FST7 bit

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Nov 02, 2010

Notes:

1. The measurement condition is VCC = 1.8 to 5.5 V and Topr = −20 to 85 °C ( N version)/−40 to 85 °C (D version).

2. Select the voltage detection level with bits VDSEL0 and VDSEL1 in the OFS r egister.

3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2

4. Time until the voltage monitor 0 reset is generated after the voltage passes Vdet0.

Notes:

1. The measurement condition is VCC = 1.8 to 5.5 V and Topr = −20 to 85 °C ( N version)/−40 to 85 °C (D version).

2. Select the voltage detection level with bits VD1S0 to VD1S3 in the VD1LS register.

3. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1.

4. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2

Table 5.8 Voltage Detection 0 Circuit Electrical Characteristics

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

Vdet0 Voltage detection level Vdet0_0 (2) 1.80 1.90 2.05 V

Voltage detection level Vdet0_1 (2) 2.15 2.35 2.50 V

Voltage detection level Vdet0_2 (2) 2.70 2.85 3.05 V

Voltage detection level Vdet0_3 (2) 3.55 3.80 4.05 V

—Voltage detection 0 circuit response time (4) At the falling of VCC from

5.0 V to (Vdet0_0 − 0.1) V — 6 150 µs

— Voltage detection circuit self power consumption VCA25 = 1, VCC = 5.0 V — 1.5 — µA

td(E-A) Waiting time until voltage detection circuit operation

starts (3) — — 100 µs

Table 5.9 Voltage Detection 1 Circuit Electrical Characteristics

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

Vdet1 Voltage detection level Vdet1_0 (2) At the falling of VCC 2.00 2.20 2.40 V

Voltage detection level Vdet1_1 (2) At the falling of VCC 2.15 2.35 2.55 V

Voltage detection level Vdet1_2 (2) At the falling of VCC 2.30 2.50 2.70 V

Voltage detection level Vdet1_3 (2) At the falling of VCC 2.45 2.65 2.85 V

Voltage detection level Vdet1_4 (2) At the falling of VCC 2.60 2.80 3.00 V

Voltage detection level Vdet1_5 (2) At the falling of VCC 2.75 2.95 3.15 V

Voltage detection level Vdet1_6 (2) At the falling of VCC 2.85 3.10 3.40 V

Voltage detection level Vdet1_7 (2) At the falling of VCC 3.00 3.25 3.55 V

Voltage detection level Vdet1_8 (2) At the falling of VCC 3.15 3.40 3.70 V

Voltage detection level Vdet1_9 (2) At the falling of VCC 3.30 3.55 3.85 V

Voltage detection level Vdet1_A (2) At the falling of VCC 3.45 3.70 4.00 V

Voltage detection level Vdet1_B (2) At the falling of VCC 3.60 3.85 4.15 V

Voltage detection level Vdet1_C (2) At the falling of VCC 3.75 4.00 4.30 V

Voltage detection level Vdet1_D (2) At the falling of VCC 3.90 4.15 4.45 V

Voltage detection level Vdet1_E (2) At the falling of VCC 4.05 4.30 4.60 V

Voltage detection level Vdet1_F (2) At the falling of VCC 4.20 4.45 4.75 V

— Hysteresis width at the rising of VCC in voltage

detection 1 circuit Vdet1_0 to Vdet1_5

selected —0.07— V

Vdet1_6 to Vdet1_F

selected —0.10— V

—Voltage detection 1 circuit response time (3) At the falling of VCC from

5.0 V to (Vdet1_0 − 0.1) V — 60 150 µs

— Voltage detection circuit self power consumption VCA26 = 1, VCC = 5.0 V — 1.7 — µA

td(E-A) Waiting time until voltage detection circuit operation

starts (4) — — 100 µs

R8C/36C Group 5. Electrical Characteristics

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Nov 02, 2010

Notes:

1. The measurement condition is VCC = 1.8 to 5.5 V and Topr = −20 to 85 °C ( N version)/−40 to 85 °C (D version).

2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2.

3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2

Notes:

1. The measurement condition is Topr = −20 to 85 °C (N version)/−40 to 85 °C (D version), unless otherwise specified.

2. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0.

Figure 5.3 Power-on Reset Circuit Electrical Characteristics

Table 5.10 Voltage Detection 2 Circuit Electrical Characteristics

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

Vdet2 Voltage detection level Vdet2_0 At the falling of VCC 3.70 4.00 4.30 V

— Hysteresis width at the rising of VCC in voltage

detection 2 circuit —0.10— V

—Voltage detection 2 circuit response time (2) At the falling of VCC from

5.0 V to (Vdet2_0 − 0.1) V — 20 150 µs

— Voltage detection circuit self power consumption VCA27 = 1, VCC = 5.0 V — 1.7 — µA

td(E-A) Waiting time until voltage detection circuit operation

starts (3) — — 100 µs

Table 5.11 Power-on Reset Circuit (2)

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

trth External power VCC rise gradient (1) 0 — 50,000 mV/msec

Notes:

1. Vdet0 indicates the voltage detect ion level of the voltage detection 0 circuit. Refer to 6. Voltage Detection

Circuit of User’s Manual: Hardware (R01UH0095EJ0110) for details.

2. tw(por) indi cates the duration the external power VCC must be held below the valid voltage (0.5 V) to enable

a power-on reset. When turning on the power after it falls with v oltage monitor 0 reset disabled, maintain

tw(por) for 1 ms or more.

Vdet0 (1)

0.5 V

Internal

reset si gnal

tw(por) (2) Voltage detection 0

circuit response time

Vdet0 (1)

External

Power VCC trth trth

fOCO-S × 32 1

fOCO-S × 32

R8C/36C Group 5. Electrical Characteristics

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Nov 02, 2010

Notes:

1. VCC = 1.8 to 5.5 V and Topr = −20 to 85 °C (N version)/−40 to 85 °C (D version), unless otherwise specified.

2. This enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in

UART mode.

Note:

1. VCC = 1.8 to 5.5 V and Topr = −20 to 85 °C (N version)/−40 to 85 °C (D version), unless otherwise specified.

Notes:

1. The measurement condition is VCC = 1.8 to 5.5 V and Topr = 25 °C.

2. Waiting time until the internal power supply generation circuit stabilizes during power-on.

Table 5.12 High-speed On-Chip Oscillator Circuit Electrical Characteristics

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

— High-speed on-chip oscillator frequency after

reset VCC = 1.8 V to 5.5 V

−20 °C ≤ Topr ≤ 85 °C38.4 40 41.6 MHz

VCC = 1.8 V to 5.5 V

−40 °C ≤ Topr ≤ 85 °C38.0 40 42.0 MHz

High-speed on-chip oscillator frequency when the

FRA4 register correction value is written into the

FRA1 register and the FRA5 register correction

value into the FRA3 register (2)

VCC = 1.8 V to 5.5 V

−20 °C ≤ Topr ≤ 85 °C35.389 36.864 38.338 MHz

VCC = 1.8 V to 5.5 V

−40 °C ≤ Topr ≤ 85 °C35.020 36.864 38.707 MHz

High-speed on-chip oscillator frequency when the

FRA6 register correction value is written into the

FRA1 register and the FRA7 register correction

value into the FRA3 register

VCC = 1.8 V to 5.5 V

−20 °C ≤ Topr ≤ 85 °C30.72 32 33.28 MHz

VCC = 1.8 V to 5.5 V

−40 °C ≤ Topr ≤ 85 °C30.40 32 33.60 MHz

— Oscillation stability time VCC = 5.0 V, Topr = 25 °C—0.53ms

— Self power consumption at oscillation VCC = 5.0 V, Topr = 25 °C — 400 — µA

Table 5.13 Low-speed On-Chip Oscillator Circuit Electrical Characteristics

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

fOCO-S Low-speed on-chip oscillator frequency 60 125 250 kHz

— Oscillation stability time VCC = 5.0 V, Topr = 25 °C — 30 100 µs

— Self power consumption at oscillation VCC = 5.0 V, Topr = 25 °C— 2 — µA

Table 5.14 Power Supply Circuit Timing Characteristics

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

td(P-R) Time for internal power supply stabilization during

power-on (2) — — 2,000 µs

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Nov 02, 2010

Notes:

1. VCC = 1.8 to 5.5 V, VSS = 0 V, and Topr = −20 to 85 °C (N version)/−40 to 85 °C (D version), unless otherwise specified.

2. 1tCYC = 1/f1(s)

Table 5.15 Timing Requirements of Synchronous Serial Communication Unit (SSU)

Symbol Parameter Conditions Standard Unit

Min. Typ. Max.

tSUCYC SSCK clock cycle time 4 — — tCYC (2)

tHI SSCK clock “H” width 0.4 — 0.6 tSUCYC

tLO SSCK clock “L” width 0.4 — 0.6 tSUCYC

tRISE SSCK clock rising

time Master — — 1 tCYC (2)

Slave — — 1 µs

tFALL SSCK clock falling

time Master — — 1 tCYC (2)

Slave — — 1 µs

tSU SSO, SSI data input setup time 100 — — ns

tHSSO, SSI data input hold time 1 — — tCYC (2)

tLEAD SCS setup time Slave 1tCYC + 50 — — ns

tLAG SCS hold time Slave 1tCYC + 50 — — ns

tOD SSO, SSI data output delay time — — 1 tCYC (2)

tSA SSI slave access time 2.7 V ≤ VCC ≤ 5.5 V — — 1.5tCYC + 100 ns

1.8 V ≤ VCC < 2.7 V — — 1.5tCYC + 200 ns

tOR SSI slave out open time 2.7 V ≤ VCC ≤ 5.5 V — — 1.5tCYC + 100 ns

1.8 V ≤ VCC < 2.7 V — — 1.5tCYC + 200 ns

R8C/36C Group 5. Electrical Characteristics

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Nov 02, 2010

Figure 5.4 I/O Timing of Synchronous Serial Communication Unit (SSU) (Master)

VIH or VOH

VIL or VOL

tHI

tLO

tHI

tFALL tRISE

tLO tSUCYC

tOD

tSU

SCS (output)

SSCK (output)

(CPOS = 1)

SSCK (output)

(CPOS = 0)

SSO (output)

SSI (input)

4-Wire Bus Communication Mode, Master, CPHS = 1

VIH or VOH

VIL or VOL

tHI

tLO

tHI

tFALL tRISE

tLO tSUCYC

tOD

tSU

SCS (output)

SSCK (output)

(CPOS = 1)

SSCK (output)

(CPOS = 0)

SSO (output)

SSI (input)

4-Wire Bus Communication Mode, Master, CPHS = 0

CPHS, CPOS: Bits in SSMR register

R8C/36C Group 5. Electrical Characteristics

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Nov 02, 2010

Figure 5.5 I/O Timing of Synchronous Serial Communication Unit (SSU) (Slave)

VIH or VOH

VIL or VOL

SCS (input)

SSCK (input)

(CPOS = 1)

SSCK (input)

(CPOS = 0)

SSO (input)

SSI (output)

4-Wire Bus Communication Mode, Slave, CPHS = 1

VIH or VOH

VIL or VOL

tHI

tLO

tHI

tFALL tRISE

tLO tSUCYC

tSU

SCS (input)

SSCK (input)

(CPOS = 1)

SSCK (input)

(CPOS = 0)

SSO (input)

SSI (output)

4-Wire Bus Communication Mode, Slave, CPHS = 0

tOD

tLEAD

tSA

tLAG

tOR

tHI

tLO

tHI

tFALL tRISE

tLO tSUCYC

tSU

tOD

tLEAD

tSA

tLAG

tOR

CPHS, CPOS: Bits in SSMR register

R8C/36C Group 5. Electrical Characteristics

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Nov 02, 2010

Figure 5.6 I/O Timing of Synchronous Serial Communication Unit (SSU) (Clock Synchronous

Communication Mode)

VIH or VOH

tHI

tLO tSUCYC

tOD

tSU

SSCK

SSO (output)

SSI (input)

VIL or VOL

R8C/36C Group 5. Electrical Characteristics

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Nov 02, 2010

Notes:

1. VCC = 1.8 to 5.5 V, VSS = 0 V, and Topr = −20 to 85 °C (N version)/−40 to 85 °C (D version), unless otherwise specified.

2. 1tCYC = 1/f1(s)

Figure 5.7 I/O Timing of I2C bus Interface

Table 5.16 Timing Requirements of I2C bus Interface

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

tSCL SCL input cycle time 12tCYC + 600 (2) ——ns

tSCLH SCL input “H” width 3tCYC + 300 (2) ——ns

tSCLL SCL input “L” width 5tCYC + 500 (2) ——ns

tsf SCL, SDA input fall time — — 300 ns

tSP SCL, SDA input spike pulse rejection time — — 1tCYC (2) ns

tBUF SDA input bus-free time 5tCYC (2) ——ns

tSTAH Start condition input hold time 3tCYC (2) ——ns

tSTAS Retransmit start condition input setup time 3tCYC (2) ——ns

tSTOP Stop condition input setup time 3tCYC (2) ——ns

tSDAS Data input setup time 1tCYC + 40 (2) ——ns

tSDAH Data input hold time 10 — — ns

SDA

SCL

Notes:

1. Start condition

2. Stop condition

3. Retransmit start condition

tBUF

VIH

VIL

P (2) S (1)

tSTAH tSCLH

tSCLL

tSf tSr

tSCL tSDAH

Sr (3) P (2)

tSDAS

tSTAS tSP tSTOP

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Nov 02, 2010

Note:

1. 4.2 V ≤ VCC ≤ 5.5 V, Topr = −20 to 85 °C (N version)/−40 to 85 °C (D version), and f(XIN) = 20 MHz, unless otherwise

specified.

Table 5.17 Electrical Characteristics (1) [4.2 V ≤ VCC ≤ 5.5 V]

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

VOH Output “H”

voltage Other than XOUT Drive capacity High VCC = 5 V IOH = −20 mA VCC − 2.0 — VCC V

Drive capacity Low VCC = 5 V IOH = −5 mA VCC − 2.0 — VCC V

XOUT VCC = 5 V IOH = −200 µA1.0 —VCC V

VOL Output “L”

voltage Other than XOUT Drive capacity High VCC = 5 V IOL = 20 mA — — 2.0 V

Drive capacity Low VCC = 5 V IOL = 5 mA — — 2.0 V

XOUT VCC = 5 V IOL = 200 µA— —0.5V

VT+-VT- Hysteresis INT0, INT1, INT2,

INT3, INT4,

KI0, KI1, KI2, KI3,

TRAIO, TRBO,

TRCIOA, TRCIOB,

TRCIOC, TRCIOD,

TRDIOA0, TRDIOB0,

TRDIOC0, TRDIOD0,

TRDIOA1, TRDIOB1,

TRDIOC1, TRDIOD1,

TRCTRG, TRCCLK,

TRFI, TRGIOA,

TRGIOB, ADTRG,

RXD0, RXD1, RXD2,

CLK0, CLK1, CLK2,

SSI, SCL, SDA, SSO

0.1 1.2 — V

RESET 0.1 1.2 — V

IIH Input “H” current VI = 5 V, VCC = 5.0 V — — 5.0 µA

IIL Input “L” current VI = 0 V, VCC = 5.0 V — — −5.0 µA

RPULLUP Pull-up resistance VI = 0 V, VCC = 5.0 V 25 50 100 kΩ

RfXIN Feedback

resistance XIN — 0.3 — MΩ

RfXCIN Feedback

resistance XCIN — 8 — MΩ

VRAM RAM hold voltage During stop mode 1.8 — — V

R8C/36C Group 5. Electrical Characteristics

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Nov 02, 2010

Table 5.18 Electrical Characteristics (2) [3.3 V ≤ VCC ≤ 5.5 V]

(Topr = −20 to 85 °C (N version)/−40 to 85 °C (D version), unless otherwise specified.)

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

ICC Power supply current

(VCC = 3.3 to 5.5 V)

Single-chip mode,

output pins are open,

other pins are VSS

High-speed

clock mode XIN = 20 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

No division

—6.515mA

XIN = 16 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

No division

— 5.3 12.5 mA

XIN = 10 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

No division

—3.6—mA

XIN = 20 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

—3.0—mA

XIN = 16 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

—2.2—mA

XIN = 10 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

—1.5—mA

High-speed

on-chip

oscillator mode

XIN clock off

High-speed on-chip oscillator on fOCO-F = 20 MHz

Low-speed on-chip oscillator on = 125 kHz

No division

—7.015mA

XIN clock off

High-speed on-chip oscillator on fOCO-F = 20 MHz

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

—3.0—mA

XIN clock off

High-speed on-chip oscillator on fOCO-F = 4 MHz

Low-speed on-chip oscillator on = 125 kHz

Divide-by-16, MSTIIC = MSTTRD = MSTTRC = 1

—1—mA

Low-speed

on-chip

oscillator mode

XIN clock off

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8, FMR27 = 1, VCA20 = 0

—90400µA

Low-speed

clock mode XIN clock off

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz

No division

FMR27 = 1, VCA20 = 0

—85400µA

XIN clock off

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz

No division

Program operation on RAM

Flash memory off, FMSTP = 1, VCA20 = 0

—47—µA

Wait mode XIN clock off

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock operation

VCA27 = VCA26 = VCA25 = 0, VCA20 = 1

—15100µA

XIN clock off

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0, VCA20 = 1

—490µA

XIN clock off

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz (peripheral clock off)

While a WAIT instruction is executed

VCA27 = VCA26 = VCA25 = 0, VCA20 = 1

—3.5—µA

Stop mode XIN clock off, Topr = 25 °C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

—2.05.0µA

XIN clock off, Topr = 85 °C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

—15—µA

R8C/36C Group 5. Electrical Characteristics

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Nov 02, 2010

Timing Requirements (Unless Otherwise Specified: VCC = 5 V, VSS = 0 V, Topr = 25 °C)

Figure 5.8 External Clock Input Timing Diagram when VCC = 5 V

Figure 5.9 TRAIO Input Timing Diagram when VCC = 5 V

Notes:

1. When using timer RF input capture mode, adjust the cycle time to (1/timer RF count source frequency × 3) or above.

2. When using timer RF input capture mode, adjust the pulse width to (1/timer RF count source frequency × 1.5) or above.

Figure 5.10 TRFI Input Timing Diagram when VCC = 5 V

Table 5.19 External Clock Input (XOUT, XCIN)

Symbol Parameter Standard Unit

Min. Max.

tc(XOUT) XOUT input cycle time 50 — ns

tWH(XOUT) XOUT input “H” width 24 — ns

tWL(XOUT) XOUT input “L” width 24 — ns

tc(XCIN) XCIN input cycle time 14 — µs

tWH(XCIN) XCIN input “H” width 7 — µs

tWL(XCIN) XCIN input “L” width 7 — µs

Table 5.20 TRAIO Input

Symbol Parameter Standard Unit

Min. Max.

tc(TRAIO) TRAIO input cycle time 100 — ns

tWH(TRAIO) TRAIO input “H” width 40 — ns

tWL(TRAIO) TRAIO input “L” width 40 — ns

Table 5.21 TRFI Input

Symbol Parameter Standard Unit

Min. Max.

tc(TRFI) TRFI input cycle time 400 (1) —ns

tWH(TRFI) TRFI input “H” width 200 (2) —ns

tWL(TRFI) TRFI input “L” width 200 (2) —ns

External clock input

tWH(XOUT),

tWH(XCIN)

tC(XOUT), tC(XCIN)

tWL(XOUT), tWL(XCIN)

VCC = 5 V

TRAIO input

VCC = 5 V

tC(TRAIO)

tWL(TRAIO)

tWH(TRAIO)

tWH(TRFI)

tc(TRFI)

tWL(TRFI)

TRFI input

VCC = 5 V

R8C/36C Group 5. Electrical Characteristics

R01DS0018EJ0110 Rev.1.10 Page 48 of 59

Nov 02, 2010

i = 0 to 2

Figure 5.11 Serial Interface Timing Diagram when VCC = 5 V

Notes:

1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

Figure 5.12 Input Timing Diagram for External Interrupt INTi and Key Input Interrupt KIi

when VCC = 5 V

Table 5.22 Serial Interface

Symbol Parameter Standard Unit

Min. Max.

tc(CK) CLKi input cycle time 200 — ns

tW(CKH) CLKi input “H” width 100 — ns

tW(CKL) CLKi input “L” width 100 — ns

td(C-Q) TXDi output delay time — 50 ns

th(C-Q) TXDi hold time 0—ns

tsu(D-C) RXDi input setup time 50 — ns

th(C-D) RXDi input hold time 90 — ns

Table 5.23 External Interrupt INTi (i = 0 to 4) Input, Key Input Interrupt KIi (i = 0 to 3)

Symbol Parameter Standard Unit

Min. Max.

tW(INH) INTi input “H” width, KIi input “H” width 250 (1) —ns

tW(INL) INTi input “L” width, KIi input “L” width 250 (2) —ns

tW(CKH)

tC(CK)

tW(CKL) th(C-Q)

th(C-D)

tsu(D-C)td(C-Q)

CLKi

TXDi

RXDi

i = 0 to 2

VCC = 5 V

INTi input

(i = 0 to 4) tW(INL)

tW(INH)

VCC = 5 V

KIi input

(i = 0 to 3)

R8C/36C Group 5. Electrical Characteristics

R01DS0018EJ0110 Rev.1.10 Page 49 of 59

Nov 02, 2010

Note:

1. 2.7 V ≤ VCC < 4.2 V, Topr = −20 to 85 °C (N version)/−40 to 85 °C (D version), and f(XIN) = 10 MHz, unless otherwise

specified.

Table 5.24 Electrical Characteristics (3) [2.7 V ≤ VCC < 4.2 V]

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

VOH Output “H” voltage Other than XOUT Drive capacity High IOH = −5 mA VCC − 0.5 — VCC V

Drive capacity Low IOH = −1 mA VCC − 0.5 — VCC V

XOUT IOH = −200 µA1.0 — VCC V

VOL Output “L” voltage Other than XOUT Drive capacity High IOL = 5 mA — — 0.5 V

Drive capacity Low IOL = 1 mA — — 0.5 V

XOUT IOL = 200 µA— —0.5V

VT+-VT- Hysteresis INT0, INT1, INT2,

INT3, INT4,

KI0, KI1, KI2, KI3,

TRAIO, TRBO,

TRCIOA, TRCIOB,

TRCIOC, TRCIOD,

TRDIOA0, TRDIOB0,

TRDIOC0, TRDIOD0,

TRDIOA1, TRDIOB1,

TRDIOC1, TRDIOD1,

TRCTRG, TRCCLK,

TRFI, TRGIOA,

TRGIOB, ADTRG,

RXD0, RXD1, RXD2,

CLK0, CLK1, CLK2,

SSI, SCL, SDA, SSO

VCC = 3.0 V 0.1 0.4 — V

RESET VCC = 3.0 V 0.1 0.5 — V

IIH Input “H” current VI = 3 V, VCC = 3.0 V — — 4.0 µA

IIL Input “L” current VI = 0 V, VCC = 3.0 V — — −4.0 µA

RPULLUP Pull-up resistance VI = 0 V, VCC = 3.0 V 42 84 168 kΩ

RfXIN Feedback

resistance XIN — 0.3 — MΩ

RfXCIN Feedback

resistance XCIN — 8 — MΩ

VRAM RAM hold voltage During stop mode 1.8 — — V

R8C/36C Group 5. Electrical Characteristics

R01DS0018EJ0110 Rev.1.10 Page 50 of 59

Nov 02, 2010

Table 5.25 Electrical Characteristics (4) [2.7 V ≤ VCC ≤ 3.3 V]

(Topr = −20 to 85 °C (N version)/−40 to 85 °C (D version), unless otherwise specified.)

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

ICC Power supply current

(VCC = 2.7 to 3.3 V)

Single-chip mode,

output pins are open,

other pins are VSS

High-speed

clock mode XIN = 10 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-ch ip oscillator on = 125 kHz

No division

—3.510mA

XIN = 10 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-ch ip oscillator on = 125 kHz

Divide-by-8

—1.57.5mA

High-speed

on-chip

oscillator mode

XIN clock off

High-speed on-chip oscillator on fOCO-F = 20 MHz

Low-speed on-ch ip oscillator on = 125 kHz

No division

—7.015mA

XIN clock off

High-speed on-chip oscillator on fOCO-F = 20 MHz

Low-speed on-ch ip oscillator on = 125 kHz

Divide-by-8

—3.0—mA

XIN clock off

High-speed on-chip oscillator on fOCO-F = 10 MHz

Low-speed on-ch ip oscillator on = 125 kHz

No division

—4.0—mA

XIN clock off

High-speed on-chip oscillator on fOCO-F = 10 MHz

Low-speed on-ch ip oscillator on = 125 kHz

Divide-by-8

—1.5—mA

XIN clock off

High-speed on-chip oscillator on fOCO-F = 4 MHz

Low-speed on-ch ip oscillator on = 125 kHz

Divide-by-16, MSTIIC = MSTTRD = MSTTRC = 1

—1—mA

Low-speed

on-chip

oscillator mode

XIN clock off

High-speed on-chip oscillator off

Low-speed on-ch ip oscillator on = 125 kHz

Divide-by-8, FMR27 = 1, VCA20 = 0

—90390µA

Low-speed

clock mode XIN clock off

High-speed on-chip oscillator off

Low-speed on-ch ip oscillator off

XCIN clock oscillator on = 32 kHz

No division

FMR27 = 1, VCA20 = 0

—80400µA

XIN clock off

High-speed on-chip oscillator off

Low-speed on-ch ip oscillator off

XCIN clock oscillator on = 32 kHz

No division

Program operation on RAM

Flash memory off, FMSTP = 1, VCA20 = 0

—40—µA

Wait mode XIN clock off

High-speed on-chip oscillator off

Low-speed on-ch ip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock operation

VCA27 = VCA26 = VCA25 = 0, VCA20 = 1

—1590µA

XIN clock off

High-speed on-chip oscillator off

Low-speed on-ch ip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0, VCA20 = 1

—480µA

XIN clock off

High-speed on-chip oscillator off

Low-speed on-ch ip oscillator off

XCIN clock oscillator on = 32 kHz (peripheral clock off)

While a WAIT instruction is executed

VCA27 = VCA26 = VCA25 = 0, VCA20 = 1

—3.5—µA

Stop mode XIN clock off, Topr = 25 °C

High-speed on-chip oscillator off

Low-speed on-ch ip oscillator off

CM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

—2.05.0µA

XIN clock off, Topr = 85 °C

High-speed on-chip oscillator off

Low-speed on-ch ip oscillator off

CM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

—15—µA

R8C/36C Group 5. Electrical Characteristics

R01DS0018EJ0110 Rev.1.10 Page 51 of 59

Nov 02, 2010

Timing requirements (Unless Otherwise Specified: VCC = 3 V, VSS = 0 V, Topr = 25 °C)

Figure 5.13 External Clock Input Timing Diagram when VCC = 3 V

Figure 5.14 TRAIO Input Timing Diagram when VCC = 3 V

Notes:

1. When using timer RF input capture mode, adjust the cycle time to (1/timer RF count source frequency × 3) or above.

2. When using timer RF input capture mode, adjust the pulse width to (1/timer RF count source frequency × 1.5) or above.

Figure 5.15 TRFI Input Timing Diagram when VCC = 3 V

Table 5.26 External Clock Input (XOUT, XCIN)

Symbol Parameter Standard Unit

Min. Max.

tc(XOUT) XOUT input cycle time 50 — ns

tWH(XOUT) XOUT input “H” width 24 — ns

tWL(XOUT) XOUT input “L” width 24 — ns

tc(XCIN) XCIN input cycle time 14 — µs

tWH(XCIN) XCIN input “H” width 7 — µs

tWL(XCIN) XCIN input “L” width 7—µs

Table 5.27 TRAIO Input

Symbol Parameter Standard Unit

Min. Max.

tc(TRAIO) TRAIO input cycle time 300 — ns

tWH(TRAIO) TRAIO input “H” width 120 — ns

tWL(TRAIO) TRAIO input “L” width 120 — ns

Table 5.28 TRFI Input

Symbol Parameter Standard Unit

Min. Max.

tc(TRFI) TRFI input cycle time 1200 (1) —ns

tWH(TRFI) TRFI input “H” width 600 (2) —ns

tWL(TRFI) TRFI input “L” width 600 (2) —ns

External clock input

tWH(XOUT),

tWH(XCIN)

tC(XOUT), tC(XCIN)

tWL(XOUT), tWL(XCIN)

VCC = 3 V

TRAIO input

VCC = 3 V

tC(TRAIO)

tWL(TRAIO)

tWH(TRAIO)

tWH(TRFI)

tc(TRFI)

tWL(TRFI)

TRFI input

VCC = 3 V

R8C/36C Group 5. Electrical Characterist ics

R01DS0018EJ0110 Rev.1.10 Page 52 of 59

Nov 02, 2010

i = 0 to 2

Figure 5.16 Serial Interface Timing Diagram when VCC = 3 V

Notes:

1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

Figure 5.17 Input Timing Diagram for External Interrupt INTi and Key Input Interrupt KIi

when VCC = 3 V

Table 5.29 Serial Interface

Symbol Parameter Standard Unit

Min. Max.

tc(CK) CLKi input cycle time 300 — ns

tW(CKH) CLKi input “H” width 150 — ns

tW(CKL) CLKi Input “L” width 150 — ns

td(C-Q) TXDi output delay time — 80 ns

th(C-Q) TXDi hold time 0—ns

tsu(D-C) RXDi input setup time 70 — ns

th(C-D) RXDi input hold time 90 — ns

Table 5.30 External Interrupt INTi (i = 0 to 4) Input, Key Input Interrupt KIi (i = 0 to 3)

Symbol Parameter Standard Unit

Min. Max.

tW(INH) INTi input “H” width, KIi input “H” width 380 (1) —ns

tW(INL) INTi input “L” width, KIi input “L” width 380 (2) —ns

tW(CKH)

tC(CK)

tW(CKL) th(C-Q)

th(C-D)

tsu(D-C)td(C-Q)

CLKi

TXDi

RXDi

VCC = 3 V

i = 0 to 2

tW(INL)

tW(INH)

VCC = 3 V

INTi input

(i = 0 to 4)

KIi input

(i = 0 to 3)

R8C/36C Group 5. Electrical Characteristics

R01DS0018EJ0110 Rev.1.10 Page 53 of 59

Nov 02, 2010

Note:

1. 1.8 V ≤ VCC < 2.7 V, Topr = −20 to 85 °C (N version)/−40 to 85 °C (D version), and f(XIN) = 5 MHz, unless otherwise specified.

Table 5.31 Electrical Characteristics (5) [1.8 V ≤ VCC < 2.7 V]

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

VOH Output “H” voltage Other than XOUT Drive capacity High IOH = −2 mA VCC − 0.5 — VCC V

Drive capacity Low IOH = −1 mA VCC − 0.5 — VCC V

XOUT IOH = −200 µA1.0 — VCC V

VOL Output “L” voltage Other than XOUT Drive capacity High IOL = 2 mA — — 0.5 V

Drive capacity Low IOL = 1 mA — — 0.5 V

XOUT IOL = 200 µA— —0.5V

VT+-VT- Hysteresis NT0, INT1, INT2,

INT3, INT4,

KI0, KI1, KI2, KI3,

TRAIO, TRBO,

TRCIOA, TRCIOB,

TRCIOC, TRCIOD,

TRDIOA0, TRDIOB0,

TRDIOC0, TRDIOD0,

TRDIOA1, TRDIOB1,

TRDIOC1, TRDIOD1,

TRCTRG, TRCCLK,

TRFI, TRGIOA,

TRGIOB, ADTRG,

RXD0, RXD1, RXD2,

CLK0, CLK1, CLK2,

SSI, SCL, SDA, SSO

0.05 0.20 — V

RESET 0.05 0.20 — V

IIH Input “H” current VI = 2.2 V, VCC = 2.2 V — — 4.0 µA

IIL Input “L” current VI = 0 V, VCC = 2.2 V — — −4.0 µA

RPULLUP Pull-up resistance VI = 0 V, VCC = 2.2 V 70 140 300 kΩ

RfXIN Feedback

resistance XIN — 0.3 — MΩ

RfXCIN Feedback

resistance XCIN — 8 — MΩ

VRAM RAM hold voltage During stop mode 1.8 — — V

R8C/36C Group 5. Electrical Characteristics

R01DS0018EJ0110 Rev.1.10 Page 54 of 59

Nov 02, 2010

Table 5.32 Electrical Characteristics (6) [1.8 V ≤ VCC < 2.7 V]

(Topr = −20 to 85 °C (N version)/−40 to 85 °C (D version), unless otherwise specified.)

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

ICC Power supply current

(VCC = 1.8 to 2.7 V)

Single-chip mode,

output pins are open,

other pins are VSS

High-speed

clock mode XIN = 5 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-ch ip oscillator on = 125 kHz

No division

—2.2—mA

XIN = 5 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-ch ip oscillator on = 125 kHz

Divide-by-8

—0.8—mA

High-speed

on-chip

oscillator mode

XIN clock off

High-speed on-chip oscillator on fOCO-F = 5 MHz

Low-speed on-ch ip oscillator on = 125 kHz

No division

—2.510mA

XIN clock off

High-speed on-chip oscillator on fOCO-F = 5 MHz

Low-speed on-ch ip oscillator on = 125 kHz

Divide-by-8

—1.7—mA

XIN clock off

High-speed on-chip oscillator on fOCO-F = 4 MHz

Low-speed on-ch ip oscillator on = 125 kHz

Divide-by-16, MSTIIC = MSTTRD = MSTTRC = 1

—1—mA

Low-speed

on-chip

oscillator mode

XIN clock off

High-speed on-chip oscillator off

Low-speed on-ch ip oscillator on = 125 kHz

Divide-by-8, FMR27 = 1, VCA20 = 0

—90300µA

Low-speed

clock mode XIN clock off

High-speed on-chip oscillator off

Low-speed on-ch ip oscillator off

XCIN clock oscillator on = 32 kHz

No division

FMR27 = 1, VCA20 = 0

—80350µA

XIN clock off

High-speed on-chip oscillator off

Low-speed on-ch ip oscillator off

XCIN clock oscillator on = 32 kHz

No division

Program operation on RAM

Flash memory off, FMSTP = 1, VCA20 = 0

—40—µA

Wait mode XIN clock off

High-speed on-chip oscillator off

Low-speed on-ch ip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock operation

VCA27 = VCA26 = VCA25 = 0, VCA20 = 1

—1590µA

XIN clock off

High-speed on-chip oscillator off

Low-speed on-ch ip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0, VCA20 = 1

—480µA

XIN clock off

High-speed on-chip oscillator off

Low-speed on-ch ip oscillator off

XCIN clock oscillator on = 32 kHz (peripheral clock off)

While a WAIT instruction is executed

VCA27 = VCA26 = VCA25 = 0, VCA20 = 1

—3.5—µA

Stop mode XIN clock off, Topr = 25 °C

High-speed on-chip oscillator off

Low-speed on-ch ip oscillator off

CM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

—2.0 5 µA

XIN clock off, Topr = 85 °C

High-speed on-chip oscillator off

Low-speed on-ch ip oscillator off

CM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

—15—µA

R8C/36C Group 5. Electrical Characteristics

R01DS0018EJ0110 Rev.1.10 Page 55 of 59

Nov 02, 2010

Timing requirements (Unless Otherwise Specified: VCC = 2.2 V, VSS = 0 V, Topr = 25 °C)

Figure 5.18 External Clock Input Timing Diagram when VCC = 2.2 V

Figure 5.19 TRAIO Input Timing Diagram when VCC = 2.2 V

Notes:

1. When using timer RF input capture mode, adjust the cycle time to (1/timer RF count source frequency × 3) or above.

2. When using timer RF input capture mode, adjust the pulse width to (1/timer RF count source frequency × 1.5) or above.

Figure 5.20 TRFI Input Timing Diagram when VCC = 2.2 V

Table 5.33 External Clock Input (XOUT, XCIN)

Symbol Parameter Standard Unit

Min. Max.

tc(XOUT) XOUT input cycle time 200 — ns

tWH(XOUT) XOUT input “H” width 90 — ns

tWL(XOUT) XOUT input “L” width 90 — ns

tc(XCIN) XCIN input cycle time 14 — µs

tWH(XCIN) XCIN input “H” width 7 — µs

tWL(XCIN) XCIN input “L” width 7—µs

Table 5.34 TRAIO Input

Symbol Parameter Standard Unit

Min. Max.

tc(TRAIO) TRAIO input cycle time 500 — ns

tWH(TRAIO) TRAIO input “H” width 200 — ns

tWL(TRAIO) TRAIO input “L” width 200 — ns

Table 5.35 TRFI Input

Symbol Parameter Standard Unit

Min. Max.

tc(TRFI) TRFI input cycle time 2000 (1) —ns

tWH(TRFI) TRFI input “H” width 1000 (2) —ns

tWL(TRFI) TRFI input “L” width 1000 (2) —ns

External clock input

tWH(XOUT),

tWH(XCIN)

tC(XOUT), tC(XCIN)

tWL(XOUT), tWL(XCIN)

VCC = 2.2 V

TRAIO input

tC(TRAIO)

tWL(TRAIO)

tWH(TRAIO) VCC = 2.2 V

tWH(TRFI)

tc(TRFI)

tWL(TRFI)

TRFI input

VCC = 2.2 V

R8C/36C Group 5. Electrical Characteristics

R01DS0018EJ0110 Rev.1.10 Page 56 of 59

Nov 02, 2010

i = 0 to 2

Figure 5.21 Serial Interface Timing Diagram when VCC = 2.2 V

Notes:

1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

Figure 5.22 Input Timing Diagram for External Interrupt INTi and Key Input Interrupt KIi

when VCC = 2.2 V

Table 5.36 Serial Interface

Symbol Parameter Standard Unit

Min. Max.

tc(CK) CLKi input cycle time 800 — ns

tW(CKH) CLKi input “H” width 400 — ns

tW(CKL) CLKi input “L” width 400 — ns

td(C-Q) TXDi output delay time — 200 ns

th(C-Q) TXDi hold time 0—ns

tsu(D-C) RXDi input setup time 150 — ns

th(C-D) RXDi input hold time 90 — ns

Table 5.37 External Interrupt INTi (i = 0 to 4) Input, Key Input Interrupt KIi (i = 0 to 3)

Symbol Parameter Standard Unit

Min. Max.

tW(INH) INTi input “H” width, KIi input “H” width 1000 (1) —ns

tW(INL) INTi input “L” width, KIi input “L” width 1000 (2) —ns

tW(CKH)

tC(CK)

tW(CKL) th(C-Q)

th(C-D)

tsu(D-C)td(C-Q)

CLKi

TXDi

RXDi

VCC = 2.2 V

i = 0 to 2

tW(INL)

tW(INH)

VCC = 2.2 V

INTi input

(i = 0 to 4)

KIi input

(i = 0 to 3)

R8C/36C Group Package Dimensions

R01DS0018EJ0110 Rev.1.10 Page 57 of 59

Nov 02, 2010

Package Dimensions

Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of

the Renesas Electronics website.

Terminal cross section

1. DIMENSIONS "*1" AND "*2"

DO NOT INCLUDE MOLD FLASH.

NOTE)

DIMENSION "*3" DOES NOT

INCLUDE TRIM OFFSET.

Index mark

116

3348

Detail F

P-LQFP64-10x10-0.50 0.3g

MASS[Typ.]

64P6Q-A / FP-64K / FP-64KVPLQP0064KB-A

RENESAS CodeJEITA Package Code Previous Code

1.0

0.125

0.18

1.25

0.08

0.20

0.145

0.09

0.250.200.15

MaxNomMin

Dimension in Millimeters

Symbol

Reference

10.110.0

9.9

10.110.0

9.9

1.4

12.212.011.8

1.7

0.15

0.1

0.05

0.65

0.5

0.35

8°0°

0.5

0.08

R8C/36C Group Package Dimensions

R01DS0018EJ0110 Rev.1.10 Page 58 of 59

Nov 02, 2010

Terminal cross section

1. DIMENSIONS "*1" AND "*2"

DO NOT INCLUDE MOLD FLASH.

NOTE)

DIMENSION "*3" DOES NOT

INCLUDE TRIM OFFSET.

116

Index mark

ebp

Detail F

Previous CodeJEITA Package Code RENESAS Code

PLQP0064GA-A 64P6U-A/ 

MASS[Typ.]

0.7gP-LQFP64-14x14-0.80

1.0

0.125

0.35

1.0

0.20

0.145

0.09

0.420.370.32

MaxNomMin

Dimension in Millimeters

Symbol

Reference

14.114.013.9

1.4

16.216.015.8

1.7

0.20.1

0.70.50.3

8°0°

0.8

0.10

R8C/36C Group Package Dimensions

R01DS0018EJ0110 Rev.1.10 Page 59 of 59

Nov 02, 2010

Detail F

NOTE)

1. DIMENSIONS"*1"AND"*2"

DO NOT INCLUDE MOLD FLASH

2. DIMENSION"*3"DOES NOT

INCLUDE TRIM OFFSET.

Terminal cross section

1.00

1.20

1.00

0° 8°

0.40

0.12 0.17 0.22

0.15

0.16

0.13 0.18 0.23

8.8 9.0 9.2

6.9 7.0 7.1

0.50

9.29.08.8

0.10

0.08

0.07

Reference

Symbol

Dimension in Millimeters

Min Nom Max

0.05 0.15

0.50

0.35 0.65

Previous Code

JEITA Package Code RENESAS Code

PTQP0064LB-A 

MASS[Typ.]

0.14gP-TQFP64-7x7-0.40

64 17

48 33

R8C/36C Group Datasheet

C - 1

Rev. Date Description

Page Summary

0.01 Oct 30, 2009 — First Edition issued

1.00 Nov 02, 2010 All pages “Preliminary”, “Under development” deleted

4 Table 1.3 revised

28 to 54 “5. Electrical Characteristics” added

1.10 Nov 02, 2010 — TN-R8C-A015A/E reflected

3 Table 1.2 “Timer RG” and “Package” revised

4 and 5 Tables 1.3 and 1.4 revised

6 Figure 1.1 revised

8 Figure 1.3 “PTQP0064LB-A” added

17 Figure 3.1 “Part Number” revised

33 Table 5.3 “tCONV”, “tSAMP” revised

47 Table 5.21 revised

51 Table 5.28 revised

55 Table 5.35 revised

59 Package (PTQP0064LB-A) added

All trademarks and registered trademarks are the property of their respective owners.

REVISION HIST ORY

General Precautions in the Handling of MPU/MCU Products

The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes

on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under

General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each

other, the description in the body of the manual takes precedence.

1. Handling of Unused Pins

Handle unused pins in accord with the directions given under Handling of Unused Pins in the

manual.

 The input pins of CMOS products are generally in the high-impedance state. In operation

with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the

vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur

due to the false recognition of the pin state as an input signal become possible. Unused

pins should be handled as described under Handling of Unused Pins in the manual.

2. Processing at Power-on

The state of the product is undefined at the moment when power is supplied.

 The states of internal circuits in the LSI are indeterminate and the states of register

settings and pins are undefined at the moment when power is supplied.

In a finished product where the reset signal is applied to the external reset pin, the states

of pins are not guaranteed from the moment when power is supplied until the reset

process is completed.

In a similar way, the states of pins in a product that is reset by an on-chip power-on reset

function are not guaranteed from the moment when power is supplied until the power

reaches the level at which resetting has been specified.

3. Prohibition of Access to Reserved Addresses

Access to reserved addresses is prohibited.

 The reserved addresses are provided for the possible future expansion of functions. Do

not access these addresses; the correct operation of LSI is not guaranteed if they are

accessed.

4. Clock Signals

After applying a reset, only release the reset line after the operating clock signal has become

stable. When switching the clock signal during program execution, wait until the target clock

signal has stabilized.

 When the clock signal is generated with an external resonator (or from an external

oscillator) during a reset, ensure that the reset line is only released after full stabilization of

the clock signal. Moreover, when switching to a clock signal produced with an external

resonator (or by an external oscillator) while program execution is in progress, wait until

the target clock signal is stable.

5. Differences between Products

Before changing from one product to another, i.e. to one with a different part number, confirm

that the change will not lead to problems.

 The characteristics of MPU/MCU in the same group but having different part numbers may

differ because of the differences in internal memory capacity and layout pattern. When

changing to products of different part numbers, implement a system-evaluation test for

each of the products.

Notice

1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas

Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to

be disclosed by Renesas Electronics such as that disclosed through our website.

2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or

technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or

others.

3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.

4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for

the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the

use of these circuits, software, or information.

5. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and

regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to

the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is

prohibited under any applicable domestic or foreign laws or regulations.

6. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics

assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.

7. Renesas Electronics products are classified according to the following three quality grades: "Standard", "High Quality", and "Specific". The recommended applications for each Renesas Electronics product

depends on the product's quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas

Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for

which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the

use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics.

The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc.

"Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools;

personal electronic equipment; and industrial robots.

"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically

designed for life support.

"Specific": Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical

implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.

8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage

range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the

use of Renesas Electronics products beyond such specified ranges.

9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and

malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the

possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to

redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,

please evaluate the safety of the final products or system manufactured by you.

10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics

products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes

no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.

11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics.

12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.

(Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.

(Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.

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Refer to "http://www.renesas.com/" for the latest and detailed information.

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