RFD16N05, RFD16N05SM Data Sheet 16A, 50V, 0.047 Ohm, N-Channel Power MOSFETs The RFD16N05 and RFD16N05SM N-channel power MOSFETs are manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits, gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, motor drivers, and relay drivers. These transistors can be operated directly from integrated circuits. Formerly developmental type TA09771. Ordering Information PART NUMBER PACKAGE BRAND November 2003 Features * 16A, 50V * rDS(ON) = 0.047 * Temperature Compensating PSPICE(R) Model * Peak Current vs Pulse Width Curve * UIS Rating Curve * 175oC Operating Temperature * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards" Symbol D RFD16N05 TO-251AA D16N05 RFD16N05SM TO-252AA D16N05 NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-252AA variant in the tape and reel, i.e., RFD16N05SM9A. G S Packaging JEDEC TO-251AA DRAIN (FLANGE) JEDEC TO-252AA SOURCE DRAIN GATE DRAIN (FLANGE) GATE SOURCE (c)2003 Fairchild Semiconductor Corporation RFD16N05, RFD16N05SM Rev. B1 RFD16N05, RFD16N05SM Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg RFD16N05, RFD16N05SM, 50 50 16 Refer to Peak Current Curve 20 Refer to Figure 5 72 0.48 -55 to 175 UNITS V V A 300 260 oC oC V W W/oC oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL Drain to Source Breakdown Voltage Gate Threshold Voltage BVDSS VGS(TH) Zero Gate Voltage Drain Current IDSS Gate to Source Leakage Current Drain to Source On Resistance (Note 2) IGSS MAX UNITS - - V VGS = VDS, ID = 250A 2 - 4 V VDS = Rated BVDSS, VGS = 0V - - 1 A VDS = 0.8 x Rated BVDSS, VGS = 0V, TC = 150oC - - 25 A VGS = 20V - - 100 nA - - 0.047 - - 65 ns - 14 - ns tr - 30 - ns td(OFF) - 55 - ns tf - 30 - ns t(OFF) - - 125 ns - - 80 nC - - 45 nC - - 2.2 nC - 900 - pF - 325 - pF Turn-On Delay Time td(ON) Rise Time Fall Time Total Gate Charge TYP 50 VDD = 25V, ID = 8A, RL = 3.125, VGS = 10V, RGS = 25 (Figure 13) t(ON) Turn-Off Time TEST CONDITIONS ID = 16A, VGS = 10V (Figure 9) rDS(ON) Turn-On Time Turn-Off Delay Time MIN ID = 250A, VGS = 0V (Figure 11) VDD = 40V, ID 16A, RL = 2.5 Ig(REF) = 0.8mA (Figure 13) Qg(TOT) VGS = 0V to 20V Gate Charge at 10V Qg(10) VGS = 0V to 10V Threshold Gate Charge Q(TH) VGS = 0V to 2V Input Capacitance CISS Output Capacitance COSS VDS = 25V, VGS = 0V, f = 1MHz (Figure 12) Reverse Transfer Capacitance CRSS - 100 - pF Thermal Resistance Junction to Case RJC - - 2.083 oC/W Thermal Resistance Junction to Ambient RJA - - 100 oC/W MIN TYP MAX UNITS ISD = 16A - - 1.5 V ISD = 16A, dISD/dt = 100A/s - - 125 ns TO-251 and TO-252 Source to Drain Diode Specifications PARAMETER SYMBOL Source to Drain Diode Voltage VSD Diode Reverse Recovery Time trr TEST CONDITIONS NOTES: 2. Pulse test: pulse width 250s, duty cycle 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3) and Peak Current Capability Curve (Figure 5). (c)2003 Fairchild Semiconductor Corporation RFD16N05, RFD16N05SM Rev. B1 RFD16N05, RFD16N05SM Typical Performance Curves Unless Otherwise Specified POWER DISSIPATION MULTIPLIER 1.2 20 ID, DRAIN CURRENT (A) 1.0 0.8 0.6 0.4 16 12 8 4 0.2 0 0 0 25 50 75 100 125 TC , CASE TEMPERATURE (oC) 150 175 25 FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TENPERATURE 50 75 100 125 TC, CASE TEMPERATURE (oC) 150 175 FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 2 Z JC, NORMALIZED THERMAL IMPEDANCE 1 0.5 0.2 PDM 0.1 0.1 0.05 t1 0.02 0.01 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x Z JA x R JA + TA SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 t, RECTANGULAR PULSE DURATION (s) 100 101 FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE SINGLE PULSE TJ = MAX RATED TC = 25oC 100s 10 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10ms VDSS(MAX) = 50V 1 100ms DC 10 1 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA (c)2003 Fairchild Semiconductor Corporation 100 VGS = 20V 200 IDM, PEAK CURRENT (A) ID, DRAIN CURRENT (A) 100 VGS = 10V 100 FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 175 - TC 150 TC = 25oC TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10 10-5 10-4 10-3 10-2 10-1 t, PULSE WIDTH (s) 100 101 FIGURE 5. PEAK CURRENT CAPABILITY RFD16N05, RFD16N05SM Rev. B1 RFD16N05, RFD16N05SM Typical Performance Curves Unless Otherwise Specified (Continued) 50 100 ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) VGS = 20V STARTING TJ = 25oC 10 STARTING TJ = 150oC If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS-VDD) +1] 1 0.01 VGS = 10V VGS = 8V VGS = 7V 40 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TC = 25oC 30 VGS = 6V 20 VGS = 5V 10 VGS = 4.5V 0 1 0.1 tAV, TIME IN AVALANCHE (ms) 10 1 2 3 VDS, DRAIN TO SOURCE VOLTAGE (V) 0 4 NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. FIGURE 7. SATURATION CHARACTERISTICS 2.5 50 VDD = 15V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 40 175oC -55oC NORMALIZED DRAIN TO SOURCE ON RESISTANCE IDS(ON), DRAIN TO SOURCE CURRENT (A) FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING 25oC 30 20 10 2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) 10 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE NORMALIZED GATE THRESHOLD VOLTAGE 1.0 0.5 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) 200 FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE (c)2003 Fairchild Semiconductor Corporation 0.5 2.0 VGS = VDS, ID = 250A -40 1.0 -40 0 40 80 120 160 200 FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 1.5 0 -80 1.5 TJ, JUNCTION TEMPERATURE (oC) FIGURE 8. TRANSFER CHARACTERISTICS 2.0 2.0 0 -80 0 0 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 16A ID = 250A 1.5 1.0 0.5 0 -80 -40 0 40 80 120 160 200 TJ , JUNCTION TEMPERATURE (oC) FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE RFD16N05, RFD16N05SM Rev. B1 RFD16N05, RFD16N05SM Unless Otherwise Specified (Continued) VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGS 1200 CISS 800 COSS 400 CRSS VDD = BVDSS 5 10 15 20 VDS, DRAIN TO SOURCE VOLTAGE (V) VDD = BVDSS 7.5 37.5 5 25 0.75 BVDSS 0.50 BVDSS 0.25 BVDSS 12.5 2.5 RL = 3.125 IG(REF) = 0.8mA VGS = 10V 0 0 0 10 50 0 I I G ( REF ) 20 ------------------------I G ( ACT ) 25 VGS , GATE TO SOURCE VOLTAGE (V) C, CAPACITANCE (pF) 1600 VDS , DRAIN TO SOURCE VOLTAGE (V) Typical Performance Curves G ( REF ) 80 ---------------------I G ( ACT ) t, TIME (ms) NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN REQUIRED PEAK IAS + RG VDS IAS VDD VDD - VGS DUT tP 0V IAS 0 0.01 tAV FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(ON) VDS td(OFF) tr VDS tf 90% 90% RL VGS + DUT RGS VGS - VDD (c)2003 Fairchild Semiconductor Corporation 10% 90% VGS 0 FIGURE 16. SWITCHING TIME TEST CIRCUIT 10% 0 10% 50% 50% PULSE WIDTH FIGURE 17. RESISTIVE SWITCHING WAVEFORMS RFD16N05, RFD16N05SM Rev. B1 RFD16N05, RFD16N05SM Test Circuits and Waveforms (Continued) VDS VDD RL Qg(TOT) VDS VGS = 20V VGS Qg(10) + VDD DUT IG(REF) VGS = 10V VGS - VGS = 2V 0 Qg(TH) IG(REF) 0 FIGURE 18. GATE CHARGE TEST CIRCUIT (c)2003 Fairchild Semiconductor Corporation FIGURE 19. GATE CHARGE WAVEFORM RFD16N05, RFD16N05SM Rev. B1 RFD16N05, RFD16N05SM PSPICE Electrical Model .SUBCKT RFD16N05 2 1 3 ; rev 10/31/94 CA 12 8 1.788e-10 CB 15 14 1.875e-10 CIN 6 8 8.33e-10 DPLCAP RSCL1 + 51 5 ESCL 51 50 ESG + 6 8 GATE 9 1 LGATE 20 RGATE VTO EVTO + 18 8 + 6 S1A S1B S2A S2B DBODY 17 18 - MOS2 MOS1 CIN 8 MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01 S1A RSOURCE 7 LSOURCE 3 SOURCE S2A 13 8 14 13 S1B RBREAK 15 17 18 S2B 13 RVTO CB CA + 11 EBREAK 21 RIN 12 DBREAK RDRAIN 16 IT 8 17 1 RBREAK 17 18 RBKMOD 1 RDRAIN 50 16 RDSMOD 0.4e-3 RGATE 9 20 3.0 RIN 6 8 1e9 RSCL1 5 51 RSCLMOD 1e-6 RSCL2 5 50 1e3 RSOURCE 8 7 RDSMOD 21.5e-3 RVTO 18 19 RVTOMOD 1 DRAIN 2 LDRAIN RSCL2 EBREAK 11 7 17 18 64.89 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1 LDRAIN 2 5 1e-9 LGATE 1 9 4.56e-9 LSOURCE 3 7 4.13e-9 5 10 DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DPLCAP 10 5 DPLCAPMOD + 6 8 EGS - + EDS - 14 5 8 IT 19 VBAT + 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD VBAT 8 19 DC 1 VTO 21 6 0.82 ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/94,7))} .MODEL DBDMOD D (IS = 2.5e-13 RS = 7.1e-3 TRS1 = 3.04e-3 TRS2 = -10e-6 CJO = 1.12e-9 TT = 5.6e-8) .MODEL DBKMOD D (RS = 2.51e-1 TRS1 = -6.57e-4 TRS2 = 1.66e-6) .MODEL DPLCAPMOD D (CJO = 6.1e-10 IS = 1e-30 N = 10) .MODEL MOSMOD NMOS (VTO = 3.96 KP = 16.68 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL RBKMOD RES (TC1 = 1.07e-3 TC2 = -7.19e-7) .MODEL RDSMOD RES (TC1 = 5.45e-3 TC2 = 1.66e-5) .MODEL RSCLMOD RES (TC1 = 1.25e-3 TC2 = 17e-6) .MODEL RVTOMOD RES (TC1 = -5.15e-3 TC2 = -4.83e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.25 VOFF= -3.25) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.25 VOFF= -5.25) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.56 VOFF= 5.56) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 5.56 VOFF= 0.56) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; written by William J. Hepp and C. Frank Wheatley. (c)2003 Fairchild Semiconductor Corporation RFD16N05, RFD16N05SM Rev. B1 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM FACT Quiet SeriesTM ActiveArrayTM FAST BottomlessTM FASTrTM CoolFETTM FRFETTM CROSSVOLTTM GlobalOptoisolatorTM DOMETM GTOTM EcoSPARKTM HiSeCTM E2CMOSTM I2CTM TM EnSigna ImpliedDisconnectTM FACTTM ISOPLANARTM Across the board. Around the world.TM The Power FranchiseTM Programmable Active DroopTM LittleFETTM MICROCOUPLERTM MicroFETTM MicroPakTM MICROWIRETM MSXTM MSXProTM OCXTM OCXProTM OPTOLOGIC OPTOPLANARTM PACMANTM POPTM Power247TM PowerTrench QFET QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM RapidConnectTM SILENT SWITCHER SMART STARTTM SPMTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogic TINYOPTOTM TruTranslationTM UHCTM UltraFET VCXTM DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I5