MOTOROLA CMOS LOGIC DATA 1
MC14557B
The MC14557B is a static clocked serial shift register whose length may
be programmed to be any number of bits between 1 and 64. The number of
bits selected is equal to the sum of the subscripts of the enabled Length
Control inputs (L1, L2, L4, L8, L16, and L32) plus one. Serial data may be
selected from the A or B data inputs with the A/B select input. This feature is
useful for recirculation purposes. A Clock Enable (CE) input is provided to
allow gating of the clock or negative edge clocking capability.
The device can be effectively used for variable digital delay lines or simply
to implement odd length shift registers.
•1–64 Bit Programmable Length
•Q and Q Serial Buffered Outputs
•Asynchronous Master Reset
•All Inputs Buffered
•No Limit On Clock Rise and Fall Times
•Supply Voltage Range = 3.0 Vdc to 18 Vdc
•Capable of Driving Two Low–power TTL Loads or one Low–power
Schottky TTL Load Over the Rated Temperature Range
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol Parameter Value Unit
VDD DC Supply Voltage – 0.5 to + 18.0 V
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
Iin, Iout Input or Output Current (DC or Transient),
per Pin ± 10 mA
PDPower Dissipation, per Package† 500 mW
Tstg Storage Temperature – 65 to + 150
_
C
TLLead Temperature (8–Second Soldering) 260
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/
_
C From 65
_
C To 125
_
C
Ceramic “L” Packages: – 12 mW/
_
C From 100
_
C To 125
_
C
LENGTH SELECT TRUTH TABLE
L32 L16 L8 L4 L2 L1 Register Length
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
1 Bit
2 Bits
3 Bits
4 Bits
5 Bits
6 Bits
33 Bits
34 Bits
61 Bits
62 Bits
63 Bits
64 Bits
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
1
1
0
1
1
0
0
0
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
2 Bits
3 Bits
4 Bits
5 Bits
6 Bits
33 Bits
34 Bits
61 Bits
62 Bits
63 Bits
64 Bits
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
1
0
0
0
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
3 Bits
4 Bits
5 Bits
6 Bits
33 Bits
34 Bits
61 Bits
62 Bits
63 Bits
64 Bits
0
0
0
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
1
1
0
0
0
0
0
1
1
0
1
0
1
0
1
0
1
0
1
4 Bits
5 Bits
6 Bits
33 Bits
34 Bits
61 Bits
62 Bits
63 Bits
64 Bits
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
0
1
0
1
0
1
5 Bits
6 Bits
33 Bits
34 Bits
61 Bits
62 Bits
63 Bits
64 Bits
0
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
0
1
0
1
0
1
0
1
6 Bits
33 Bits
34 Bits
61 Bits
62 Bits
63 Bits
64 Bits
1
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
1
33 Bits
34 Bits
61 Bits
62 Bits
63 Bits
64 Bits
1
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
1
33 Bits
34 Bits
61 Bits
62 Bits
63 Bits
64 Bits
1
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
1
33 Bits
34 Bits
61 Bits
62 Bits
63 Bits
64 Bits
1
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
1
33 Bits
34 Bits
61 Bits
62 Bits
63 Bits
64 Bits
1
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
1
33 Bits
34 Bits
61 Bits
62 Bits
63 Bits
64 Bits
1
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
1
33 Bits
34 Bits
61 Bits
62 Bits
63 Bits
64 Bits
1
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
1
33 Bits
34 Bits
61 Bits
62 Bits
63 Bits
64 Bits
1
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
1
33 Bits
34 Bits
61 Bits
62 Bits
63 Bits
64 Bits
NOTE: Length equals the sum of the binary length control
subscripts plus one.
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
REV 3
1/94
BLOCK DIAGRAM
L SUFFIX
CERAMIC
CASE 620
ORDERING INFORMATION
MC14XXXBCP Plastic
MC14XXXBCL Ceramic
MC14XXXBDW SOIC
TA = – 55° to 125°C for all packages.
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
TRUTH TABLE
Inputs Output
Rst A/B Clock CE Q
0 0 0 B
0 1 0 A
0 0 1 B
0 1 1 A
1 X X X 0
Q is the output of the first selected shift
register stage.
X = Don’t Care
12
13
14
1
15
2
9
7
6
5
4
3
11
10
RESET
CLOCK
CE
B
A
A/B SELECT
L1
L2
L4
L8
L16
L32
Q
Q
VDD = PIN 16
VSS = PIN 8
MOTOROLA CMOS LOGIC DATAMC14557B
2
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic
Symbol
VDD
Vdc
– 55
_
C 25
_
C 125
_
C
Unit
Characteristic
Symbol
VDD
Vdc
Min Max Min Typ # Max Min Max
Unit
Output Voltage “0” Level
Vin = VDD or 0 VOL 5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
“1” Level
Vin = 0 or VDD VOH 5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Input Voltage “0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL 5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
Vdc
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH 5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
Vdc
Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
IOH 5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
mAdc
(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
IOL 5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
Input Current Iin 15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdc
Input Capacitance
(Vin = 0) Cin — — — — 5.0 7.5 — — pF
Quiescent Current
(Per Package) IDD 5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.010
0.020
0.030
5.0
10
20
—
—
—
150
300
600
µAdc
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
IT5.0
10
15
IT = (1.75 µA/kHz) f + IDD
IT = (3.50 µA/kHz) f + IDD
IT = (5.25 µA/kHz) f + IDD
µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’ s potential performance.
**The formulas given are for the typical characteristics only at 25
_
C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However ,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.
MOTOROLA CMOS LOGIC DATA 3
MC14557B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25
_
C)
Characteristic Symbol VDD Min Typ # Max Unit
Rise and Fall Time, Q or Q Output
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
tTHL 5
10
15
—
—
—
100
50
40
200
100
80
ns
Propagation Delay, Clock or CE to Q or Q
tPLH, tPHL = (1.7 ns/pF) CL + 215 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 65 ns
tPLH,
tPHL 5
10
15
—
—
—
300
130
90
600
260
180
ns
Propagation Delay, Reset to Q or Q
tPLH, tPHL = (1.7 ns/pF) CL + 215 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 70 ns
tPLH,
tPHL 5
10
15
—
—
—
300
130
95
600
260
190
ns
Pulse Width, Clock tWH(cl) 5
10
15
200
100
75
95
45
35
—
—
—
ns
Pulse Width, Reset tWH(rst) 5
10
15
300
140
100
150
70
50
—
—
—
ns
Clock Frequency (50% Duty Cycle) fcl 5
10
15
—
—
—
3.0
7.5
13.0
1.7
5.0
6.7
MHz
Setup Time, A or B to Clock or CE
Worst case condition: L1 = L2 = L4 = L8 =
L16 = L32 = VSS (Register Length = 1)
tsu
5
10
15
700
290
145
350
130
85
—
—
—
ns
Best case condition: L32 = VDD, L1 through L16 =
Don’t Care (Any register length from 33 to 64) 5
10
15
400
165
60
45
5
0
—
—
—
Hold Time, Clock or CE to A or B
Best case condition: L1 = L2 = L4 = L8 = L16 =
L32 = VSS (Register Length = 1)
th
5
10
15
200
100
10
– 150
– 60
– 50
—
—
—
ns
Worst case condition: L32 = VDD, L1 through L16 =
Don’t Care (Any register length from 33 to 64) 5
10
15
400
185
85
50
25
22
—
—
—
Rise and Fall Time, Clock tr,
tf5
10
15 No Limit —
Rise and Fall Time, Reset or CE tr,
tf5
10
15
—
—
—
—
—
—
15
5
4
µs
Removal Time, Reset to Clock or CE trem 5
10
15
160
80
70
80
40
35
—
—
—
ns
*The formulas given are for the typical characteristics only at 25
_
C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
TIMING DIAGRAM
1–bit length:
CE = 0
A/B = 1
L1 = L2 = L4 = L8 = L16 = L32 = 0
PWR
50% tWH(cl)
th
50%
tsu trem
50%
tTLH tTHL
tPHL
tPHL
tPLH
90%
50%
10%
A INPUT
CLOCK
RESET
Q
VDD
VSS
VDD
VSS
VDD
VSS
VOH
VOL
1/fcl
MOTOROLA CMOS LOGIC DATAMC14557B
4
LOGIC DIAGRAM
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
L32
L16
L8
L4
VDD
A/B SEL
Q
Q
CLOCK
RESET
L1
L2
VSS
A
B
CE
A/B
SELECT
B
A
RESET
CLOCK
CE
9
6
7
3
4
5
C R
32 BIT
12
L32
C R
2 BIT
1
L2
2
L1
C R
1 BIT
C R
16 BIT
13
L16
14
L8
C R
1 BIT
C R
8 BIT
10
11
Q
Q
15
L4
C R
4 BIT
VDD= PIN 16
VSS= PIN 8
MOTOROLA CMOS LOGIC DATA 5
MC14557B
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
B
FC
S
HGD
J
L
M
16 PL
SEATING
1 8
916
K
PLANE
–T–
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.740 0.770 18.80 19.55
B0.250 0.270 6.35 6.85
C0.145 0.175 3.69 4.44
D0.015 0.021 0.39 0.53
F0.040 0.70 1.02 1.77
G0.100 BSC 2.54 BSC
H0.050 BSC 1.27 BSC
J0.008 0.015 0.21 0.38
K0.110 0.130 2.80 3.30
L0.295 0.305 7.50 7.74
M0 10 0 10
S0.020 0.040 0.51 1.01
____
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
–A–
–B–
–T–
FE
G
NK
C
SEATING
PLANE
16 PLD
S
A
M
0.25 (0.010) T
16 PLJ
S
B
M
0.25 (0.010) T
M
L
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.750 0.785 19.05 19.93
B0.240 0.295 6.10 7.49
C––– 0.200 ––– 5.08
D0.015 0.020 0.39 0.50
E0.050 BSC 1.27 BSC
F0.055 0.065 1.40 1.65
G0.100 BSC 2.54 BSC
H0.008 0.015 0.21 0.38
K0.125 0.170 3.18 4.31
L0.300 BSC 7.62 BSC
M0 15 0 15
N0.020 0.040 0.51 1.01
_ _ _ _
16 9
1 8
MOTOROLA CMOS LOGIC DATAMC14557B
6
OUTLINE DIMENSIONS
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751G–02
ISSUE A
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A10.15 10.45 0.400 0.411
B7.40 7.60 0.292 0.299
C2.35 2.65 0.093 0.104
D0.35 0.49 0.014 0.019
F0.50 0.90 0.020 0.035
G1.27 BSC 0.050 BSC
J0.25 0.32 0.010 0.012
K0.10 0.25 0.004 0.009
M0 7 0 7
P10.05 10.55 0.395 0.415
R0.25 0.75 0.010 0.029
M
B
M
0.010 (0.25)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
–A–
–B– P8X
G14X
D16X
SEATING
PLANE
–T–
S
A
M
0.010 (0.25) B S
T
16 9
81
F
J
RX 45
_
_ _ _ _
M
C
K
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