LT8584 2.5A Monolithic Active Cell Balancer with Telemetry Interface Description Features n n n n n n n n n n 2.5A Typical Average Cell Discharge Current Integrated 6A, 50V Power Switch Integrates Seamlessly with LTC680x Family: No Additional Software Required Selectable Current and Temperature Monitors Ultralow Quiescent Current in Shutdown Engineered for ISO 26262 Compliant Systems Isolated Balancing: n Can Return Charge to Top of Stack n Can Return Charge to Any Combination of Cells in Stack n Can Return Charge to 12V Battery for Alternator Replacement Can Be Paralleled for Greater Discharge Capability All Quiescent Current in Operation Taken from Local Cell 16-Lead TSSOP Package Applications n n n n Active Battery Stack Balancing Electric and Hybrid Electric Vehicles Fail-Safe Power Supplies Energy Storage Systems Typical Application MODULE + The LT8584 includes an integrated 6A, 50V power switch, reducing the design complexity of the application circuit. The part runs completely off of the cell which it is discharging, removing the need for complicated biasing schemes commonly required for external power switches. The enable pin (DIN) of the part is designed to work seamlessly with the LTC680x family of battery stack voltage monitoring ICs. The LT8584 also provides system telemetry including current and temperature monitoring when used with the LTC680x family of parts. When the LT8584 is disabled, less than 20nA of total quiescent current is typically consumed from the battery. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and Hot Swap and isoSPI are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 6518733 and 6636021. 12-Cell Battery Stack Module with Active Balancing 2.5A AVERAGE DISCHARGE + The LT(R)8584 is a monolithic flyback DC/DC converter designed to actively balance high voltage stacks of batteries. The high efficiency of a switching regulator significantly increases the achievable balancing current while reducing heat generation. Active balancing also allows for capacity recovery in stacks of mismatched batteries, a feat unattainable with passive balance systems. In a typical system, greater than 99% of the total battery capacity can be recovered. BAT 12 MODULE + * * MODULE - V+ READ CELL PARAMETERS LT8584 ENABLE BALANCING 2.5A AVERAGE DISCHARGE + BAT 2 MEASURABLE CELL PARAMETERS * VCELL * IDISCHARGE * VREF * TEMPERATURE EXTRACTABLE CELL PARAMETERS * RCABLE + RCONNECTOR * SWITCHING FAULTS * UNDERVOLTAGE * SERIAL FAULTS * COULOMB COUNTING MODULE + * MODULE - READ CELL PARAMETERS ENABLE BALANCING 2.5A AVERAGE DISCHARGE BAT 1 C12 S12 * LT8584 + LTC6804 BATTERY STACK MONITOR C2 S2 MODULE + * * MODULE - READ CELL PARAMETERS LT8584 ENABLE BALANCING C1 S1 V-/C0 LT8584 TA01a MODULE - 8584fb For more information www.linear.com/LT8584 1 LT8584 Absolute Maximum Ratings Pin Configuration (Note 1) DIN to GND Voltage.................................................. 10V VIN, VCELL, VSNS, MODE, OUT, DCHRG Voltage............................................. -0.3V to 9V RTMR Voltage..................................................... (Note 2) SW Voltage (Note 3)................................... -0.4V to 50V VIN - VCELL Voltage.............................................200mV VIN - VSNS Voltage..............................................200mV MODE - VIN Voltage..............................................200mV VSNS, MODE Pin Current......................................... 1mA VCELL, OUT Pin Current......................................... 10mA SW Pin Negative Current...........................................-2A Operating Junction Temperature Range (Note 4) LT8584E.................................................. -40C to 125C LT8584I.................................................. -40C to 125C LT8584H................................................. -40C to 150C Storage Temperature Range................... -65C to 150C Lead Temperature (Soldering, 10 sec).................... 300C TOP VIEW GND 1 16 SW GND 2 15 SW GND 3 14 SW GND 4 MODE 5 RTMR 6 11 VSNS DIN 7 10 VCELL OUT 8 9 17 GND 13 SW 12 DCHRG VIN FE PACKAGE 16-LEAD PLASTIC TSSOP TJMAX = 150C, JA = 38C/W EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT8584EFE#PBF LT8584EFE#TRPBF 8584FE 16-Lead Plastic TSSOP -40C to 125C LT8584IFE#PBF LT8584IFE#TRPBF 8584FE 16-Lead Plastic TSSOP -40C to 125C LT8584HFE#PBF LT8584HFE#TRPBF 8584FE 16-Lead Plastic TSSOP -40C to 150C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 2 8584fb For more information www.linear.com/LT8584 LT8584 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 4.2V, DIN = GND unless otherwise noted. (Note 4) PARAMETER CONDITIONS VIN Recommended Voltage Range Switching Nonswitching VIN Quiescent Current Switching Nonswitching In Shutdown, DIN = OUT In Shutdown, DIN = OUT MIN l l 2.5 2.45 l l 2.1 Switch DC Current Limit l 6 Current Limit Blanking Time ISW = 4A Switch Leakage Current VSW = 4.2V VSW = 4.2V 6.3 3 90 1 UNITS V mA mA nA A 2.45 V 6.8 A 450 ns 200 mV 5 l 70 4 nA A l 30 50 70 s l 0.5 0.85 1.2 s ISW = 2mA ISW = 6A 42 45 50 48 V V Note 6 80 200 360 ns 95 150 mV 100 180 ns Switch Maximum On Time Switch Short Detection Timeout Note 5 Switch Clamp Voltage Switch Clamp Blanking Time DCM Comparator Trip Voltage VSW - VVIN l DCM Comparator Propagation Delay 200mV Overdrive l 40 DCM Blanking Time 230 MODE Threshold DIN Shutdown Threshold MAX 5.3 5.3 45 2.5 1 l VIN UVLO Switch VCESAT TYP ns 1.7 1 1.2 V 1.4 V High Low, Referred to GND l DIN Data Threshold High Low, VTH = VOUT - VDIN, MODE = 0V l 0.3 0.7 0.9 V DIN Data Threshold Hysteresis VTH = VOUT - VDIN, MODE = 0V l 20 80 160 mV DIN Pin Current VDIN = 0V VDIN = -1V l -6 -18 -3 -14 -1 -6 A A DCHRG Threshold MODE Tied to VIN l 0.5 0.8 1.1 V DIN Shutdown Threshold Hysteresis 100 mV 100 mV 300 A 300 A 1.22 V DCHRG Hysteresis MODE Tied to VIN DCHRG Pull-down Current Pin Voltage = 0.4V l 220 DCHRG Pull-up Current Pin Voltage = VIN - 0.4V l 220 RMTR Pin High Voltage RRTMR = 50k RMTR Pin Low Voltage RRTMR = 50k 0 V VCELL Switch RDSON 55 VSNS Dynamic Input Range Gain Error 8% l -30 70 mV VSNS Average Input Range Gain Error 3% l 15 45 mV -1.1 VSNS Amplifier Input Referred Offset VCELL - VSNS = 40mV l VSNS Amplifier Gain Over VSNS Average Input Range l 18.7 Handshake Voltage Error Measured with Respect to: VMODE1 = 0.2V VMODE2 = 0.4V VMODE3 = 0.6V VMODE4 = 0.8V VSW,ERR = 1.2V VFAULT = 1.4V VFAULT = 1.4V l l l l l l -13 -14 -18 -22 -31 -35 -28 19 1.1 mV 19.3 V/V 13 14 18 22 31 35 28 mV mV mV mV mV mV mV 8584fb For more information www.linear.com/LT8584 3 LT8584 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 4.2V, DIN = GND unless otherwise noted. (Note 4) PARAMETER CONDITIONS MIN TYP MAX 0.75 UNITS Handshake Voltage Line Regulation From VVIN = 2.5V to VVIN = 4.2V 0.2 VTEMP Temperature Coefficient (TC) Note 7, K = (VCELL - VTEMP)/TC 2 %/V VTEMP VTEMP = VIN - VOUT, TJ = 25C 0.658 V OUT Pin Clamp Voltage 10mA Sourced from Pin l 1.53 1.6 V OUT Pin Amplifier Load Regulation IOUT = 10A to 1mA l 0 0.2 mV/K 0.4 %/mA Timing Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. MODE = 0V. Refer to Timing Diagram for parameter definition. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS l l l l tW Decode Window Duration RRTMR = 10k RRTMR = 50k RRTMR = 100k RRTMR = 200k 1.76 8 15.6 29.3 1.86 8.4 16.4 31.5 1.96 8.8 17.2 33.7 ms ms ms ms tRST Decode Window Range l 1.76 33.7 ms DIN Serial Communication Reset Time l 10 t1 RTMR Start-Up Time t2 t3 t4 DIN Low Time t5 Discharger Activation Time t6 Discharger Deactivation Time SR DIN Slew Rate RRTMR = 10k 1.8 l 5 s DIN Hold-Off Time l 50 s DIN High Time l 50 s l 50 RRTMR = 10k l Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Do not apply a positive or negative voltage or current source to RTMR, otherwise permanent damage may occur. Note 3: ABSMAX rating refers to the maximum DC + AC leakage spike. Do not exceed 40VDC on any of the SW pins. Note 4: The LT8584E is guaranteed to meet performance specifications from 0C to 125C junction temperature. Specifications over the -40C to 125C operating junction temperature range are assured by design, characterization, and correlation with statistical process controls. The LT8584I is guaranteed over the full -40C to 125C operating junction temperature range. The LT8584H is guaranteed over the full -40C to 150C operating junction temperature range. 4 s 9 s 900 ns 2.1 s V/ms Note 5: This is a measure of time duration from the onset of the switch turning on to the time the short-circuit protection circuit is disabled. If the current comparator trips during this duration, the switch error latch is set. This indicates that the connection to the transformer primary is most likely shorted. Note 6: This is a measure of time duration for the switch clamp to operate continuously without setting the switch error latch. If the switch clamp remains engaged longer than the switch clamp blanking time, the switch error latch is set and switching is disabled. Note 7: The voltage proportional to temperature (VTEMP) is measured on the OUT pin while in analog multiplexer MODE 3 or 4. VTEMP must be subtracted from the VCELL voltage that is measured while in analog mux MODE 1. Both measurements should be taken within 100ms of each other to reduce errors in absolute temperature calculation. 8584fb For more information www.linear.com/LT8584 LT8584 Typical Performance Characteristics TA = 25C, VIN = VCELL = VSNS = 4.2V, unless otherwise noted. VIN Pin Current Switching Disabled 5 DIN = 0V, PART ENABLED ENABLED CURRENT (mA) 2.4 2.3 2.2 2.1 2.0 -60 -20 20 60 100 TEMPERATURE (C) 4 3 0.4 2 0.2 1 0 140 0.6 2 4 6 PIN VOLTAGE (V) 8584 G01 Switch Current Limit CURRENT (A) 6.2 5.8 5.4 2.1 -20 20 60 100 TEMPERATURE (C) 5.0 -60 140 -20 60 100 20 TEMPERATURE (C) 8584 G04 48 53 44 42 40 -60 Switch Clamp Voltage (ISW = 6A) 60 100 20 TEMPERATURE (C) 140 8584 G07 0.4 30 0.3 25 -20 20 60 100 TEMPERATURE (C) 140 20 DCM Comparator Threshold 130 110 51 49 90 70 47 -20 35 8584 G06 VOLTAGE (mV) 55 VOLTAGE (V) 50 46 0.5 0.2 -60 140 40 ISW = 5.8A 8584 G05 Switch Maximum On-Time TIME (s) Switch Characteristics 0.6 6.6 2.2 140 BETA (A/A) VOLTAGE (V) 2.5 2.3 60 100 20 TEMPERATURE (C) 8584 G03 7.0 2.4 -20 8584 G02 VIN Internal UVLO 2.0 -60 2 0 -60 VCE,SAT (V) 2.6 3 1 0 8 DIN = OUT DCHRG = 0V MODE = VIN 4 SHDN CURRENT (mA) CURRENT (mA) 2.5 5 0.8 CURRENT (A) 2.6 Total Input Leakage IVIN + IVCELL + IVSNS + ISW VIN Pin Current 45 -60 -20 60 100 20 TEMPERATURE (C) 140 8584 G08 50 -60 -20 20 60 100 TEMPERATURE (C) 140 8584 G09 8584fb For more information www.linear.com/LT8584 5 LT8584 Typical Performance Characteristics TA = 25C, VIN = VCELL = VSNS = 4.2V, unless otherwise noted. DIN Pin Current DIN Pin Current 180 DIN SHDN Threshold 0 1.6 150 90 60 -10 0 -10 -8 -6 -4 -2 0 DIN VOLTAGE (V) 2 -15 -60 4 -20 20 60 100 TEMPERATURE (C) 8584 G10 0.8 -60 140 0.4 0.2 RISING 350 0.6 FALLING 0.4 0 -60 -20 60 100 20 TEMPERATURE (C) RESISTANCE () VOLTAGE (V) 100 1.4 60 100 20 TEMPERATURE (C) 140 8584 G16 6 1.0 VCELL = 2.5V VCELL = 3V VCELL = 3.6V VCELL = 4.2V 80 60 20 -60 20 60 100 TEMPERATURE (C) 140 VTEMP 0.9 40 -20 -20 8584 G15 VCELL Switch RDS(ON) 120 2.0 1.2 -60 200 -60 140 VCELL - VOUT (V) MODE Pin Threshold 2.2 1.6 SINK 8584 G14 8584 G13 1.8 SOURCE 300 250 0.2 140 140 400 CURRENT (A) VOLTAGE (V) VOUT - VDIN (V) RISING 60 100 20 TEMPERATURE (C) DCHRG Drive Current (Serial Mode) FALLING 0.6 -20 8584 G12 1.0 0.8 60 100 20 TEMPERATURE (C) FALLING DCHRG Threshold (Simple Mode) 0.8 -20 1.2 8584 G11 DIN Data Threshold 0 -60 RISING 1.0 VDIN = -1V 30 1.0 1.4 -5 VOLTAGE (V) CURRENT (A) CURRENT (A) VDIN = 0V 120 0.8 0.7 0.6 0.5 -20 60 100 20 TEMPERATURE (C) 140 8584 G17 0.4 -60 -20 60 100 20 TEMPERATURE (C) 140 8584 G18 8584fb For more information www.linear.com/LT8584 LT8584 Typical Performance Characteristics TA = 25C, VIN = VCELL = VSNS = 4.2V, unless otherwise noted. 1200 VSNS Transfer Function VSNS Amplifier Input Referred Offset VSNS Amplifier Gain 19.50 500 19.25 250 600 OFFSET (V) 800 GAIN (V/V) VCELL - VOUT (mV) 1000 19.00 400 18.75 0 -250 200 0 0 10 30 40 50 20 VCELL - VSNS (mV) 60 18.50 -60 70 8584 G19 20 60 100 TEMPERATURE (C) 140 -500 -60 10 -10 -60 -20 20 60 100 TEMPERATURE (C) 3 0.25 2 0.20 1 ERROR (%) REGULATION (%/V) SW, ERR FAULT MODE4 MODE3 MODE2 MODE1 140 Decode Window Duration Error 0.30 100k 50k 5 -5 20 60 100 TEMPERATURE (C) 8584 G21 Handshake Voltage Line Regulation 0 -20 8584 G20 Handshake Voltage Error ERROR VOLTAGE (mV) -20 0.15 0 0.10 -1 0.05 -2 0 -60 140 -20 8584 G22 60 100 20 TEMPERATURE (C) 10k -3 -60 140 -20 60 100 20 TEMPERATURE (C) 8584 G24 8584 G23 OUT Pin Clamp Voltage IOUT = 10mA OUT Pin Amplifier 1% Settling Time, COUT = 220nF OUT Pin Amplifier Drive Current 2.0 140 10 400 9 300 1.6 1.4 7 SINK 6 5 SOURCE 4 1.2 TIME (s) 8 CURRENT (mA) VIN - VOUT (V) 1.8 VIN - VOUT = 1.4V 0.2V 200 VIN - VOUT = 0V 1.4V 100 3 1.0 -60 -20 60 100 20 TEMPERATURE (C) 140 8584 G25 2 -60 -20 60 100 20 TEMPERATURE (C) 140 8584 G26 0 -60 -20 20 60 100 TEMPERATURE (C) 140 8584 G27 8584fb For more information www.linear.com/LT8584 7 LT8584 Typical Performance Characteristics TA = 25C, VIN = VCELL = VSNS = 4.2V, unless otherwise noted. Switching Waveform Average Discharge Current 2.6 T1 = NA5920-AL D1 = 2 SERIES ES1J 2.4 ISW 2A/DIV 2s/DIV T1 = NA5920-AL D1 = 2 SERIES ES1J VCELL = 4.2V VSTACK = 400V 8584 G28 2.0 1.8 1.6 1.4 50 100 150 200 250 300 350 STACK VOLTAGE (VSTACK+ - VSTACK-) 80 75 VCELL = 2.5V VCELL = 3V VCELL = 3.6V VCELL = 4.2V 1.2 1.0 T1 = NA5920-AL D1 = 2 SERIES ES1J 85 2.2 EFFICIENCY (%) DISCHARGE CURRENT (A) VSW 10V/DIV Conversion Efficiency 90 70 400 VCELL = 2.5V VCELL = 3V VCELL = 3.6V VCELL = 4.2V 50 Average Discharge Current 3.0 ISW 2A/DIV 2s/DIV T1 = NA5743-AL D1 = ES1D VCELL = 3.6V VMODULE = 40V RCD SNUBBER = 4.99k, 22nF 8584 G31 T1 = NA5743-AL D1 = ES1D 2.8 2.4 30 30 8584 G34 Conversion Efficiency 90 T1 = NA6252-AL D1 = STPS3H100U 2.8 2.6 2.4 10 15 20 25 30 AUXILLARY VOLTAGE (V) 80 75 VCELL = 2.5V VCELL = 3V VCELL = 3.6V VCELL = 4.2V 2.2 2.0 T1 = NA6252-AL D1 = STPS3H100U 85 EFFICIENCY (%) DISCHARGE CURRENT (A) ISW 2A/DIV 40 50 60 70 80 MODULE VOLTAGE (VMODULE+ - VMODULE-) 8584 G33 Average Discharge Current VSW 10V/DIV 8 70 40 50 60 70 80 MODULE VOLTAGE (VMODULE+ - VMODULE-) VCELL = 2.5V VCELL = 3V VCELL = 3.6V VCELL = 4.2V 8584 G32 3.0 T1 = NA6252-AL D1 = STPS3H100U VCELL = 4.2V VAUX = 13.8V RCD SNUBBER = 4.99k, 22nF 80 75 VCELL = 2.5V VCELL = 3V VCELL = 3.6V VCELL = 4.2V 2.2 2.0 T1 = NA5743-AL D1 = ES1D 85 2.6 Switching Waveform 2s/DIV Conversion Efficiency 90 EFFICIENCY (%) DISCHARGE CURRENT (A) VSW 10V/DIV 400 8584 G30 8584 G29 Switching Waveform 100 150 200 250 300 350 STACK VOLTAGE (VSTACK+ - VSTACK-) 35 8584 G35 70 VCELL = 2.5V VCELL = 3V VCELL = 3.6V VCELL = 4.2V 6 12 18 24 30 AUXILLARY VOLTAGE (V) 36 8584 G36 8584fb For more information www.linear.com/LT8584 LT8584 Pin Functions GND (Pin1, Pin 2, Pin 3, Pin 4, Pin 17): Must be soldered directly to local ground plane. MODE (Pin 5): Serial Enable Pin. Connect this pin to ground to enable serial interface for analog mux control. Connect this pin to VIN to disable the analog mux. When the analog mux is disabled, the OUT pin defaults to VTEMP measurement. Do not float this pin. RTMR (Pin 6): Serial Interface Timer Pin. Place a resistor from this pin to ground to set the serial count duration window, tW. See the Applications Information section for proper resistor selection. DIN (Pin 7): Data Input Pin. Take this pin to ground to initiate switching if MODE pin is connected to VIN, or to select the desired analog mux state if MODE pin is tied to ground. This pin is designed to be directly driven from the LTC680x family's S pins. OUT (Pin 8): Analog Output Pin. Connect this pin to an accurate voltage monitor to measure a voltage proportional to the internal IC temperature, VTEMP, if MODE pin is connected to VIN, or measure the output of the internal analog mux if MODE pin is connected to ground. In analog mux mode, the OUT pin allows voltage monitoring of the VCELL pin, the VSNS pin, or VTEMP. This pin is designed to be directly connected to the LTC680x family's C pins. Must connect a compensation capacitor to this pin. See the Applications Information section for proper capacitor sizing and placement. VIN (Pin 9): Supply Pin. Connect this pin directly to the positive battery cell terminal. Must be bypassed with high grade (X5R or better) ceramic capacitor placed close to the transformer's primary winding connection. VCELL (Pin 10): Cell Voltage Monitor Pin. This pin provides a Kelvin connection to the battery cell for accurate voltage monitoring. Connect this pin directly to the positive battery cell terminal. The recommended cell voltage is 2.5V to 5.3V. VSNS (Pin 11): Voltage Sense Pin. Connect this pin to the current sense resistor connected to the primary side of the transformer. Use this pin to measure average current discharged from battery cell (see the Block Diagram). MODE pin must be connected to ground and the internal analog mux must have the VSNS pin selected to use this feature. Input current is determined as (VVCELL - VVSNS)/RSNS. DCHRG (Pin 12): Discharge Pin. The Discharge pin can be configured as an input or output pin. Connect MODE pin to ground to configure DCHRG as an output pin where DCHRG is driven to VIN during switching and driven to ground when switching is deactivated. The output configuration can be used to drive multiple LT8584's or other switching regulators in parallel, to boost discharge capability. Connect MODE pin high to configure DCHRG as an input. When configured as an input pin, drive DCHRG pin to VIN to enable switching. Note in this mode that serial communication is disabled and the DIN pin must be grounded to initiate switching. SW (Pin 13, Pin 14, Pin 15, Pin 16): Switch Pin. This is the collector of the internal 6A NPN power switch. Minimize the metal trace area connected to this pin to minimize EMI. Connect the bottom side of the transformer primary to this pin. 8584fb For more information www.linear.com/LT8584 9 10 For more information www.linear.com/LT8584 CFBO RRTMR TO PARALLEL DISCHARGERS (OPTIONAL) MODULE- - VMODULE + MODULE+ * * VSW RTMR MODE 1.22V 40mV -+ 6.3m SW DCHRG Q1 T1 - + - + A3 VIN VIN SIMPLE MODE SERIAL MODE A1 TIMER A2 LATCH POWER DURING TIMER VIN DIE TEMPERATURE VSNS AMP VVIN - 1.4V VTEMP VVIN - 1.2V VVIN - 0.8V VVIN - 0.6V VVIN - 0.4V ANALOG MUX -+ 1V CHIP ENABLE VVIN - 0.2V +- 95mV TO S PIN (LTC680x) DIN VCELL - + DCM COMPARATOR SWITCH PROTECTION CIRCUITRY 11-BIT COUNTER CONTROL LOGIC Q R SWITCH S LATCH CURRENT COMPARATOR CTRAN + - D1 + - CHIP POWER M1 TO ANALOG MUX CVIN + - 1.6V M2 VIN + - - + 5k OUT PIN CLAMP 19x VSNS AMP 8584 BD GND OUT VCELL VSNS RSNS CELL BEING BALANCED CELL BELOW COUT TO C PIN LTC680x CVCELL CELL ABOVE LT8584 Block Diagram 8584fb LT8584 Timing Diagram DIN SR tRST t2 t3 t4 t6 RTMR t1 tW DCHRG t5 8584 TD Operation Many systems use multiple battery cells connected in series to increase the available capacity and voltage. In such systems, the individual battery cells must be constantly monitored to ensure that they operate within a controlled range. Otherwise, the battery's capacity and life span may be compromised. Linear Technology offers the LTC680x family series of multicell battery stack monitors (BSM) to accomplish this task. The LTC680x monitors each individual cell in the stack and communicates this information through a proprietary serial bus to a central processing unit. As a cell begins to reach the upper charge limit, commands are issued to the LTC680x to turn on that cell's passive shunt, bypassing the charging current to that cell and allowing the current to continue to the rest of the cells. The passive shunt current and/or power capability constrains the maximum charging current for the battery stack. Using a passive shunt is also inefficient, and the shunted current produces considerable heat at higher charging currents. The LT8584 solves the two limitations of passive shunting balancers by actively shunting the charging current and returning the energy back to the battery stack. Instead of the energy being lost as heat, it is reused to charge the rest of the batteries in the stack. The architecture of the LT8584 also solves the problem of reduced run time when one or more of the cells in the stack reaches the lower safety voltage threshold before the entire stack capacity is extracted. Only active balancing can redistribute the charge from the stronger cells (cells with higher voltage) to charge the weaker cells. This allows the weaker cells to continue to supply the load, extracting greater than 96% of entire stack capacity where passive balancing may only extract 80%. The LT8584 has an integrated 6A switch designed to operate as a boundary mode flyback converter and provides 2.5A average discharge current. The average discharge current is also scalable by using multiple LT8584s to balance each cell. Note that each battery in the stack requires an LT8584 active cell balancer. The LT8584 flyback topology allows the charge to return between any two points in the battery stack. Most applications use a module approach and return the charge to a local set of 12 series-connected cells monitored by a 12 channel BSM IC, where the output of the flyback converter is designated as VMODULE. The entire battery stack is then constructed using several 12-cell modules connected in series. A second approach is to return the charge to the entire battery stack, where the flyback output is designated as VSTACK. A final option is to return the charge to an auxiliary power rail, designated as VAUX. The LT8584 has two modes of operation--selectable by the MODE pin--that can be integrated with the LTC680x or other battery stack system. In simple mode, the LT8584 8584fb For more information www.linear.com/LT8584 11 LT8584 Operation discharger is toggled on/off using a logic input pin. In serial mode, the LT8584 allows the user to measure the discharge current and the die temperature, in addition to the cell voltage. ILPRI VVIN - VCESAT LPRI IPK General Flyback Operation t The first cycle will commence approximately 2s after LT8584 has been commanded to discharge a cell. The LT8584 is configured as a flyback converter operating in boundary mode (the edge of continuous operation), and has three basic states (see Figure 1). ILSEC VMODULE + VDIODE LSEC IPK N t VPRI 1. Primary-Side Charging VVIN - VCESAT When the switch latch is set, the internal NPN switch turns on, forcing (VVIN - VCESAT) across the primary winding. Consequently, current in the primary coil rises linearly at a rate of (VVIN - VCESAT)/LPRI. The input voltage is mirrored on the secondary winding as -N * (VVIN - VCESAT) which reverse-biases the secondary-side series diode and prevents current flow in the secondary winding. Thus, energy is stored in the core of the transformer. t -(VMODULE + VDIODE) N VSEC VMODULE + VDIODE t 2. Secondary-Side Energy Transfer When current limit is reached, the current limit comparator resets the switch latch and the device enters the second phase of operation, secondary-side energy transfer. The energy stored in the transformer core forward-biases the series diode and current flows into the output capacitor and/or battery. During this time, the output voltage plus the diode drop is reflected back to the primary coil. VSW VVIN + VMODULE + VDIODE N VVIN VCESAT VCESAT t 3. Discontinuous Mode Detection During secondary-side energy transfer to the output capacitor, (VMODULE + VDIODE)/N will appear across the primary winding. A transformer with no energy cannot support a DC voltage, so the voltage across the primary winding will decay to zero. In other words, the collector of the internal NPN, SW pins, will ring down from VVIN + (VMODULE + VDIODE)/N to VVIN. When the SW pin voltage falls below VVIN + 95mV, the DCM comparator sets the switch latch and a new switch cycle begins. States 1-3 continue until the part is disabled. 12 -N(VVIN - VCESAT) (1) (2) (3) PRIMARY-SIDE SECONDARY-SIDE DISCONTINUOUS CHARGING ENERGY TRANSFER MODE AND OUTPUT DETECTION DETECTION 8584 F01 Figure 1. Simplified Discharging Waveforms 8584fb For more information www.linear.com/LT8584 LT8584 Operation Switch Protection Overvoltage Protection (OVP) Several protection features are included to reduce the likelihood of permanent damage to the internal power NPN switch: the short-circuit detector, the high-impedance detector, the switch overvoltage protection (OVP), and internal undervoltage lockout (UVLO). These also alert the user when the integrity of the discharge converter has been compromised because of a fault. Switching is disabled during fault conditions. The OVP circuitry dynamically clamps the NPN collector's SW pins to 50V. This protects the internal power switch from entering breakdown and causing permanent damage. The clamp is also used as a primary-side snubber to absorb the leakage inductance energy. The 200ns switch clamp blanking time determines if the clamp is absorbing a leakage spike or if the switch is turning off while the secondary of the transformer is open. If the switch clamp is on longer than approximately 200ns, the switch error latch is set. The part must be reset to clear the switch error fault. Short-Circuit Detector The short-circuit detector detects when the power NPN switch turns off prematurely due to a short in the primaryside winding. If the current comparator trips before the 850ns short detection timeout, the switch error latch will trip. The OUT pin is driven to VVIN - 1.2V, VSW,ERR, during a switch error. The part must be reset to clear the switch error fault. High-Impedance Detector The high-impedance detector monitors how long the power NPN switch has been on. If the switch remains on longer than 50s, the switch maximum on-time, the switch error latch is set and the OUT pin is driven to VVIN - 1.2V, VSW,ERR. The part must be reset to clear the switch error fault. Internal Undervoltage Lockout (UVLO) LT8584 protects itself during a UVLO condition by disabling switching. The OUT pin is driven to VVIN - 1.4V, VFAULT, during a UVLO condition. A UVLO fault is non-latching and dominates over a switch fault (Serial Mode requires VIN to remain above 2V for a UVLO fault to be non-latching). Once the UVLO condition is cleared, the OUT pin reverts to normal operation and switching resumes. If the switch fault latch was tripped prior to the UVLO event, the OUT pin will indicate a switch fault, VSW,ERR, only after the UVLO condition is cleared and switching would remain disabled. STACK+ STACK+ * LOCAL IC GND LOCAL IC GND * * LT8584 MODE VIN OFF ON DIN GND LT8584 MODE OFF ON * STACK- VSNS VCELL SW DCHRG OUT LOCAL IC GND STACK- VSNS VCELL VIN LOCAL IC GND SW DCHRG DIN OUT RTMR GND RTMR 8584 F02 ACTIVE LOW ACTIVE HIGH Figure 2. Simple Mode Configurations 8584fb For more information www.linear.com/LT8584 13 LT8584 Operation Simple Mode Operation OUT Pin in Simple Mode Connecting the MODE pin to the VIN pin configures the LT8584 as a simple discharger with a simple on/off shutdown pin. Two shutdown options are provided to handle either an active high (DCHRG) or an active low input (DIN), see Figure 2. Connect DIN to ground and use DCHRG pin for an active high input, or connect DCHRG to VIN and use DIN as an active low input. The part will begin switching once the DIN pin is low and DCHRG is high. Figure 3 shows the enable logic function. Never drive DIN more than 0.4V below the local ground while operating in active-high simple mode. The OUT pin defaults to VTEMP, a voltage proportional to the die temperature, and is measured with respect to the cell voltage such that VTEMP = VVCELL - VOUT. This can be used to monitor the internal die temperature for system diagnostics. The OUT pin will also output two distinct indication voltage levels, VVIN - 1.4V, VFAULT, for an internal UVLO condition, or VVIN - 1.2V, VSW,ERR, for a switch error. VTEMP is not allowed to exceed 1V (equivalent to 180C)1. This makes both the fault and switch error voltages deterministic. The switch error latch is set when the power NPN switch has encountered a fault (see the Switch Protection section for more details). DCHRG ENABLE BALANCING DIN 1 Not verified during production testing. 8584 F03 Figure 3. Simple Mode Enable Logic DIN SHUTDOWN ENABLED WITH CORRECT STATE SERIAL DECODE VVIN SHUTDOWN t RTMR DECODE WINDOW 1.22V 16.3ms RRTMR = 100k t OUT VVIN VVIN - 0.2V VVIN - 0.4V VVIN - 0.6V VVIN - 0.8V VVIN - 1.4V OUT WILL NEVER BE DRIVEN BELOW VVIN - 1.435V OUT PIN CLAMP IS ACTIVE BELOW VVIN - 1.53V t VCELL SELECTED VOLTAGE MODE HANDSHAKE ANALOG MUX ACTIVATED TO DESIRED INPUT VCELL SELECTED 8584 F04 Figure 4. Serial Communication Decode 14 8584fb For more information www.linear.com/LT8584 LT8584 Operation OSCILLATOR EN POR 11-BIT Y0 RIPPLE RST COUNTER Y11 2x4 DECODER 1-SHOT POR VDD DIN POR 2-BIT RIPPLE Y0 RST COUNTER Y1 POR S Q R Q S Q R Q VDD a A MODE 1 B MODE 2 C MODE 3 D b MODE 4 8584 F05 Figure 5. Serial Communication Architecture Serial Mode Operation Serial Architecture Use serial mode if monitoring the discharging current and/or the die temperature are required. Connecting the MODE pin to GND enables serial communication. The DIN pin is used to input serial data through a custom serial bus (see Figures 4 and 5). Power to the part is latched on the first negative edge of DIN signal and remains latched for the duration of the decode window, tW. This allows the DIN pin to be toggled for communicating serial data without resetting the part. Serial Mode Safety Features The LT8584 provides the user with several levels of safety and verification. The LT8584 has built in switch protection that detects and halts power delivery during either a primary-side open or short, a secondary-side open or short, or an overvoltage on the primary or secondary. The LT8584 outputs the VSW,ERR handshake that can be read back by the battery stack monitor (BSM). The LT8584 also detects communication errors including too many or too few DIN pulses or a UVLO condition. The LT8584 outputs the VFAULT handshake that can be read back by the BSM. The LT8584 also provides critical cell parameters including temperature, discharge current, cell voltage, and cell and connection DC resistance. These are all read back by the BSM. As the cell starts to age, the cell impedance increases. This allows the user to perform preventative maintenance, keeping the system down time to a minimum. Finally, the LT8584 handshake voltages are 3% accurate independent references that can be used to verify that every channel in the BSM is measuring accurately. The LT8584 counts the number of negative edges seen on the DIN pin. Note that the first edge, which initiates serial communication and latches the part, is not counted. There are four active modes the user can select as shown in Table 1. Handshaking is accomplished by reading the analog voltage on the OUT pin. Handshaking voltages are asserted on the negative edge of the DIN signal, corresponding to the serial decode count. Once the decode window expires and RTMR pin returns to ground, three actions are initiated: the OUT pin analog multiplexer switches to the desired measurement, the discharger turns on depending on selected mode in Table 1, and the input power latch disables. Note that the LT8584 can only be disabled after the decode window has expired and the DIN pin has been taken high. Table 1.Serial Mode States MODE DISCHARGER STATE MUX OUTPUT HANDSHAKE VOLTAGE (VVIN - VOUT) Part Disabled 0 Disabled VCELL N/A PULSE COUNT 0 Fault Disabled VFAULT 1.4 1 1 Enabled VCELL 0.2 2 2 Enabled VSNS 0.4 3 3 Enabled VTEMP 0.6 4 4 Disabled VTEMP 0.8 5 Fault Disabled VFAULT 1.4 8584fb For more information www.linear.com/LT8584 15 LT8584 Operation Serial Timer Decode Window OUT Pin Analog MUX The timer initiates on the first negative edge on the DIN pin. RTMR pin remains high for the duration of the timer which signifies the decode window for the serial input counter. A resistor from the RTMR pin to ground sets the decode window duration. The duration can be accurately set from 1.9ms (RRTMR = 10k) to 31ms (RRTMR = 200k). The timer can be set outside this range, but the accuracy decreases. The serial input counter stops counting and latches the data once the RTMR pin goes low; after which, the OUT pin amplifier input MUX selects the desired measurement, and the discharger is set to the right state. An internal multiplexer, MUX, selects between VCELL and the OUT pin amplifier based on one of the selected Serial Modes shown in Table 1. The OUT pin amplifier has a 5k internal load and has several inputs including: VTEMP, the 19*VSNS amplifier, and six handshake voltages. The internal MUX defaults to VCELL in shutdown--consuming no power in the process--and provides a 55 nominal resistance from the VCELL pin to the OUT pin. Figure 6 shows the connection of the OUT pin to a BSM and its internal analog MUX. The serial interface has several fault monitors that prevent entering undesired modes due to a communication error. The OUT pin is set to VVIN - 1.4V to indicate the LT8584 is in fault. The part remains in fault from the onset of RTMR going high until the first count is detected. If no count is seen by the serial input counter during the decode window, the fault is latched. If the serial input counter counts higher than 4 negative edges, the fault latch is set. The MUX switches over to one of the handshake voltage levels once both the LT8584 and the decode window are activated. The OUT amplifier will indicate a fault at start-up until the serial input counter recognizes the first negative edge on DIN. Subsequent negative edges on DIN cause the MUX to select the handshake voltage corresponding to the number of edges counted. These voltage levels provide a means of verifying if the serial interface has recognized the correct count. Note that the OUT pin amplifier has an approximate 200s one percent settling time when driving a 220nF load capacitance. A third latching fault occurs if an internal undervoltage lockout (UVLO) is detected during the decode window. This protects against undesired operation if data latches or the serial input counter were reset. The part must be reset by taking DIN high to clear a fault. Once the RTMR pin goes low, the MUX selects the OUT pin mode corresponding to the number of serial input counts (see Table 1 for available modes). The part can also be placed in shutdown when RTMR is low and the decode window has expired. DIN Pin and Serial Bus Timing VCELL Measurement Several internal passive filters are added to the data bus to prevent injected system noise corrupting serial communication. These filters have time constants that place constraints on the serial communication timing requirements (see the Timing Diagram). The LT8584 can reject up to 4s of erroneous glitches on the DIN pin in either direction. The power latch filter can also reject up to a 4s glitch on DIN. The user can measure the cell voltage by measuring the voltage on the OUT pin either with the part disabled (discharger off) or with the part enabled in MODE 1 (discharger on), see Table 1. The LT8584 uses an internal PMOS switch with RDSON = 55 to connect VCELL to the OUT pin. Note that any current flowing into or out of the OUT pin will cause a measurement error due to the IR drop across the switch. Serial Communication Fault Modes The DIN pin has built-in hysteresis of approximately 100mV. This allows the serial input counter to recognize both slow and fast edges without erroneous behavior. The discharger activation or deactivation time is typically less than 3s and is a direct indication of the switch enable latch state. 16 VSNS 19x Amplifier An amplifier is provided to allow the user to monitor the discharger current. This measurement can only be performed when the discharger is on (MODE 2). The differential voltage between VVCELL and VVSNS is amplified 19x. 8584fb For more information www.linear.com/LT8584 LT8584 Operation RSNS 1:4 + * * VCELL VIN VSNS LTC680x - SW LT8584 ANALOG MUX DCHRG VMODULE VCELL VTEMP VSNS AMP + VIN - 0.2V VIN - 0.4V BAT2 OUT C2 DIN S2 VIN - 0.6V RTMR VIN - 0.8V VIN - 1.2V VIN - 1.4V MODE GND CONTROL COUNTER DCC2 BIT RSNS 1:4 + * * VCELL VIN VSNS ANALOG MUX DCHRG ADC VMODULE - SW LT8584 VCELL VTEMP VSNS AMP + VIN - 0.2V VIN - 0.4V BAT1 OUT C1 DIN S1 VIN - 0.6V RTMR VIN - 0.8V VIN - 1.2V VIN - 1.4V MODE GND CONTROL COUNTER DCC1 BIT C0 8584 F06 Figure 6. Serial Mode Analog MUX Connection 8584fb For more information www.linear.com/LT8584 17 LT8584 Operation This reduces errors due to input offset in the measurement circuitry connected to the OUT pin. It also allows the use of low-value resistors, and thus, yields greater overall efficiency. where TJ,CORR is the corrected die temperature and TJ,CAL is die temperature calculated from the previous equation. For accuracy, the VIN pin should be tied to the VSNS pin to include both the LT8584 bias current and the internal NPN base drive current. Tying the VIN pin to the VSNS pin changes the overall gain to 20x. Tying the VIN pin to the VCELL measures transformer current only and the overall gain remains 19x. All parameters including handshake voltages, VSNS, and VTEMP are extracted differentially by taking two sequential measurements and doing a subtraction. Figure 7 shows the method for extracting a given parameter, VPAR, from the highlighted LT8584. The LT8584 directly below the LT8584 under measurement must be forced to select VCELL (MODE 0) and becomes the negative reference for both sequential measurements. The VSNS amplifier has a -30mV to 70mV dynamic input range. Internal filtering and circuit architecture allows accurate measurements even when the input current contains negative components. The VSNS amplifier requires that the average input current remain positive. VVIN - VOUT is not allowed to exceed 1V during VSNS measurement to guarantee that both VFAULT and VSW,ERR are deterministic. This sets the maximum average input range, VVCELL - VVSNS, to 50mV. Die Temperature Output The user can also monitor the die temperature by selecting either MODE 3 (discharger enabled) or MODE 4 (discharger disabled). The voltage VVCELL - VOUT, VTEMP, is proportional to the absolute temperature in degrees Kelvin. Thus, the user needs to take two measurements to calculate the die temperature. Temperature data gives the user a second means to verify if the discharger is on as well as to monitor environmental conditions. VTEMP is not allowed to exceed 1V (equivalent to 180C)1 to make both VFAULT and VSW,ERR deterministic. The following equation is used to determine the internal die temperature in degrees Celsius: TJ (C) = VTEMP - 0.609 0.00197 where VTEMP = VVCELL - VOUT and expressed in volts. Although the absolute die temperature can deviate from the above equation by 25C, the relationship between VTEMP and the change in die temperature is well defined. The offset error can be calibrated out using an accurate system temperature monitor like that in the LTC680x family of parts. There is also a small VVCELL dependence on VTEMP which can be corrected using the following expression: TJ,CORR (C) = TJ,CAL + (4.2V - VCELL) * 2C 18 Serial Mode Differential Measurements Table 2. MODE Selection During Differential Measurements DESIRED PARAMETER Handshake Voltage VSNS VTEMP, Balancer Enabled VTEMP, Balancer Disabled SERIAL MODE STATE 1ST MEASUREMENT 2ND MEASUREMENT MODE 0 MODE 1 MODE 1 MODE 0 During Decode Window MODE 2 MODE 3 MODE 4 Selecting VCELL for the first measurement is performed by entering either MODE 0 (balancer disabled) or MODE 1 (balancer enabled). Use Table 2 to determine which VCELL to reference for a given parameter. All measurements are taken after the decode window has expired, unless otherwise noted. VPAR = 1st Measurement - (2nd Measurement) = VCELL - (VCELL - VPAR) The LTC6803's channel above the channel under measurement will have a voltage higher than a standard cell, VCELL + VPAR, see Figure 7. The LT8584 was architected to protect the LTC6803's ADC inputs and to guarantee that they well never be stressed beyond their absolute maximum rating. DCHRG Output The DCHRG pin allows the LT8584 to operate several dischargers in parallel. The DCHRG pin goes high when the switch enable latch is set. The DCHRG pin can be used to directly drive the DCHRG pin of another LT8584 configured in simple mode (MODE pin connected to VIN) or to directly drive the shutdown pin of another power converter. It has the ability to sink or source currents up to 300A. 1 Not verified during production testing. For more information www.linear.com/LT8584 8584fb BAT1 BAT2 BAT3 * * * - GND - GND LT8584 VCELL LT8584 VCELL2 VCELL GND + LT8584 VCELL3 VCELL GND - + LT8584 VCELL4 VCELL OUT OUT OUT OUT ANALOG MUX SELECTING VCELL ANALOG MUX SELECTING VCELL - VCELL2 + - VCELL3 + - VCELL4 + * * * * * * For more information www.linear.com/LT8584 ADC BAT1 BAT2 BAT3 BAT4 GND - GND LT8584 VCELL LT8584 VCELL2 VCELL - + GND VCELL LT8584 VCELL3 + GND - VCELL LT8584 VCELL4 + OUT OUT OUT OUT ANALOG MUX SELECTING VCELL ANALOG MUX SELECTING PARAMETER - VCELL2 + - VCELL3 - VPAR,3 + - VCELL4 + VPAR,3 + C0 C1 C2 C3 C4 ADC LTC680x * * * * * * * * * * * * * * * * * * * * * 8584 F07 * * * Figure 7. Serial Mode Differential Measurements C0 C1 C2 C3 C4 LTC680x MEASUREMENT 2 (VCELL - VPAR) * * * BAT4 + MEASUREMENT 1 (VCELL) LT8584 Operation * * * * * * 8584fb 19 LT8584 Applications Information The LT8584 can be used as a discharger for balancing the charge in battery or supercapacitor stack systems. The user can choose either simple mode or serial mode. The LT8584 can be driven from any battery stack monitor such as the LTC680x. Simple mode can be employed using either active high or active low logic, increasing its interface flexibility. Component Selection Few external components are required to achieve balancing. The only external components are the transformer, the output diode(s), the VIN bypass capacitors, the RSNS resistor (for measuring discharge current), the RRTMR resistor (for serial mode), and in some cases, a RCD snubber. The equations are shown for a module based approach described in the Operation section. VMODULE becomes VSTACK in all equations for applications returning charge to the entire stack voltage, and VMODULE becomes VAUX for all applications returning charge to an auxiliary power rail. turns to achieve a desired primary inductance; thus, a balance can be achieved between core and winding losses. Recommended transformers are given in Table 3 that have been optimized for efficiency and size. Use the following guidelines when designing new transformers. Reduce the transformer size by designing the boundarymode operating frequency between 100kHz and 150kHz. The peak primary current is fixed at 6A by the chip. The transformer turns ratio, N, should be selected by optimizing the converter input RMS current, i.e. battery discharge current. The RMS input current can be estimated as: IRMS,IN = IPK * BM * tON 3 Note that negative switch current reduces the RMS input current by effectively reducing the boundary-mode frequency, BM, (see Figure 8). Reduce the overall reflected capacitance on the SW node by reducing the output diode and transformer interwinding parasitic capacitances. Transformer Design The transformer design should yield overall converter efficiencies greater than 80%. This reduces heat dissipation and allows for a smaller converter PCB footprint. A proper transformer design balances core losses with winding losses. The LT8584 converter operates in DCM where the flux swing in the transformer is the greatest. This shifts most of the heat loss from winding loss to core loss. Reduce transformer core flux swing by lowering the air-gap permeability. A lower permeability requires more VSW ISEC NO SEC. CAPACITANCE IPRI SEC. DISCHARGE 8584 F08 t Figure 8. Effect of Secondary Winding Capacitance Table 3. Recommended Transformers RECOMMENDED RCD SNUBBER OUTPUT RANGE (V) REQUIRED SIZE W x L x H (mm) MANUFACTURER PART NUMBER LPRI (H) TURNS RATIO (PRI:SEC) Coilcraft www.coilcraft.com NA6252-AL NA5743-AL NA5920-AL* 10 to 35 30 to 80 100 to 400 Yes Yes No 15.24 x 12.7 x 11.43 15.24 x 12.7 x 11.43 15.24 x 12.7 x 11.43 4 4 4 11:15 1:4 1:24 Cooper Bussmann www.cooperindustries.com CTX02-19175-R CTX02-19174-R CTX02-19176-R* 10 to 35 30 to 80 100 to 400 Yes Yes No 15 x 13 x 12 15 x 13 x 12 15 x 13 x 12 4 4 4 3:4 1:4 1:24 Wurth www.we-online.com 750314019_R01 750314018_R02 750314020_R01* 10 to 35 30 to 80 100 to 400 Yes Yes No 15.24 x 13.34 x 11.43 15.24 x 13.34 x 11.43 15.24 x 13.34 x 11.43 4 4 4 3:4 1:4 1:24 * Switch error latch may trip when starting at voltages lower than the recommended output range. 20 8584fb For more information www.linear.com/LT8584 LT8584 Applications Information The RMS input current can be increased by increasing the ratio between the effective switch on-time, tON, and off-time, tOFF. This off-time ratio is set by the transformer ratio, N. The following equation sets the switch off-time to approximately 1/3 of the switch on-time to optimize power transfer and efficiency. N= Secondary Turns VMODULE = Primary Turns 3 * VIN VSW LEAKAGE SPIKE CLAMPED TO 50V VVIN + VSTACK/N MUST BE LESS THAN 40V 0V 8584 F06 The off-time ratio should not be decreased much beyond 1/5; otherwise, secondary-side energy transfer time becomes too short, and the converter efficiency is reduced. Some applications may require a lower RMS current due to charging limitations or thermal dissipation limitations. Both can be reduced by increasing the turns ratio, N. Use the following equation to size the transformer's primary inductance: LPRI = IPK 1 1 N * BM * + VIN V MODULE t Figure 9. Internal Switch Voltage Waveform Higher transformer turns ratios benefit from higher reflected capacitance that helps snub the leakage spike. N ratios less than 8 usually require an RCD snubber to help clamp this primary-side leakage spike and increase the converter efficiency. Good values for the resistor and capacitor are 4.99k and 22nF, respectively. Output Diode Keep the primary inductance in the range of 2.2H to 10H. The lower limit guarantees proper detection of an open circuit in the transformer's secondary. The upper limit guarantees the high-impedance detector does not activate a false switch error during normal operation. Leakage Inductance Leakage inductance causes added voltage stress on the internal power NPN collector. The LT8584 uses an internal Zener clamp to absorb this leakage spike energy and clamp the switch node voltage to 50V. The leakage spike energy should be limited to improve efficiency. Figure 9 shows the waveform of the internal NPN switch. Design the transformer to have minimum leakage inductance. Keep both transformer windings tightly wound around the core air gap. Using a bifilar winding or a sandwiched secondary decreases leakage inductance. Note that increased interwinding capacitance is a trade-off with lower leakage inductance. Several iterations may be required to optimize the transformer design. The output diode(s) are selected based on the maximum repetitive reverse voltage (VRRM) and the average forward current, IF(AVG). The output diode's VRRM should at a minimum exceed VMODULE + N * VVIN. The LT8584's internal OVP circuitry triggers at 50V, and VRRM should therefore exceed N*(50 + VVIN) to prevent damage to the output diode during an OVP event. Note that the leakage spike will usually cause the OVP to trigger roughly 10% lower than the nominal reflected voltage on the primary. The output diode's IF(AVG) should exceed IPK /2N, the average short-circuit current. The average diode current is also a function of the output voltage. IPK * VVIN IF(AVG) = 2 * VMODULE +N * VVIN ( ) The highest average diode current occurs at low output voltages and decreases as the output voltage increases. Reverse recovery time, reverse bias leakage, and junction capacitance should also be considered. All affect the overall charging efficiency. Excessive diode reverse recovery times can cause appreciable discharging of the output stack, thereby decreasing charge recovery. Choose a diode with a reverse recovery time of less than 75ns. 8584fb For more information www.linear.com/LT8584 21 LT8584 Applications Information Diode leakage current under high reverse bias bleeds the output battery/capacitor stack of charge. Choose a diode that has minimal reverse bias leakage current. Diode junction capacitance is reflected back to the primary, and energy is lost during negative NPN collection conduction. Choose a diode with minimal junction capacitance. Table 4 recommends several output diodes for various output voltages that have adequate reverse recovery times. Flyback Output Capacitor Every balancer flyback output must have a ceramic capacitor on its output. The output capacitor serves as a local, low impedance return path. It also aids during a connection failure, adding charge storage to allow the OVP circuit to detect an open. The capacitor should be sized to allow roughly 10 switch cycles when charging the output from ground to the nominal output voltage, VOUTPUT,NOM. Use the following equation to size the output capacitor: C FBO 400 * LPRIMARY V 2OUTPUT,NOM The voltage surge rating must exceed 50*N. The voltage surge rating is usually specified as a multiple of the maximum operating voltage. For capacitor maximum operating voltages less than 100V, the surge rating is 2.5x. For operating voltage between 100V and 630V, the surge rating is typically 1.5x; and for voltages higher than 1000V, the surge rating is 1.2x. Bypass Capacitors The LT8584 should be bypassed using 3 capacitors, CVIN, CVCELL, and CTRAN (see Block Diagram), using a high-grade (X5R or better) ceramic capacitors. CVIN should be placed close to the VIN pin and should be sized between 1F and 4.7F. CTRAN must be placed close to the transformer's primary winding connection and the IC local ground. The capacitance should range between 47F and 100F. Simple mode should have VSNS, VCELL, and DCHRG shorted to VIN, which provides an excellent landing for both the transformer primary and a single bypass cap (see the Recommended Layout section). CVIN may be omitted in Simple Mode provided that the CTRAN capacitor is in close proximity to the VIN pin. CVCELL is used for bulk capacitance and should be place close to the battery input connection. Ceramic capacitors are a good choice for bypassing due to their moderate density, low internal series impedance, and very low leakage current. Note that capacitor leakage current at a given operating voltage goes down with increasing capacitor voltage rating. Ceramic capacitors offer the lowest leakage current, while most electrolytic capacitors are quite leaky. Table 4. Recommended Output Diodes MANUFACTURER STMicroelectronics Fairchild Semiconductor www.fairchildsemi.com Vishay www.vishay.com RECOMMENDED TRANSFORMER TURNS RATIO (N) RANGE 1 to 2 PART NUMBER IF(AVG) (A) VRRM (V) trr (ns) JUNCTION CAPACITANCE (pF) PACKAGE STPS3H100U 3 100 N/A 90 SMB STPS2H100AY* 2 100 N/A 50 SMA 2 to 4 STTH102AY* 1 200 20 12 SMA 10 to 24 STTH112A 1 1200 75 1 to 2 ES2B 2 100 20 SMA 18 SMB 2 to 4 ES1D 1 200 15 7 SMA 4 to 8 ES1G 1 400 35 10 SMA 6 to 12 ES1J 1 600 35 8 SMA 1 to 2 SS2H10* 2 100 N/A 70 SMB U2B 2 100 20 16 SMB 2 to 4 10 to 20 ES1D 1 200 15 10 SMA ES07D-M* 1.2 200 25 5 SMF US1M 1 1000 50 10 SMA *AEC-Q101 Qualified 22 8584fb For more information www.linear.com/LT8584 LT8584 Applications Information Discharge Current Sense Resistor OUT Pin Compensation and Filtering The discharge current sense resistor, RSNS, should only be used in serial mode. Omit this resistor and short VSNS and VCELL to VIN in simple mode. The maximum sense voltage between VVSNS and VVCELL is 50mV. It is recommended to design for a nominal sense voltage of 30mV. It is not recommended to design for a nominal sense voltage below 20mV since the input offset voltage of the differential amplifier contributes more error at the lower range. V - VVSNS 30mV RSNS = VCELL = = 12m IDIS,AV 2.5A The OUT pin must have external compensation, COUT, for all applications including both serial mode and simple mode. The external capacitor also provides necessary filtering for the input to the BSM. The OUT amplifier is internally compensated to handle capacitance ranging from 20nF to 220nF. Use 47nF for most applications to yield approximately 100s 1% settling time. A faster amplifier response can be achieved by adding a zero using a resistor in series with the external filter capacitor. Use 4.7nF capacitor with a 60 series resistor to achieve a sub-100s settling time. Note that in serial mode, the capacitors are placed between adjacent LT8584 OUT pins. This effectively doubles the compensation capacitance from the capacitor value used. The OUT amplifier also has internal filtering to both improve PSRR and handle large-signal steps or spikes that may be present on the supply lines. The internal amplifier amplifies the voltage difference between VVSNS and VVCELL 20x when VIN is tied to VSNS. The voltage is referenced from VCELL such that: VVCELL - VOUT = 20 * (RSNS * IDIS,AV) The measurement is the average discharge current, IDIS,AV, and not the RMS value. The output, VVIN - VOUT, is clamped to a maximum of 1V. Decode Window Resistor, RRTMR RTMR pin is used to set the duration of the decode window and is programmed by selecting the value of the resistor connected between RTMR and GND. This pin is used in serial mode only. Ground this pin when using simple mode. The decode window is programmable from 1.9ms to 31ms. Set the decode window duration 30% longer than the required time to set the LT8584 in MODE 4 and read back the handshake voltage. This allows the system to detect if there is a communication error. Set RRTMR based on following equation: RRTMR (k) = 0.015 * t2 W + 5.9 * tW - 1.1 Additional filtering may be required in noisy environments. Figure 10 shows a two-pole filter with the LT8584 operating in serial mode. The resistors must be kept small to minimize error due to non-zero input currents into the BSM. The LTC6804 is guaranteed to have 2A or less input bias current during measurement. There are two resistors in any given measurement path. Thus, a 50 series resistor will introduce up to a 200V error. DIN pin current will also cause an error when enabling a particular LT8584, but the error term is canceled when making differential measurements. LT8584 OUT OUT AMP where RRTMR is given in k and tW is given in ms. The RTMR pin is driven to 1.22V approximately 2s after the part is first enabled. This indicates the decode window is active. The RTMR pin is taken low after the decode window expires. The internal decoder states are latched on the falling edge of RTMR (see Figure 4). The OUT pin multiplexer then selects the correct input corresponding to the programmed mode (refer to Table 1). LT8584 OUT OUT AMP COUT 47nF 50 COUT 47nF 100nF TO BSM 2A 100nF 2A FROM BSM 50 COUT 47nF 100nF 8584 F10 Figure 10. Optional OUT Pin Filtering 8584fb For more information www.linear.com/LT8584 23 LT8584 Applications Information Hot SwapTM Protection Large currents are developed when hot swapping a battery with a LT8584 application due to the large input bulk capacitance coupled with the low ESR of the batteries. In most cases, the LT8584 should have no problem handling the overshoot voltage that follows the large inrush current. The downstream BSM, however, might encounter damage that requires additional steps and/or circuitry to protect against hot swapping. Several solutions use a two-path method incorporating a pre-charge resistive path and a shunt path (see Figure 11). 10 This method has the disadvantage of lower efficiency and higher cost. Use FETs for M1 in Figure 12 that have low RDS,ON to maximize converter efficiency and have less than a 1.25V VGS threshold. Table 7 lists several recommended FETs for M1. C1 should be sized such that C1 CVIN /500. The third active solution protects the flyback output capacitors. All flyback outputs sum together and flow through D13. During a Hot Swap condition, D13 will reverse bias and prevent a large inrush current into the flyback output capacitors. The peak repetitive reverse voltage, VRRM, should exceed the maximum module voltage, VMODULE. Several recommended diodes for D13 are given in Table 8. Mechanical Solution + VBAT - CVIN BATTERY CONNECTION LT8584 DIN 8584 F11 Figure 11. Dual Path Hot Swap Solution For most applications, use the recommended Hot Swap Solution shown as Active Solution 1 in Figure 12 and in the Typical Application Section. Several other mechanical, active, and order-of-assembly solutions are also given as alternatives or as supplements. Active Solution An active solution has the added advantage of automatic hot swap protection; no additional steps are needed when connecting batteries. Two input protection solutions are shown with the first solution using only TVS diodes. D1 is selected to trigger around 6V and to take the brunt of the connection input pulse. The reverse leakage current is more significant in low-voltage TVS's. Table 5 gives several diodes for D1 that have adequate current and voltage characteristics while minimizing reverse leakage current. D2 provides secondary protection for the BSM inputs. These should be smaller than D1 since the LT8584's OUT pin limits current. Table 6 gives several diodes that are optimal for D2. The second active solution has additional overvoltage protection via a fuse, F1, and a pre-charge MOSFET circuit. 24 A mechanical approach may result in a more cost effective solution. A 10 resistor is used to pre-charge the CVIN capacitor to the battery voltage, limiting the inrush current. After the CVIN cap is charged, a mechanical short is connected across the resistor and remains there during all normal operations. There are three recommended solutions for the mechanical short: 1.) use a > 3A rated jumper 2.) use a mechanical switch or 3.) use a staggered-pin battery connector. The staggered pin connection has the long pins connecting to LT8584 through the 10 resistor. The short pins connect directly to the LT8584, shorting out the 10 resistor. Normal insertion has a delay on the order of milliseconds between the long pin connecting and short pin connecting to the circuit, allowing CVIN to charge up through a current limiting resistor before the mechanical short is made. Order of Assembly The order of assembly of the battery stack, the LT8584 balancers, and the BSM can also mitigate hot swapping issues. Having separate boards for both the LT8584 balancers and the BSM is recommended. This allows the LT8584 balancers to be built and connected during the battery stack assembly. The last step involves mating the battery stack and LT8584 assembly with the BSM board. Additional filters on the inputs into the BSM also reduce possible issues during final assembly, see the OUT Pin Compensation and Filtering section for more detail. 8584fb For more information www.linear.com/LT8584 LT8584 Applications Information TOP OF STACK + VBAT - TOP OF STACK BATTERY CONNECTION + D2 D1 CVIN LT8584 VBAT TO C12 - F1, 5A BATTERY D1 CONNECTION 10 C1 M1 LT8584 100k D2 + VBAT D1 - CVIN LT8584 F1, 5A + TO C11 VBAT D1 - 10 C1 M1 + VBAT - D1 CVIN LT8584 F1, 5A + TO C10 VBAT D1 - CVIN LT8584 100k D2 CVIN 10 C1 M1 100k CVIN LT8584 8584 F12 ACTIVE SOLUTION 1 ACTIVE SOLUTION 2 20k MODULE + + D13 BAT12 * BAT2 * BAT1 LT8584 GND SW D2A T2 1:4 C2 1F * LT8584 GND SW + C12 * LT8584 GND SW + D12A T12 1:4 * D1A T1 1:4 * C1 1F MODULE - FLYBACK OUTPUT HOT SWAP PROTECTION Figure 12. Active Hot Swap Solutions 8584fb For more information www.linear.com/LT8584 25 LT8584 Applications Information Table 5. Recommended Transient Voltage Suppressors (TVS) for D1 in Figure 12 MANUFACTURER PART NUMBER REVERSE LEAKAGE (A) VP-P AT IP-P PACKAGE STMicroelectronics SM2T6V8A 50 at 5V 9.2V at 19.6A DO-216AA SM4T6V7AY* 20 at 5V 9.2V at 43.5A SMA SMA6T6V7AY* 20 at 5V 9.1V at 68A SMA VESD05A1-02V 1 at 5V 12V at 16A SOD-523 GSOT05* 10 at 5V 12 at 30A SOT-23 NXP PESD5V0S1UA 4 at 5V 13.5V at 25A SOD-323 Infineon ESD5V0S1U-03W 20 at 5V 14V at 40A SOD323 REVERSE LEAKAGE (A) VP-P AT IP-P PACKAGE Vishay *AEC-Q101 Qualified Table 6. Recommended Transient Voltage Suppressors (TVS) for D2 in Figure 12 MANUFACTURER PART NUMBER STMicroelectronics ESDALC6V1-1M2 0.1 at 3V 9.2V at 6A SOD882 Vishay VBUS051BD-HD1 0.1 at 5V 16V at 3A LLP1006-2L VESD05-02V 0.1 at 5V 20V at 6A SOD-523 Diode Inc T5V0S5-7 0.05 at 5V 15V at 5A SOD-523 NXP PESD9X5.0L* 0.2 at 5V 10V at 1A SOD-882 *AEC-Q101 Qualified Table 7. Recommended FETs for M1 in Figure 12 MANUFACTURER PART NUMBER Fairchild Semiconductor www.fairchildsemi.com Vishay www.vishay.com RDS,ON (m) AT VGS = 2.5V IDS,MAX (A) PACKAGE FDS4465 10.5 13.5 SO-8 FDS6576 20 11 SO-8 FDMA905P 21 10 MicroFET 2x2 FDMA910PZ 24 9.4 MicroFET 2x2 Si7623DN 9 35 PowerPAK 1212-8 Si7615ADN 9.8 35 PowerPAK 1212-8 SiS407DN 13.8 25 PowerPAK 1212-8 SiA447DJ 19.4 12 PowerPAK SC-70 IF(AVG) (A) VRRM (V) PACKAGE Table 8. Recommended Diodes for D13 in Figure 12 MANUFACTURER PART NUMBER Diodes, Inc. www.diodes.com SBR8U60P5 8 60 POWERDI5 PDS760-13 7 60 POWERDI5 Vishay www.vishay.com V8P10-M3 8 100 TO-277A SS10P6 7 60 TO-277A 26 8584fb For more information www.linear.com/LT8584 LT8584 Applications Information Operating Paralleled LT8584s Multiple LT8584s may be used if more discharge current is required. The LT8584 connected to a battery stack monitor (LTC6804 is recommended) becomes the master balancer. Connect its MODE pin to ground. Limit the maximum number of parallel slave balancers to 20. This gives a maximum discharge current of 50A. Other converters may also be used as a slave, including the LT3751 (must connect its VIN to the cell above) and the LT3750. Connect all slave MODE pins to VIN. This forces those parts into simple mode and makes their DCHRG pin an input pin. Connect all slave DCHRG pins (SHDN pins if using other converters) to the master DCHRG pin. Figure 13 shows a 5A discharger circuit using two LT8584s. Each part operates asynchronously from the other one. Use separate transformers for each LT8584 balancer. The slave balancers operate only when the master balancer is operating. A fault on the master balancer will turn off all slave balancers. A fault in any of the slave balancers will not turn off any of the other balancers. Use an external sense resistor, RSNS, and the VSNS pin to determine if the average current is at the expected value. RSNS MODULE+ BAT - + BAT VCELL VSNS MODE BAT - MODULE+ BAT - * TO ADJACENT OUT PIN * VIN VCELL VSNS MODULE- SW MODE LT8584 * VIN MODULE- SW LT8584 TO C PIN OUT DCHRG OUT TO S PIN DIN RTMR DIN GND * DCHRG GND RTMR TO ADJACENT OUT PIN 8584 F13 MASTER BALANCER SLAVE BALANCER Figure 13. LT8584 Parallel Operation THERMAL VIAS GND 1 16 2 15 3 14 4 13 17 R1 5 T1 6 11 VSNS 7 10 VCELL OUT 8 9 GND CFBO 12 DCHRG DIN CVIN VIN GND D1 * * RTMR COUT THERMAL VIAS TOP OF BATTERY STACK RSNS VIN BATTERY STACK GROUND CVTRAN CVCELL CELL INPUT VIN 1 16 2 15 3 14 4 13 17 5 6 11 7 10 OUT 8 9 VIN GND SERIAL MODE For more information www.linear.com/LT8584 D1 CFBO BATTERY STACK GROUND CVTRAN CVCELL SIMPLE MODE Figure 14. LT8584 Suggested Layout T1 * * 12 DIN COUT TOP OF BATTERY STACK CELL INPUT 8584 F14 8584fb 27 LT8584 Applications Information Recommended Layout Connecting to a Battery Stack Monitor The potentially high voltage operation of the LT8584 demands careful attention to the board layout, observing the following points: There are two methods used to connect the LT8584 balancer to a battery stack monitor (BSM): either a single-wire or two-wire. Both have advantages and disadvantages. Both methods may require Kelvin connections for the BSM supply rails depending upon the magnitude of IR drop across the connections to the battery stack. In most cases, keeping the individual connection resistances less than 60m allows the BSM supply rails to share the return path through RW0 and RW12, see Figure 16. 1. Minimize the board trace area of the high voltage end of the secondary winding. 2. Keep the electrical path formed by CVTRAN, the primary of T1, the SW node, and ground as short as possible. Increasing the length of this path effectively increases the leakage inductance of T1, resulting in excessive energy loss in the internal Zener clamp or RCD snubber. 3. Thermal vias should be added underneath the chip's exposed pad, pin 17, to enhance the LT8584's thermal performance. These vias should go directly to a local ground plane with a minimum area of 650mm2. 4. Make Kelvin connections for VSNS, VCELL, and RSNS to the battery cell when using the LT8584 in serial mode. The IR drop in the battery connection can be calibrated out using a software algorithm. Consult Application Engineering. 5. Care should be taken when routing VCELL, VSNS and VIN connections. RTRACE in Figure 15 should be minimized for better efficiency. RTRACE should never exceed 19*RSNS. This guarantees that the OUT pin amplifier headroom is sufficient enough for reporting the VSNS amplifier output. 6. Minimize the total connection resistance from the battery terminals to the VCELL and GND pins of the LT8584. It is recommended to keep the total resistance less than 60m to improve converter efficiency. Excessive IR drops in the PCB traces or connector terminals could also cause the LT8584 to prematurely enter UVLO. RSNS VCELL + VBAT - Note that in the two-wire connection scheme, the ground connection impedance can not be determined when calculating wire impedance and will be invisible to the measurement system. On the flip side, the algorithms for computing two-wire connection impedance and back calculating VCELL during discharging are more straightforward. The two-wire method also has the advantage of only losing visibility of a single cell during an open connection instead of two as in the single-wire method. Integrating with the LTC680x Family The LTC680x family of parts are multi-cell battery stack monitors that are described in the Operation section of this data sheet. For more information, consult the LTC680x data sheets. Several operational flavors are available with their inherent differences shown in Table 9. Table 9. LTC680x Feature Differences RTRACE VSNS The single-wire connection is recommended due to complete system visibility of the wire connection impedance. The single-wire is also cheaper and more reliable due to fewer wire connections. See the Typical Application section for proper Kelvin connection between adjacent LT8584 channels in single-wire mode. VIN * ISW LPRI Q1 8584 F15 PART COMMUNICATION COMPATIBLE MODES LTC6802-1 Daisy Chained Serial Simple Mode Only LTC6802-2 Addressable Parallel Simple Mode Only LTC6804-1/LTC6803-1/ Daisy Chained Serial LTC6803-3 Serial / Simple Mode LTC6804-2/LTC6803-2/ Addressable Parallel LTC6803-4 Serial / Simple Mode Figure 15. RTRACE Minimization 28 8584fb For more information www.linear.com/LT8584 LT8584 Applications Information SINGLE-WIRE BATTERY CONNECTION TWO-WIRE BATTERY CONNECTION VMODULE+ VMODULE+ V+ RW12 BSM V+ RW12 BAT 12 BSM BAT 12 RW11 + VERR - BAT 11 RW10 BALANCING CURRENT LT8584 BALANCER ON BALANCING CURRENT LT8584 BALANCER ON RW9 BALANCING CURRENT LT8584 BALANCER ON BAT 11 C11 RW0 BALANCING CURRENT LT8584 BALANCER ON C12 C11 RW10 C10 BAT 10 RW1 BAT 1 LT8584 BALANCER ON RW11 ADC + VERR - BAT 10 C12 BALANCING CURRENT ADC BALANCING CURRENT LT8584 BALANCER ON BALANCING CURRENT LT8584 BALANCER ON C10 RW1 BALANCING CURRENT LT8584 BALANCER ON C1 BAT 1 C1 C0 V- C0 V- VMODULE- 8584 F16 VMODULE- Figure 16. LT8584 Battery Connections The LTC6803 and LTC6804 draw only 3A of static current on the S pin, allowing the LT8584 to be enabled without noticeable measurement error. The LTC6804 offers improved ADC performance over the LTC6803 by reducing conversion time approximately 10x and reducing measurement error below 1.2mV. The LTC6804 also utilizes isoSPI with improved RF-immunity. to turn on one balancer where N = number of LTC680x in the system and = frequency of the SCKI clock. Table 10. Approximate Time to Enable One LT8584 STEP TIME (s) LTC6802-1/LTC6802-3 LTC6803-1/LTC6803-3 LTC6802-2/LTC6802-4 LTC6803-2/LTC6803-4 (16 + 56 * N) 72 Enable Balancing in Simple Mode Send WRCFG Command, Write `1' to Enable Balancer Write a `1' to the corresponding DCCx bit in the configuration register of the LTC680x. This pulls its S pin low and activates the LT8584. Table 10 shows the required time Note that the addressable serial interface is much faster when writing to a single channel in a multi-chip system. 8584fb For more information www.linear.com/LT8584 29 LT8584 Applications Information Enable Balancing in Serial Mode In serial mode, the configuration register has to be written several times to toggle the DCCx bit and pipe data into the serial bus. The RTMR resistor needs to be set accordingly to guarantee that enough time is allocated to enter any one of the four serial modes and read back the handshake voltage on the OUT pin. There are speed limitations when sending information to the LT8584 (see the Timing Diagram). Use Table 11 to determine overall timing requirements. Table 11. Turning on LT8584 in MODE 4 LTC6803/LTC6804 VIN VCELL OUT LT8584 DIN GND DCCx STATE 1 - DIN Low 0 - DIN High 1 - DIN Low (MODE 1) 0 - DIN High 1 - DIN Low (MODE 2) 0 - DIN High 1 - DIN Low (MODE 3) 0 - DIN High 1 - DIN Low (MODE 4) Total VIN SON ADC VCELL OUT C(N) LT8584 LTC6803-2/ LTC6803-4 DIN GND S(N) SON MODE C(N-1) (16 + 56 * N) (16 + 56 * N) * 9 72 648 Filtering and ADC Measurements The LTC680x has an internal multichannel differential ADC that measures the voltage between each consecutive pair of C pins. Figure 17 shows the ADC connected to C(N) and C(N+1), measuring the difference between the two adjacent LT8584's OUT pins. Most parameters require two measurements, one with the top LT8584 selecting VCELL and another one with the top LT8584 selecting the desired parameter. The difference between these two measurements yields the desired parameter value. This is required since the LTC680x is not directly connected to the battery cells. See the Serial Mode Differential Measurements section for more detail. Filter capacitors (typically 47nF) have to be placed between adjacent C pins to provide the required 16kHz lowpass filter for the ADC input path. This provides 30dB of noise reduction. No external filter resistors are needed since the 30 S(N+1) MODE TIME (s) LTC6803-1/ LTC6803-2 C(N+1) 8584 F17 Figure 17. LTC6803/LTC6804 Simplified Connections internal impedance from VCELL to OUT is approximately 55. Note that the effective capacitance on the OUT pin becomes 2x 47nF or 94nF. Figure 17 has omitted these capacitors for the sake of simplicity (see the Typical Applications for proper connection of the filter capacitors). Adequate bypass capacitors need to be connected from VIN to ground for each LT8584 to provide a low-impedance path for high-frequency switching noise. Ceramic capacitors work well for this purpose. Several passive filters internal to the LT8584 are included to remove erroneous glitches on the DIN pin that are up to 4s in duration. Test Circuit Use the circuit in Figure 18 for testing the LT8584 in Serial Mode without using a BSM. The inverter directly driving the LT8584 should be placed close to the LT8584 and have less than 1V VGS thresholds. Figure 19 shows typical serial communication waveforms using a 100k timer resistor and a 2ms data period. 8584fb For more information www.linear.com/LT8584 LT8584 Applications Information VISHAY Si1035x 100 VISHAY SFH6720T + - 5V TO 10V VOUT PULSE GENERATOR LT8584 D2 49.9 D1 49.9 10 DIN G1 GND 100nF OUT G2 VCC 2.3k S2 S1 100 GND 8584 F18 Figure 18. Serial Mode Test Circuit VRTMR 1V/DIV VDIN 2V/DIV VOUT 1V/DIV 2ms/DIV PREVIOUS MODE SELECTED RESET PULSE COUNTING MODE4 HANDSHAKE MODE4 SELECTED 8584 F19 Figure 19. Typical Serial Mode Communication Waveforms 8584fb For more information www.linear.com/LT8584 31 LT8584 Typical Applications Stackable Fast-Charge 8 to 12-Cell Battery Module, 4.6A Discharge Capability with 2 Parallel LT8584 per Cell MODULE+ R12A 5m BATTERY STACK TO PCB CONNECTION C12A 100F x2 D12A C12B 22nF R12C 4.99k C12E 100F * T12B 1:4 BAT12 VCELL VSNS VIN D12D RTMR LOCAL VIN * R12B 100k DIN RTMR C13 47nF + C12C MODULE 1F * - LTC680x BSM OUT C12 DIN S12 LT8584 MASTER MODE GND T12A 1:4 SW DCHRG C12G 47nF LT8584 SLAVE * D12F - VCELL VSNS VIN OUT MODE R12D 4.99k C12F 1F MODULE SW DCHRG C12H 22nF + D12E + V+ D13 D12B GND R2A 5m C2A 100F x2 D2A C2B 22nF R2C 4.99k C2E 100F * T2B 1:4 + D2D VCELL VSNS VIN BAT2 * RTMR LOCAL VIN VCELL VSNS VIN OUT MODE R2B 100k DIN RTMR C3D 47nF + C2C MODULE 1F * - OUT C2 DIN S2 LT8584 MASTER MODE GND D3C D2B SW DCHRG C2G 47nF LT8584 SLAVE * T2A 1:4 D2F - SW DCHRG R2D 4.99k C2F MODULE 1F D2E + C2H 22nF GND KELVIN CONNECTION TO R1A R1A 5m C1A 100F x2 C1B 22nF R1C 4.99k C2E 100F * T1B 1:4 VCELL VSNS VIN DCHRG + RTMR D1D BAT1 LOCAL VIN R1D 4.99k C1F MODULE 1F * - SW OUT LT8584 SLAVE C1H 22nF + D1E D1A D2C DCHRG R1B 100k DIN D1B * RTMR MODE MODE GND GND LT8584 MASTER + C1C 1F MODULE - D1F VCELL VSNS VIN C1G 47nF * T1A 1:4 C2D 47nF SW OUT C1 DIN S1 C1D 47nF RPASS 250 10W D1C M1 GPIO1 C0 V- 8584 TA02a MODULE- Average Cell Discharge Current 3 2 5 ERROR (%) 1 4 3 0 -1 VCELL = 2.5V VCELL = 3V VCELL = 3.6V VCELL = 4.2V 30 35 40 45 50 MODULE VOLTAGE (VMODULE+ - VMODULE-) 8584 TA02b 32 Typical Current Measurement Error 6 DISCHARGE CURRENT (A) C1A-C12A: 6.3V X5R OR X7R CERAMIC CAPACITOR C1B-C12B, C1H-C12H: 50V X5R OR X7R CERAMIC CAPACITOR C1C-C12C: 100V X5R OR X7R CERAMIC CAPACITOR C1D-C12D, C13: 50V NPO CERAMIC CAPACITOR C1E-C12E: 6.3V X5R OR X7R CERAMIC CAPACITOR C1F-C12F: 100V X5R OR X7R CERAMIC CAPACITOR C1G-C12G: 6.3V X5R OR X7R CERAMIC CAPACITOR D1A-D12A: STMICROELECTRONICS SMA6T6V7AY TVS DIODE D1B-D12B: FAIRCHILD ES1D 200V, 1A ULTRAFAST RECTIFIER D1C-D12C, D13: STMICROELECTRONICS ESDALC6V1-1M2 TVS D1D-D12D: FAIRCHILD ES1D 200V, 1A ULTRAFAST RECTIFIER D1E-D12E, D1F-D12F: FAIRCHILD SS16 60V, 1A M1: FAIRCHILD FDMC86102L 100V, 5.5A R1A-R12A: USE 1% 1206 RESISTORS R1B-R12B, R1C-R12C, R1D-R12D: USE 1% 0603 RESISTORS RPASS: 10W WIREWOUND T1A-T12A, T1B-T12B: COILCRAFT NA5743-AL U1: LINEAR TECHNOLOGY LTC680x FAMILY INCLUDING BUT NOT LIMITED TO LTC6802, LTC6803, LTC6804 For more information www.linear.com/LT8584 VCELL = 2.5V VCELL = 3V VCELL = 3.6V VCELL = 4.2V -2 -3 30 35 40 45 50 MODULE VOLTAGE (VMODULE+ - VMODULE-) 8584 TA02b 8584fb LT8584 Typical Applications Stackable Fast-Charge 8 to 12-Cell Battery Module Application Notes Stackable 8 to 12-Cell Battery Module Application Notes 1. Channels 3 through 11 are omitted for clarity. These channels should be integrated similar to channel 2. Not all required components for the LTC680x are shown. Consult the LTC680x data sheet for recommended components and their connections. See the last page Typical Application. 2. Up to 20 LT8584 balancers may be connected in parallel to farther increase discharge current. The DCHRG pin can also drive an enable pin of a separate DC/DC converter like the LT3750 capacitor charger. 3. Multiple modules can be stacked in series to achieve a larger battery stack. Each module must contain an integer multiple of the total number of cells in the stack. For instance, an 80 cell stack should be constructed with 8 modules each having 10 cells. Use consecutive BSM channels starting with BSM channel 1when populating a module with less than 12 channels. Tie all unused LTC680x C pins to MODULE+. 4. Place one CnE capacitor close to the Master LT8584's transformer primary, and place the other CnE capacitor close to the Slave LT8584's transformer primary. The symbol `n' denotes a particular channel ranging from 1 to 12. 5. Place RCD snubber composed of DnF, DnE, RnC, RnD, CnB, CnH, as close as possible to the respective transformer primary. The symbol `n' denotes a particular channel ranging from 1 to 12. 6. RPASS and M1 may be omitted for applications using only one module in the stack. 7. Each LT8584 channel should have no less than 650mm2 of PCB pad footprint for proper heat sinking. 8. Consult Application Engineering for proper communication with LTC680x family of parts as well as a proper algorithm for extracting cell parameters. 9. Recommended for cells that operate within a 2.5V to 5.3V range. 1. Channels 4 through 11 are omitted for clarity. These channels should be integrated similar to channel 2. Not all required components for the LTC680x are shown. Consult the LTC680x data sheet for recommended components and their connections. 2. Multiple modules can be stacked in series to achieve a larger battery stack. Each module must contain an integer multiple of the total number of cells in the stack. For instance, an 80 cell stack should be constructed with 8 modules each having 10 cells. Use consecutive BSM channels starting with BSM channel 1 when populating a module with less than 12 channels. Tie all unused LTC680x C pins to MODULE+. 3. Place the CnB capacitor close to the LT8584's transformer primary. The RCD snubber composed of CnE, RnC and DnD should also be placed close the LT8584's transformer primary. The symbol `n' denotes a particular channel ranging from 1 to 12. 4. The BSM V+ pin may share cell 12's positive battery connection, and the BSM V- pin may share cell 0's negative battery connection as long as the summation of each battery connection's PCB trace, wire, and interconnection resistance is less than 60m. 5. RPASS and M1 may be omitted for applications using only one module in the stack. 6. Each LT8584 channel should have no less than 650mm2 of PCB pad footprint for proper heat sinking. 7. Consult Application Engineering for proper communication with LTC680x family of parts as well as a proper algorithm for extracting cell parameters. 8. Recommended for cells that operate within a 2.5V to 5.3V range. 8584fb For more information www.linear.com/LT8584 33 LT8584 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. FE Package 16-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663 Rev K) Exposed Pad Variation BC 4.60 3.58 (.141) 4.90 - 5.10* (.193 - .201) 16 1514 13 12 11 SEE NOTE 5 6.60 0.10 4.50 0.10 0.48 (.019) REF 3.58 (.141) 2.94 (.116) 10 9 DETAIL B 6.40 2.94 (.252) (.116) BSC SEE NOTE 4 0.45 0.05 1.05 0.10 0.51 (.020) REF DETAIL B IS THE PART OF THE LEAD FRAME FEATURE FOR REFERENCE ONLY NO MEASUREMENT PURPOSE 0.65 BSC 1 2 3 4 5 6 7 8 RECOMMENDED SOLDER PAD LAYOUT 4.30 - 4.50* (.169 - .177) 0.09 - 0.20 (.0035 - .0079) 0.25 REF 0.50 - 0.75 (.020 - .030) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT 34 1.10 (.0433) MAX 0 - 8 0.65 (.0256) BSC 0.195 - 0.30 (.0077 - .0118) TYP 0.05 - 0.15 (.002 - .006) FE16 (BC) TSSOP REV K 1013 5. BOTTOM EXPOSED PADDLE MAY HAVE METAL PROTRUSION IN THIS AREA. THIS REGION MUST BE FREE OF ANY EXPOSED TRACES OR VIAS ON PCB LAYOUT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE 8584fb For more information www.linear.com/LT8584 LT8584 Revision History REV DATE DESCRIPTION A 05/14 Clarified Features PAGE NUMBER 1 Clarified Electrical Characteristics 3 Clarified Data Threshold graph 6 Clarified OUT Pin Amplifier graph 7 Clarified Operation description 11 Clarified Operation description 15 Clarified Applications Information Clarified Figures 17, 18 B 8/14 20, 24, 30 30, 31 Clarified Absolute Maximum Ratings 2 Clarified Handshake Voltage Error Conditions 3 Clarified DIN Pin Function 9 Clarified Block Diagram 10 Clarified Figure 1 12 Clarified Sense Resistor Formula 23 Clarified Figure 16 in Applications Information 29 8584fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. For more information www.linear.com/LT8584 35 LT8584 Typical Application Stackable 8 to 12-Cell Battery Module, LT8584 in Serial Mode, Single-Wire Configuration Average Cell Discharge Current MODULE+ R12A 12m C12E 22nF C12A 100F C12B 100F D12A + BAT12 R12B 100k R12C 4.99k + * C12C * 1F MODULE SW DCHRG OUT V+ D13 C13 47nF - D12D VCELL VSNS VIN RTMR D12B T12 1:4 DISCHARGE CURRENT (A) BATTERY STACK TO PCB CONNECTION 3.0 LTC6804 BSM C12 LT8584 MODE S12 DIN C2A 100F R2A 12m C2B 100F C2E 22nF R2C 4.99k * T2 1:4 C2C 1F MODULE - + BAT2 R2B 100k D3C OUT C2 DIN S2 LT8584 GND KELVIN CONNECTION TO R1A C1A 100F C1B 100F D1A C1E 22nF R1C 4.99k * 40 45 50 35 MODULE VOLTAGE (VMODULE+ - VMODULE-) 0.25 SW R1A 12m 30 0.30 DCHRG MODE 2.2 Average Flyback Output Current C3D 47nF VCELL VSNS VIN RTMR 2.4 8584 TA03b + * D2D D2A 2.6 D2B OUTPUT CURRENT (A) KELVIN CONNECTION TO R2A 2.8 2.0 GND VCELL = 2.5V VCELL = 3V VCELL = 3.6V VCELL = 4.2V D1B T1 1:4 + * C1C 1F MODULE D1D - 0.20 0.15 0.10 VCELL = 2.5V VCELL = 3V VCELL = 3.6V VCELL = 4.2V 0.05 D2C 0 C2D 47nF + 30 40 45 50 35 MODULE VOLTAGE (VMODULE+ - VMODULE-) 8584 TA03c BAT1 R1B 100k VCELL VSNS VIN SW DCHRG OUT C1 DIN S1 RTMR LT8584 MODE GND C1D 47nF GPIO1 D1C C0 V- C1A-C12A: 6.3V X5R OR X7R CERAMIC CAPACITOR C1B-C12B: 6.3V X5R OR X7R CERAMIC CAPACITOR RPASS C1C-C12C: 100V X5R OR X7R CERAMIC CAPACITOR 500 C1D-C12D, C1E-C12E, C13: 50V NPO CERAMIC CAPACITOR D1A-D12A: STMICROELECTRONICS SMA6T6V7AY TVS DIODE 5W D1B-D12B: FAIRCHILD ES1D 200V ULTRAFAST RECTIFIER D1C-D12C, D13: STMICROELECTRONICS ESDALC6V1-1M2 TVS D1D-D12D: FAIRCHILD SS16 60V, 1A SCHOTTKY M1 M1: FAIRCHILD FDMC86102L 100V, 5.5A R1A-R12A: USE 1% 1206 RESISTORS R1B-R12B, R1C-R12C: USE 1% 0603 RESISTORS RPASS: 2 PARALLEL 2.5W WIREWOUND T1-T12: COILCRAFT NA5743-AL U1: LINEAR TECHNOLOGY LTC680x FAMILY INCLUDING BUT NOT LIMITED TO LTC6802, LTC6803, LTC6804 8584 TA03a MODULE- Related Parts PART NUMBER DESCRIPTION COMMENTS LTC3300-1 High Efficiency Bidirectional Multicell Balancer Synchronous Flyback, Up to 6 Cells in Series, 48-Lead QFN LTC6803 Multicell Battery Stack Monitor Measures Up to 12 Li-Ion Cells in Series, SSOP-44 LTC6804 Multicell Battery Stack Monitor Measures Up to 12 Li-Ion Cells in Series, Built-In isoSPITM, SSOP-48 36 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LT8584 (408) 432-1900 FAX: (408) 434-0507 www.linear.com/LT8584 8584fb LT 0814 REV B * PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2013