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5V TOLERANT INPUTS AND OUTPUTS
HIGH SPEED :
tPD = 5.4 ns (MAX.) at VCC =3V
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH|=I
OL = 24mA (MIN) at VCC =3V
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
tPLH tPHL
OPERATING VOLTAGE RANGE:
VCC(OPR) = 2.0V to 3.6V (1.5V Data
Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 16373
LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTION
The 74LCX16373 is a low voltage CMOS 16 BIT
D-TYPE LATCH with 3 STATE OUTPUTS NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C2MOS
technology. It is ideal for low power and high
speed 3.3V applications; it can be interfaced to 5V
signal environment for both inputs and outputs.
These 16 bit D-TYPE latches are byte controlled
by two latch enable inputs (nLE) and two output
enable inputs(OE).
While the nLE input is held at a high level, the nQ
outputs will follow the data input precisely.
When the nLE is taken LOW, the nQ outputs will
be latched precisely at the logic level of D input
data.
While the (nOE) input is low, the nQoutputs will be
in a normal logic state (high or low logic level) and
while high levelthe outputs will be in a high imped-
ance state.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with protec-
tion circuits against static discharge, giving them
2KV ESD immunity and transient excess voltage.
74LCX16373
LOW VOLTAGE CMOS 16-BIT D-TYPE LATCH (3-STATE)
WITH 5V TOLERANT INPUTS AND OUTPUTS
ORDER CODES
PACKAGE TUBE T & R
TSSOP 74LCX16373TTR
TSSOP
PIN CONNECTION
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INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE
X : Don‘t Care
Z : High Impedance
* : Q outputs are latched atthetime when the LE inputis taken low
logic level.
IEC LOGIC SYMBOLS
PIN No SYMBOL NAME AND FUNCTION
1 1OE 3 State Output Enable
Input (Active LOW)
2, 3, 5, 6, 8, 9,
11, 12 1Q0 to 1Q7 3-State Outputs
13,14,16, 17,
19, 20, 22, 23 2Q0 to 2Q7 3-State Outputs
24 2OE 3 State Output Enable
Input (Active LOW)
25 2LE Latch Enable Input
36,35,33, 32,
30, 29, 27, 26 2D0 to 2D7 Data Inputs
47,46,44, 43,
41, 40, 38, 37 1D0 to 1D7 Data Inputs
48 1LE Latch Enable Input
4, 10, 15, 21,
28, 34, 39, 45 GND Ground (0V)
7, 18, 31, 42 VCC Positive Supply Voltage
INPUTS OUTPUT
OE LE D Q
HXX Z
L L X NO CHANGE *
LHL L
LHH H
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LOGIC DIAGRAM
This logic diagram has not to be used to estimate propagation delays
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) IOabsolute maximum rating must be observed
2) VO<GND
RECOMMENDED OPERATING CONDITIONS
1) Truth Table guaranteed: 1.5V to 3.6V
2) VIN from 0.8V to 2V at VCC =3.0V
Symbol Parameter Value Unit
VCC Supply Voltage -0.5 to +7.0 V
VIDC Input Voltage -0.5 to +7.0 V
VODC Output Voltage (OFF State) -0.5 to +7.0 V
VODC Output Voltage (High or Low State) (note 1) -0.5 to VCC + 0.5 V
IIK DC Input Diode Current -50 mA
I
OK DC Output Diode Current (note 2) -50 mA
I
ODC Output Current ±50 mA
ICC DC Supply Current per Supply Pin ±100 mA
IGND DC Ground Current per Supply Pin ±100 mA
Tstg Storage Temperature -65 to +150 °C
TLLead Temperature (10 sec) 300 °C
Symbol Parameter Value Unit
VCC Supply Voltage (note 1) 2.0 to 3.6 V
VIInput Voltage 0 to 5.5 V
VOOutput Voltage (OFF State) 0 to 5.5 V
VOOutput Voltage (High or Low State) 0 to VCC V
IOH,I
OL High or Low Level Output Current (VCC = 3.0 to 3.6V) ±24 mA
IOH,I
OL High or Low Level Output Current (VCC = 2.7V) ±12 mA
Top Operating Temperature -55 to 125 °C
dt/dv Input Rise and Fall Time (note 2) 0 to 10 ns/V
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DC SPECIFICATIONS
DYNAMIC SWITCHING CHARACTERISTICS
1) Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is
measured in the LOW state.
Symbol Parameter
Test Condition Value
Unit
VCC
(V)
-40to8C -55to12C
Min. Max. Min. Max.
VIH High Level Input
Voltage 2.7to3.6 2.0 2.0 V
VIL Low Level Input
Voltage 0.8 0.8 V
VOH High Level Output
Voltage 2.7to3.6 I
O
=-100 µAV
CC-0.2 VCC-0.2
V
2.7 IO=-12 mA 2.2 2.2
3.0 IO=-18 mA 2.4 2.4
IO=-24 mA 2.2 2.2
VOL Low Level Output
Voltage 2.7to3.6 I
O
=100 µA0.2 0.2
V
2.7 IO=12 mA 0.4 0.4
3.0 IO=16 mA 0.4 0.4
IO=24 mA 0.55 0.55
IIInput Leakage
Current 2.7to3.6 V
I= 0 to 5.5V ±5±5µA
Ioff Power Off Leakage
Current 0VIor VO=5.5V 10 10 µA
IOZ High Impedance
Output Leakage
Current 2.7to3.6 V
I=V
IH or VIL
VO= 0 to VCC ±5±5µA
ICC Quiescent Supply
Current 2.7to3.6 V
I=V
CC or GND 20 20 µA
VIor VO= 3.6 to 5.5V ±20 ±20
ICC ICC incr. per Input 2.7to3.6 V
IH =V
CC -0.6V 500 500 µA
Symbol Parameter
Test Condition Value
Unit
VCC
(V)
TA=2C
Min. Typ. Max.
VOLP Dynamic Low Level Quiet
Output (note 1) 3.3 CL=50pF
V
IL =0V,V
IH = 3.3V 0.8 V
VOLV -0.8
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AC ELECTRICAL CHARACTERISTICS
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the samedevice switch-
ing in the same direction, either HIGH or LOW (tOSLH =|t
PLHm -t
PLHn|, tOSHL =|t
PHLm -t
PHLn|)
2) Parameter guaranteed by design
CAPACITIVE CHARACTERISTICS
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) =C
PD xV
CC xf
IN +I
CC/16 (per
circuit)
Symbol Parameter
Test Condition Value
Unit
VCC
(V) CL
(pF) RL
()ts=tr
(ns)
-40 to 85 °C -55 to 125 °C
Min. Max. Min. Max.
tPLH tPHL Propagation Delay
Time (Dn to Qn) 2.7 50 500 2.5 1.5 5.9 1.5 5.9 ns
3.0 to 3.6 1.5 5.4 1.5 5.4
tPLH tPHL Propagation Delay
Time (LE to Qn) 2.7 50 500 2.5 1.5 6.4 1.5 6.4 ns
3.0 to 3.6 1.5 5.5 1.5 5.5
tPZL tPZH Output Enable Time
to HIGH and LOW
level
2.7 50 500 2.5 1.5 6.5 1.5 6.5 ns
3.0 to 3.6 1.5 6.1 1.5 6.1
tPLZ tPHZ Output Disable Time
from HIGH to LOW
level
2.7 50 500 2.5 1.5 6.3 1.5 6.3 ns
3.0 to 3.6 1.5 6.0 1.5 6.0
tSSet-Up Time, HIGH
or LOW level
(DntoLE)
2.7 50 500 2.5 2.5 2.5 ns
3.0 to 3.6 2.5 2.5
thHold Time, HIGH or
LOW level
(DntoLE)
2.7 50 500 2.5 1.5 1.5 ns
3.0 to 3.6 1.5 1.5
tWLE Pulse Width,
HIGH 2.7 50 500 2.5 3.0 3.0 ns
3.0 to 3.6 3.0 3.0
tOSLH
tOSHL
Output To Output
Skew Time (note1,
2)
3.0 to 3.6 50 500 2.5 1.0 1.0 ns
Symbol Parameter
Test Condition Value
Unit
VCC
(V)
TA=2C
Min. Typ. Max.
CIN Input Capacitance 3.3 VIN = 0 to VCC 7pF
C
OUT Output Capacitance 3.3 VIN = 0 to VCC 8pF
C
PD Power Dissipation Capacitance
(note 1) 3.3 fIN = 10MHz
VIN = 0 or VCC
20 pF
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TEST CIRCUIT
CL= 50 pF or equivalent (includes jig and probe capacitance)
RL=R1=500 or equivalent
RT=Z
OUT of pulse generator (typically 50)
WAVEFORM 1 : LE TO Qn PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH, Dn TO LE
SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
TEST SWITCH
tPLH,t
PHL Open
tPZL,t
PLZ 6V
tPZH,t
PHZ GND
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WAVEFORM 2 : OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)
WAVEFORM 3 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
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DIM. mm. inch
MIN. TYP MAX. MIN. TYP. MAX.
A 1.2 0.047
A1 0.05 0.15 0.002 0.006
A2 0.9 0.035
b 0.17 0.27 0.0067 0.011
c 0.09 0.20 0.0035 0.0079
D 12.4 12.6 0.488 0.496
E 8.1 BSC 0.31 8 BSC
E1 6.0 6.2 0.236 0.244
e 0.5 BSC 0.019 7 BSC
K0˚ 8˚0˚ 8˚
L 0.50 0.75 0.020 0.030
TSSOP48 MECHANICAL DATA
cE
b
A2
A
E1
D
1
PIN 1 IDENTIFICATION
A1 L
K
e
7065588C
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DIM. mm. inch
MIN. TYP MAX. MIN. TYP. MAX.
A 330 12.992
C 12.8 13.2 0.504 0.519
D 20.2 0.795
N 60 2.362
T 30.4 1.197
Ao 8.7 8.9 0.343 0.350
Bo 13.1 13.3 0.516 0.524
Ko 1.5 1.7 0.059 0.067
Po 3.9 4.1 0.153 0.161
P 11.9 12.1 0.468 0.476
Tape & Reel TSSOP48 MECHANICAL DATA
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