RT8101GSP - Richtek - Datasheet.Directory

RT8101/A

DS8101/A-06 April 2011 www.richtek.com

Features

zSingle 12V Bias Supply

zDrives All Low Cost N-MOSFET s

zHigh-Gain Voltage Model PWM Control

z300kHz/600kHz Fixed Frequency Oscillator

zFa st Tra n sient Re sponse :

` High-Speed GM Amplifier

` Full 0 to 100% Duty Ratio

` External Compensation in the Control Loop

zInternal Soft-Start

zAdaptive Non-Overlapping Gate Driver

zOver Current Fault Monitor on MOSFET, No

Current Sense Resistor Required

zRoHS Compliant and 100% Lead (Pb)-Free

12V Synchronous Buck PWM DC/DC Controller

General Description

The RT8101/A are DC/DC synchronous buck PWM

controllers with embedded driver support up to 12V + 12V

boot-strapped voltage for high efficiency power driving. The

parts are with full functions of voltage regulation, power

monitoring and protection into a single small footprint

pa ckages SOP-8 a nd SOP-8 (Exposed Pad).

The RT8101/A apply a high-gain voltage mode PWM control

for si mple application design. An intern al 0.8V reference

allows the output voltage to be precisely regulated to low

voltage requirement. The parts are proposed with two type

including RT8101 and RT8101A with fixed operating

frequency of 300kHz and 600kHz respectively . Ba sed on

the features that R T8101/A offered, the parts provide an

optimum solution between efficiency , total B.O.M. count,

and cost.

Ordering Information

Applications

zGra phic Card

zMotherboard, Desktop Servers

zIA Equipments

zTelecomm Equipments

zHigh Power DC/DC Regulators

Pin Configurations

(TOP VIEW)

SOP-8

SOP-8 (Exposed Pad)

Note :

Richtek products are :

` RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

` Suitable for use in SnPb or Pb-free soldering processes. BOOT

UGATE

GND

LGATE

PHASE

COMP

VCC

GND

PHASE

BOOT

UGATE

LGATE

GND VCC

COMP

Package Typ e

S : SOP-8

SP : SOP-8 (Exposed Pad-Option 2)

RT8101/A

600kHz

300kHz

Lead Plating System

P : Pb Free

G : Green (Halogen Free and Pb Free)

RT8101/A

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Functional Pin Description

BOOT (Pin 1)

Bootstrap supply for the upper gate driver. Connect the

bootstrap capacitor between BOOT pin and the PHASE

pin. The bootstrap capacitor provides the charge to turn

on the upper MOSFET.

UGA TE (Pin 2)

Upper gate driver output. Connect to gate of the high-

side power N-Channel MOSFET. This pin is monitored by

the adaptive shoot-through protection circuitry to

determine when the upper MOSFET is turned off.

GND (Pin 3)

Signal ground for the IC.

LGA TE (Pin 4)

Lower gate driver output. Connect to the gate of the low-

side power N-Channel MOSFET. This pin is monitored by

the ada ptive shoot-through protection circuitry to determine

when the lower MOSFET is turned off.

VCC (Pin 5)

Connect this pin to a well-decoupled 12V bias supply. It

is also the positive supply for the lower gate driver , LGATE.

FB (Pin 6)

Buck converter feedback voltage. This pin is the inverting

input of the error a mplifier . FB senses the switcher output

through an external resistor divider network.

COMP (Pin 7)

Buck converter external compensation. This pin is used

to compensate the control loop of the buck converter .

PHASE (Pin 8)

Connect this pin to the source of the upper MOSFET a nd

the drain of the lower MOSFET. This pin is monitored by

the adaptive shoot-through protection circuitry to

determine when the upper MOSFET is turned off.

Exposed Pad (9)

The exposed pad must be soldered to a large PCB and

connected to GND f or maximum power dissi pation.

Typical Application Circuit

12V

OUT

CIN

RT8101/A

(+3.3V/+5V/+12V)

PSC

BOOT

VCC PHASE

UGATE

LGATEFB

GND

OUT

COMP

RBOOT

RUGATE

RT8101/A

DS8101/A-06 April 2011 www.richtek.com

Function Block Diagram

Driver

Logic

GND

LGATE

BOOT

UGATE

PHASE

PH_M

Soft-Start

Fault Logic

Oscillator

Power On

Reset (POR)

VCC

Bias

Voltage

Reference

1.5V

5VDD

+PWM

POR

INHIBIT

SSE

Regulator

0.8V

0.4V

0.8V

COMP

Enable

0.4V

30uA

21.6k

RT8101/A

www.richtek.com DS8101/A-06 April 2011

Electrical Characteristics

(VCC = 12V, TA = 25°C, unless otherwise specified)

To be continued

Absolute Maximum Ratings (Note 1)

zSupply Voltage, VCC ----------------------------------------------------------------------------------16V

zPHASE to GN D

DC---------------------------------------------------------------------------------------------------------−5V to 15V

< 200ns--------------------------------------------------------------------------------------------------−10V to 30V

zBOOT to PHASE --------------------------------------------------------------------------------------15V

zUGATE ---------------------------------------------------------------------------------------------------(VPHASE − 0.3V) to (VBOOT + 0.3V)

zLGATE ---------------------------------------------------------------------------------------------------(GND − 0.3V) to (VCC + 0.3V)

< 200ns--------------------------------------------------------------------------------------------------−1.5V to 13.5V

zInput, Output or I/O Voltage-------------------------------------------------------------------------GND − 0.3V to 7V

zPower Dissipation, PD @ TA = 25°C (Note 2)

SOP-8----------------------------------------------------------------------------------------------------0.83W

SOP-8 (Exposed Pad) -------------------------------------------------------------------------------1.33W

zPackage Thermal Resistance

SOP-8, θJA ----------------------------------------------------------------------------------------------120°C/W

SOP-8 (Exposed Pad), θJA --------------------------------------------------------------------------75°C/W

zJunction T emperature---------------------------------------------------------------------------------150°C

zLead T emperature (Soldering, 10 sec.)-----------------------------------------------------------2 60°C

zStorage T emperature Range ------------------------------------------------------------------------−65°C to 150°C

zESD Susceptibility (Note 3)

HBM (Human Body Mode) --------------------------------------------------------------------------2kV

MM (Ma chine Mode) ----------------------------------------------------------------------------------200V

Recommended Operating Conditions (Note 4)

zSupply Voltage, VCC ----------------------------------------------------------------------------------12V ± 10%

zJunction T emperature Range------------------------------------------------------------------------−40°C to 125°C

zAmbient T emperature Range------------------------------------------------------------------------−40°C to 85°C

Parameter Symbol Test Conditions Min Typ Max Unit

Supply Input

S upply Voltage VCC UGATE and LGATE Open 10.8 12 13.2 V

Supply Current ICC V

CC = 12V -- 3 -- mA

Power-On Reset

POR Threshold VCCRTH 8.8 9.6 10.4 V

POR Hysteresis VCCHYS -- 0.8 1.6 V

Oscillator VCC = 12V, RT8101 250 300 350

Fr ee Running F r equency fOSC VCC = 12V , RT81 01A 5 00 600 70 0 kHz

Ra mp Amplitude ΔVOSC V

CC = 12V -- 1.5 -- VP-P

RT8101/A

DS8101/A-06 April 2011 www.richtek.com

Parameter Symbol Test Conditions Min Typ Max Unit

Reference Voltage

PWM E rror Amplifier Reference VREF 0.792 0.8 0.808 V

E rror Amplifier

Open Loop DC Gain AO -- 88 -- dB

G ai n- Bandwi dt h Pr oduct GB W - - 15 - - M H z

Sl ew Rate SR -- 6 -- V/μs

PWM Controller Gate Drivers (VCC = 12V)

Upper Ga te So u rce IUGATE VBOOT − VPHASE = 12V,

VBOOT − VUGATE = 6V -- 300 -- mA

Upper Ga te So u rce RUGATE VBOOT − VPHASE = 12V,

VBOOT − VUGATE = 1V -- 7 10 Ω

Upper Ga te Sin k RUGATE VBOOT − VPHASE = 12V,

VUGATE − VPHASE = 1V -- 4 8 Ω

Lower Gate So u rce ILGATE V

CC = 12V, VLGATE = 6V - - 500 - - m A

Lower Gate So u rce RLGATE V

CC − VLGATE = 1V - - 4 6 Ω

Lower Gate Sin k RLGATE V

LGATE = 1V - - 2 4 Ω

Protection

U nder V oltage Pr ot ection Measur ing V FB 0.3 0.4 0.5 V

Over Current Threshold VOC Measuring VPHASE −210 −250 −290 mV

Soft-Start In te rv a l T SS COM P pi n re lea s ed to 90% VOUT 2 3.5 5 ms

Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for

stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the

operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended

periods may remain possibility to affect device reliability.

Note 2. θJA is measured in the natural convection at TA = 25°C on a high effective 4-layers thermal conductivity test board of

JEDEC 51-7 thermal measurement standard.

Note 3. Devices are ESD sensitive. Handling precaution is recommended.

Note 4. The device is not guaranteed to function outside its operating conditions.

RT8101/A

www.richtek.com DS8101/A-06 April 2011

Typical Operating Characteristics

Efficiency vs. Output Current

0.75

0.80

0.85

0.90

0.95

1.00

0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25

Output Current (A)

Efficien cy (%)

VCC = 12V

VIN = 5V

RT8101

RT8101A

100

Output Voltage vs. Output Current

2.45

2.46

2.47

2.48

2.49

2.50

2.51

2.52

2.53

2.54

2.55

0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25

Output Current (A)

Output Voltage (V)

VIN = 12V

VIN = 5V

RT8101A

Output Voltage vs. Output Current

2.45

2.46

2.47

2.48

2.49

2.50

2.51

2.52

2.53

2.54

2.55

0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25

Output Current (A)

Output Voltage (V)

VIN = 12V

VIN = 5V

RT8101

Frequency vs. Temperature

280

285

290

295

300

305

310

315

320

325

-40 -10 20 50 80 110 140

Tempera ture (°C)

Fr equency (kHz) 1

Frequency vs. Temperature

520

540

560

580

600

620

640

-40 -10 20 50 80 110 140

Tempera tu re (°C )

Fr equency (kHz) 1

RT8101A

Reference Voltage vs. Temperature

0.7917

0.7938

0.7959

0.7980

0.8001

0.8022

0.8043

0.8064

-50-25 0 255075100125

Tempera tu re (°C )

Refer ence V oltage (V)

VCC = 12V

VIN = 5V

RT8101/A

DS8101/A-06 April 2011 www.richtek.com

Dead Time (Falling)

Time (25ns/Div)

UGATE

LGATE

PHASE

VCC = 12V

VIN = 12V

IOUT = 25A

(5V/Div)

Dead Time (Rising)

Time (50ns/Div)

UGATE

LGATE

PHASE

VCC = 12V

VIN = 12V

IOUT = 25A

(5V/Div)

Power On from VIN

Time (5ms/Div)

UGATE

(20V/Div)

VOUT

(2V/Div)

VIN

(10V/Div)

VCC

(10V/Div)

Power On from VIN

Time (5ms/Div)

UGATE

(20V/Div)

VOUT

(2V/Div)

VIN

(10V/Div)

VCC

(10V/Div)

Power On from VCC

Time (5ms/Div)

UGATE

(20V/Div)

VOUT

(2V/Div)

VIN

(10V/Div)

VCC

(10V/Div)

Power Off from VCC

Time (5ms/Div)

UGATE

(20V/Div)

VOUT

(2V/Div)

VIN

(10V/Div)

VCC

(10V/Div)

RT8101/A

www.richtek.com DS8101/A-06 April 2011

Transient Response (Rising)

Time (5μs/Div)

VOUT

(100mV/Div)

IOUT

(10A/Div)

UGATE

(20V/Div)

RT8101, VCC = VIN = 12V, I OUT = 0A to 15A,

f = 1/20ms, SR = 2.5A/μs, L = 2.2μH, C = 2000μF

Transient Response (Rising)

Time (5μs/Div)

VOUT

(100mV/Div)

IOUT

(10A/Div)

UGATE

(20V/Div)

RT8101A, VCC = VIN = 12V, IOUT = 0A to 15A,

f = 1/20ms, SR = 2.5A/μs, L = 2.2μH, C = 2000μF

Transient Response (Falling)

Time (5μs/Div)

RT8101A, VCC = VIN = 12V, I OUT = 15A to 0A,

f = 1/20ms, SR = 2.5A/μs, L = 2.2μH, C = 2000μF

VOUT

(100mV/Div)

IOUT

(10A/Div)

UGATE

(20V/Div)

Transient Response (Falling)

Time (5μs/Div)

RT8101, VCC = VIN = 12V, IOUT = 15A to 0A,

f = 1/20ms, SR = 2.5A/μs, L = 2.2μH, C = 2000μF

VOUT

(100mV/Div)

IOUT

(10A/Div)

UGATE

(20V/Div)

RT8101/A

DS8101/A-06 April 2011 www.richtek.com

Application Information

Power On Reset

The RT8101/A automatically initializes upon applying of

input power VCC. The power on reset function (POR)

continually monitors the input bias supply voltage at the

VCC pin. The POR trip level is typically 9.6V at VCC

rising.

VIN Detection

After POR the RT8101/A continuously generates a 10kHz

pulse train with 1μs pulse width to turn on the upper

MOSFET for detecting the existence of VIN. RT8101/A

keeps monitoring PHASE pin voltage during the detection

period.

As soon as the PHASE voltage crosses 1.5V two tim es,

VIN existence is recognized and the RT8101/A initiates

its soft-start cycle as described in next section.

Figure 1

Soft-Start

A built-in soft-start is used to prevent surge current from

VIN to VOUT during power on. After the existence of VIN is

detected, soft-start (SS) begins automatically. The

feedback voltage (VFB) is clamped by internal linear ra mping

up SS voltage, causing PWM pulse width increasing

slowly and thus inducing little surge current. Soft-start

completes when SS voltage exceeds internal reference

voltage (0.8V), the time duration is about 3.2ms.

Over Current Protection

The RT8101/A senses the current flowing through lower

MOSFET for Over Current Protection (OCP) by sensing

the PHASE pin voltage a s shown in the Functional Block

Diagram.

VIN POR_H PHASE

UGATE

PHASE_M 1.5V

Internal Counter will count (VPHASE > 1.5V)

two times (rising & falling) to recognize when

VIN is ready.

1st 2nd PHASE

waveform

A 30μA current source flows through the internal resistor

21.6kΩ to PHASE pin causing 0.65V voltage drop a cross

the resistor . OCP is triggered if the voltage at PHASE pin

(drop of lower MOSFET VDS) is lower than −0.25V when

low side MOSFET conducting. Accordingly inductor

current threshold for OCP is a function of conducting

resista nce of lower MOSFET RDS(ON) as :

OCSET DS(ON)

30 A 21.6k-0.4V

If MOSFET with RDS(ON) = 10mΩ is used, the OCP

threshold current is about 25A. Once OCP is triggered,

the RT8101/A enters hiccup mode and re-soft starts again.

The RT8101/A shuts down after OCP hiccups twice.

Figure 3. Power On then Shorted

Figure 4. Shorted then Power On

OCP

Time (2.5ms/Div)

UGATE

(10V/Div)

IOUT

(10A/Div)

OCP

Time (2.5ms/Div)

UGATE

(10V/Div)

IOUT

(10A/Div)

RT8101/A

www.richtek.com DS8101/A-06 April 2011

1) Modulator Frequency Equations

The modulator transfer function is the small-signal transfer

function of VOUT / VCOMP (output voltage over the error

amplifier output. This tra n sfer function is domin ated by a

DC gain, a double pole, and a zero a s shown in Figure 7.

The DC gain of the modulator is the input voltage (VIN)

divided by the peak to peak oscillator voltage VOSC. The

output LC filter introduces a double pole, 40dB/decade

gain slope above its corner resonant frequency , and a total

pha se lag of 180 degrees. The resona nt frequency of the

LC filter is expressed as below:

OUTOUT

LC CL2 1

f×

ESRC2 1

fOUT

ESR ××

The ESR zero is contributed by the ESR a ssociated with

the output capacitance. Note that this requires that the

output capacitor should have enough ESR to satisfy

stability requirements. The ESR zero of the output

capacitor is expressed as follows :

2) Compensation Frequency Equations

The compensation network consists of the error amplifier

and the impedance networks ZC and ZF as shown in

Figure 6.

Figure 6. Compensation Loop

C2 x R2 x 2 1

fZ1

C2C1 C2 x C1

x R2 x 2 1

fP1

-FB

VREF

COMP EA

R2 R1

VOUT

Feedback Compensation

The RT8101/A is a voltage mode controller. The control

loop is a single voltage feedback path including a

compensator and modulator as shown in Figur e 5. The

modulator consists of the PWM comparator and power

stage. The PWM comparator compares error a mplifier EA

output (COMP) with oscillator (OSC) sawtooth wave to

provide a pulse-width modulated (PWM) with an amplitude

of VIN at the PHASE node. The PWM wave is smoothed

by the output filter LOUT and COUT. The output voltage (VOUT)

is sensed and fed to the inverting input of the error a mplifier.

A well-designed compensator regulates the output voltage

to the reference voltage VREF with fa st transient response

a nd good sta bility.

In order to achieve fast tran sient respon se and accurate

output regulation, an adequate compensator design is

necessary. The goal of the compensation network is to

provide adequate pha se margin (greater than 45 degrees)

and the highest 0dB crossing frequency. It is also

recommended to manipulate loop frequency response that

its gain crosses over 0dB at a slope of −20dB/dec.

Figure 5. Closed Loop

OSC

ΔVOSC

ZFB

ZIN

VIN

Driver

REF

PWM

Comparator

COMP

REF

ZFB ZIN VOUT

COMP

R2 R3

ESR

PHASE

COUT

VOUT

LOUT

RT8101/A

DS8101/A-06 April 2011 www.richtek.com

Figure 7 shows the DC/DC converter's gain vs. frequency.

The compensation gain uses external impedance networks

ZC a nd ZF to provide a sta ble, high ba ndwidth loop. High

crossover frequency is desirable for fast transient

response, but it often jeopardizes the system stability. In

order to cancel one of the LC filter poles, place the zero

before the LC filter resonant frequency . In the experience,

place the zero at 75% LC filter resonant frequency.

Crossover frequency should be higher than the ESR zero

but less tha n 1/5 of the switching frequency . The second

pole is pla ced at half of the switching frequency.

Figure 7. Bode Plot

Component Selection

1) Inductor Selection

The selection of output inductor is based on the

considerations of ef ficiency, output power and operating

frequency. Low inductance value has smaller size, but

results in low efficiency, large ripple current and high output

ripple voltage. Generally , an inductor that limits the ripple

current (ΔIL) between 20% and 50% of the output current

is appropriate. Figure 8 shows the typical topology of

synchronous step-down converter and its related

waveforms.

VIN

iS1

iS2 IOUT

VOUT

COUT

VOR

VOC

LIL

Frequency

10Hz 100Hz 1.0KHz 10KHz 100KHz 1.0MHz

vdb(vo) vdb(comp2) vdb(lo)

-40

-60

10 100 1k 10k 100k 1M

-20

-40

-60

Loop Gain

Compensation

Gain

Modulator

Gain

Frequency (Hz)

G a in (d B)

Figure 8. The waveforms of synchronous step-down

converter

According to Figure 8 the ripple current of inductor ca n be

calculated as follows :

(1)

Where :

VIN = Maximum input voltage

VOUT = Output Voltage

Δt = S1 turn on time

ΔIL = Inductor current ripple

fS = Switching frequency

D = Duty Cycle

rC = Equivalent series resistor of output capa citor

LIN OUT

OUTIN

OUT

OUTIN

IfsV V

) V(V L

D ;

t ;

L VV

Δ××

×−=

==Δ

=−

VIN - VOUT

- VOUT

IL = IOUT

ΔIL

IS1

IS2

TON TOFF

Vg1

Vg2

RT8101/A

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3) Input Capacitor

The selection of input capacitor is mainly based on its

maximum ripple current capability. The buck converter

draws pulsewise current from the input capacitor during

the on time of S1 a s shown in Figure 8. The RMS value of

ripple current flowing through the input capacitor is

described as :

(6)

The input ca pacitor must be capable of handling this ripple

current. Sometimes, for higher efficiency the low ESR

capacitor is necessarily.

(A) D)-D(1I

rms

IOUT

Figure 9. The related waveforms of output ca pacitor

2) Output Ca pa citor

The selection of output capa citor depends on the output

ripple voltage requirement. Practically, the output ripple

voltage is a function of both capacitance value and the

Equivalent Series Resistance (ESR) rC. Figure 9 shows

the related waveforms of output ca pa citor.

The AC impedance of output capacitor at operating

frequency is quite smaller than the load impedance, so

the ripple current (ΔIL) of the inductor current flows mainly

through output capacitor. The output ripple voltage is

described as :

where ΔVOR is caused by ESR and ΔVOC by ca pacitance.

For electrolytic ca p a citor application, typically 90 to 95%

of the output voltage ripple is contributed by the ESR of

output ca p acitor. So Equation (4) could be simplif ied a s :

ΔVOUT = ΔIL x rC

Users could connect ca pacitors in parallel to get calculated

ESR.

(2)

(3)

(4)

(5)

OUT OR OC

t2 C

OUT L C t1

OUT

OUT L L C S

V V V

V I r I dt

C1V

V I Ir (1D)T

Δ=Δ+Δ

Δ=Δ×+

Δ=Δ×Δ×+ −

∫

dt =dt L

VOUT

VOR

dIL

ΔIL

1/2

ΔIL x rC

VOC

t1 t2

ΔVOC

ΔIL

VIN-VOUT

IOUT

dIL

Thermal Considerations

For continuous operation, do not exceed absolute

maximum operation junction temperature 125°C. The

maximum power dissipation depends on the thermal

resistance of IC package, PCB layout, the rate of

surroundings airflow and temperature difference between

junction to a mbient. The maximum power dissipation can

be calculated by following formula :

PD(MAX) = ( TJ(MAX) − TA ) / θJA

Where TJ(MAX) is the maximum operation junction

temperature 125°C, TA is the ambient temperature and the

θJA is the junction to ambient thermal resistance.

For recommended operating conditions specification of

RT8101/A, where TJ(MAX) is the maximum junction

temperature of the die (125°C) and TA is the maximum

ambient temperature. The junction to ambient thermal

resistance θJA is layout dependent.

The maximum power dissipation at TA = 25°C can be

calculated by following formula :

PD(MAX) = ( 125°C − 25°C) / (120°C/W) = 0.83W for

SOP-8 pa ckages

PD(MAX) = ( 125°C − 25°C) / (75°C/W) = 1.33W for

SOP-8 (Exposed Pad) pa ck ages

The maximum power dissipation depends on operating

ambient temperature for fixed TJ (MAX) and thermal

resistance θJA. For RT8101/A packages, Figure 10 allows

the designer to see the effect of rising a mbient temperature

on the maximum power allowed.

RT8101/A

DS8101/A-06 April 2011 www.richtek.com

Figure 11. The connections of the critical components

in the converter

LOAD

VCC GND

RT8101/A

LGATE

UGATE

IQ1

VOUT

IQ2

5V/12V

GND

The power components and the PWM controller should

be placed firstly. Place the input capacitors, especially

the high-frequency cera mic decoupling ca pacitors, close

to the power switches. Place the output inductor and

output capacitors between the MOSFETs and the load.

Also locate the PWM controller near by MOSFETs. A

multi-layer printed circuit board is recommended.

Figure 11 shows the connections of the critical

components in the converter . Note that the capacitors CIN

and COUT each of them represents numerous physical

capacitors.

Use a dedicated grounding pla ne and use via s to ground

all critical components to this layer. Apply another solid

layer as a power plane and cut this plane into smaller

islands of common voltage levels. The power plane should

support the input power and output power nodes. Use

copper filled polygons on the top a nd bottom circuit layers

for the PHASE node, but it is not necessary to oversize

this particular island. Since the PHASE node is subjected

to very high dV/dt voltages, the stray ca pacitance formed

between these islands and the surrounding circuitry will

tend to couple switching noise. Use the remaining printed

circuit layers for small signal routing. The PCB traces

between the PWM controller and the gate of MOSFET

and also the traces connecting source of MOSFET s should

be sized to carry 2A peak currents.

PCB Layout Considerations

MOSFETs switch very fast and efficiently . The speed with

which the current tra n sition s from one device to another

causes voltage spikes across the interconnecting

impedances and parasitic circuit elements. The voltage

spikes can degrade efficiency and radiate noise, that results

in over voltage stress on devices. Careful component

placement layout and printed circuit design can minimize

the voltage spikes induced in the converter . Consider, a s

a n exa mple, the turn-off tra nsition of the upper MOSFET

prior to turn-off, the upper MOSFET wa s carrying the full

load current. During turn-off, current stops flowing in the

upper MOSFET and is picked up by the low side MOSFET

or schottky diode.

Any inducta nce in the switched current path generates a

large voltage spike during the switching interval. Careful

component selections, layout of the critical components,

a nd use shorter and wider PCB tra ces help in minimizing

the magnitude of voltage spikes.

There are two sets of critical components in a DC/DC

converter using the RT8101/A. The switching power

components are most critical because they switch large

amounts of energy, and as such, they tend to generate

equally large amounts of noise. The critical small signal

components are those connected to sensitive nodes or

those supplying critical bypass current.

Figure 10. Derating Curves for RT8101/A Packages

0.2

0.4

0.6

0.8

1.2

1.4

0 20 40 60 80 100 120 140

Ambien t Temper at ur e (°C)

Power Dissipat ion (W)

SOP-8

SOP-8 (Exposed Pad)

RT8101/A

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Outline Dimension

8-Lead SOP Plastic Package

Dimen sions In Millimeters Dimensions In In ches

Symbol Min Max Min Max

A 4.801 5.004 0.189 0.197

B 3.810 3.988 0.150 0.157

C 1.346 1.753 0.053 0.069

D 0.330 0.508 0.013 0.020

F 1.194 1.346 0.047 0.053

H 0.170 0.254 0.007 0.010

I 0.050 0.254 0.002 0.010

J 5.791 6.200 0.228 0.244

M 0.400 1.270 0.016 0.050

RT8101/A

DS8101/A-06 April 2011 www.richtek.com

Richtek Technology Corporation

Headquarter

5F, No. 20, Taiyuen Street, Chupei City

Hsinchu, Taiwan, R.O.C.

Tel: (8863)5526789 Fax: (8863)5526611

Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit

design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be

guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.

Richtek Technology Corporation

Taipei Office (Marketing)

5F, No. 95, Minchiuan Road, Hsintien City

Taipei County, Taiwan, R.O.C.

Tel: (8862)86672399 Fax: (8862)86672377

Email: marketing@richtek.com

EXPOSED THERMAL PAD

(Bottom of Package)

8-Lead SOP (Exposed Pad) Plastic Package

Dimensions In Millimeters Dimensions In Inches

Symbol Min Max Min Max

A 4.801 5.004 0.189 0.197

B 3.810 4.000 0.150 0.157

C 1.346 1.753 0.053 0.069

D 0.330 0.510 0.013 0.020

F 1.194 1.346 0.047 0.053

H 0.170 0.254 0.007 0.010

I 0.000 0.152 0.000 0.006

J 5.791 6.200 0.228 0.244

M 0.406 1.270 0.016 0.050

X 2.000 2.300 0.079 0.091

Option 1 Y 2.000 2.300 0.079 0.091

X 2.100 2.500 0.083 0.098

Option 2 Y 3.000 3.500 0.118 0.138