CMOS, Low Voltage, 3-Wire
Serially-Controlled, Matrix Switches
Data Sheet
ADG738/ADG739
Rev. A Document Feedback
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FEATURES
3-wire serial interface
2.7 V to 5.5 V single supply
2.5 Ω on resistance
0.75 Ω on-resistance flatness
100 pA leakage currents
Single 8-to-1 multiplexer ADG738
Dual 4-to-1 multiplexer ADG739
Power-on reset
TTL/CMOS-compatible
Qualified for automotive applications
APPLICATIONS
Data acquisition systems
Communication systems
Relay replacement
Audio and video switching
GENERAL DESCRIPTION
The ADG738 and ADG739 are CMOS analog matrix switches
with a serially-controlled 3-wire interface. The ADG738 is an
8-channel matrix switch, while the ADG739 is a dual 4-channel
matrix switch. On resistance is closely matched between switches
and very flat over the full signal range.
FUNCTIONAL BLOCK DIAGRAMS
Figure 1.
Figure 2.
The ADG738 and ADG739 utilize a 3-wire serial interface
that is compatible with SPI™, QSPI™, MICROWIRE®, and some
DSP interface standards. The output of the input shift register,
DOUT, enables a number of these parts to be daisy-chained.
On power-up, the internal input shift register contains all zeros
and all switches are in the off state.
Each switch conducts equally well in both directions when on,
making these parts suitable for both multiplexing and demulti-
plexing applications. As each switch is turned on or off by a
separate bit, these parts can also be configured as a type of
switch array, where any, all, or none of the eight switches may
be closed at any time. The input signal range extends to the
supply rails.
All channels exhibit break-before-make switching action,
preventing momentary shorting when switching channels.
The ADG738 and ADG739 are available in 16-lead TSSOP
packages.
PRODUCT HIGHLIGHTS
1. 3-Wire Serial Interface.
2. Single Supply Operation. The ADG738/ADG739 are fully
specified and guaranteed with 3 V and 5 V supply rails.
3. Low On Resistance, 2.5 Ω typical.
4. Any configuration of switches may be on or off at any
one time.
5. Guaranteed Break-Before-Make Switching Action.
6. Small 16-lead TSSOP Package.
S1
S8
SCLK
D
DIN SYNC
ADG738
RESET
DOUT
INPUT SHIFT
REGISTER
10758-001
S1A
SCLK
DA
DIN
S4A
S1B
S4B DB
ADG739
DOUT
SYNC
INPUT SHIFT
REGISTER
10758-002
ADG738/ADG739 Data Sheet
Rev. A | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 9
Test Circuits ..................................................................................... 12
Terminology .................................................................................... 14
Theory of Operation ...................................................................... 15
Power-On Reset .......................................................................... 15
Serial Interface ............................................................................ 15
Microprocessor Interfacing ....................................................... 15
ADSP-21xx to ADG738/ADG739 ........................................... 15
8051 Interface to ADG738/ADG739 ....................................... 16
MC68HC11 Interface to ADG738/ADG739 .......................... 16
Applications Information .............................................................. 17
Expand the Number of Selectable Serial Devices Using an
ADG739 ....................................................................................... 17
Daisy-Chaining Multiple ADG738s ........................................ 17
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 18
Automotive Products ................................................................. 18
REVISION HISTORY
11/12—Rev. 0 to Rev. A
Updated Format .................................................................. Universal
Changes to Features Section............................................................ 1
Added W Version Specifications to Table 1 .................................. 3
Added W Version Specifications to Table 2 .................................. 4
Changes to Table 4 ............................................................................ 6
Changes to Figure 7, Figure 8, and Figure 11 ............................... 9
Changes to Figure 12 ...................................................................... 10
Deleted Figure 22 ............................................................................ 12
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 19
4/00—Revision 0: Initial Version
Data Sheet ADG738/ADG739
Rev. A | Page 3 of 20
SPECIFICATIONS
VDD = 5 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
B Version W Version
Parameter 25°C −40°C to +85°C −40°C to +105°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
0 V to V
DD
V
On Resistance (RON) 2.5 Ω typ VS = 0 V to VDD, IS = 10 mA; see Figure 19
4.5 5 6 Ω max
On-Resistance Match Between
Channels (∆R
ON
)
0.4 Ω typ VS = 0 V to VDD, IS = 10 mA
0.8 1 Ω max
On-Resistance Flatness (R
FLAT(ON)
) 0.75 Ω typ V
S
= 0 V to V
DD
, I
S
= 10 mA
1.2 1.5 Ω max
LEAKAGE CURRENTS V
DD
= 5.5 V
Source Off Leakage IS (Off)
±0.01
nA typ
VD = 4.5 V/1 V, VS = 1 V/4.5 V; see Figure 20
±0.1
±0.6
nA max
Drain Off Leakage I
D
(Off)
±0.01
nA typ
V
D
= 4.5 V/1 V, V
S
= 1 V/4.5 V
±0.1 ±1 ±1.3 nA max
Channel On Leakage ID, IS (On) ±0.01 nA typ VD = VS = 1 V/4.5 V, see Figure 21
±0.1 ±1 ±1.3 nA max
DIGITAL INPUTS
Input High Voltage, V
INH
2.4 V min
Input Low Voltage, V
INL
0.8 V max
Input Current, I
INL
or I
INH
0.005 µA typ V
IN
= V
INL
or V
INH
±0.1
µA max
CIN, Digital Input Capacitance 3 pF typ
DIGITAL OUTPUT
Output Low Voltage 0.4 max I
SINK
= 6 mA
C
OUT
, Digital Output Capacitance 4 pF typ
DYNAMIC CHARACTERISTICS
1
t
ON
20 ns typ R
L
= 300 Ω, C
L
= 35 pF, see Figure 22; V
S1
= 3 V
32 35 ns max
t
OFF
10 ns typ R
L
= 300 Ω, C
L
= 35 pF, see Figure 22; V
S1
= 3 V
17 20 ns max
Break-Before-Make Time Delay, t
D
9 ns typ R
L
= 300 Ω, C
L
= 35 pF;
1 1 ns min V
S1
= V
S8
= 3 V, see Figure 22
Charge Injection ±3 pC typ V
S
= 2.5 V, R
S
= 0 Ω, C
L
= 1 nF; see Figure 23
Off Isolation −55 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 10 MHz
−75 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz; see Figure 25
Channel-to-Channel Crosstalk −55 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 10 MHz
−75 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz; see Figure 24
−3 dB Bandwidth
ADG738 65 MHz typ R
L
= 50 Ω, C
L
= 5 pF, see Figure 25
ADG739 100 MHz typ
C
S
(Off) 13 pF typ
CD (Off)
ADG738
85
pF typ
ADG739 42 pF typ
CD, CS (On)
ADG738 96 pF typ
ADG739 48 pF typ
POWER REQUIREMENTS V
DD
= 5.5 V
I
DD
10 µA typ Digital Inputs = 0 V or 5.5 V
20 20 µA max
1 Guaranteed by design, not subject to production test.
ADG738/ADG739 Data Sheet
Rev. A | Page 4 of 20
VDD = 3 V ± 10%, GND = 0 V, unless otherwise noted.
Table 2.
B Version W Version
Parameter 25°C −40°C to +85°C −40°C to +105°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to V
DD
V
On Resistance (R
ON
) 6 Ω typ V
S
= 0 V to V
DD
, I
S
= 10 mA; see Figure 19
11 12 16 Ω max
On-Resistance Match Between
Channels (∆RON)
0.4 Ω typ VS = 0 V to VDD, IS = 10 mA
1.2 1.4 Ω max
On-Resistance Flatness (RFLAT(ON))
3.5
Ω typ
VS = 0 V to VDD, IS = 10 mA
LEAKAGE CURRENTS V
DD
= 3.3 V
Source Off Leakage IS (Off) ±0.01 nA typ VS = 3 V/1 V, VD = 1 V/3 V; see Figure 20
±0.1 ±0.3 ±0.6 nA max
Drain Off Leakage I
D
(Off) ±0.01 nA typ V
D
= 3 V/1 V, V
D
= 1 V/3 V
±0.1 ±1 ±1.3 nA max
Channel On Leakage I
D
, I
S
(On) ±0.01 nA typ V
D
= V
S
= 3 V/1 V, see Figure 21
±0.1 ±1 ±1.3 nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min
Input Low Voltage, V
INL
0.4 V max
Input Current, I
INL
or I
INH
0.005 µA typ V
IN
= V
INL
or V
INH
±0.1 ±0.1 µA max
C
IN
, Digital Input Capacitance 3 pF typ
DIGITAL OUTPUT
Output Low Voltage 0.4 max ISINK = 6 mA
C
OUT
, Digital Output Capacitance 4 pF typ
DYNAMIC CHARACTERISTICS1
t
ON
40 ns typ R
L
= 300 Ω, C
L
= 35 pF, see Figure 22; V
S1
= 2 V
70 75 ns max
t
OFF
14 ns typ R
L
= 300 Ω, C
L
= 35 pF, see Figure 22; V
S1
= 2 V
25 40 ns max
Break-Before-Make Time Delay, tD 12 ns typ RL = 300 Ω, CL = 35 pF;
1
1
ns min
VS = 2 V, see Figure 22
Charge Injection ±3 pC typ VS = 1.5 V, RS = 0 Ω, CL = 1 nF; see Figure 23
Off Isolation −55 dB typ RL = 50 Ω, CL = 5 pF, f = 10 MHz
−75
dB typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 25
Channel-to-Channel Crosstalk −55 dB typ RL = 50 Ω, CL = 5 pF, f = 10 MHz
−75 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz; see Figure 24
−3 dB Bandwidth
ADG738 65 MHz typ RL = 50 Ω, CL = 5 pF, see Figure 25
ADG739
100
MHz typ
CS (Off) 13 pF typ
C
D
(Off)
ADG738 85 pF typ
ADG739 42 pF typ
CD, CS (On)
ADG738 96 pF typ
ADG739 48 pF typ
POWER REQUIREMENTS VDD = 3.3 V
IDD
10
µA typ
Digital Inputs = 0 V or 3.3 V
20 20 µA max
1 Guaranteed by design, not subject to production test.
Data Sheet ADG738/ADG739
Rev. A | Page 5 of 20
TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V. All specifications −40°C to +105°C, unless otherwise noted.
Table 3.
Parameter1, 2
Limit at T
MIN
, T
MAX
Unit Test Conditions/Comments Min Max
f
SCLK
30 MHz SCLK cycle frequency
t
1
33 ns SCLK cycle time
t
2
13 ns SCLK high time
t
3
13 ns SCLK low time
t4 0 ns SYNC to SCLK active edge setup time
t5
5
ns
Data setup time
t
6
4.5 ns Data hold time
t7 0 ns SCLK falling edge to SYNC rising edge
t8 33 ns Minimum SYNC high time
t
9
3 20 ns min SCLK rising edge to DOUT valid
1 See Figure 3.
2 All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
3 CL = 20 pF, RL = 1 kΩ.
Figure 3. 3-Wire Serial Interface Timing Diagram
SCLK
SYNC
DIN
DB7 DB0
DB71DB01
DOUT
1
DATA FROM LAST W RIT E CY CLE.
t3
t2
t1
t
4
t8
t
6
t
5
t9
t
7
10758-003
ADG738/ADG739 Data Sheet
Rev. A | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise noted.
Table 4.
Parameter Rating
VDD to GND −0.3 V to +7 V
Analog, Digital Inputs1 −0.3 V to VDD + 0.3 V or
30 mA, Whichever
Occurs First
Peak Current, S or D 100 mA
(Pulsed at 1 ms, 10%
Duty Cycle Max)
Continuous Current, Each S 30 mA
Continuous Current D
ADG739 80 mA
ADG738 120 mA
Operating Temperature Range
Industrial (B Version) −40°C to +85°C
Industrial (W Version) −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
TSSOP Package
θJA Thermal Impedance 150.4°C/W
θJC Thermal Impedance 27.6°C/W
Lead Temperature, Soldering As per JEDEC J-STD-020
1 Overvoltages at IN, S, or D are clamped by internal diodes. Limit current to
the maximum ratings given.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Data Sheet ADG738/ADG739
Rev. A | Page 7 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 4. ADG738 Pin Configuration
Table 5. ADG738 Pin Function Descriptions
Pin No. Mnemonic Description
1 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.
These devices can accommodate serial input rates of up to 30 MHz.
2 RESET Active Low Control Input. This pin clears the input register and turns all switches to the off condition.
3 DIN Serial Data Input. Data is clocked into the 8-bit input register on the falling edge of the serial clock input.
4, 5, 6, 7 S1, S2, S3, S4 Source. May be an input or output.
8
D
Drain. May be an input or output.
9, 10, 11, 12 S8, S7, S6, S5 Source. May be an input or output.
13 V
DD
Power Supply Input. These parts can be operated from a supply of 2.7 V to 5.5 V.
14 GND Ground Reference.
15 DOUT Data Output. This allows a number a parts to be daisy-chained. Data is clocked out of the input shift
register on the rising edge of SCLK. This is an open drain output, which should be pulled to the supply
with an external resistor.
16 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low,
it powers on the SCLK and DIN buffers and the input shift register is enabled. Data is transferred on the
falling edges of the following clocks. Taking SYNC high updates the switch conditions.
SCLK
RESET
S2
S3
S4
S1
D
SYNC
DOUT
S5
S6
S7
GND
V
DD
S8
DIN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ADG738
TOP VIEW
(No t t o Scal e)
10758-004
ADG738/ADG739 Data Sheet
Rev. A | Page 8 of 20
Figure 5. ADG739 Pin Configuration
Table 6. ADG739 Pin Function Descriptions
Pin No. Mnemonic Description
1 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. These devices can accommodate serial input rates of up to 30 MHz.
2 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC
goes low, it powers on the SCLK and DIN buffers and the input shift register is enabled. Data is
transferred on the falling edges of the following clocks. Taking SYNC high updates the switch
conditions.
3 DIN Serial Data Input. Data is clocked into the 8-bit input register on the falling edge of the serial
clock input.
4, 5, 6, 7 S1A, S2A, S3A, S4A Source. May be an input or output.
8, 9 DA, DB Drain. May be an input or output.
10, 11, 12, 13 S4B, S3B, S2B, S1B Source. May be an input or output.
14 V
DD
Power Supply Input. These parts can be operated from a supply of 2.7 V to 5.5 V.
15 GND Ground Reference.
16 DOUT Data Output. This allows a number a parts to be daisy-chained. Data is clocked out of the input
shift register on the rising edge of SCLK. This is an open drain output, which should be pulled to
the supply with an external resistor.
SCLK
S2A
S3A
S4A
S1A
DA
S1B
DOUT
S2B
S3B
S4B
GND
VDD
DB
DIN
SYNC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ADG739
TOP VIEW
(No t t o Scal e)
10758-005
Data Sheet ADG738/ADG739
Rev. A | Page 9 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 6. On Resistance as a Function of VD (VS)
Figure 7. On Resistance as a Function of VD (VS) for Different Temperatures,
VDD = 5 V
Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures,
VDD = 3 V
Figure 9. Leakage Currents as a Function of VD (VS), VDD = 5 V
Figure 10. Leakage Currents as a Function of VD (VS), VDD = 3 V
Figure 11. Leakage Currents as a Function of Temperature, VDD = 5 V
8
0 1 2 3 4
7
6
5
4
3
2
1
0
ON RE S ISTANCE (Ω)
V
DD
= 3.3V
V
DD
= 4.5V
V
DD
= 5.5V
V
DD
= 2.7V
5
V
D
OR V
S
– DRAIN OR SO URCE V OLTAGE (V)
T
A
= 25° C
V
SS
= 0V
10758-006
10758-007
0 1 2 3 4 5
7
6
5
4
3
2
1
0
+85°C
+25°C
+125°C
–40°C
V
DD
= 5V
V
SS
= 0V
8
V
D
OR V
S
– DRAIN OR SO URCE V OL TAG E ( V )
10758-008
+85°C
–40°C
V
DD
= 3V
V
SS
= 0V
7
6
5
4
3
2
1
0
8
00.5 1.0 1.5 2.0 3.02.5
V
D
OR V
S
– DRAIN OR SO URCE V OL TAG E ( V )
+25°C
+125°C
ON RE S IST ANCE ( Ω)
012345
V
D
[V
S
] (V)
0.12
CURRENT ( nA)
0.08
0.04
0
–0.04
–0.08
–0.12
I
D
(O N)
I
S
(OFF)
I
D
(OFF)
V
DD
= 5V
V
SS
= 0V
T
A
= 25° C
10758-009
V
D
[V
S
] (V)
0.12
CURRENT ( nA)
00.5 1.0 1.5 2.0 2.5 3.0
0.08
0.04
0
0.04
0.08
0.12
I
D
(O N)
I
S
(OFF) I
D
(OFF)
V
DD
= 3V
V
SS
= 0V
T
A
= 25° C
10758-010
10758-011
0
020 40 60 80 100 120
CURRENT ( nA)
TEMPERATURE (°C)
0.05
0.10
0.15
0.20
0.25
0.30
0.35 V
DD
= 5V
V
SS
= 0V
I
D
(OFF) I
S
(OFF)
I
D
(O N)
ADG738/ADG739 Data Sheet
Rev. A | Page 10 of 20
Figure 12. Leakage Currents as a Function of Temperature, VDD = 3 V
Figure 13. Input Currents vs. Switching Frequency
Figure 14. Charge Injection vs. Source Voltage
Figure 15. TON/TOFF Times vs. Temperature
10758-012
0
020 40 60 80 100 120
CURRENT ( nA)
TEMPERATURE (°C)
0.05
0.10
0.15
0.20
0.25
0.30
0.35 V
DD
= 3V
I
D
(OFF)
I
S
(OFF)
I
D
(O N)
FREQUENCY (Hz)
CURRENT ( A)
1µ
10k
10µ
100µ
1m
10m
100k 1M 10M 100M
TA = 25° C
VDD = 5V
VDD = 3V
10758-013
VOLTAGE (V)
Q
INJ
(p C)
–40
–30
–20
–10
0
10
20
012345
T
A
= 25° C
V
DD
= 3V
V
SS
= 0V
V
DD
= 5V
V
SS
= 0V
10758-014
TEMPERATURE (°C)
TIME (n s)
0
5
10
15
20
25
30
35
40
–40 –20 020 40 60
45
50
80
10758-015
TON, VDD = 3V
TOFF, VDD = 3V
TON, VDD = 5V
TOFF, VDD = 5V
Data Sheet ADG738/ADG739
Rev. A | Page 11 of 20
Figure 16. Off Isolation vs. Frequency
Figure 17. Crosstalk vs. Frequency
Figure 18. On Response vs. Frequency
100k 1M 10M 100M
FREQUENCY (Hz)
0
30k
ATTENUATION (dB)
–20
–40
–60
–80
–100
–120
V
DD
= 5V
T
A
= 25° C
10758-016
FREQUENCY (Hz)
100k 1M 10M 100M30k
0
–20
–40
–60
–80
–100
–120
ATTENUATION (dB)
V
DD
= 5V
T
A
= 25° C
10758-017
FREQUENCY (Hz)
0
30k
ATTENUATION (dB)
–5
100M
100k 1M 10M
–10
–15
–20
VDD = 5V
TA = 25° C
ADG738
ADG739
10758-018
ADG738/ADG739 Data Sheet
Rev. A | Page 12 of 20
TEST CIRCUITS
Figure 19. On Resistance
Figure 20. ID (Off), IS (Off)
Figure 21. IS, ID (On)
Figure 22. Switching Times and Break-Before-Make Times
Figure 23. Charge Injection
I
DS
SD
V
S
V
10758-025
R
ON
=V/I
DS
S1 D
V
S
A A
V
D
I
S
(OFF) I
D
(OFF)
Sn
10758-026
A
10758-028
S2
V
D
V
D
Sn
S1 A
D
I
D
(ON)
NC
NC = NO CONNECT
GND
V
DD
V
DD
50%
t
OFF
90%
90%
50%
V
OUT
D
V
S1
ADG738*
S1
S8
S2 THRU S7
R
L
300Ω
C
L
35pF
V
S1
80% 80%
V
S1
= V
S8
V
S8
V
OUT
V
OUT
SYNC
t
ON
t
OPEN
*SIMILAR CONNECTION FOR ADG739.
10758-029
SYNC
GND
V
DD
ADG738*
1nF
INPUT LOGIC
V
OUT
C
L
V
S
R
S
D
*SIMILAR CONNECTION FOR ADG739.
SSWITCH OFF
SWITCH ON
∆V
OUT
Q
INJ
= C
L
× V
OUT
10758-030
SYNC
Data Sheet ADG738/ADG739
Rev. A | Page 13 of 20
Figure 24. Channel-to-Channel Crosstalk
Figure 25. Off Isolation and Bandwidth
GND
ADG738*
S1
S2
S8
*SI M ILAR CONNECTI ON F OR ADG739.
CHANNEL - TO- CHANNE L CRO S S TAL K = 20LO G
10
(V
OUT
/V
S
)
V
OUT
VDD
V
DD
50Ω
V
S
D
50Ω
R
L
10758-031
50Ω
GND
ADG738*
S1
S8
V
OUT
V
DD
RL
V
DD
V
S
D
*SI M ILAR CONNECTI ON F OR ADG739.
OFF ISOLATION = 20LOG
10 (VOUT/VS)
V
OUT
WITHOUT SWITCH
INSERTION LOSS = 20LOG
10
V
OUT
WITH SWITCH
S1 IS SWITCHED OFF FOR OFF ISOLATION MEASUREMENTS
AND ON FOR BANDWI DTH ME AS URE M E NTS
10758-032
ADG738/ADG739 Data Sheet
Rev. A | Page 14 of 20
TERMINOLOGY
VDD
Most positive power supply potential.
IDD
Positive supply current.
GND
Ground (0 V) reference.
S
Source terminal. May be an input or output.
D
Drain terminal. May be an input or output.
VD (VS)
Analog voltage on Terminal D, Terminal S.
RON
Ohmic resistance between D and S.
∆RON
On resistance match between any two channels, that is, RONmax
− RONmin.
RFLAT(ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance as measured over the specified
analog signal range.
IS (Off)
Source leakage current with the switch off.
ID (Off)
Drain leakage current with the switch off.
ID, IS (On)
Channel leakage current with the switch on.
VINL
Maximum input voltage for Logic 0.
VINH
Minimum input voltage for Logic 1.
IINL (IINH)
Input current of the digital input.
CS (Off)
Off switch source capacitance. Measured with reference to
ground.
CD (Off)
Off switch drain capacitance. Measured with reference to
ground.
CD, CS (On)
On switch capacitance. Measured with reference to ground.
CIN
Digital input capacitance.
tON
Delay time between the 50% and 90% points of the SYNC rising
edge and the switch on condition.
tOFF
Delay time between the 50% and 90% points of the SYNC rising
edge and the switch off condition.
tD
Off time measured between the 80% points of both switches
when switching from one switch to another.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
Off Isolation
A measure of unwanted signal coupling through an off switch.
Crosstalk
A measure of unwanted signal which is coupled through from
one channel to another as a result of parasitic capacitance.
Bandwidth
The frequency at which the output is attenuated by 3 dB.
On Response
The frequency response of the on switch.
Insertion Loss
The loss due to the on resistance of the switch.
Data Sheet ADG738/ADG739
Rev. A | Page 15 of 20
THEORY OF OPERATION
The ADG738 and ADG739 are serially controlled, 8-channel
and dual 4-channel matrix switches, respectively. While provid-
ing the normal multiplexing and demultiplexing functions,
these parts also provide the user with more flexibility as to
where their signal may be routed. Each bit of the 8-bit serial
word corresponds to one switch of the part. A Logic 1 in the
particular bit position turns on the switch, while a Logic 0 turns
the switch off. Because each switch is independently controlled
by an individual bit, this provides the option of having any, all,
or none of the switches on. This feature may be particularly
useful in the demultiplexing application where the user may
wish to direct one signal from the drain to a number of outputs
(sources). Take care, however, in the multiplexing situation
where a number of inputs may be shorted together (separated
only by the small on resistance of the switch).
When changing the switch conditions, a new 8-bit word is
written to the input shift register. Some of the bits may be the
same as the previous write cycle, as the user may not wish to
change the state of some switches. To minimize glitches on the
output of these switches, the part cleverly compares the state of
switches from the previous write cycle. If the switch is already
in the on condition, and is required to stay on, there will be
minimal glitches on the output of the switch.
POWER-ON RESET
During device power-up, all switches will be in the off condi-
tion and the internal input shift register is filled with zeros and
remains so until a valid write takes place.
SERIAL INTERFACE
The ADG738 and ADG739 have a 3-wire serial interface
(SYNC, SCLK, and DIN), which is compatible with SPI, QSPI,
MICROWIRE interface standards and most DSPs. Figure 3
shows the timing diagram of a typical write sequence.
Data is written to the 8-bit input shift register via DIN under
the control of the SYNC and SCLK signals. Data may be written
to the input shift register in more or less than eight bits. In each
case, the input shift register retains the last eight bits that were
written.
When SYNC goes low, the input shift register is enabled. Data
from DIN is clocked into the input shift register on each falling
edge of SCLK. Each bit of the 8-bit word corresponds to one of
the eight switches. Figure 26 shows the contents of the input
shift register. Data appears on the DOUT pin on the rising edge
of SCLK suitable for daisy-chaining, delayed, of course, by eight
bits. When all eight bits have been written into the shift register,
the SYNC line is brought high again. The switches are updated
with the new configuration and the input shift register is
disabled. With SYNC held high, any further data or noise
on the DIN line has no effect on the shift register.
Figure 26. Input Shift Register Contents
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the ADG738/ADG739 is via
a serial bus that uses a standard protocol compatible with
microcontrollers and DSP processors. The communications
channel is a 3-wire (minimum) interface consisting of a
clock signal, a data signal, and a synchronization signal.
The ADG738/ADG739 requires an 8-bit data word with
data valid on the falling edge of SCLK.
Data from the previous write cycle is available on the DOUT
pin. The following sections illustrate simple 3-wire interfaces
with popular microcontrollers and DSPs.
ADSP-21xx TO ADG738/ADG739
An interface between the ADG738/ADG739 and the ADSP-
21xx is shown in Figure 27. In the interface example shown,
SPORT0 is used to transfer data to the matrix switch. The
SPORT control register should be configured as follows:
internal clock operation, alternate framing mode; active low
framing signal.
Transmission is initiated by writing a word to the Tx register
after the SPORT has been enabled. As the data is clocked out of
the DSP on the rising edge of SCLK, no glue logic is required to
interface the DSP to the matrix switch. The update of each switch
condition takes place automatically when TFS is taken high.
Figure 27. ADSP-21xx to ADG738/ADG739 Interface
S8 S7 S6 S5 S4 S3 S2 S1
DB0 (L S B)
DB7 (MS B)
DATA BITS
10758-019
SCLK
DIN
SYNC
TFS
DT
SCLK
ADSP-21xx*
*ADDITIONAL PINS OMITTED FOR CLARITY.
ADG738/
ADG739
10758-020
ADG738/ADG739 Data Sheet
Rev. A | Page 16 of 20
8051 INTERFACE TO ADG738/ADG739
A serial interface between the ADG738/ADG739 and the 8051
is shown in Figure 28. TXD of the 8051 drives SCLK of the
ADG738/ADG739, while RXD drives the serial data line, DIN.
P3.3 is a bit-programmable pin on the serial port and is used to
drive SYNC.
The 8051 provides the LSB of its SBUF register as the first bit in
the data stream. The user has to ensure that the data in the SBUF
register is arranged correctly as the switch expects MSB first.
When data is to be transmitted to the matrix switch, P3.3 is
taken low. Data on RXD is clocked out of the microcontroller
on the rising edge of TXD and is valid on the falling edge. As a
result no glue logic is required between the ADG738/ADG739
and microcontroller interface.
Figure 28. 8051 Interface to ADG738/ADG739
MC68HC11 INTERFACE TO ADG738/ADG739
Figure 29 shows an example of a serial interface between the
ADG738/ADG739 and the MC68HC11 microcontroller. SCK
of the 68HC11 drives the SCLK of the matrix switch, while the
MOSI output drives the serial data line, DIN. SYNC is driven
from one of the port lines, in this case PC7.
Figure 29. MC68HC11 Interface to ADG738/ADG739
The 68HC11 is configured for master mode; MSTR = 1, CPOL
= 0, and CPHA = 1. When data is transferred to the part, PC7 is
taken low, data is transmitted MSB first. Data appearing on the
MOSI output is valid on the falling edge of SCK.
If the user wishes to verify the data previously written to the
input shift register, the DOUT line could be connected to MISO
of the MC68HC11, and with SYNC low, the input shift register
would clock data out on the rising edges of SCLK.
ADG738/
ADG739
SCLK
DIN
P3.3
RXD
TXD
80C51/80L51*
*ADDITIONAL PINS OMITTED FOR CLARITY.
SYNC
10758-021
ADG738/
ADG739
SCLK
DIN
PC7
MOSI
SCK
MC68HC11*
*ADDITIONAL PINS OMITTED FOR CLARITY.
SYNC
10758-022
Data Sheet ADG738/ADG739
Rev. A | Page 17 of 20
APPLICATIONS INFORMATION
EXPAND THE NUMBER OF SELECTABLE SERIAL
DEVICES USING AN ADG739
The dual 4-channel ADG739 multiplexer can be used to
multiplex a single chip select line to provide chip selects for
up to four devices on the SPI bus. Figure 30 illustrates the
ADG739 in such a typical configuration. All devices receive
the same serial clock and serial data, but only one device
receives the SYNC signal at any one time. The ADG739 is a
serially controlled device also. One bit programmable pin of
the microcontroller is used to enable the ADG739 via SYNC2,
while another bit programmable pin is used as the chip select
for the other serial devices, SYNC1. Driving SYNC2 low enables
changes to be made to the addressed serial devices. By
bringing SYNC1 low, the selected serial device hanging from
the SPI bus is enabled and data will be clocked into its input
shift register on the falling edges of SCLK. The convenient
design of the matrix switch allows for different combinations of
the four serial devices to be addressed at any one time. If more
devices need to be addressed via one chip select line, the
ADG738 is an 8-channel device and would allow further
expansion of the chip select scheme. There may be some digital
feedthrough from the digital input lines because SCLK and DIN
are permanently connected to each device. Using a burst clock
minimizes the effects of digital feedthrough on the analog
channels.
Figure 30. Addressing Multiple Serial Devices Using an ADG739
DAISY-CHAINING MULTIPLE ADG738S
A number of ADG738 matrix switches may be daisy-chained
simply by using the DOUT pin. DOUT is an open-drain output
that should be pulled to the supply with an external resistor.
Figure 31 shows a typical implementation. The SYNC pin of
all three parts in the example are tied together. When SYNC
is brought low, the input shift registers of all parts are enabled,
data is written to the parts via DIN, and clocked through the
shift registers. When the transfer is complete, SYNC is brought
high and all switches are updated simultaneously. Further shift
registers may be added in series.
Figure 31. Multiple ADG739 Devices in a Daisy-Chained Configuration
DA
1/2 OF
ADG739
V
DD
SCLK DIN SYNC
S1A
S2A
S3A
S4A
SYNC1
DIN
SCLK
DIN
SCLK
DIN
SCLK
DIN
SCLK
DIN
SCLK
ADG739
ADG738
OTHER SPI
DEVICE
SYNC2
FROM
MICRO-
CONTROLLER
OR DSP OTHER SPI
DEVICE
SYNC
SYNC
SYNC
SYNC
10758-023
SCLK
DIN DOUT
ADG739
SCLK
DIN
ADG739
SCLK
DIN TUOD
TUOD
SCLK
DIN
TO OTHER
SERIAL DEVICES
ADG739
V
DD
RR
R
SYNCSYNC SYNC SYNC
10758-024
ADG738/ADG739 Data Sheet
Rev. A | Page 18 of 20
OUTLINE DIMENSIONS
Figure 32. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2 Temperature Range Package Description Package Option
ADG738BRU −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG738BRUZ −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG738BRUZ-REEL −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG738BRUZ-REEL7 −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG738WBRUZ-REEL −40°C to +105°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG739BRU −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG739BRU-REEL7 −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG739BRUZ −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG739BRUZ-REEL −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG739BRUZ-REEL7 −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The ADG738W model is available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.
16 9
81
PIN 1
SEATING
PLANE
8°
0°
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.65
BSC
0.15
0.05
1.20
MAX 0.20
0.09 0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COM P LI ANT T O JE DE C S TANDARDS M O-153 - AB
Data Sheet ADG738/ADG739
Rev. A | Page 19 of 20
NOTES
ADG738/ADG739 Data Sheet
Rev. A | Page 20 of 20
NOTES
©2000–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10758-0-11/12(A)