DATA SHEET
8-BIT SINGLE-CHIP MICROCONTROLLERS
MOS INTEGRATED CIRCUIT
µ
µµ
µ
PD78F9436
,
78F9456
Document No. U15379EJ1V0DS00 (1st edition)
Date Published June 2001 N CP(K)
Printed in Japan
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
DESCRIPTION
The
µ
PD78F9436 and 78F9456 belong to the
µ
PD789436, 789456 Subseries (for LCD drivers) in the 78K/0S
Series.
The
µ
PD78F9436 has flash memory in place of the internal ROM of the
µ
PD789435 and 789436, and the
µ
PD78F9456 has flash memory in place of the internal ROM of the
µ
PD789455 and 789456.
Because flash memory allows the program to be written and erased electrically with the device mounted on the
board, this product is ideal for the evaluation stages of system development, small-scale production, and rapid
development of new products.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
µ
µµ
µ
PD789426, 789436, 789446, 789456 Subseries User’s Manual: U15075E
78K/0S Series User’s Manual Instructions: U11047E
FEATURES
• Pin compatible with mask ROM version (except VPP pin)
•Flash memory and RAM capacities
Data MemoryItem
Part Number
Flash Memory
Internal High-Speed RAM LCD Display RAM
µ
PD78F9436 5 × 4 bits
µ
PD78F9456
16 KB 512 bytes
15 × 4 bits
•Minimum instruction execution time can be changed from high-speed (0.4
µ
s at 5.0 MHz operation with main
system clock) to ultra-low-speed (122
µ
s at 32.768 kHz operation with subsystem clock).
•I/O ports : 40 (
µ
PD78F9436)
: 30 (
µ
PD78F9456)
•Timer: 5 channels
•A/D converter
10-bit resolution: 6 channels
•Serial interface: 1 channel
•LCD controller/driver
Segment signals: 5, common signals: 4 (
µ
PD78F9436)
Segment signals: 15, common signals: 4 (
µ
PD78F9456)
•Power supply voltage: VDD = 1.8 to 5.5 V
APPLICATIONS
Portable audio systems, cameras, healthcare equipment, etc.
©1996, 1999
2001
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS
2
ORDERING INFORMATION
Part Number Package
µ
PD78F9436GK-9ET 64-pin plastic TQFP (12 × 12)
µ
PD78F9456GK-9ET 64-pin plastic TQFP (12 × 12)
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS 3
78K/0S SERIES LINEUP
The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.
Remark VFD (Vacuum Fluorescent Display) is referred to as “FIPTM” (fluorescent Indicator panel) in some
documents, but the functions of the two are the same.
PD789327
µ
PD789467
µ
PD789014
Products under development
Products in mass production
PD789074
Small-scale package, general-purpose applications
78K/0S
Series
28-pin
PD789014 with enhanced timer and increased ROM, RAM capacity
On-chip UART and capable of low voltage (1.8 V) operation
PD789074 with added subsystem clock
LCD drive
Inverter control
44-pin PD789842 On-chip inverter controller and UART
ASSP
80-pin
80-pin
PD789446
PD789456
PD789436
PD789417A
PD789407A
PD789426
PD789306
PD789316
PD789426 with enhanced A/D converter
PD789446 with enhanced A/D converter
SIO, 8-bit A/D converter, and resistance division type LCD (28 × 4)
SIO, 8-bit A/D converter, and on-chip voltage booster type LCD (15 × 4)
PD789407A with enhanced A/D converter
SIO, 8-bit A/D converter, and on-chip voltage booster type LCD (5 × 4)
RC oscillation version of the PD789306
SIO and on-chip voltage booster type LCD (24 × 4)
64-pin
64-pin
64-pin
64-pin
64-pin
64-pin
PD789146
PD789156
44-pin
Small-scale package, general-purpose applications and A/D converter
44-pin
30-pin
30-pin
30-pin
30-pin
PD789124A
PD789134A
PD789177
PD789167
30-pin
30-pin
PD789104A
PD789114A
PD789167 with enhanced A/D converter
PD789104A with enhanced timer
PD789124A with enhanced A/D converter
RC oscillation version of the PD789104A
PD789104A with enhanced A/D converter
PD789026 with added A/D converter and multiplier
PD789104A with added EEPROM
TM
PD789146 with enhanced A/D converter
PD789177Y
PD789167Y
Y Subseries products support SMB.
Dot LCD drive
20-pin PD789860
PD789840
44-pin
44-pin PD789800
20-pin PD789861
For keyless entry, on-chip POC and key return circuit
For keypad, on-chip POC
For PC keyboard, on-chip USB function
RC oscillation version of the PD789860
52-pin
52-pin
SIO and resistance division type LCD
8-bit A/D converter and on-chip voltage booster type LCD
88-pin PD789830
PD789835
144-pin
Segments: 40, commons: 16
Segment/common outputs: 96
42-/44-pin
44-pin PD789046
PD789088
PD789026
30-pin PD789026 with enhanced timer
VFD drive
52-pin PD789871 Total display outputs: 25
SIO, 10-bit A/D converter, and on-chip voltage booster type LCD (28 × 4)
80-pin
SIO, 8-bit A/D converter, and resistance division type LCD (28 × 4)
80-pin
PD78980364-pin For PC keyboard, on-chip USB HUB function
µµ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µµ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
PD789477
µ
µ
µ
µ
µ
µ
30-pin
µ
PD789074 with enhanced timer and increased ROM and RAM capacity
µ
PD789488
µ
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS
4
The major functional differences among the subseries are listed below.
Timer VDD
Function
Subseries Name
ROM
Capacity
(Bytes)
8-Bit 16-Bit Watch WDT
8-Bit
A/D
10-Bit
A/D
Serial
Interface
I/O
MIN.
Value
Remarks
µ
PD789046 16 K 1 ch
µ
PD789026 4 K to 16 K
1 ch 34
µ
PD789088 16 K to 32 K 3 ch
µ
PD789074 2 K to 8 K 1 ch
1 ch
24
Small-scale
package,
general-
purpose
applications
µ
PD789014 2 K to 4 K 2 ch −
−
1 ch −−1 ch (UART:
1 ch)
22
1.8 V −
µ
PD789177 −8 ch
µ
PD789167
16 K to 24 K 3 ch 1 ch
8 ch −
31 −
µ
PD789156 −4 ch
µ
PD789146
8 K to 16 K
4 ch −
On-chip
EEPROM
µ
PD789134A −4 ch
µ
PD789124A 4 ch −
RC-
oscillation
version
µ
PD789114A −4 ch
Small-scale
package,
general-
purpose
applications
and A/D
converter
µ
PD789104A
2 K to 8 K
1 ch
1 ch
−
1 ch
4 ch −
1 ch (UART:
1 ch)
20
1.8 V
−
Inverter
control
µ
PD789842 8 K to 16 K 3 ch Note 1 ch 1 ch 8 ch −1 ch (UART:
1 ch)
30 4.0 V −
VFD drive
µ
PD789871 4 K to 8 K 3 ch –1 ch 1 ch ––1 ch 33 2.7 V –
µ
PD789488 32 K –8 ch
µ
PD789477 24 K 8 ch −
2 ch (UART:
1 ch)
45
µ
PD789417A −7 ch
µ
PD789407A
12 K to
24 K
3 ch
7 ch −
43
µ
PD789456 –6 ch
µ
PD789446 6 ch –
30
µ
PD789436 –6 ch
µ
PD789426
12 K to
16 K
6 ch
1 ch (UART:
1 ch)
40
−
µ
PD789316 RC-
oscillation
version
µ
PD789306
8 K to 16 K
1 ch
–2 ch (UART:
1 ch)
23
µ
PD789427 1 ch –18
LCD drive
µ
PD789327
4 K to 24 K
2 ch
–
1 ch 1 ch
–
–
1 ch 21
1.8 V
–
µ
PD789835 24 K to
60 K
6 ch –3 ch 28 1.8 V
Dot LCD
drive
µ
PD789830 24 K 1 ch 1 ch
1 ch 1 ch
–
–1 ch (UART:
1 ch)
30 2.7 V
−
µ
PD789803 8 K to 16 K 41 3.6 V
µ
PD789800
–2 ch
(USB: 1 ch) 31 4.0 V
µ
PD789840
8 K
4 ch 1 ch 29 2.8 V
−
µ
PD789861 RC-
oscillation
version,
on-chip
EEPROM
ASSP
µ
PD789860
4 K
2 ch –−1 ch
−
–
–14 1.8 V
On-chip
EEPROM
Note 10-bit timer: 1 channel
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS 5
OVERVIEW OF FUNCTIONS
Item
µ
PD78F9436
µ
PD78F9456
Flash memory 16 KB
High-speed RAM 512 bytes
Internal
memory
LCD display RAM 5 × 4 bits 15 × 4 bits
Minimum instruction execution time 0.4
µ
s/1.6
µ
s (@ 5.0 MHz operation with main system clock)
122
µ
s (@ 32.768 kHz operation with subsystem clock)
General-purpose registers 8 bits × 8 registers
Instruction set • 16-bit operation
• Bit manipulation (set, reset, test)
I/O ports Total: 40
• CMOS I/O: 30
• CMOS input: 6
• N-ch open drain: 4
Total: 30
• CMOS I/O: 20
• CMOS input: 6
• N-ch open drain: 4
Timers • 16-bit timer: 1 channel
• 8-bit timer: 2 channels
• Watch timer: 1 channel
• Watchdog timer: 1 channel
A/D converter 10-bit resolution × 6 channels
Serial interface • Switchable between 3-wire serial I/O mode and UART mode: 1 channel
LCD controller/driver • Segment signal outputs: 5 (max.)
• Common signal outputs: 4 (max.)
• Segment signal outputs: 15 (max.)
• Common signal outputs: 4 (max.)
Maskable Internal: 9, external: 5Vectored interrupt
sources Non-maskable Internal: 1
Power supply voltage VDD = 1.8 to 5.5 V
Operating ambient temperature TA = –40 to +85°C
Package 64-pin plastic TQFP (12 × 12)
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS
6
CONTENTS
1. PIN CONFIGURATION (Top View) ...................................................................................................................... 7
1.1 Pin Configuration of the
µ
µµ
µ
PD78F9436 (Top View) ................................................................................. 7
1.2 Pin Configuration of the
µ
µµ
µ
PD78F9456 (Top View) ................................................................................. 8
2. BLOCK DIAGRAM.............................................................................................................................................. 10
3. PIN FUNCTIONS................................................................................................................................................. 11
3.1 Port Pins.................................................................................................................................................. 11
3.2 Non-Port Pins ......................................................................................................................................... 12
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins ...................................................... 13
4. MEMORY SPACE ............................................................................................................................................... 15
5. FLASH MEMORY PROGRAMMING................................................................................................................... 16
5.1 Selecting Communication Mode ........................................................................................................... 16
5.2 Function of Flash Memory Programming............................................................................................. 17
5.3 Connecting Flashpro III.......................................................................................................................... 17
5.4 Example of Settings for Flashpro III (PG-FP3) ..................................................................................... 19
6. OVERVIEW OF INSTRUCTION SET .................................................................................................................. 20
6.1 Conventions............................................................................................................................................ 20
6.2 List of Operations................................................................................................................................... 22
7. ELECTRICAL SPECIFICATIONS ....................................................................................................................... 27
8. CHARACTERISTICS CURVES OF LCD CONTROLLER/DRIVER (REFRENCE VALUES).............................. 42
9. PACKAGE DRAWINGS ...................................................................................................................................... 44
10. RECOMMENDED SOLDERING CONDITIONS .................................................................................................. 45
APPENDIX A. DIFFERENCES BETWEEN
µ
µµ
µ
PD78F9436, 78F9456 AND MASK ROM VERSIONS ................ 46
APPENDIX B. DEVELOPMENT TOOLS................................................................................................................... 47
APPENDIX C. RELATED DOCUMENTS .................................................................................................................. 49
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS 7
1. PIN CONFIGURATION (TOP VIEW)
1.1 Pin Configuration of the
µ
µµ
µ
PD78F9436 (Top View)
64-pin plastic TQFP (12 ×
××
× 12)
µ
PD78F9436GK-9ET
Cautions 1. Connect the VPP pin directly to VSS.
2. Connect the AVDD pin to VDD.
3. Connect the AVSS pin to VSS.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P50
P51
P52
P53
V
PP
XT1
XT2
VDD
VSS
X1
X2
RESET
P00/KR0
P01/KR1
P02/KR2
P03/KR3 32
CAPH
CAPL
VLC0
VLC1
VLC2
COM0
COM1
COM2
COM3
S0
S1
S2
S3
S4
P90
P91
P62/ANI2
P63/ANI3
P64/ANI4
P65/ANI5
AVDD
P72
P71
P70
P81
P80
P97
P96
P95
P94
P93
P92
P20
P21/BZO90
P22/SS20
P23/SCK20/ASCK20
P24/SO20/TxD20
P25/SI20/RxD20
P26/TO90
P30/INTP0/CPT90
P31/INTP1/TO50/TMI60
P32/INTP2/TO60
P33/INTP3/TO61
P10
P11
AVSS
P60/ANI0
P61/ANI1
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS
8
1.2 Pin Configuration of the
µ
µµ
µ
PD78F9456 (Top View)
64-pin plastic TQFP (12 ×
××
× 12)
µ
PD78F9456-9ET
Cautions 1. Connect the VPP pin directly to VSS.
2. Connect the AVDD pin to VDD.
3. Connect the AVSS pin to VSS.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P50
P51
P52
P53
V
PP
XT1
XT2
V
DD
V
SS
X1
X2
RESET
P00/KR0
P01/KR1
P02/KR2
P03/KR3 32
CAPH
CAPL
V
LC0
V
LC1
V
LC2
COM0
COM1
COM2
COM3
S0
S1
S2
S3
S4
S5
S6
P62/ANI2
P63/ANI3
P64/ANI4
P65/ANI5
AV
DD
P72
P71
P70
S14
S13
S12
S11
S10
S9
S8
S7
P20
P21/BZO90
P22/SS20
P23/SCK20/ASCK20
P24/SO20/TxD20
P25/SI20/RxD20
P26/TO90
P30/INTP0/CPT90
P31/INTP1/TO50/TMI60
P32/INTP2/TO60
P33/INTP3/TO61
P10
P11
AV
SS
P60/ANI0
P61/ANI1
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS 9
ANI0 to ANI5: Analog input P90 to P97Note:Port 9
ASCK20: Asynchronous serial input RESET: Reset
AVDD: Analog power supply RxD20: Receive data
AVSS: Analog ground SS20: Serial chip select
BZO90: Buzzer output S0 to S14: Segment output
CAPH, CAPL: LCD power supply capacitance control SCK20: Serial clock
COM0 to COM3: Common output SI20: Serial input
CPT90: Capture trigger input SO20: Serial output
INTP0 to INTP3: External interrupt input TMI60: Timer input
KR0 to KR3: Key return TO90, TO50, TO60,
P00 to P03: Port 0 TO61: Timer output
P10, P11: Port 1 TxD20: Transmit data
P20 to P26: Port 2 VDD: Power supply
P30 to P33: Port 3 VLC0 to VLC2: LCD power supply
P50 to P53: Port 5 VPP: Programming power supply
P60 to P63: Port 6 VSS: Ground
P70 to P72: Port 7 X1, X2: Crystal (Main system clock)
P80 to P81Note: Port 8 XT1, XT2: Crystal (Subsystem clock)
Note
µ
PD78F9436 only
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS
10
2. BLOCK DIAGRAM
Note
µ
PD78F9436 only
Remark Descriptions in parentheses are for the
µ
PD78F9456.
VDD VSS VPP
78K/0S
CPU core
Flash
memory
TO50/TMI60/P31
8-bit
timer 50
P00 to P03
Port 0
P10, P11
Port 1
P20 to P26
Port 2
P30 to P33
Port 3
TMI60/TO50/P31
16-bit timer 90
Watch timer
Watchdog timer
TO90/P26
S0 to S4 (S0 to S14)
COM0 to COM3
RAM
RAM
space
for LCD
data
8-bit
timer/event
counter 60
Cascaded
16-bit
timer/
event
counter
TO60/P32
CPT90/P30
VLC0 to VLC2
CAPH
CAPL
LCD
controller driver
P50 to P53
Port 5
System control
RESET
X1
X2
XT1
XT2
Interrupt control
INTP0/P30
INTP1/P31
INTP2/P32
INTP3/P33
KR0/P00 to
KR3/P03
TO61/P33
BZO90/P21
Serial interface 20
SCK20/ASCK20/P23
SI20/RxD20/P25
SO20/TxD20/P24
SS20/P22
A/D converter
ANI0/P60 to
ANI5/P65
AVSS
AVDD
P70 to P72
Port 7
P60 to P65
Port 6
P80, P81Note
Port 8Note
P90 to P97Note
Port 9Note
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS 11
3. PIN FUNCTIONS
3.1 Port Pins
Pin Name I/O Function After Reset Alternate Function
P00 to P03 I/O Port 0.
4-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, use of an on-chip pull-up resistor
can be specified by a software setting.
Input KR0 to KR3
P10, P11 I/O Port 1.
2-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, use of an on-chip pull-up resistor
can be specified by a software setting.
Input —
P20 —
P21 BZO90
P22 SS20
P23 SCK20/ASCK20
P24 SO20/TxD20
P25 SI20/RxD20
P26
I/O Port 2.
7-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, use of an on-chip pull-up resistor
can be specified by a software setting.
Input
TO90
P30 INTP0/CPT90
P31 INTP1/TO50/TMI60
P32 INTP2/TO60
P33
I/O Port 3.
4-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, use of an on-chip pull-up resistor
can be specified by a software setting.
Input
INTP3/TO61
P50 to P53 I/O Port 5.
4-bit I/O port.
Input/output can be specified in 1-bit units.
Input —
P60 to P65 Input Port 6.
6-bit input port.
Input ANI0 to ANI5
P70 to P72 I/O Port 7.
3-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, use of an on-chip pull-up resistor
can be specified by a software setting.
Input —
P80, P81Note I/O Port 8.
2-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, use of an on-chip pull-up resistor
can be specified by a software setting.
Input —
P90 to P97Note I/O Port 9.
8-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, use of an on-chip pull-up resistor
can be specified by a software setting.
Input —
Note
µ
PD78F9436 only
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS
12
3.2 Non-Port Pins
Pin Name I/O Function After Reset Alternate Function
INTP0 P30/CPT90
INTP1 P31/TO50/TMI60
INTP2 P32/TO60
INTP3
Input External interrupt input for which the valid edge (rising edge,
falling edge, or both rising and falling edges) can be specified
Input
P33/TO61
KR0 to KR3 Input Key return signal detection Input P00 to P03
SS20 Input Serial interface (SIO20) chip select Input P22
SCK20 I/O Serial interface (SIO20) serial clock input/output Input P23/ASCK20
SI20 Input SIO20 serial interface serial data input Input P25/RxD20
SO20 Output SIO20 serial interface serial data output Input P24/TxD20
ASCK20 I/O Asynchronous serial interface serial clock input Input P23/SCK20
RxD20 Input Asynchronous serial interface serial data input Input P25/SI20
TxD20 Output Asynchronous serial interface serial data output Input P24/SO20
TO90 Output 16-bit timer (TM90) output Input P26
CPT90 Input Capture edge input Input P30/INTP0
TO50 Output 8-bit timer (TM50) output Input P31/INTP1/TMI60
TO60 Output 8-bit timer (TM60) output Input P32/INTP2
TO61 Output 8-bit timer (TM60) output Input P33/INTP3
TMI60 Input External count clock input to 8-bit timer (TM60) Input P31/INTP1/TO50
ANI0 to ANI5 Input A/D converter analog inputs Input P60 to P65
S0 to S4 Output Segment signal outputs for LCD controller/driver Output —
S5 to S14Note Output Segment signal outputs for LCD controller/driver Output —
COM0 to COM3 Output Common signal outputs for LCD controller/driver Output —
VLC0 to VLC2 — LCD drive voltage — —
CAPH — ——
CAPL —
Connection pin for LCD driver’s capacitor
——
X1 Input ——
X2 —
Connecting crystal resonator for main system clock oscillation
——
XT1 Input ——
XT2 —
Connecting crystal resonator for subsystem clock oscillation
——
RESET Input System reset input Input —
VDD — Positive power supply for ports — —
VSS — Ground potential — —
AVDD — A/D converter analog potential — —
AVSS — A/D converter ground potential — —
VPP — Flash memory programming mode setting. High-voltage
application for program write/verify. In normal operation mode,
connect directly to VSS.
——
Note
µ
PD78F9456 only
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS 13
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1.
For the input/output circuit configuration of each type, refer to Figure 3-1.
Table 3-1. Types of Pin Input/Output Circuits and Recommended Connection of Unused Pins
Pin Name I/O
Circuit Type
I/O Recommended Connection of Unused Pins
P00 to P03 8-A
P10, P11 5-A
P20
P21/BZO90
P22/SS20
P23/SCK20/ASCK20
P24/SO20/TxD20
P25/SI20/RxD20
P26/TO90
Input: Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P30/INTP0/CPT90
P31/INTP1/TO50/
TMI60
P32/INTP2/TO60
P33/INTP3/TO61
8-A
Input: Independently connect to VSS via a resistor.
Output: Leave open.
P50 to P53 13-V
I/O
Input: Independently connect to VDD via a resistor.
Output: Leave open.
P60/ANI0 to P65/ANI5 9-C Input Connect directly to VDD or VSS.
P70 to P72
P80, P81Note 1
P90 and P97Note 1
5-A I/O Input: Independently connect to VDD or VSS via a resistor.
Output: Leave open.
S0 to S4
S5 to S14Note 2
17 Output
COM0 to COM3 18
VLC0 to VLC2
CAPH, CAPL
—
Leave open.
XT1 Input Connect to VSS.
XT2 Leave open.
AVSS Connect to VSS.
AVDD
—
—
Connect to VDD.
RESET 2 Input —
VPP — — Connect directly to VSS.
Notes 1.
µ
PD78F9436 only
2.
µ
PD78F9456 only
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS
14
Figure 3-1. Pin Input/Output Circuits
Type 2 Type 9-C
Schmitt-triggered input with hysteresis characteristics
IN
IN
Comparator
+
VREF
(Threshold voltage)
AVSS
P-ch
N-ch
Input
enable
-
Type 5-A Type 13-V
Pull-up
enable
V
DD
P-ch
P-ch
IN/OUT
Data
Output
disable
Input
enable
V
DD
N-ch
V
SS
V
SS
Output data
Output disable
IN/OUT
N-ch
Middle-voltage input buffer
Input enable
Type 8-A Type 17
Pull-up
enable
VDD
P-ch
Data
VDD
P-ch
Output
disable
IN/OUT
N-ch
VSS
P-ch
N-ch
P-ch
N-ch
N-ch
N-ch
data OUT
V
LC0
V
LC1
SEG
V
LC2
P-ch
P-ch
Type 18
P-ch
N-ch
P-ch
N-ch
P-ch
N-ch P-ch
N-ch
P-ch N-ch
VLC1
COM
data
VLC0
VLC2
OUT
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS 15
4. MEMORY SPACE
Figure 4-1 shows the memory map.
Figure 4-1. Memory Map
Note The capacity of the LCD display RAM varies depending on the product (see following table).
Part Number Last Address of LCD display RAM mmmmH
µ
PD78F9436 FA04H
µ
PD78F9456 FA0EH
4000H
3FFFH
Special function registers
(SFRs)
256 × 8 bits
Internal high-speed RAM
512 × 8 bits
LCD display RAM
Note
FFFFH
FF00H
FEFFH
FD00H
FCFFH
0000H
Program memory
space
Data memory
space 3FFFH
0000H
Program area
0080H
007FH
Program area
0040H
003FH
CALLT table area
Reserved
0022H
0021H
Vector table area
Flash memory
16384 × 8 bits
mmmm + 1H
mmmmH
FA00H
F9FFH
Reserved
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS
16
5. FLASH MEMORY PROGRAMMING
The program memory that is incorporated in the
µ
PD78F9436 and 78F9456 is flash memory.
With flash memory, it is possible to write programs on-board. Writing is performed by connecting a dedicated flash
programmer (Flashpro III (Part No. FL-PR3, PG-FP3)) to the host machine and the target system.
Remark FL-PR3 is a product of Naito Densei Machida Mfg. Co., Ltd.
5.1 Selecting Communication Mode
Writing to flash memory is performed using the Flashpro III in a serial communication mode. Select one of the
communication modes in Table 5-1. The selection of the communication mode is made by using the format shown in
Figure 5-1. Each communication mode is selected using the number of VPP pulses shown in Table 5-1.
Table 5-1. List of Communication Mode
Communication Mode PinsNote VPP Pulses
SCK20/P23
SO20/P24
SI20/P25
0
3-wire serial I/O
P00/KR0 (serial clock input)
P01/KR1 (serial data output)
P02/KR2 (serial data input)
1
UART TxD20/P24
RxD20/P25
8
Note Shifting to the flash memory programming mode sets all pins not used for flash memory programming to the
same state as immediately after reset. If the external device connected to the port does not acknowledge
the port state immediately after reset, handling such as connecting to VDD or VSS via a resistor or connecting
to is required.
Caution Be sure to select a communication mode using the number of VPP pulses shown in
Table 5-1.
Figure 5-1. Format of Communication Mode Selection
12 n
V
DD
V
SS
V
DD
V
PP
RESET
10 V
V
SS
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS 17
5.2 Function of Flash Memory Programming
Operations such as writing to flash memory are performed by various command/data transmission and reception
operations according to the selected communication mode. Table 5-2 shows the major functions of flash memory
programming.
Table 5-2. Major Function of Flash Memory Programming
Function Description
Batch erase Deletes the entire memory contents.
Batch blank check Checks the deletion status of the entire memory.
Data write Performs a write operation to the flash memory based on the write start address and the number of
data to be written (number of bytes).
Batch verify Compares the entire memory contents with the input data.
5.3 Connecting Flashpro III
The connection of the Flashpro III and the
µ
PD78F9436 and 78F9456 differs according to the communication
mode (3-wire serial I/O or UART). The connections for each communication mode are shown in Figures 5-2 and 5-3,
respectively.
Figure 5-2. Connection Example of Flashpro III When Using 3-Wire Serial I/O Mode (1/2)
Note n = 1, 2
V
PP
n
Note
V
DD
RESET
CLK
SCK
SO
SI
GND
V
PP
V
DD
RESET
X1
SCK20
SI20
SO20
V
SS
Flashpro III PD78F9436, 78F9456
µ
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS
18
Figure 5-2. Connection Example of Flashpro III When Using 3-Wire Serial I/O Mode (2/2)
Note n = 1, 2
Figure 5-3. Connection Example of Flashpro III When Using UART Mode
Note n = 1, 2
V
PP
n
Note
V
DD
RESET
CLK
SO
SI
GND
V
PP
V
DD
RESET
X1
RxD20
TxD20
V
SS
Flashpro III PD78F9436, 78F9456
µ
V
PP
n
Note
V
DD
RESET
CLK
SCK
SO
SI
GND
V
PP
V
DD
RESET
X1
P00/KR0 (Serial clock)
P02/KR2 (Serial input)
P01/KR1 (Serial output)
V
SS
Flashpro III PD78F9436, 78F9456
µ
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS 19
5.4 Example of Settings for Flashpro III (PG-FP3)
When writing to flash memory using Flashpro III (PG-FP3), make the following settings.
<1> Load a parameter file.
<2> Select the mode of serial communication and serial clock with a type command.
<3> Make the settings according to the example of settings for PG-FP3 shown below.
Table 5-3. Example of Settings for PG-FP3
Communication Mode Example of Settings for PG-FP3 VPP Pulse NumberNote 1
COMM PORT SIO-ch0
On Target BoardCPU CLK
In Flashpro
On Target Board 4.1943 MHz
SIO CLK 1.0 MHz
In Flashpro 4.0 MHz
SIO CLK 1.0 MHz
0
COMM PORT SIO-ch1
On Target BoardCPU CLK
In Flashpro
On Target Board 4.1943 MHz
SIO CLK 1.0 MHz
In Flashpro 4.0 MHz
3-wire serial I/O
SIO CLK 1.0 MHz
1
COMM PORT UART-ch0
CPU CLK On Target Board
On Target Board 4.1943 MHz
UART
UART BPS 9600 bpsNote 2
8
Notes 1. This is the number of VPP pulses that are supplied by the Flashpro III at serial communication
initialization. The pins that will be used for communication are determined according to this number.
2. Select one of 9600 bps, 19200 bps, 38400 bps, or 76800 bps.
Remark COMM PORT: Serial port selection
SIO CLK: Serial clock frequency selection
CPU CLK: Input CPU clock source selection
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS
20
6. OVERVIEW OF INSTRUCTION SET
This section lists the instruction set for the
µ
PD78F9436 and 78F9456.
6.1 Conventions
6.1.1 Operand expressions and description methods
Operands are described in the “Operand” column of each instruction in accordance with the description method of
the instruction operand expression (see the assembler specifications for details). When there are two or more
description methods, select one of them. Uppercase letters and symbols, #, !, $, and [ ] are key words and are
described as they are. The meaning of each symbol is described below.
•#: Immediate data specification •$: Relative address specification
•!: Absolute address specification •[ ]: Indirect address specification
For immediate data, enter an appropriate numeric value or a label. When using a label, be sure to enter the #, !, $
and [ ] symbols.
For operand register expressions, r and rp, either function names (X, A, C, etc.) or absolute names (names in
parenthesis in the table below, R0, R1, R2, etc.) can be used for the description.
Table 6-1. Operand Expressions and Description Methods
Expression Description Method
r
rp
sfr
X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)
AX (RP0), BC (RP1), DE (RP2), HL (RP3)
Special function register symbol
saddr
saddrp
FE20H to FF1FH: immediate data or label
FE20H to FF1FH: immediate data or label (even addresses only)
addr16
addr5
0000H to FFFFH: immediate data or label
(even addresses only for 16-bit data transfer instruction)
0040H to 007FH: immediate data or label (even addresses only)
word
byte
bit
16-bit immediate data or label
8-bit immediate data or label
3-bit immediate data or label
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS 21
6.1.2 Description of “Operation” column
A: A register; 8-bit accumulator
X: X register
B: B register
C: C register
D: D register
E: E register
H: H register
L: L register
AX: AX register pair; 16-bit accumulator
BC: BC register pair
DE: DE register pair
HL: HL register pair
PC: Program counter
SP: Stack pointer
PSW: Program status word
CY: Carry flag
AC: Auxiliary carry flag
Z: Zero flag
IE: Interrupt request enable flag
NMIS: Flag indicating non-maskable interrupt servicing in progress
( ): Memory contents indicated by address or register contents in parenthesis
XH, XL: Higher 8 bits and lower 8 bits of 16-bit register
∧: Logical product (AND)
∨: Logical sum (OR)
∨: Exclusive logical sum (exclusive OR)
: Inverted data
addr16: 16-bit immediate data or label
jdisp8: Signed 8-bit data (displacement value)
6.1.3 Description of “Flag” column
(Blank): Unchanged
0: Cleared to 0
1: Set to 1
×: Set/cleared according to the result
R: Previously saved value is restored
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS
22
6.2 List of Operations
FlagMnemonic Operand Bytes Clocks Operation
ZACCY
r, #byte 3 6 r ← byte
saddr, #byte 3 6 (saddr) ← byte
sfr, #byte 3 6 sfr ← byte
A, r Note 1 24A ← r
r, A Note 1 24r ← A
A, saddr 2 4 A ← (saddr)
saddr, A 2 4 (saddr) ← A
A, sfr 2 4 A ← sfr
sfr, A 2 4 sfr ← A
A, !addr16 3 8 A ← (addr16)
!addr16, A 3 8 (addr16) ← A
PSW, #byte 3 6 PSW ← byte ×××
A, PSW 2 4 A ← PSW
PSW, A 2 4 PSW ← A ×××
A, [DE] 1 6 A ← (DE)
[DE], A 1 6 (DE) ← A
A, [HL] 1 6 A ← (HL)
[HL], A 1 6 (HL) ← A
A, [HL + byte] 2 6 A ← (HL + byte)
MOV
[HL + byte], A 2 6 (HL + byte) ← A
A, X 1 4 A ↔ X
A, r Note 2 26A ↔ r
A, saddr 2 6 A ↔ (saddr)
A, sfr 2 6 A ↔ (sfr)
A, [DE] 1 8 A ↔ (DE)
A, [HL] 1 8 A ↔ (HL)
XCH
A, [HL + byte] 2 8 A ↔ (HL + byte)
rp, #word 3 6 rp ← word
AX, saddrp 2 6 AX ← (saddrp)
saddrp, AX 2 8 (saddrp) ← AX
AX, rp Note 3 14AX ← rp
MOVW
rp, AX Note 3 14rp ← AX
XCHW AX, rp Note 3 18AX ↔ rp
Notes 1. Except r = A
2. Except r = A, X
3. Only when rp = BC, DE, HL
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected via the processor clock control register
(PCC).
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS 23
FlagMnemonic Operand Bytes Clocks Operation
ZACCY
A, #byte 2 4 A, CY ← A + byte ×××
saddr, #byte 3 6 (saddr), CY ← (saddr) + byte ×××
A, r 2 4 A, CY ← A + r ×××
A, saddr 2 4 A, CY ← A + (saddr) ×××
A, !addr16 3 8 A, CY ← A + (addr16) ×××
A, [HL] 1 6 A, CY ← A + (HL) ×××
ADD
A, [HL + byte] 2 6 A, CY ← A + (HL + byte) ×××
A, #byte 2 4 A, CY ← A + byte + CY ×××
saddr, #byte 3 6 (saddr), CY ← (saddr) + byte + CY ×××
A, r 2 4 A, CY ← A + r + CY ×××
A, saddr 2 4 A, CY ← A + (saddr) + CY ×××
A, !addr16 3 8 A, CY ← A + (addr16) + CY ×××
A, [HL] 1 6 A, CY ← A + (HL) + CY ×××
ADDC
A, [HL + byte] 2 6 A, CY ← A + (HL + byte) + CY ×××
A, #byte 2 4 A, CY ← A – byte ×××
saddr, #byte 3 6 (saddr), CY ← (saddr) – byte ×××
A, r 2 4 A, CY ← A – r ×××
A, saddr 2 4 A, CY ← A – (saddr) ×××
A, !addr16 3 8 A, CY ← A – (addr16) ×××
A, [HL] 1 6 A, CY ← A – (HL) ×××
SUB
A, [HL + byte] 2 6 A, CY ← A – (HL + byte) ×××
A, #byte 2 4 A, CY ← A – byte – CY ×××
saddr, #byte 3 6 (saddr), CY ← (saddr) – byte – CY ×××
A, r 2 4 A, CY ← A – r – CY ×××
A, saddr 2 4 A, CY ← A – (saddr) – CY ×××
A, !addr16 3 8 A, CY ← A – (addr16) – CY ×××
A, [HL] 1 6 A, CY ← A – (HL) – CY ×××
SUBC
A, [HL + byte] 2 6 A, CY ← A – (HL + byte) – CY ×××
A, #byte 2 4 A ← A ∧ byte ×
saddr, #byte 3 6 (saddr) ← (saddr) ∧ byte ×
A, r 2 4 A ← A ∧ r ×
A, saddr 2 4 A ← A ∧ (saddr) ×
A, !addr16 3 8 A ← A ∧ (addr16) ×
A, [HL] 1 6 A ← A ∧ (HL) ×
AND
A, [HL + byte] 2 6 A ← A ∧ (HL + byte) ×
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected via the processor clock control register
(PCC).
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS
24
FlagMnemonic Operand Bytes Clocks Operation
ZACCY
A, #byte 2 4 A ← A ∨ byte ×
saddr, #byte 3 6 (saddr) ← (saddr) ∨ byte ×
A, r 2 4 A ← A ∨ r ×
A, saddr 2 4 A ← A ∨ (saddr) ×
A, !addr16 3 8 A ← A ∨ (addr16) ×
A, [HL] 1 6 A ← A ∨ (HL) ×
OR
A, [HL + byte] 2 6 A ← A ∨ (HL + byte) ×
A, #byte 2 4 A ← A ∨ byte ×
saddr, #byte 3 6 (saddr) ← (saddr) ∨ byte ×
A, r 2 4 A ← A ∨ r ×
A, saddr 2 4 A ← A ∨ (saddr) ×
A, !addr16 3 8 A ← A ∨ (addr16) ×
A, [HL] 1 6 A ← A ∨ (HL) ×
XOR
A, [HL + byte] 2 6 A ← A ∨ (HL + byte) ×
A, #byte 2 4 A – byte ×××
saddr, #byte 3 6 (saddr) – byte ×××
A, r 2 4 A – r ×××
A, saddr 2 4 A – (saddr) ×××
A, !addr16 3 8 A – (addr16) ×××
A, [HL] 1 6 A – (HL) ×××
CMP
A, [HL + byte] 2 6 A – (HL + byte) ×××
ADDW AX, #word 3 6 AX, CY ← AX + word ×××
SUBW AX, #word 3 6 AX, CY ← AX – word ×××
CMPW AX, #word 3 6 AX – word ×××
r24r ← r + 1 ××INC
saddr 2 4 (saddr) ← (saddr) + 1 ××
r24r ← r – 1 ××DEC
saddr 2 4 (saddr) ← (saddr) – 1 ××
INCW rp 1 4 rp ← rp + 1
DECW rp 1 4 rp ← rp – 1
ROR A, 1 1 2 (CY, A7 ← A0, Am – 1 ← Am) × 1 time ×
ROL A, 1 1 2 (CY, A0 ← A7, Am + 1 ← Am) × 1 time ×
RORC A, 1 1 2 (CY ← A0, A7 ← CY, Am – 1 ← Am) × 1 time ×
ROLC A, 1 1 2 (CY ← A7, A0 ← CY, Am + 1 ← Am) × 1 time ×
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected via the processor clock control register
(PCC).
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS 25
FlagMnemonic Operand Bytes Clocks Operation
ZACCY
saddr. bit 3 6 (saddr. bit) ← 1
sfr. bit 3 6 sfr. bit ← 1
A. bit 2 4 A. bit ← 1
PSW. bit 3 6 PSW. bit ← 1 ×××
SET1
[HL]. bit 2 10 (HL). bit ← 1
saddr. bit 3 6 (saddr. bit) ← 0
sfr. bit 3 6 sfr. bit ← 0
A. bit 2 4 A. bit ← 0
PSW. bit 3 6 PSW. bit ← 0 ×××
CLR1
[HL]. bit 2 10 (HL). bit ← 0
SET1 CY 1 2 CY ← 11
CLR1 CY 1 2 CY ← 00
NOT1 CY 1 2 CY ← CY ×
CALL !addr16 3 6 (SP – 1) ← (PC + 3)H, (SP – 2) ← (PC + 3)L,
PC ← addr16, SP ← SP – 2
CALLT [addr5] 1 8 (SP – 1) ← (PC + 1)H, (SP – 2) ← (PC + 1)L,
PCH ← (00000000, addr5 + 1),
PCL ← (00000000, addr5),
SP ← SP – 2
RET 1 6 PCH ← (SP + 1), PCL ← (SP),
SP ← SP + 2
RETI 1 8 PCH ← (SP + 1), PCL ← (SP),
PSW ← (SP + 2), SP ← SP + 3,
NMIS ← 0
RRR
PSW 1 2 (SP – 1) ← PSW, SP ← SP – 1PUSH
rp 1 4 (SP – 1) ← rpH, (SP – 2) ← rpL,
SP ← SP – 2
PSW 1 4 PSW ← (SP), SP ← SP + 1 R R RPOP
rp 1 6 rpH ← (SP + 1), rpL ← (SP),
SP ← SP + 2
SP, AX 2 8 SP ← AXMOVW
AX, SP 2 6 AX ← SP
!addr16 3 6 PC ← addr16
$addr16 2 6 PC ← PC + 2 + jdisp8
BR
AX 1 6 PCH ← A, PCL ← X
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected via the processor clock control register
(PCC).
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS
26
FlagMnemonic Operand Bytes Clocks Operation
ZACCY
BC $addr16 2 6 PC ← PC + 2 + jdisp8 if CY = 1
BNC $addr16 2 6 PC ← PC + 2 + jdisp8 if CY = 0
BZ $addr16 2 6 PC ← PC + 2 + jdisp8 if Z = 1
BNZ $addr16 2 6 PC ← PC + 2 + jdisp8 if Z = 0
saddr. bit, $addr16 4 10 PC ← PC + 4 + jdisp8
if (saddr. bit) = 1
sfr. bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if sfr. bit = 1
A. bit, $addr16 3 8 PC ← PC + 3 + jdisp8 if A. bit = 1
BT
PSW. bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if PSW. bit = 1
saddr. bit, $addr16 4 10 PC ← PC + 4 + jdisp8
if (saddr. bit) = 0
sfr. bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if sfr. bit = 0
A. bit, $addr16 3 8 PC ← PC + 3 + jdisp8 if A. bit = 0
BF
PSW. bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if PSW. bit = 0
B, $addr16 2 6 B ← B – 1, then
PC ← PC + 2 + jdisp8 if B ≠ 0
C, $addr16 2 6 C ← C – 1, then
PC ← PC + 2 + jdisp8 if C ≠ 0
DBNZ
saddr, $addr16 3 8 (saddr) ← (saddr) – 1, then
PC ← PC + 3 + jdisp8 if (saddr) ≠ 0
NOP 1 2 No Operation
EI 3 6 IE ← 1 (Enable Interrupt)
DI 3 6 IE ← 0 (Disable Interrupt)
HALT 1 2 Set HALT Mode
STOP 1 2 Set STOP Mode
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected via the processor clock control register
(PCC).
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS 27
7. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°
°°
°C)
Parameter Symbol Conditions Ratings Unit
VDD
AVDD
–0.3 to +6.5 VPower supply voltage
VPP
VDD = AVDD
–0.3 to +10.5 V
VI1 P00 to P03, P10, P11, P20 to P26, P30 to
P33, P60 to P65, P70 to P72, P80Note 1,
P81Note 1, P90 to P97Note 1, X1, X2, XT1, XT2,
RESET
–0.3 to VDD + 0.3Note 2 VInput voltage
VI2 P50 to P53 N-ch open drain –0.3 to +13 V
Output voltage VO–0.3 to VDD + 0.3Note 2 V
Per pin –10 mAOutput current, high IOH
Total for all pins –30 mA
Per pin 30 mAOutput current, low IOL
Total for all pins 160 mA
In normal operation mode –40 to +85 °COperating ambient temperature TA
During flash memory programming 10 to 40 °C
Storage temperature Tstg –40 to +125 °C
Notes 1. For
µ
PD78F9436
2. 6.5 V or less
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions
that ensure that the absolute maximum ratings are not exceeded.
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port
pins.
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS
28
Main System Clock Oscillator Characteristics (TA = –40 to +85°
°°
°C, VDD = 1.8 to 5.5 V)
Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit
Oscillation frequency (fX)Note 1 1.0 5.0 MHzCeramic
resonator
X2X1V
PP
C2C1
Oscillation stabilization
timeNote 2
After VDD reaches
oscillation voltage
range MIN.
4ms
Oscillation frequency(fX)Note 1 1.0 5.0 MHz
VDD = 4.5 to 5.5 V 10 ms
Crystal
resonator
X2X1V
PP
C2C1
Oscillation stabilization
timeNote 2
30 ms
X1 input frequency (fX)Note 1 1.0 5.0 MHz
X1 X2
X1 input high-/low-level width
(tXH, tXL)
85 500 ns
X1 input frequency (fX)Note 1 VDD = 2.7 to 5.5 V 1.0 5.0 MHz
External
clock
X1 X2
OPEN
X1 input high-/low-level width
(tXH, tXL)
VDD = 2.7 to 5.5 V 85 500 ns
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release.
Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the
broken lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. When the main system clock is stopped and the device is operating on the subsystem clock,
wait until the oscillation stabilization time has been secured by the program before switching
back to the main system clock.
Remark For the resonator selection and oscillator constant, customers are required to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS 29
Subsystem Clock Oscillator Characteristics (TA = –40 to +85°
°°
°C, VDD = 1.8 to 5.5 V)
Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit
Oscillation frequency
(fXT)Note 1
32 32.768 35 kHz
VDD = 4.5 to 5.5 V 1.2 2
Crystal
resonator
XT2XT1
VPP
C4
C3
R
Oscillation stabilization
timeNote 2
10
s
XT1 input frequency
(fXT)Note 1
32 35 kHzExternal
clock
XT1 XT2
XT1 input high-/low-level
width (tXTH, tXTL)
14.3 15.6
µ
s
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after VDD reaches oscillation voltage range MIN.
Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the
broken lines in the above figure to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current
consumption, and is more prone to malfunction due to noise than the main system clock
oscillator. Particular care is therefore required with the wiring method when the subsystem
clock is used.
Remark For the resonator selection and oscillator constant, customers are required to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS
30
DC Characteristics (TA = –40 to +85°
°°
°C, VDD = 1.8 to 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Per pin 10 mAOutput current, low IOL
All pins 80 mA
Per pin –1mAOutput current, high IOH
All pins –15 mA
VDD = 2.7 to 5.5 V 0.7VDD VDD VVIH1 P10, P11, P60 to P65,
P70 to P72, P80Note,
P81Note, P90 to P97Note 0.9VDD VDD V
VDD = 2.7 to 5.5 V 0.7VDD 12 VVIH2 P50 to
P53
N-ch open
drain 0.9VDD 12 V
VDD = 2.7 to 5.5 V 0.8VDD VDD VVIH3 RESET, P00 to P03,
P20 to P26, P30 to P33 0.9VDD VDD V
VDD = 4.5 to 5.5 V VDD – 0.5 VDD V
Input voltage, high
VIH4 X1, X2, XT1, XT2
VDD – 0.1 VDD V
VDD = 2.7 to 5.5 V 0 0.3VDD VVIL1 P10, P11, P60 to P65,
P70 to P72, P80Note,
P81Note, P90 to P97Note 00.1V
DD V
VDD = 2.7 to 5.5 V 0 0.3VDD VVIL2 P50 to P53
00.1V
DD V
VDD = 2.7 to 5.5 V 0 0.2VDD VVIL3 RESET, P00 to P03,
P20 to P26, P30 to P33 00.1V
DD V
VDD = 4.5 to 5.5 V 0 0.4 V
Input voltage, low
VIL4 X1, X2, XT1, XT2
00.1V
VDD = 4.5 to 5.5 V, IOH = –1 mA VDD – 1.0 VOutput voltage, high VOH
VDD = 1.8 to 5.5 V, IOH = –100
µ
AV
DD – 0.5 V
4.5 ≤ VDD ≤ 5.5 V,
IOL = 10 mA
1.0 V
VOL1 P00 to P03, P10, P11,
P20 to P26, P30 to P33,
P60 to P65, P70 to P72,
P80Note, P81Note, P90 to
P97Note, X1, X2, XT1, XT2
1.8 ≤ VDD < 4.5 V,
IOL = 400
µ
A
0.5 V
4.5 ≤ VDD < 5.5 V,
IOL = 10 mA
1.0 V
Output voltage, low
VOL2 P50 to P53
1.8 ≤ VDD < 4.5 V,
IOL = 1.6 mA
0.4 V
Note
µ
PD78F9436 only
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port
pins.
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS 31
DC Characteristics (TA = –40 to +85°
°°
°C, VDD = 1.8 to 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
ILIH1 P00 to P03, P10, P11,
P20 to P26, P30 to P33,
P60 to P65, P70 to P72,
P80Note 1, P81Note 1, P90 to
P97Note 1, RESET
3
µ
A
ILIH2
VI = VDD
X1, X2, XT1, XT2 20
µ
A
Input leakage current,
high
ILIH3 VI = 12 V P50 to P53
(N-ch open drain)
20
µ
A
ILIL1 P00 to P03, P10, P11,
P20 to P26, P30 to P33,
P60 to P65, P70 to P72,
P80Note 1, P81Note 1, P90 to
P97Note 1, RESET
–3
µ
A
ILIL2 X1, X2, XT1, XT2 –20
µ
A
Input leakage current,
low
ILIL3
VI = 0 V
P50 to P53
(N-ch open drain)
–3Note 2
µ
A
Output leakage current,
high
ILOH VO = VDD 3
µ
A
Output leakage current,
low
ILOL VO = 0 V –3
µ
A
Software pull-up
resistor
R1VI = 0 V P00 to P03, P10, P11,
P20 to P26, P30 to P33,
P70 to P72, P80Note 1,
P81Note 1, P90 to P97Note 1
50 100 200 kΩ
Notes 1.
µ
PD78F9436 only
2. If P50 to P53 have been set to input mode when a read instruction is executed to read from P50 to P53,
a low-level input leakage current of up to –30
µ
A flows during only one cycle. At all other times, the
maximum leakage current is –3
µ
A.
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port
pins.
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS
32
DC Characteristics (TA = –40 to +85°
°°
°C, VDD = 1.8 to 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 5.0 V ±10%Note 2 4.5 9 mA
VDD = 3.0 V ±10%Note 3 12mA
IDD1 5.0 MHz crystal oscillation
operation mode
(C1 = C2 = 22 pF)
VDD = 2.0 V ±10%Note 3 0.65 1.5 mA
VDD = 5.0 V ±10%Note 2 1.4 2 mA
VDD = 3.0 V ±10%Note 3 0.4 0.8 mA
IDD2 5.0 MHz crystal oscillation
HALT mode
(C1 = C2 = 22 pF)
VDD = 2.0 V ±10%Note 3 0.19 0.42 mA
VDD = 5.0 V ±10% 100 230
µ
A
VDD = 3.0 V ±10% 70 160
µ
A
IDD3 32.768 kHz crystal
oscillation operation
modeNote 4
(C3 = C4 = 22 pF, R1 =
220kΩ)
VDD = 2.0 V ±10% 58 120
µ
A
VDD = 5.0 V ±10% 25 65
µ
A
VDD = 3.0 V ±10% 7 29
µ
A
LCD not
operating
VDD = 2.0 V ±10% 4 20
µ
A
VDD = 5.0 V ±10% 28 70
µ
A
VDD = 3.0 V ±10% 9.6 34
µ
A
IDD4 32.768
kHz
crystal
oscillation
HALT
modeNote 4
LCD
operatingNote 5
VDD = 2.0 V ±10% 6 25
µ
A
VDD = 5.0 V ±10% 0.1 17
µ
A
VDD = 3.0 V ±10% 0.05 5.5
µ
A
IDD5 STOP modeNote 6
VDD = 2.0 V ±10% 0.05 3.5
µ
A
VDD = 5.0 V ±10%Note 2 5.2 10.8 mA
VDD = 3.0 V ±10%Note 3 1.4 3.8 mA
Power supply
currentNote 1
IDD6 5.0 MHz crystal oscillation
A/D operating modeNote 7
(C1 = C2 = 22 pF)
VDD = 2.0 V ±10%Note 3 1.0 2.9 mA
Notes 1. The port current (including the current that flows to the on-chip pull-up resistor) is not included.
2. High-speed mode operation (when the processor clock control register (PCC) is set to 00H)
3. Low-speed mode operation (when PCC is set to 02H)
4. When the main system clock is stopped
5. This is the current when the LCD controller/driver is operating (LCDON0 = 1, VAON0 = 1, LIPS0 = 1).
The power supply current when the LCD is not operating (LCDON0 = 0, VAON0 = 1, LIPS0 = 0) is
included in IDD2 (HALT mode).
6. When the LCD voltage amplifier is stopped (LCDON0 = 0, VAON0 = 0)
7. This is the total current that flows to VDD and AVDD.
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port
pins.
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS 33
AC Characteristics
(1) Basic operation (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 0.4 8.0
µ
sOperating with main
system clock 1.6 8.0
µ
s
Cycle time (minimum
instruction execution
time)
TCY
Operating with subsystem clock 114 122 125
µ
s
Capture input high-/low-
level width
tCPTH,
tCPTL
CPT90 10
µ
s
VDD = 2.7 to 5.5 V 0 4 MHzTMI60 input frequency fTMI
0 275 kHz
VDD = 2.7 to 5.5 V 0.1
µ
sTMI60 input high-/low-
level width
tTIMH,
tTIML 1.8
µ
s
Interrupt input high-
/low-level width
tINTH,
tINTL
INTP0 to INTP3 10
µ
s
Key return input low-
level width
tKRL KR0 to KR3 10
µ
s
RESET low-level width tRSL 10
µ
s
TCY vs. VDD (main system clock)
Power supply voltage V
DD
(V)
Cycle time T
CY
[ s]
µ
123456
0.1
0.4
1.0
10
60
8.0
Guaranteed
operation range
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS
34
(2) Serial interface 20 (SIO20) (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
(a) 3-wire serial I/O mode (internal clock output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 800 nsSCK20 cycle time tKCY1
3200 ns
VDD = 2.7 to 5.5 V tKCY1/2–50 nsSCK20 high-/low-level
width
tKH1,
tKL1 tKCY1/2–150 ns
VDD = 2.7 to 5.5 V 150 nsSI20 setup time
(to SCK20↑)
tSIK1
500 ns
VDD = 2.7 to 5.5 V 400 nsSI20 hold time
(from SCK20↑)
tSI1
600 ns
VDD = 2.7 to 5.5 V 0 250 nsDelay time from
SCK20↓ to SO20 output
tSO1 R = 1 kΩ, C = 100 pFNote
0 1000 ns
Note R and C are the load resistance and load capacitance of the SO20 output line.
(b) 3-wire serial I/O mode (external clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 800 nsSCK20 cycle time tKCY2
3200 ns
VDD = 2.7 to 5.5 V 400 nsSCK20 high-/low-level
width
tKH2,
tKL2 1600 ns
VDD = 2.7 to 5.5 V 100 nsSI20 setup time
(to SCK20↑)
tSIK2
150 ns
VDD = 2.7 to 5.5 V 400 nsSI20 hold time
(from SCK20↑)
tSI2
600 ns
VDD = 2.7 to 5.5 V 0 300 nsDelay time from
SCK20↓ to SO20 output
tSO2 R = 1 kΩ, C = 100 pFNote
0 1000 ns
VDD = 2.7 to 5.5 V 120 ns
SO20 setup time (with
SS20, to SCK20↓)
tKAS2
400 ns
VDD = 2.7 to 5.5 V 240 nsSO20 disable time (with
SS20, from SCK20↑)
tKDS2
800 ns
Note R and C are the load resistance and load capacitance of the SO20 output line.
(c) UART mode (dedicated baud rate generator output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 78125 bpsTransfer rate
19531 bps
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS 35
(d) UART mode (external clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 800 nsASCK20 cycle time tKCY3
3200 ns
VDD = 2.7 to 5.5 V 400 nsASCK20 high-/low-
level width
tKH3,
tKL3 1600 ns
VDD = 2.7 to 5.5 V 39063 bpsTransfer rate
9766 bps
ASCK20 rise/fall time tR,
tF
1
µ
s
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS
36
AC Timing Test Points (excluding X1 and XT1 inputs)
Clock Timing
1/fX
tXL tXH
X1 input VIH4 (MIN.)
VIL4 (MAX.)
Capture Input Timing
CPT90
t
CPTL
t
CPTH
TMI Timing
1/f
TI
t
TIL
t
TIH
TMI60
Interrupt Input Timing
INTP0 to INTP3
t
INTL
t
INTH
Key Return Input Timing
KR0 to KR3
t
KRL
0.8V
DD
0.2V
DD
Test points 0.8V
DD
0.2V
DD
1/f
XT
t
XTL
t
XTH
XT1 input V
IH4
(MIN.)
V
IL4
(MAX.)
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS 37
RESET Input Timing
RESET
t
RSL
Serial Transfer Timing
3-wire serial I/O mode:
t
KCYm
t
KLm
t
KHm
SCK20
t
SIKm
t
KSIm
t
KSOm
Input data
Output data
SI20
SO20
Remark m = 1, 2
3-wire serial I/O mode (when using SS20):
tKAS2
SO20
SS20
Output data
tKDS2
UART mode (external clock input):
t
KCY3
t
KL3
t
KH3
ASCK20
t
R
t
F
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS
38
10-Bit A/D Converter Characteristics (TA = –40 to +85°
°°
°C, 1.8 V ≤
≤≤
≤ AVDD = VDD ≤
≤≤
≤ 5.5 V, AVSS = VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution 10 10 10 bit
4.5 V ≤ AVDD ≤ 5.5 V ±0.2 ±0.4 %FSR
2.7 V ≤ AVDD < 4.5 V ±0.4 ±0.6 %FSR
Overall errorNote
1.8 V ≤ AVDD < 2.7 V ±0.8 ±1.2 %FSR
4.5 V ≤ AVDD ≤ 5.5 V 14 100
µ
s
2.7 V ≤ AVDD < 4.5 V 19 100
µ
s
Conversion time tCONV
1.8 V ≤ AVDD < 2.7 V 28 100
µ
s
4.5 V ≤ AVDD ≤ 5.5 V ±0.4 %FSR
2.7 V ≤ AVDD < 4.5 V ±0.6 %FSR
Zero-scale errorNote AINL
1.8 V ≤ AVDD < 2.7 V ±1.2 %FSR
4.5 V ≤ AVDD ≤ 5.5 V ±0.4 %FSR
2.7 V ≤ AVDD < 4.5 V ±0.6 %FSR
Full-scale errorNote AINL
1.8 V ≤ AVDD < 2.7 V ±1.2 %FSR
4.5 V ≤ AVDD ≤ 5.5 V ±2.5 LSB
2.7 V ≤ AVDD < 4.5 V ±4.5 LSB
Non-integral linearityNote INL
1.8 V ≤ AVDD < 2.7 V ±8.5 LSB
4.5 V ≤ AVDD ≤ 5.5 V ±1.5 LSB
2.7 V ≤ AVDD < 4.5 V ±2.0 LSB
Non-differential
linearityNote
DNL
1.8 V ≤ AVDD < 2.7 V ±3.5 LSB
Analog input voltage VIAN 0AV
DD V
Note Excludes quantization error (±0.05%)
Remark FSR: Full scale range
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS 39
LCD Characteristics (TA = –40 to +85°
°°
°C, VDD = 1.8 to 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
GAIN = 1 0.84 1.0 1.165 VLCD output voltage
variation range
VLCD2 C1 to C4Note 1 = 0.47
µ
F
GAIN = 0 1.26 1.5 1.74 V
Doubler output VLCD1 C1 to C4Note 1 = 0.47
µ
F2V
LCD2 –0.1 2.0VLCD2 2.0VLCD2 V
Tripler output VLCD0 C1 to C4Note 1 = 0.47
µ
F3V
LCD2 –0.15 3.0VLCD2 3.0VLCD2 V
GAIN = 0 0.5 s
5.0 ≤ VDD ≤ 5.5 V 2.0 s
4.5 ≤ VDD < 5.0 V 1.0 s
Voltage amplification wait
timeNote 2
tVAWAIT
GAIN = 1
1.8 ≤ VDD < 4.5 V 0.5 s
LCD output voltage
differentialNote 3 (common)
VODC IO = ±5
µ
A0±0.2 V
LCD output voltage
differentialNote 3 (segment)
VODS IO = ±1
µ
A0±0.2 V
Notes 1. This is a capacitor that is connected between voltage pins used to drive the LCD.
C1: A capacitor connected between CAPH and CAPL
C2: A capacitor connected between VLC0 and VSS
C3: A capacitor connected between VLC1 and VSS
C4: A capacitor connected between VLC2 and VSS
2. This is the wait time from when voltage amplification is started (VAON0 = 1) until display is enabled
(LCDON0 = 0).
3. The voltage differential is the difference between the segment and common signal output’s actual and
ideal output voltages.
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°
°°
°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data retention power
supply voltage
VDDDR 1.8 5.5 V
Release signal set time tSREL 0
µ
s
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS
40
Data Retention Timing (STOP Mode Release by RESET)
V
DD
Data retention mode
STOP mode
HALT mode
Internal reset operation
Operation mode
t
SREL
t
WAIT
STOP instruction execution
V
DDDR
RESET
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Request Signal)
VDD
Data retention mode
STOP mode
HALT mode
Operation mode
tSREL
tWAIT
STOP instruction execution
VDDDR
Standby release signal
(interrupt request)
Oscillation Stabilization Wait Time (TA = –40 to +85°
°°
°C, VDD = 1.8 to 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Release by RESET 215/fXsOscillation stabilization wait
timeNote 1
tWAIT
Release by interrupt Note 2 s
Notes 1. Use a resonator whose oscillation stabilizes within the oscillation stabilization wait time.
2. Selection of 212/fX, 215/fX, or 217/fX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time selection register (OSTS).
Remark fX: Main system clock oscillation frequency
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS 41
Flash Memory Write/Erase Characteristics (TA = 10 to 40°
°°
°C, VDD = 1.8 to 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 1.0 5 MHzOperating frequency fX
1.0 1.25 MHz
Write currentNote
(VDD pin)
IDDW When VPP supply
voltage = VPP1
During fX = 5.0 MHz
operation
7mA
Write currentNote
(VPP pin)
IPPW When VPP supply voltage = VPP1 12 mA
Erase currentNote
(VDD pin)
IDDE When VPP supply
voltage = VPP1
During fX = 5.0 MHz
operation
7mA
Erase currentNote
(VPP pin)
IPPE When VPP supply voltage = VPP1 100 mA
Unit erase time ter 0.5 1 1 s
Total erase time tera 20 s
Write count Erase/write are regarded as 1 cycle 20 Times
VPP0 In normal operation 0 0.2VDD VVPP supply voltage
VPP1 During flash memory programming 9.7 10.0 10.3 V
Note The port current (including the current that flows to the on-chip pull-up resistors) is not included.
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS
42
8. CHARACTERISTICS CURVES OF LCD CONTROLLER/DRIVER (REFRENCE VALUES)
(1) Characteristics curves of voltage amplification stabilization time
The following shows the characteristics curves of the time from the start of voltage amplification (VAON0 = 1)
and the changes in the LCD output voltage (when GAIN is set as 1 (using the 3 V display panel)).
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
LCD output voltage [V]
V
DD
= 4.5 V V
DD
= 5 V V
DD
= 5.5 V
0 500 1000 1500 2000 2500 3000 3500 4000
Voltage amplification time [ms]
V
LCD0
V
LCD1
V
LCD2
LCD output voltage/Voltage amplification time
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS 43
(2) Temperature characteristics of LCD output voltage
The following shows the temperature characteristics curves of LCD output voltage.
LCD output voltage [V]
VLCD2 VLCD1 VLCD0
VLCD2 VLCD1 VLCD0
−40 −30 −20 −100 1020304050607080
−40 −30 −20 −100 1020304050607080
Temperature [˚C]
LCD output voltage/ Temperature (When GAIN = 1)
5
4
3
2
1
0
5
4
3
2
1
0
LCD output voltage [V]
Temperature [˚C]
LCD output voltage/ Temperature (When GAIN = 0)
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS
44
9. PACKAGE DRAWINGS
48
32
33
64
1
17
16
49
S
S
64-PIN PLASTIC TQFP (12x12)
ITEM MILLIMETERS
G 1.125
A 14.0±0.2
C 12.0±0.2
D
F 1.125
14.0±0.2
B 12.0±0.2
N0.10
P
Q0.1±0.05
1.0
S
R3°+4°
−3°
R
H
K
J
Q
G
I
S
P
detail of lead end
NOTE
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
M
H0.32+0.06
−0.10
I0.13
J
K1.0±0.2
0.65 (T.P.)
L0.5
M0.17+0.03
−0.07
P64GK-65-9ET-3
T
U0.6±0.15
0.25
F
M
A
B
CD
N
T
L
U
1.1±0.1
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS 45
10. RECOMMENDED SOLDERING CONDITIONS
The
µ
PD78F9436 and 78F9456 should be soldered and mounted under the following recommended conditions.
For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting
Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact your NEC sales
representative.
Table 10-1. Surface Mounting Type Soldering Conditions
µ
PD78F9436-9ET: 64-pin plastic TQFP (12 × 12)
µ
PD78F9456-9ET: 64-pin plastic TQFP (12 × 12)
Soldering Method Soldering Conditions Recommended
Condition Symbol
Interface reflow Package peak temperature: 235°C, Time:30 seconds max.
(at 210°C or higher), Count: Two times or less, Exposure limit: 7
daysNote (after that, prebake at 125°C for 10 hours)
IR35-107-2
VPS Package peak temperature: 215°C, Time:40 seconds max.
(at 200°C or higher), Count: Two times or less, Exposure limit: 7
daysNote (after that, prebake at 125°C for 10 hours)
VP15-107-2
Partial heating Pin temperature: 300°C max., Time: 3 seconds max. (per pin row) −
Note After opening the dry peak, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS
46
APPENDIX A. DIFFERENCES BETWEEN
µ
µµ
µ
PD78F9436, 78F9456 AND MASK ROM VERSIONS
The
µ
PD78F9436 and 78F9456 have flash memory in place of the internal ROM of the mask ROM versions.
Differences between the
µ
PD78F9436 and 78F9456 and the mask ROM versions are shown in Table A-1.
Table A-1. Differences Between
µ
µµ
µ
PD78F9436, 78F9456 and Mask ROM Versions
Flash Memory Versions Mask ROM VersionsPart Number
Item
µ
PD78F9436
µ
PD78F9456
µ
PD789435
µ
PD789436
µ
PD789455
µ
PD789456
ROM 16 KB 12 KB 16 KB 12 KB 16 KB
High-speed
RAM
512 bytes
Internal
memory
LCD display
RAM
5 × 4 bits 15 × 4 bits 5 × 4 bits 15 × 4 bits
IC pin Not available Available
VPP pin Available Not available
Pull-up resistors 30 (software
control: 30)
20 (software
control: 20)
34 (software control: 30, mask
option: 4)
24 (software control: 20, mask
option: 4)
Electrical specifications Refer to the relevant data sheet.
Caution There are differences in noise immunity and noise radiation between the flash memory and mask
ROM versions. When pre-producing an application set with the flash memory version and then
mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations for the
commercial samples (not engineering samples) of the mask ROM version.
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS 47
APPENDIX B. DEVELOPMENT TOOLS
The following development tools are available for system development using the
µ
PD78F9436 and 78F9456.
Language Processing Software
RA78K0SNotes 1, 2, 3 Assembler package common to 78K/0S Series
CC78K0SNotes 1, 2, 3 C compiler package common to 78K/0S Series
DF789456Notes 1, 2, 3, Device file for
µ
PD789426, 789436, 789446, 789456 Subseries
CC78K0S-LNotes 1, 2, 3 C compiler library source file common to 78K/0S Series
Flash Memory Writing Tools
Flashpro III
(Part No. FL-PR3Note 4, PG-FP3)
Flash programmer dedicated to on-chip flash memory microcontroller
FA-64GK-9ETNote 4 Flash memory writing adapter for 64-pin plastic TQFP (GK-9ET type)
Debugging Tools
IE-78K0S-NS
In-circuit emulator
This is an in-circuit emulator for debugging the hardware and software of an application
system using the 78K/0S Series. It supports the integrated debugger (ID78K0S-NS). It is
used with an AC adapter, emulation probe, and interface adapter for connecting the host
machine.
IE-78K0S-NS-A
In-circuit emulator
This is a board to expand the functions of the IE-78K0S-NS. The addition of this board
enhances debugging functions such as the coverage, tracer, and timer functions.
IE-70000-MC-PS-B
AC adapter
This is the adapter for supplying power from an AC-100 to 240 V outlet.
IE-70000-98-IF-C
Interface adapter
This adapter is needed when a PC-9800 series PC (except notebook type) is used as the
host machine for an IE-78K0S-NS (supports C bus).
IE-70000-CD-IF-A
PC card interface
This PC card and interface cable are needed when a PC-9800 series notebook-type PC is
used as the host machine for an IE-78K0S-NS (supports PCMCIA socket).
IE-70000-PC-IF-C
Interface adapter
This adapter is needed when an IBM PC/AT™ or compatible PC is used as the host
machine for an IE-78K0S-NS (supports ISA bus).
IE-70000-PCI-IF-A
Interface adapter
This adapter is needed when a PC that includes a PCI bus is used as the host machine for
an IE-78K0S-NS.
IE-789436-NS-EM1
Emulation board
This is an emulation board for emulating the peripheral hardware inherent to
µ
PD789426,
789436 Subseries devices. It is used with an in-circuit emulator.
IE-789456-NS-EM1
Emulation board
This is an emulation board for emulating the peripheral hardware inherent to
µ
PD789446,
789456 Subseries devices. It is used with an in-circuit emulator.
NP-64GKNote 4
Emulator probe
This is a cable that is used to connect an in-circuit emulator to the target system. It is for a
64-pin plastic TQFP (GK-9ET type).
SM78K0SNotes 1, 2 System simulator common to 78K/0S Series
ID78K0S-NSNotes 1, 2 Integrated debugger common to 78K/0S Series
DF789456Notes 1, 2 Device file for
µ
PD789426, 789436, 789446, 789456 Subseries
Real-Time OS
MX78K0SNotes 1, 2 OS for 78K/0S Series
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS
48
Notes 1. Based on PC-9800 Series (Japanese Windows™)
2. Based on IBM PC/AT compatibles (Japanese/English Windows)
3. Based on HP9000 Series 700™ (HP-UX™), or SPARCstation™ (SunOS™, Solaris™)
4. This product is manufactured by Naito Densei Machida Mfg. Co., Ltd. (TEL +81-45-475-4191).
Remark The RA78K0S, CC78K0S, and SM78K0S are used in combination with the DF789456.
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS 49
APPENDIX C. RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
Documents related to devices
Document Name Document No.
µ
PD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456 Data Sheet U14493E
µ
PD78F9436, 78F9456 Data Sheet This document
µ
PD789426, 789436, 789446, 789456 Subseries User’s Manual U15075E
78K/0S Series User’s Manual Instructions U11047E
78K/0, 78K/0S Series Application Note Flash Memory Write U14458E
Documents related to development tools (user’s manuals)
Document Name Document No.
Operation U11622E
Language U11599E
RA78K0S Assembler Package
Structured Assembly Language U11623E
Operation U11816ECC78K0S C Compiler
Language U11817E
SM78K0S, SM78K0, System Simulator Ver.2.10 or
later Windows Based
Operation U14611E
SM78K Series System Simulator Ver 2.10 or Later External Part User Open Interface
Specifications
U15006E
ID78K0-NS, ID78K0S-NS Integrated Debugger
Ver.2.20 or later Windows Based
Operation U14910E
IE-78K0S-NS In-circuit Emulator U13549E
IE-789436-NS-EM1 Emulation Board To be prepared
IE-789456-NS-EM1 Emulation Board To be prepared
PG-FP3 Flash Memory Programmer U13502E
Documents related to embedded software (user’s manuals)
Document Name Document No.
78K/0S Series OS MX78K0S Fundamental U12938E
Other documents
Document Name Document No.
SEMICONDUCTOR SELECTION GUIDE - Products & Packages - (CD-ROM) X13769E
Semiconductor Device Mounting Technology Manual C10535E
Quality Grades on NEC Semiconductor Devices C11531E
NEC Semiconductor Device Reliability/Quality Control System C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E
Caution The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS
50
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
EEPROM and FIP are trademarks of NEC Corporation.
Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or
other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
µ
µµ
µ
PD78F9436, 78F9456
Data Sheet U15379EJ1V0DS 51
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Italiana s.r.l.
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-3067-5800
Fax: 01-3067-5899
NEC Electronics (France) S.A.
Madrid Office
Madrid, Spain
Tel: 091-504-2787
Fax: 091-504-2860
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: 253-8311
Fax: 250-3583
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Guarulhos-SP, Brasil
Tel: 11-6462-6810
Fax: 11-6462-6829
J01.2
µ
µµ
µ
PD78F9436, 78F9456
M8E 00. 4
The information in this document is current as of April, 2001. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
•
•
•
•
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