X9314 (R) Terminal Voltages 5V, 32 Taps, Log Taper Data Sheet September 5, 2006 Single Digitally Controlled Potentiometer (XDCPTM) FN8178.2 Features * Solid State Potentiometer The Intersil X9314 is a solid state nonvolatile potentiometer and is ideal for digitally controlled resistance trimming. * 32 Taps * 10k End to End Resistance The X9314 is a resistor array composed of 31 resistive elements. Between each element and at either end are tap points accessible to the wiper element. The position of the wiper element is controlled by the CS, U/D, and INC inputs. The position of the wiper can be stored in nonvolatile memory and then be recalled upon a subsequent power-up operation. * Three-Wire Up/Down Serial Interface * Wiper Resistance, 40 Typical * Nonvolatile Storage and Recall on Power-up of Wiper Position Standby Current < 500A Max (Total Package) * VCC = 3V to 5.5V Operation * 100 Year Data Retention The XDCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. * Offered in 8 Ld MSOP, SOIC and PDIP Packages * Pb-Free Plus Anneal Available (RoHS Compliant) Block Diagram U/D INC 31 5-Bit Up/Down Counter CS VH/RH 30 29 5-Bit Nonvolatile Memory 28 One of Thirty-Two Decoder Transfer Gates Resistor Array 2 Store and Recall Control Circuitry VCC VSS 1 0 VL/RL VW/RW 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X9314 Ordering Information PART NUMBER PART MARKING X9314WMI* 14WI X9314WP X9314WP X9314WPI X9314WP I X9314WS* VCC RANGE (V) RTOTAL (k) TEMP RANGE (C) 5 10% 10 -40 to +85 PKG. DWG. # PACKAGE 8 Ld MSOP M8.118 0 to +70 8 Ld PDIP MDP0031 -40 to +85 8 Ld PDIP MDP0031 X9314W 0 to +70 8 Ld SOIC M8.15 X9314WSI* X9314W I -40 to +85 8 Ld SOIC M8.15 X9314WSIZ (Note) X9314W ZI -40 to +85 8 Ld SOIC (Pb-free) M8.15 X9314WSZ* (Note) X9314W Z 0 to +70 8 Ld SOIC (Pb-free) M8.15 X9314WMI-3* AAY X9314WMIZ-3* (Note) DEX X9314WS-3* X9314W D 0 to +70 8 Ld SOIC X9314WSZ-3* (Note) X9314W ZD 0 to +70 8 Ld SOIC (Pb-free) M8.15 3 to 5.5 -40 to +85 8 Ld MSOP M8.118 -40 to +85 8 Ld MSOP (Pb-free) M8.118 M8.15 *Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Pin Descriptions Pin Configuration VH/RH and VL/RL 8 LD PDIP/SOIC The high (VH/RH) and low (VL/RL) terminals of the X9314 are equivalent to the fixed terminals of a mechanical potentiometer. The minimum voltage is -5V and the maximum is +5V. It should be noted that the terminology of VL/RL and VH/RH references the relative position of the terminal in relation to wiper movement direction selected by the U/D input and not the voltage potential on the terminal. INC 1 8 VCC U/D 2 7 CS VH/RH 3 6 VL/RL VSS 4 5 VW/RW X9314 8 LD MSOP VW/RW VW/RW is the wiper terminal, equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the control inputs. The wiper terminal series resistance is typically 40. VH/RH VSS U/D 1 8 2 7 INC 6 VCC 5 CS VW/RW 3 VL/RL 4 X9314 Up/Down (U/D) The U/D input controls the direction of the wiper movement and whether the counter is incremented or decremented. Pin Names Increment (INC) The INC input is negative-edge triggered. Toggling INC will move the wiper and either increment or decrement the counter in the direction indicated by the logic level on the U/D input. Chip Select (CS) The device is selected when the CS input is LOW. The current counter value is stored in nonvolatile memory when CS is returned HIGH while the INC input is also HIGH. After the store operation is complete the X9314 will be placed in the low power standby mode until the device is selected once again. 2 SYMBOL DESCRIPTION VH/RH High Terminal VW/RW Wiper Terminal VL/RL Low Terminal VSS Ground VCC Supply Voltage U/D Up/Down Input INC Increment Input CS Chip Select Input FN8178.2 September 5, 2006 X9314 Typical Attenuation Characteristics (dB) Attenuation (dB) 0 -20 -40 -43.5 -60 31 28 24 20 16 12 8 0 4 Tap Position Principles of Operation Operation Notes There are three sections of the X9314: the input control, counter and decode section; the nonvolatile memory; and the resistor array. The input control section operates just like an up/down counter. The output of this counter is decoded to turn on a single electronic switch connecting a point on the resistor array to the wiper output. Under the proper conditions the contents of the counter can be stored in nonvolatile memory and retained for future use. The resistor array is comprised of 31 individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The system may select the X9314, move the wiper and deselect the device without having to store the latest wiper position in nonvolatile memory. The wiper The INC, U/D and CS inputs control the movement of the wiper along the resistor array. With CS set LOW the X9314 is selected and enabled to respond to the U/D and INC inputs. HIGH to LOW transitions on INC will increment or decrement (depending on the state of the U/D input) a five bit counter. The output of this counter is decoded to select one of thirty-two wiper positions along the resistive array. The wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. That is, the counter does not wrap around when clocked to either extreme. The value of the counter is stored in nonvolatile memory whenever CS transistions HIGH while the INC input is also HIGH. When the X9314 is powered-down, the last counter position stored will be maintained in the nonvolatile memory. When power is restored, the contents of the memory are recalled and the counter is reset to the value last stored. 3 movement is performed as described above; once the new position is reached, the system would keep the INC LOW while taking CS HIGH. The new wiper position would be maintained until changed by the system or until a powerup/down cycle recalled the previously stored data. This would allow the system to always power-up to a preset value stored in nonvolatile memory; then during system operation minor adjustments could be made. The adjustments might be based on user preference, system parameter changes due to temperature drift, etc. The state of U/D may be changed while CS remains LOW. This allows the host system to enable the X9314 and then move the wiper up and down until the proper trim is attained. tIW/RTOTAL The electronic switches on the X9314 operate in a "make before break" mode when the wiper changes tap positions. If the wiper is moved several positions multiple taps are connected to the wiper for tIW (INC to VW change). The RTOTAL value for the device can temporarily be reduced by a significant amount if the wiper is moved several positions. Power-up and Down Requirement The are no restrictions on the sequencing of VCC and the voltages applied to the potentiometer pins during power-up or power-down conditions. During power-up, the data sheet parameters for the DCP do not fully apply until 1 millisecond after VCC reaches its final value. The VCC ramp rate spec is always in effect. FN8178.2 September 5, 2006 X9314 Absolute Maximum Ratings Recommended Operating Conditions Temperature under bias . . . . . . . . . . . . . . . . . . . . . .-65C to +135C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Voltage on CS, INC, U/D, and VCC with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V Voltage on VH/RH and VL/RL referenced to VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -8V to +8V V = |VH/RH - VL/RL| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10V Lead temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . . +300C Wiper current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8.8mA Temperature (Commercial) . . . . . . . . . . . . . . . . . . . . . 0C to +70C Temperature (Industrial). . . . . . . . . . . . . . . . . . . . . . .-40C to +85C Supply Voltage (VCC) Limits X9314. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V 10% X9314-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 5.5V CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Potentiometer Characteristics (Over recommended operating conditions unless otherwise stated.) LIMITS SYMBOL RTOTAL VVL/RL PARAMETER TEST CONDITIONS/NOTES MIN TYP End to End Resistance Tolerance UNITS 20 % VH/RH Terminal Voltage -5 +5 V VL/RL Terminal Voltage -5 +5 V 10 mW 100 4.4 mA Power Rating at +25C RW Wiper Resistance IW = 1mA, VCC = 5V IW Wiper Current Noise Ref: 1kHz Relative variation. Error in step size between taps. log (Rw(n)) - log Rw(n - 1)) RTOTAL Temperature Coefficient for -40C to +85C 40 -120 0.070.003 Potentiometer Capacitance dBV 0.07 + 0.003 600 Ratiometric Temperature Coefficient CH/CL/CW MAX ppm/C 20 See Circuit #3 10/10/25 ppm/C pF NOTE: 1. This parameter is periodically sampled and not 100% tested. 4 FN8178.2 September 5, 2006 X9314 DC Electrical Specifications (Over recommended operating conditions unless otherwise specified.) LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN TYP(2) MAX UNITS 1 3 mA ICC VCC Active Current CS = VIL, U/D = VIL or VIH and INC = 0.4V/2.4V @ max. tCYC ISB Standby Supply Current CS = VCC - 0.3V, U/D and INC = VSS or VCC - 0.3V 500 A ILI CS, INC, U/D Input Leakage Current VIN = VSS to VCC 10 A VIH CS, INC, U/D Input HIGH Voltage 2 VCC + 1 V VIL CS, INC, U/D Input LOW Voltage -1 0.8 V CIN(3) CS, INC, U/D Input Capacitance 10 pF VCC = 5V, VIN = VSS, TA = +25C, f = 1MHz Standard Parts PART NUMBER MAXIMUM RESISTANCE WIPER INCREMENTS MINIMUM RESISTANCE X9314W 10k Log Taper 40 NOTES: 2. Typical values are for TA = +25C and nominal supply voltage. 3. This parameter is periodically sampled and not 100% tested. Test Circuit #1 Test Circuit #2 Circuit #3 SPICE Macromodel Macro Model VH/RH VH/RH RTOTAL Test Point Test Point VW/RW RH CH VW/RW Force Current CW 10pF VL/RL VL/RL CL RL 10pF 25pF RW SYMBOL TABLE A.C. Conditions of Test INPUT PULSE LEVELS 0V to 3V Input rise and fall times 10ns Input reference levels 1.5V Mode Selection CS INC U/D MODE L H Wiper up L L Wiper down H X Store wiper position X X Standby L X No store, return to standby H 5 WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Low to High Will change from Low to High May change from High to Low Will change from High to Low Don't Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance FN8178.2 September 5, 2006 X9314 AC Electrical Specifications (Over recommended operating conditions unless otherwise specified) LIMITS SYMBOL PARAMETER MIN TYP(4) UNITS MAX tCl CS to INC Setup 100 ns tlD INC HIGH to U/D Change 100 ns tDI U/D to INC Setup 2.9 s tlL INC LOW Period 1 s tlH INC HIGH Period 1 s tlC INC Inactive to CS Inactive 1 s tCPH CS Deselect Time 20 ms tIW INC to VW Change tCYC 100 INC Cycle Time 500 s 4 s tR, tF(5) tPU(5) INC Input Rise and Fall Time 500 s Power-up to Wiper Stable 500 s tR VCC VCC Power-up Rate 50 mV/s 0.2 A.C. Timing CS tCYC tIL tCI tIC tIH tCPH 90% INC tID tDI tF 90% 10% tR U/D tIW VW MI (6) NOTES: 4. Typical values are for TA = +25C and nominal supply voltage. 5. This parameter is periodically sampled and not 100% tested. 6. MI in the A.C. timing diagram refers to the minimum incremental change in the VW output due to a change in the wiper position. 6 FN8178.2 September 5, 2006 X9314 Mini Small Outline Plastic Packages (MSOP) N M8.118 (JEDEC MO-187AA) 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE E1 INCHES E -B- INDEX AREA 1 2 0.20 (0.008) A B C TOP VIEW 4X 0.25 (0.010) R1 R GAUGE PLANE A SEATING PLANE -C- A2 A1 b -He D 0.10 (0.004) 4X L1 SEATING PLANE C 0.20 (0.008) C a CL E1 C D MAX MIN MAX NOTES 0.037 0.043 0.94 1.10 - A1 0.002 0.006 0.05 0.15 - A2 0.030 0.037 0.75 0.95 - b 0.010 0.014 0.25 0.36 9 c 0.004 0.008 0.09 0.20 - D 0.116 0.120 2.95 3.05 3 E1 0.116 0.120 2.95 3.05 4 0.026 BSC -B- 0.65 BSC - E 0.187 0.199 4.75 5.05 - L 0.016 0.028 0.40 0.70 6 0.037 REF N C 0.20 (0.008) MIN A L1 -A- SIDE VIEW SYMBOL e L MILLIMETERS 0.95 REF 8 R 0.003 R1 0 - 8 - 0.07 0.003 - 5o 15o 0o 6o 7 - - 0.07 - - 5o 15o - 0o 6o Rev. 2 01/03 END VIEW NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension "D" does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (0.004) at seating Plane. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B - to be determined at Datum plane 11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only. 7 FN8178.2 September 5, 2006 X9314 Small Outline Plastic Packages (SOIC) M8.15 (JEDEC MS-012-AA ISSUE C) N 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA 0.25(0.010) M H B M INCHES E SYMBOL -B- 1 2 3 L SEATING PLANE -A- A D h x 45 -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M MIN MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 e B S 0.050 BSC - 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 1.27 BSC H N NOTES: MILLIMETERS 8 0 8 8 0 7 8 Rev. 1 6/05 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 8 FN8178.2 September 5, 2006 X9314 Plastic Dual-In-Line Packages (PDIP) E D A2 SEATING PLANE L N A PIN #1 INDEX E1 c e b A1 NOTE 5 1 eA eB 2 N/2 b2 MDP0031 PLASTIC DUAL-IN-LINE PACKAGE SYMBOL PDIP8 PDIP14 PDIP16 PDIP18 PDIP20 TOLERANCE A 0.210 0.210 0.210 0.210 0.210 MAX A1 0.015 0.015 0.015 0.015 0.015 MIN A2 0.130 0.130 0.130 0.130 0.130 0.005 b 0.018 0.018 0.018 0.018 0.018 0.002 b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015 c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002 D 0.375 0.750 0.750 0.890 1.020 0.010 E 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010 E1 0.250 0.250 0.250 0.250 0.250 0.005 e 0.100 0.100 0.100 0.100 0.100 Basic eA 0.300 0.300 0.300 0.300 0.300 Basic eB 0.345 0.345 0.345 0.345 0.345 0.025 L 0.125 0.125 0.125 0.125 0.125 0.010 N 8 14 16 18 20 Reference NOTES 1 2 Rev. B 2/99 NOTES: 1. Plastic or metal protrusions of 0.010" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane. 4. Dimension eB is measured with the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 9 FN8178.2 September 5, 2006