Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
VC-709
HCSL, LVDS, LVPECL Crystal Oscillator Data Sheet
Vectron’s VC-709 Crystal Oscillator is a quartz stabilized, di erential output oscillator, operating o a 2.5 or 3.3 volt supply in a
hermetically sealed 5x7 ceramic package.
Ultra Low Jitter Performance, 3rd OT or Fundamental Crystal Design•
13.500-170.0000MHz Output Frequencies•
Low Power•
400ps max Rise and Fall Time•
Excellent Power Supply Rejection Ratio•
Enable/Disable•
3.3 or 2.5V operation•
-10/70°C or -40/85°C Operation•
Hermetically Sealed 5x7 Ceramic Package•
Product is compliant to RoHS directive •
and fully compatible with lead free assembly
Features Applications
Description
VC-709
Block Diagram Phase Noise
PCI Express•
Ethernet, GbE, Synchronous Ethernet•
Fiber Channel•
Enterprise Servers•
Telecom•
Clock source for A/D’s, D/A’s•
Driving FPGA’s•
Test and Measurement•
PON•
Medical•
COTS •
VDD Output
E/D or NC GND
Oscillator
Crystal
E/D or NC
Complementary
Output
Voltage Regulator
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Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Page2
Performance Speci cations
Table 1. Electrical Performance, LVPECL Option
Parameter Symbol Min Typical Maximum Units
Supply
Voltage1VDD 3.135
2.375
3.3
2.5
3.465
2.625
V
V
Current (No Load) IDD 35 50 mA
Frequency
Nominal Frequency fN13.5 170.000 MHz
Stability,3 (Ordering Option) ±25, ±50 or ±100 ppm
Outputs
Output Logic Levels4
Output Logic High
Output Logic Low
VOH
VOL
VDD-1.085
VDD-1.830
VDD-0.880
VDD-1.555
V
V
Output Rise and Fall Time3tR/tF500 ps
Load 50 ohms into VDD-1.3V
Duty Cycle445 55 %
Jitter, 156.250MHz5
12kHz-50MHz
12kHz -20MHz
10kHz-1MHz
фJ
200
150
100
fs
fs
fs
Period Jitter6
RMS
P/P
Cycle-Cycle6
RMS
P/P
Random Jitter7
Deterministic Jitter7
фJ
1.1
10.5
1.9
17.7
2.2
0
ps
ps
ps
ps
ps
ps
Enable/Disable
Output Enabled8
Output Disabled
VIH
VIL
0.7*VDD
0.3*VDD
V
V
Disable Time tD200 ns
Enable/Disable Leakage Current ±200 uA
Start-Up Time tSU 2ms
Operating Temp. (Ordering Option) TOP -10/70 or -40/85 °C
Package Size 5.0 x 7.0 x 1.6 mm
1. The VC-709 power supply pin should be ltered, eg, a 0.1 and 0.01uf capacitor.
2. Includes calibration tolerance, operating temperature, supply voltage variations, aging and IR re ow.
3. Figure 3 de nes the test circuit and Figure 4 de nes these parameters.
4. Duty Cycle is de ned as the On/Time Period.
5. Measured using an Agilent E5052.
6. Measured using a LeCroy Wavemaster 8600A, 90K samples
7. Measured using a Wavecrest SIA3300C, 90K samples.
8. Outputs will be Enabled if Enable/Disable is left open.
tRtF
VAMP*0.8
VAMP*0.2
Cross Point
On Time
Period
VAMP
Figure 2.
1
2
3
6
5
4
-1.3V
NC
NC
VDD -1.3V
50 ȍ50 ȍ
Figure 1.
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Page3
Performance Speci cations
1. The VC-709 power supply pin should be ltered, eg, a 0.1 and 0.01uf capacitor.
2. Includes calibration tolerance, operating temperature, supply voltage variations, aging and IR re ow.
3. Figure 5 de nes these parameters and Figure 4 de nes the test circuit.
4. Duty Cycle is de ned as the On/Time Period.
5. Measured using an Agilent E5052.
6. Measured using a LeCroy Wavemaster 8600A, 90K samples.
7. Measured using a Wavecrest SIA3300C, 90K samples.
8. Outputs will be Enabled if Enable/Disable is left open.
Table 2. Electrical Performance, LVDS Option
Parameter Symbol Min Typical Maximum Units
Supply
Voltage1VDD 3.135
2.375
3.3
2.5
3.465
2.625
V
V
Current (No Load) IDD 60 mA
Frequency
Nominal Frequency fN13.5 170.000 MHz
Stability2 (Ordering Option) ±25, ±50 or ±100 ppm
Outputs
Output Logic Levels3
Output Logic High
Output Logic Low
VOH
VOL 0.9
1.43
1.10
1.6 V
V
Di erential Output Amplitude 250 350 450 mV
Di erential Output Error 50 mV
O set Voltage 1.125 1.25 1.375 V
O set Voltage Error 50 mV
Output Leakage Current 10 uA
Output Rise and Fall Time3tR/tF400 ps
Load 100 ohms di erential
Duty Cycle445 55 %
Jitter, 156.250MHz5
12kHz - 50MHz
12kHz - 20MHz
10kHz - 1MHz
фJ
200
150
100
fs
fs
fs
Period Jitter6
RMS
P/P
Cycle-Cycle Jitter6
RMS
P/P
Random Jitter7
Deterministic Jitter7
фJ
1.1
10.5
1.9
17.7
2.2
0
ps
ps
ps
ps
ps
ps
Enable/Disable
Output Enabled8
Output Disabled
VIH
VIL
0.7*VDD
0.3*VDD
V
V
Disable Time tD200 ns
Enable/Disable Leakage Current IE/D ±200 uA
Start-Up Time tSU 2ms
Operating Temp. (Ordering Option) TOP -10/70 or -40/85 °C
Package Size 5.0 x 7.0 x 1.6 mm
DC 1
4
3
65
2
50
50
0.01 uF
Out
Out
Figure 3.
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Performance Speci cations
Table 3. Electrical Performance, HCSL Output
Parameter Symbol Min Typical Maximum Units
Supply
Voltage1VDD 2.375
3.165
2.5
3.3
2.625
3.465
V
V
Current (No Load) IDD 30 mA
Frequency
Nominal Frequency fN13.5 170 MHz
Stability2 (Ordering Options) ±25, ±50 or ±100 ppm
Outputs
Output Logic Swing VOH 0.62 0.78 V
Output Rise and Fall Time3tR/tF400 ps
Load 50 ohms to ground
Duty Cycle445 55 %
Jitter (12 kHz - 20 MHz ) 100.000MHz5фJ 300 fs
Period Jitter6
RMS
P/P
Cycle-Cycle Jitter6
RMS
P/P
Random Jitter7
Deterministic Jitter7
фJ
1.0
9.7
1.8
18.3
2.2
0
ps
ps
ps
ps
ps
ps
Enable/Disable
Output Enabled8
Output Disabled
VIH
VIL
0.7*VDD
0.3*VDD
V
V
Disable Time tD200 ns
Enable/Disable Leakage Current IE/D ±200 uA
Start-Up Time tSU 2ms
Operating Temp. (Ordering Option) TOP -10/70 or -40/85 °C
Package Size 5.0 x 7.0 x 1.6 mm
tRtF
VAMP*0.8
VAMP*0.2
Cross Point
On Time
Period
Figure 5.
VAMP
1. The VC-709 power supply pin should be ltered, e.g., a 0.1 and 0.01uf capacitor.
2. Includes calibration tolerance, operating temperature, supply voltage variations, aging and IR re ow.
3. Figure 1 de nes the test circuit and Figure 2 de nes these parameters.
4. Duty Cycle is de ned as the On Time/Period.
5. Measured using an Agilent E5052.
6. Measured using a LeCroy Wavemaster 8600A, 90K samples.
7. Measured using a Wavecrest SIA3300C, 90K samples.
8. Outputs will be Enabled if the Enable/Disable pad is left open.
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Figure 4.
50 Ω
50 Ω
1 6
2 5
3 4
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Package and Pinout
Table 4. Pinout
Pin # Symbol Function
1 E/D or NC Enable/Disable
2 E/D or NC Enable/Disable
3 GND Electrical and Lid Ground
4f
OOutput Frequency
5Cf
OComplementary Output Frequency
6V
DD Supply Voltage
Figure 7. Package Outline Drawing
7.0±0.15
5.0±0.15
1.40 1.10
3.7
2.54
5.08
Frequency
Date Code
1
31
Bottom View
5
2
23
65 4
64
1.6 max
Figure 6. Pad Layout
1.96
3.66
5.08
2.54
1.78
HCSL Application Diagrams
The VC-709 incorporates a standard High Speed Current Logic, HCSL ,output scheme which is a 15mA current source switched between Out and Comple-
mentary Out. Being un-terminated drains, as shown in Figure 8, they require external 50 ohm resistors to ground as shown in Figure 9. HCSL is a high im-
pedance output with quick switching times, in can be advantageous to use a 10 to 30 ohm series resistor as shown in Figure 10, to help reduce overshoot/
ringing.
Figure 8.
Standard HCSL Output Con guration
Figure 9.
Single Resistor Termination Scheme
Figure 10.
In some cases a 10-30 ohm series resistor is
used to help reduce overshoot.
One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left un-termi-
nated, and if it one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 50 ohm impedance matching
into account. Load matching and power supply noise are the main contributors to jitter related problems.
15mA
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50 Ω50 Ω
1 6
2 5
3 4
ZL=50 ohms
ZL=50 ohms
50 Ω
1 6
2 5
3 4
50 Ω
ZL=50 ohms
ZL=50 ohms
10-30 Ω
10-30 Ω
Dimensions are in mm
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Environmental and IR Compliance
Table 5. Environmental Compliance
Parameter Condition
Mechanical Shock MIL-STD-883 Method 2002
Mechanical Vibration MIL-STD-883 Method 2007
Temperature Cycle MIL-STD-883 Method 1010
Solderability MIL-STD-883 Method 2003
Fine and Gross Leak
Fine and Gross Leak MIL-STD-883 Method 1014
Resistance to Solvents MIL-STD-202 Method 215
Moisture Sensitivity Level
Moisture Sensitivity Level MSL1
Contact Pads Gold over Nickel
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LVPECL Application Diagrams
LVDS Application Diagrams
The VC-709 incorporates a standard PECL output scheme, which are un-terminated FET drains. There are numerous application notes on terminating and
interfacing PECL logic and the two most common methods are a single resistor to ground, Figure 11, or for best 50 ohm matching a pull-up/pull-down
scheme as shown in Figure 12 should be used. AC coupling capacitor are optional, depending on the application and the input logic requirements of the
next stage.
1
2
3
6
5
4
NC
NC
VDD
140 ȍ140 ȍ
0.01uF
0.01uF
0.01uF
Figure 11. Single Resistor Termination Scheme
Resistor values are typically 140 ohms for 3.3V operation and
84 ohms for 2.5V operation.
Figure 12. Pull-Up Pull Down Termination
Resistor values shown are typical for 3.3 V opertaion. For 2.5V operation, the
resistor to ground is 62 ohms and the resistor to supply is 250 ohms
One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left un-termi-
nated, and if it one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 50 ohm impedance matching
into account. Load matching and power supply noise are the main contributors to jitter related problems.
100ȍ
LVDS
Driver LVDS
Receiver 100ȍ
LVDS
Driver Receiver
Figure 13. LVDS to LVDS Connection, Internal 100ohm Resistor
Some LVDS structures have an internal 100 ohm resistor on the in-
put and do not need additional components. AC blocking capacitors
can be used if the DC levels are incompatible.
Figure 14. LVDS to LVDS Connection
Some input structures may not have an internal 100 ohm resis-
tor on the input and will need an external 100ohm resistor for
impedance matching. Also, the input may have an internal DC
bias which may not be compatible with LVDS levels, AC block-
ing capacitors can be used.
One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left un-termi-
nated, and if it one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 50 ohm impedance matching
into account. Load matching and power supply noise are the main contributors to jitter related problems.
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Table 6. Re ow Pro le
Parameter Symbol Value
PreHeat Time ts 200 sec Max
Ramp Up RUP 3°C/sec Max
Time above 217°C tL 150 sec Max
Time to Peak Temperature tAMB-P 480 sec Max
Time at 260°C
Time at 260°C tP 30 sec Max
Time at 240°C tP2 60 sec Max
Ramp down
Ramp down RDN 6°C/sec Max
Suggested IR Pro le
Devices are built using lead free epoxy and can be subjected to
standard lead free IR re ow conditions shown in Table 6. Contact
pads are gold over nickel and lower maximum temperatures can also
be used, such as 220C.
S
IR Compliance
Absolute Maximum Ratings and Handling Precautions
Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional operation is not implied or any other
excess of conditions represented in the operational sections of this data sheet. Exposure to absolute maximum ratings for extended
periods may adversely a ect device reliability.
Although ESD protection circuitry has been designed into the VC-709, proper precautions should be taken when handling and mounting,
VI employs a Human Body Model and Charged Device Model for ESD susceptibility testing and design evaluation.
ESD thresholds are dependent on the circuit parameters used to de ne the model. Although no industry standard has been adopted for
the CDM a standard resistance of 1.5kOhms and capacitance of 100pF is widely used and therefor can be used for comparison purposes.
S
Table 7. Maximum Ratings
Parameter Unit
Storage Temperature -55 to 125 °C
Junction Temperature 150 C
Supply Voltage -0.5 to 5.0 V
Enable Disable Voltage -0.5 to VDD+0.5 V
ESD, Human Body Model 1500 V
ESD, Charged Device Model 1500 V
Maximum Ratings, Tape & Reel
Table 8. Tape and Reel Information
Tape Dimensions (mm) Reel Dimensions (mm)
W F Do Po P1 A B C D N W1 W2 #/Reel
16 7.5 1.5 4 8 180 2 13 21 50 17 21 250
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Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
VC-709- PCIE2 - 100M000000
Product
XO
Options
Supply =2.25-3.63V
Output = HCSL
Stability = ±50 ppm over -40/85°C
Enable/Disable on Pin 1
Frequency in MHz
Package
5x7
Page8
Disclaimer
Vectron International reserves the right to make changes to the product(s) and or information contained herein without notice. No liability is assumed as a result of their use or application.
No rights under any patent accompany the sale of any such product(s) or information.
Rev: 03/28/2011
For Additional Information, Please Contact
USA:
Vectron International
267 Lowell Road
Hudson, NH 03051
Tel: 1.888.328.7661
Fax: 1.888.329.8328
Europe:
Vectron International
Landstrasse, D-74924
Neckarbischofsheim, Germany
Tel: +49 (0) 3328.4784.17
Fax: +49 (0) 3328.4784.30
Asia:
VI Shanghai
1589 Century Avenue, the 19th Floor
Chamtime International Financial Center
Shanghai, China
Tel: 86.21.6081.2888
Fax: 86.21.6163.3598
Ordering Information
Example: VC-709-ECE-KAAN-156M250
VC-709- E C E - K A A N - xxxMxxxxxx
Product
XO
Voltage Options
E: +3.3 Vdc ±5%
H: +2.5 Vdc ±5%
Output
H: HCSL
C: LVPECL
D: LVDS
Frequency in MHz
*Note: not all combination of options are available.
Other speci cations may be available upon request.
Temp Range
W: -10/70°C
E: -40/85°C
Other (Future Use)
N: Standard
Stability
F: ±25ppm
K: ±50ppm
S: ±100ppm
Enable/Disable Pin
A: Pin 1
B: Pin 2
Package
5x7
Enable/Disable Logic
A: Enable High
PCI Express Ordering Information
VC-709-107-frequency= LVPECL, +3.3V, ±20ppm over -10/70°C, E/D on Pin1
VC-709-109-frequency= LVDS, +3.3V, ±20ppm over -10/70°C, E/D on Pin1
VC-709-110-frequency= LVPECL, +2.5V, ±20ppm over -10/70°C, E/D on Pin1
VC-709-111-frequency= LVDS, +2.5V, ±20ppm over -10/70°C, E/D on Pin1
±20ppm Options
