http://www.cirrus.com Copyright Cirrus Logic, Inc. 2009
(All Rights Reserved)
CS3001
CS3002
Precision Low-voltage Amplifier; DC to 2 kHz
Features & Description
Low Offset: 10 μV Max
Low Drift: 0.05 μV/°C Max
Low Noise
–6 nV/√Hz @ 0.5 Hz
– 0.1 to 10 Hz = 125 nVp-p
– 1/f corner @ 0.08 Hz
Open-loop Voltage Gain
– 300 dB Typical
– 200 dB Minimum
Rail-to-rail Output Swing
Slew Rate: 5 V/μs
Applications
Thermocouple/Thermopile Amplifiers
Load Cell and Bridge Transducer Amplifiers
Precision Instrumentation
Battery-powered Systems
Description
The CS3001 single amplifier and the CS3002 dual am-
plifier are designed for precision amplification of low-
level signals and are ideally suited to applications that
require very high closed-loop gains. These amplifiers
achieve excellent offset stability, super-high open-loop
gain, and low noise over time and temperature. The de-
vices also exhibit excellent CMRR and PSRR. The
common mode input rang e includes the nega tive supply
rail. The amplifiers operate with any total supply voltage
from 2.7 V to 6.7 V (±1.35 V to ±3.35 V).
Pin Configurations
PWDN
-In
+In
V-
NC
V+
Output
NC
1
2
3
4
8
7
6
5
-
+
Out A
-In A
+In A
V-
V+
Out B
-In B
+In B
A
B
-
-
+
+
1
2
3
4
8
7
6
5
CS3001
8-lead SOIC
CS3002
8-lead SOIC
Noise vs. Frequency (Measured)
1
10
100
0.001 0.01 0.1 1 10
Frequency (Hz)
nV/√Hz
CS3001
R1
100
R2
64.9k
C1
0.015μF
Dexter Research
Thermopile 1M
Thermopile Amplifier with a Gain of 650 V/V
JUL ‘09
DS490F9
CS3001
CS3002
2DS490F9
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS .............................................. 3
ELECTRICAL CHARACTERISTI CS.............. ................... ... ... .... ... ... ... ...............3
ABSOLUTE MAXIMUM RATINGS.....................................................................4
2. TYPICAL PERFORMANCE PLOTS .............................................................. 4
3. CS3001/CS3002 OVERVIEW ......................................................................... 8
3.1 Open-loop Gain and Phase Response .................................................................8
3.2 Open-loop Gain and Stability Compensation .......................................................9
3.2.1 Discussion ...................................................................................................9
3.2.2 Gain Calculations Summary and Recommendations ...............................12
3.3 Powerdown (PDWN) ...................... .... ... ... ... .... ... ................... .................... .........12
3.4 Applications .... ... .................... ................... .................................... ................... ...12
4. PACKAGE DRAWING .................................................................................. 14
5. ORDERING INFORMATION ........................................................................ 15
6. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION .. 15
7. REVISION HISTORY ...................................................................................16
LIST OF FIGURES
Figure 1. Noise vs. Frequency (Measured) ............ ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ..4
Figure 2. 0.01 Hz to 10 Hz Noise .......................................................................................4
Figure 3. Supply Current vs. Temperature, 3001 ...............................................................4
Figure 4. Noise vs. Frequency .. ................... .... ... ... ... .................... ... ... ... .... ................... ... ..4
Figure 5. Offset Voltage Stability (DC to 3.2 Hz) ...............................................................4
Figure 6. Supply Current vs. Temperature, 3002 ...............................................................4
Figure 7. Supply Current vs. Voltage, 3001 .......................................................................5
Figure 8. Supply Current vs. Voltage, 3002 .......................................................................5
Figure 9. Open-loop Gain and Phase vs. Frequency .........................................................5
Figure 10. Open-loop Gain and Phase vs. Frequency (Expanded) ...................................6
Figure 11. Input Bias Current vs. Supply Voltage (CS3002) ..............................................6
Figure 12. Input Bias Current vs. Common Mode Voltage ................................................7
Figure 13. Voltage Swing vs. Output Current (2.7 V) .......... ...............................................7
Figure 14. Voltage Swing vs. Output Current (5 V) ....... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ..7
Figure 15. CS3001/CS3002 Open-loop Gain and Phase Response ............ ... ... .... ... ... ... ..8
Figure 16. Non-inverting Gain Configuration .....................................................................9
Figure 17. Non-inverting Gain Configuration with Compensation ....................................10
Figure 18. Loop Gain Plot: Unity Gain and with Pole-zero Compensation ......................11
Figure 19. Thermopile Amplifier with a Gain of 650 V/V ..................................................13
Figure 20. Load Cell Bridge Amplifier and A/D Converter ...............................................13
CS3001
CS3002
DS490F9 3
1. CHARACTERISTICS AND SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
V+ = +5 V, V- = 0V, VCM = 2.5 V
(Note 1)
Notes: 1. Symbol “•” denotes specification applies over -40 to +85 ° C.
2. This paramet er is guaranteed by design and laboratory characterization. Thermocouple effects pr ohibit
accurate measurement of these parameters in automatic test systems.
3. 1000-hour life test data @ 125 °C indicates randomly distributed variatio n approximately equal to
measurement repeatability of 1 µV.
4. Measured within the specified common mode range limits.
5. Guaranteed with in the output limits of (V+ -0.3 V) to (V- +0.3 V). Tested with proprietary production test
method.
6. PWDN input has an internal pullup resistor to V+ of approximately 800 kΩ and is the major source of
current consumption when PWDN is active low.
7. The device has a controlled start-u p behavior due to its complex open loop gain character istics. Start-
up time applies when supply voltage is applied or when PDWN is released.
Parameter
CS3001/CS3002
UnitMin Typ Max
Input Offset Voltage (Note 2)•--±10 µV
Average Input Offset Drift (Note 2)•- ±0.01 ±0.05 µV/ºC
Long Term Input Offset Voltage Stability (Note 3)
Input Bias Current TA = 25º C •-
-±100
--
±1000 pA
pA
Input Offset Current TA = 25º C •-
-±200
--
±2000 pA
pA
Input Noise Voltage Density RS = 100 Ω, f0 = 1 Hz
RS = 100 Ω, f0 = 1 kHz -
-6
6
Input Noise Voltage 0.1 to 10 Hz - 125 nVp-p
Input Noise Current Densityf0 = 1 Hz - 100
Input Noise Current 0.1 to 10 Hz - 1.9 pAp-p
Input Common Mode Voltage Range •-0.1 - (V+)-1.25 V
Common Mode Rejection Ratio (dc) (Note 4)•115 120 - dB
Power Supply Rejection Ratio •120 136 - dB
Large Signal Voltage Gain RL = 2 kΩ to V+/2 (Note 5)•200 300 - dB
Output Voltage Swing RL = 2 kΩ to V+/2
RL = 100 kΩ to V+/2 •+4.7 -
+4.99 -V
V
Slew Rate RL = 2 k, 100 pF 5 - V/µs
Overload Recovery Time - 100 - µs
Supply Current CS3001
CS3002
PWDN active (CS3001 Only) (Note 6)
•
•
•
-
-2.1
3.6 2.8
4.8
15
mA
mA
µA
PWDN Threshold (Note 6)•(V+) -1.0 - - V
Start-up Time (Note 7)•-912 ms
nV/ Hz
nV/ Hz
fA/ Hz
CS3001
CS3002
4DS490F9
ABSOLUTE MAXIMUM RATINGS
2. TYPICAL PERFORMANCE PLOTS
Parameter Min Typ Max Unit
Supply Voltage [(V+) - (V-)] 6.8 V
Input Voltage V- -0.3 V+ +0.3 V
Storage Temperature Range -65 +150 ºC
Noise vs. Frequency (Measured)
1
10
100
0.001 0.01 0.1 1 10
Frequency (Hz)
nV/√Hz
Figure 1. Noise vs. Frequency (Measured)
-
1
0
0
-
5
0
0
5
0
1
0
0
TIM E (Se c)
n
V
01234 5678 910
Figure 3. 0.01 Hz to 10 Hz Noise
1
1.5
2
2.5
3
-40-200 20406080
Temperature (°C)
Supply Current (mA)
2.7 V
5V
6.7 V
Figure 5. Supply Current vs. Temperatur e, CS3001
1
10
100
1000
10 100 1K 10K 100K 1M 10M
Fre quency (Hz)
nV
/
√
Hz
Figure 2. Noise vs. Frequency
Time (1 Hour)
-100
-75
-50
-25
0
25
50
75
100
nV
= 13 nVσ
Figure 4. Offset Voltage Stability (DC to 3.2 Hz)
Temperature (°C)
Supply Current (mA)
2.7 V
6.7 V
2.0
2.5
3.0
3.5
4.0
4.5
-40 -20 0 20 40 60 80
Figure 6. Supply Current vs. Temperatur e, CS3002
CS3001
CS3002
DS490F9 5
Typical Performance Plots (Cont.)
1.5
1.6
1.7
1.8
1.9
2
234567
Supply Voltage (V)
Supply Current (mA)
Figure 7. Supply Current vs. Voltage , CS30 01
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
234567
Supply Voltage (V)
Supply Current (mA)
Figure 8. Supply Current vs. Voltage , CS30 02
-500
-400
-300
-200
-100
0
100
200
300
400
500
Figure 9. Open-loop Gain and Phase vs. Frequency
1 10 100 1k 10k 1M 10M
Frequency (Hz)
100k
GAIN
PHASE
CS3001
CS3002
6DS490F9
Typical Performance Plots (Cont.)
-360
-315
-270
-225
-180
-135
-90
-45
10K 100K 1M 10M
Gain (dB)
Phase (Degrees)
0
20
40
60
80
100
Figure 10. Open-loop Gain and Phase vs. Frequency (Expanded)
Supply Voltage (±V)
Input Bias Current (pA)
A1-
A1+
B1-
A2+
B1+
A2-
B2-
B2+
±1.35 ±2 ±2.5 ±3.35
-200
-150
-150
-100
-100
0
-50
-50
CM = 0 V
Figure 11. Input Bias Current vs. Supply Voltage
CS3001
CS3002
DS490F9 7
Typical Performance Plots (Cont.)
-3
-2
-1
0
1
2
3
012345
Common Mode Voltage (Vs = 5V)
Bias Current
Normalized to CM = 2.5 V
Figure 12. Input Bias Current vs. Common Mode Voltage
-200
-150
-250
-100
-50
V+
V–
+50
+100
+150
+200
+250
012 34 5
Output Current (mA)
Output Voltage (mV)
+125°C
-40°C
+125°C
+25°C
+25°C
-40°C
Figure 13. Voltage Swing vs. Output Curre nt (2.7 V)
-200
-150
-250
-100
-50
V+
V–
+50
+100
+150
+200
+250
012 34 5
Output Current (mA)
Output Voltage (mV)
+125°C
-40°C
+125°C
+25°C
+25°C
-40°C
Figure 14. Voltage Swing vs. Output Current (5 V)
CS3001
CS3002
8DS490F9
3. CS3001/CS3002 OVERVIEW
The CS3001/CS3002 amplifiers are designed for
precision measurement of signals from DC to
2 kHz when operating from a supply voltage of
+2.7 V to +6.7 V (± 1.35 to ± 3.35 V). The ampli-
fiers are designed with a patented architecture that
utilizes multiple amplifier stages to yield very high
open loop gain at frequencies of 10 kHz and below.
The amplifiers yield low noise and low offset drift
while consuming relatively low supply current. An
increase in noise floor above 2 kHz is the result of
intermediate stages of the amplif ier being ope rated
at very low currents. The amplifiers are intended
for amplifying small signals with large gains in ap-
plications where the output of the amplifier can be
band-limited to frequencies below 2 kHz.
3.1 Open-loop Gain and Phase
Response
Figure 15 illustrates the open loop gain and phase
response of the CS3001/CS3002. The gain slope of
the amplifier is about –100 dB/decade between
500 Hz and 60 kHz and transitions to –20 dB/de-
cade between 60 kHz and its unity gain crossover
frequency at about 4.8 MHz. Phase margin at unity
gain is about 70 degrees; gain margin is about
20 dB.
-360
-315
-270
-225
-180
-135
-90
-45
10K 100K 1M 10M
Gain (dB)
Phase (Degrees)
0
20
40
60
80
100
-100 dB/ dec
-20 dB/ dec
Figure 15. CS3001/CS3002 Open-loop Gain and Phase Response
CS3001
CS3002
DS490F9 9
3.2 Open-loop Gain and Stability Compensation
3.2.1 Discussion
The CS3001 and CS3002 achieve ultra-high open
loop gain. Figure 16 illustrates the amplifier in a
non-inverting gain configuration. The open loop
gain and phase plots indicate that the amplifier is
stable for closed-loop gains less than 50 V/V and
R1 ≤100 Ohms. For a gain of 50, the phase margin
is between 40° and 60° depending upon the loading
conditions. As shown in Figure 17, on page 10, the
operational amplifier has an input capacitance at
the + and – signal inputs of typically 50 pF. This
capacitance adds an additional pole in the loop gain
transfer function at a frequency of f = 1/(2πR*Cin)
where R is the parallel combination of R1 and R2
(R1 || R2). A higher value for R produces a pole at
a lower frequency, thus reducing the phase margin.
R1 is recommended to be less than or equal to 100
ohms, which results in a pole at 30 MHz or higher.
If a higher value of R1 is desired, a compensation
capacitor (C2) should be added in parallel with R2.
C2 should be chosen such that R2*C2 ≥ R1*Cin.
R1
R2
Vin
Vo
RS
Figure 16. Non-inverting Gain Config uratio n
CS3001
CS3002
10 DS490F9
The feedback capacitor C2 is required for closed-
loop gains greater than 50 V/V. The capacitor in- troduces a pole and a zero in the loop gain transfer
function,
This indicates that the separation of the pole and
the zero is governed by the closed loop gain. It is
required that the zero falls on the steep slope
(–100 dB/decade) of the loop gain plot so that there
is some gain higher than 0 dB (typically 20 dB) at
the hand-over frequency (the frequency at which
the slope changes from – 100 dB/decade to
–20 dB/decade).
50 pF
50 pF
R1
R2
Vin
Vo
C2
Cin
Cin
Choose C2 so that R2 •C2 ≥?R1 •Cin
Figure 17. Non-inverting Gain Configuration with Compensation
T
1s
z1
-----+
–
1s
p1
-----+
----------------------- Aol
=
P11
2πR1R2
||
()C2
-------------------------------------1
2πR1C2
()
-------------------------
≅=forR
2R1
»
Z11
2πAR
1
×()C2
-----------------------------------=whereA
R2
R1
------=
Z11
2πR2
()C2
-------------------------=
CS3001
CS3002
DS490F9 11
The loop gain plot shown in Figure 18 illustrates
the unity gain configuration, and indicates how this
is modified when using the amplifier in a higher
gain configuration with compensation. If it is con-
figured for higher gain, for example, 60 dB, the
x–axis will move up by 60 dB (line B). Capacitor
C2 adds a zero and a pole. The modified plot indi-
cates the effects of introducing the pole and zero
due to capacitor C2. The pole can be located at any
frequency higher than the hand-over frequency, the
zero has to be at a frequency lower than the hand-
over frequency so as to provide adequate gain mar-
gin. The separation between the pole and the zero
is governed by the closed loop gain. The zero (z1)
occurs at the intersection of the –100 dB/decade
and –80 dB/decade slopes. The point X in the fig-
ure should be at closed loop gain plus 20 dB gain
margin. The value for C2 = 1/(2πR1 P1). Setting
the pole of the filter to P1 = 1 MHz works very well
and is independent of gain. As the closed loop gain
is changed, the zero location is also modified if R1
remains fixed. Capacitor C2 can be increased in
value to limit the amplifier’s rising noise above
2kHz.
-100 dB/dec
|T| (Log gain)
-80 dB/dec
z
1
p
1
Margin
-20 dB/dec
50kHz 1MHz 5MHz
Desired Closed
Loop Gain
X
FREQUENCY
B
Figure 18. Loop Ga in Plot: Unity Gain and with Pol e-zero Compensatio n
CS3001
CS3002
12 DS490F9
3.2.2 Gain Calculations Summary and
Recommendations
Condition #1: |Av| ≤50 and R1 ≤100 Ω
The Opamp is inherently stable for |Av| ≤50 and
R1 ≤100 Ω . No C2 compensation capacitor across
R2 is required.
• |Av| = 1 configuration has 70° phase margin
and 20 dB gain margin.
• |Av| = 50 configuration has phase margin be-
tween 40° for CLOAD ≤100 pF and 60° for
CLOAD =0pF.
Condition #2: |Av| ≤50 and R1 >100 Ω
Compensation capacitor C2 across R2 is required.
Calculate C2 using the following formula:
•C2≥(R1 •Cin) / R2, where Cin = 50 pF
Condition #3: |Av| >50
Compensation capacitor C2 across R2 is required.
Calculate and verify a value for C2 using the fol-
lowing steps.
Calculate the Compensation Capacitor Value:
1) Calculate a value for C2 using the following
formula:
C2 =1/[2π(R1| |R2) •P1], where P1 = 1 MHz
To simplify the calculation, set the po le of the filter
to P1 = 1 MHz. P1 must be set higher than the
opamp’s internal 50 kHz crossover frequency.
2) Calculate a second value for C2 using the fol-
lowing formula:
C2 ≥(R1 •Cin) / R2, where Cin = 50 pF
3) Use the larger of the two values calculated in
steps 1 & 2.
Verify the Opamp Compensation:
Verify the opamp compensation using the open-
loop gain and phase response Bode plot in
Figure 15. Plot the calculated closed loop gain
transfer function and verify the following design
criteria are met:
• Pole P1 > opamp internal 50 kHz crossover fre-
quency
- P1=1/[2π(R1| |R2) •C2], where P1 = 1 MHz
- To simplify the calculation, set the pole to
P1 = 1 MHz.
• Z1 < opamp internal 50 kHz crossover frequency
- Z1=1/(2πR2 •C2)
• Gain margin above the open-loop gain transfer
function is required. A gain margin of +20 dB
above the open loop gain transfer function is
optimal.
3.3 Powerdown (PDWN)
The CS3001 single amplifier provides a power-
down function on pin 1. If this pin is left open the
amplifier will operate normally. If the powerdown
is asserted low, the amplifier will go into a low
power state. There is a pull-up resistor (approxi-
mately 800 kΩ) inside the amplifier from pin 1 to
the V+ supply. The current through this pull-up re-
sistor is the main source of current drain in the
powerdown state.
CS3001
CS3002
DS490F9 13
3.4 Applications
The CS3001 and CS3002 amplifiers are optimum
for applications that require high gain and low drift.
Figure 19 illustrates a thermopile amplifier with a
gain of 650 V/V. The thermopile outputs only a few
millivolts when subjected to infrared radiation. The
amplifier is compensated and bandlimited by C1 in
combination with R2.
Figure 20, on page 13 illustrates a load cell bridge
amplifier with a gain of 768 V/V. The load cell is
excited with +5 V and has a 1 mV/V sensitivity. Its
full scale output signal is amplified to produce a
fully differential ± 3.8 V into the CS5510/12 A/D
converter. This circuit operates from +5 V.
CS3001
R1
100
R2
64.9k
C1
0.015μF
Dexter R esearch
Therm opile 1M
Therm opile A m plifier w ith a G ain of 650 V/V
Figure 19. Thermopile Amplifier with a Gain of 650 V/V
+5 V
VA
1 m V /V
-+
350
Ω
+
-
-
+
x768
140 k
Ω
365
Ω
140 k
Ω
100
Ω
100
Ω
0.22
μ
F
0.22
μ
F
0.047
μ
F
0.1
μ
F
VREF
AIN+
AIN1
V-
V+
CS
SDO
SCLK
CS5510/12
μ
+5 V +5 V
Counter/Timer
SCL K = 10 k Hz to 1 0 0
(32.768
)
SCLK = 10 kHz to 100 kHz
(32.768 nom inal)
Figure 20. Load Cell Bridge Amplifier and A/D Converter
CS3001
CS3002
14 DS490F9
4. PACKAGE DRAWING
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 0.053 0.069 1.35 1.75
A1 0.004 0.010 0.10 0.25
B 0.013 0.020 0.33 0.51
C 0.007 0.010 0.19 0.25
D 0.189 0.197 4.80 5.00
E 0.150 0.157 3.80 4.00
e 0.040 0.060 1.02 1.52
H 0.228 0.244 5.80 6.20
L 0.016 0.050 0.40 1.27
∝0° 8° 0° 8°
JEDEC #: MS-012
8L SOIC (150 MIL BODY) PACKAGE DRAWING
D
H
E
e
b
A1
A
c
L
∝
SEATING
PLANE
1
CS3001
CS3002
DS490F9 15
5. ORDERING INFORMATION
6. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
Model Temperature Package
CS3001-ISZ (lead free) -40 to +85 °C 8-pin SOIC (Lead Fr ee)
CS3002-ISZ (lead free)
Model Number Peak Reflow Temp MSL Rating* Max Floor Life
CS3001-ISZ (lead free) 260 °C 2 365 Days
CS3002-ISZ (lead free)
CS3001
CS3002
16 DS490F9
7. REVISION HISTORY
Revision Date Changes
F3 OCT 2004 Added lead-free device ordering information.
F4 AUG 2005 Added MSL specifications. Updated legal notice. Added leaded (Pb) devices.
F5 AUG 2006 Updated Typical Performance Plots.
F6 SEP 2006 Corrected error in Ordering Information section.
F7 NOV 2007 Added additional information regarding open-loop and gain stability compensation.
F8 OCT 2008 Minor, cosmetic correction to caption for Figu re 10.
F9 JUL 2009 Removed lead-containing devices from ordering information.
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
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