TC74VHCT573AF/AFT/AFK TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VHCT573AF, TC74VHCT573AFT, TC74VHCT573AFK Octal D-Type Latch with 3-State Output The TC74VHCT573A is an advanced high speed CMOS OCTAL LATCH with 3-STATE OUTPUT fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type latch is controlled by a latch enable input (LE) and an output enable input ( OE ). When the OE input is high, the eight outputs are in a high impedance state. The input voltage are compatible with TTL output voltage. This device may be used as a level converter for interfacing 3.3 V to 5 V system. Input protection and output circuit ensure that 0 to 5.5 V can be applied to the input and output (Note) pins without regard to the supply voltage. These structure prevents device destruction due to mismatched supply and input/output voltages such as battery back up, hot board insertion, etc. Note: TC74VHCT573AF TC74VHCT573AFT Output in off-state TC74VHCT573AFK Features * High speed: tpd = 7.7 ns (typ.) at VCC = 5 V * Low power dissipation: ICC = 4 A (max) at Ta = 25C * Compatible with TTL inputs: * Power down protection is provided on all inputs and outputs. VIL = 0.8 V (max) VIH = 2.0 V (min) * Balanced propagation delays: tpLH tpHL * Low noise: VOLP = 1.5 V (max) * Pin and function compatible with the 74 series (74AC/HC/F/ALS/LS etc.) 573 type. Weight SOP20-P-300-1.27A: TSSOP20-P-0044-0.65A: VSSOP20-P-0030-0.50: 0.22 g (typ.) 0.08 g (typ.) 0.03 g (typ.) Start of commercial production 1995-12 1 2014-03-01 TC74VHCT573AF/AFT/AFK Pin Assignment IEC Logic Symbol OE 1 20 VCC D0 2 19 Q0 D1 3 18 Q1 D2 4 17 Q2 D3 5 16 Q3 D4 6 15 Q4 D5 7 14 Q5 D6 8 13 Q6 D7 9 12 Q7 GND 10 11 LE OE LE D0 D1 D2 D3 D4 D5 D6 D7 (1) (11) EN C1 (2) (3) (4) (5) (6) (7) (8) (9) 1D (19) (18) (17) (16) (15) (14) (13) (12) Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 (top view) Truth Table Inputs Output OE LE D H X X Z L L X Qn L H L L L H H H X: Don't care Z: High impedance Qn: Q outputs are latched at the time when the LE input is taken to a low logic level. System Diagram D0 D1 2 LE OE 11 D2 3 D3 4 D4 5 D5 6 D6 7 D7 8 9 D D D D D D D D L Q L Q L Q L Q L Q L Q L Q L Q 1 19 Q0 18 Q1 17 16 Q2 Q3 2 15 Q4 14 Q5 13 Q6 12 Q7 2014-03-01 TC74VHCT573AF/AFT/AFK Absolute Maximum Ratings (Note 1) Characteristics Symbol Rating Unit Supply voltage range VCC -0.5 to 7.0 V DC input voltage VIN -0.5 to 7.0 V DC output voltage VOUT -0.5 to 7.0 (Note 2) -0.5 to VCC + 0.5 (Note 3) V Input diode current IIK -20 mA Output diode current IOK 20 DC output current IOUT 25 mA DC VCC/ground current ICC 75 mA Power dissipation PD 180 mW Storage temperature Tstg -65 to 150 C (Note 4) mA Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook ("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 2: Output in off-state Note 3: High or low state. IOUT absolute maximum rating must be observed. Note 4: VOUT < GND, VOUT > VCC Operating Ranges (Note 1) Characteristics Symbol Rating Unit Supply voltage VCC 4.5 to 5.5 V Input voltage VIN 0 to 5.5 V Output voltage VOUT 0 to 5.5 (Note 2) 0 to VCC (Note 3) V Operating temperature Topr -40 to 85 C Input rise and fall time dt/dV 0 to 20 ns/V Note 1: The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must be tied to either VCC or GND. Note 2: VCC = 0 V Note 3: High or low state 3 2014-03-01 TC74VHCT573AF/AFT/AFK Electrical Characteristics DC Characteristics Characteristics Test Condition Symbol Ta = -40 to 85C Ta = 25C VCC (V) Min Typ. Max Min Max Unit High-level input voltage VIH 4.5 to 5.5 2.0 2.0 V Low-level input voltage VIL 4.5 to 5.5 0.8 0.8 V High-level output voltage VOH VIN = VIH or VIL IOH = -50 A 4.5 4.40 4.50 4.40 IOH = -8 mA 4.5 3.94 3.80 Low-level output voltage VOL VIN = VIH or VIL IOL = 50 A 4.5 0.0 0.1 0.1 IOL = 8 mA 4.5 0.36 0.44 3-state output off-state current IOZ VIN = VIH or VIL VOUT = VCC or GND 5.5 0.25 2.50 A Input leakage current IIN VIN = 5.5 V or GND 0 to 5.5 0.1 1.0 A ICC VIN = VCC or GND 5.5 4.0 40.0 A ICCT Per input: VIN = 3.4 V Other input: VCC or GND 5.5 1.35 1.50 mA IOPD VOUT = 5.5 V 0 0.5 5.0 A Ta = -40 to 85C Unit Quiescent supply current Output leakage current V V Timing Requirements (input: tr = tf = 3 ns) Characteristics Minimum pulse width Symbol Test Condition Ta = 25C VCC (V) Typ. Limit Limit tw (H) 5.0 0.5 6.5 8.5 ns Minimum set-up time ts 5.0 0.5 1.5 1.5 ns Minimum hold time th 5.0 0.5 3.5 3.5 ns (LE) 4 2014-03-01 TC74VHCT573AF/AFT/AFK AC Characteristics (input: tr = tf = 3 ns) Characteristics Test Condition Symbol VCC (V) Propagation delay time tpLH (LE-Q) tpHL Propagation delay time tpLH (D-Q) tpHL tpZL 3-state output enable time tpZH tpLZ 3-state output disable time Output to output skew tpHZ RL = 1 k tosHL Min Typ. Max Min Max 15 7.7 12.3 1.0 13.5 50 8.5 13.3 1.0 14.5 15 5.1 8.5 1.0 9.5 50 5.9 9.5 1.0 10.5 15 6.3 10.9 1.0 12.5 50 7.1 11.9 1.0 13.5 5.0 0.5 50 8.8 11.2 1.0 12.0 ns 5.0 0.5 50 1.0 1.0 ns ns 5.0 0.5 RL = 1 k (Note 1) Unit CL (pF) 5.0 0.5 tosLH Input capacitance Output capacitance Ta = -40 to 85C Ta = 25C ns 5.0 0.5 ns CIN 4 10 10 pF COUT 9 pF 25 pF Power dissipation capacitance CPD (Note 2) Note 1: Parameter guaranteed by design. tosLH = |tpLHm - tpLHn|, tosHL = |tpHLm - tpHLn| Note 2: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr) = CPD*VCC*fIN + ICC / 8 (per latch) And the total CPD when n pcs. of latch operate can be gained by the following equation: CPD (total) = 14 + 11*n Noise Characteristics (input: tr = tf = 3 ns) Characteristics Test Condition Symbol Ta = 25C VCC (V) Typ. Limit Unit Quiet output maximum dynamic VOL VOLP CL = 50 pF 5.0 1.1 1.5 V Quiet output minimum dynamic VOL VOLV CL = 50 pF 5.0 -1.1 -1.5 V Minimum high level dynamic input voltage VIHD CL = 50 pF 5.0 2.0 V Maximum low level dynamic input voltage VILD CL = 50 pF 5.0 0.8 V 5 2014-03-01 TC74VHCT573AF/AFT/AFK Package Dimensions Weight: 0.22 g (typ.) 6 2014-03-01 TC74VHCT573AF/AFT/AFK Package Dimensions Weight: 0.08 g (typ.) 7 2014-03-01 TC74VHCT573AF/AFT/AFK Package Dimensions Weight: 0.03 g (typ.) 8 2014-03-01 TC74VHCT573AF/AFT/AFK RESTRICTIONS ON PRODUCT USE * Toshiba Corporation, and its subsidiaries and affiliates (collectively "TOSHIBA"), reserve the right to make changes to the information in this document, and related hardware, software and systems (collectively "Product") without notice. * This document and any information herein may not be reproduced without prior written permission from TOSHIBA. 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