CY62148G MoBL®
4-Mbit (512K words × 8 bit) Static RAM
with Error-Correcting Code (ECC)
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-95415 Rev. *E Revised December 1, 2017
4-Mbit (512K words × 8 bit) Static RAM with Error-Correcting Code (ECC)
Features
■High speed: 45 ns/55 ns
■Ultra-low standby power
❐Typical standby current: 3.5 A
❐Maximum standby current: 8.7 A
■Embedded ECC for single-bit error correction[1]
■Wide voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, 4.5 V to 5.5 V
■1.0-V data retention
■TTL-compatible inputs and outputs
■Pb-free 32-pin SOIC and 32-pin TSOP II packages
Functional Description
CY62148G is a high-performance CMOS low-power (MoBL)
SRAM device with embedded ECC[1]. This device is offered
multiple pin configurations.
Device is accessed by asserting the chip enable (CE) input LOW.
Data writes are performed by asserting the Write Enable (WE)
input LOW, while providing the data on I/O0 through I/O7 and
address on A0 through A18 pins.
Data reads are performed by asserting the Output Enable (OE)
input and providing the required address on the address lines.
Read data is accessible on the I/O lines (I/O0 through I/O7).
All I/Os (I/O0 through I/O7) are placed in a HI-Z state when the
device is deselected (CE HIGH or control signal OE is
de-asserted).
See the Truth Table – CY62148G on page 12 for a complete
description of read and write modes.
The logic block diagrams are on page 2.
Logic Block Diagram – CY62148G
512K x 8
RAM ARRAY
ROW DECODER
A1
A2
A3
A4
A5
A6
A7
A8
A9
A0
COLUMNDECODER
A10
SENSE
AMPLIFIERS
ECC DECODER
A11
A12
A13
A14
A15
A16
A17
A18
ECC ENCODER DATAIN
DRIVERS
I/O0-I/O7
WE
OE CE
Note
1. This device does not support automatic write-back on error detection.
Document Number: 001-95415 Rev. *E Page 2 of 17
CY62148G MoBL®
Contents
Pin Configurations ...........................................................3
Product Portfolio ..............................................................3
Maximum Ratings .............................................................4
Operating Range ............................................................... 4
DC Electrical Characteristics ..........................................4
Capacitance ......................................................................6
Thermal Resistance ..........................................................6
AC Test Loads and Waveforms .......................................6
Data Retention Characteristics ....................................... 7
Data Retention Waveform ................................................ 7
AC Switching Characteristics .........................................8
Switching Waveforms ......................................................9
Truth Table – CY62148G ................................................ 12
Ordering Information ...................................................... 13
Ordering Code Definitions ......................................... 13
Package Diagrams .......................................................... 14
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure .......................................................15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 17
Worldwide Sales and Design Support ....................... 17
Products ....................................................................17
PSoC®Solutions ....................................................... 17
Cypress Developer Community .................................17
Technical Support ..................................................... 17
Document Number: 001-95415 Rev. *E Page 3 of 17
CY62148G MoBL®
Pin Configurations
Figure 1. 32-pin SOIC/TSOP II pinout
Product Portfolio
Product Range VCC Range (V) Speed (ns)
Power Dissipation
Operating ICC, (mA) Standby, ISB2 (µA)
f = fmax
Typ[2] Max Typ[2] Max
CY62148G18 Industrial 1.65 V–2.2 V 55 – 20 – 10
CY62148G30 2.2 V–3.6 V 45 – 20 3.5 8.7
CY62148G 4.5 V–5.5 V
A15A16 231
A18A14 330
/WEA12 429
A9A5 726
A8
627
A6
/OEA3 924
A10A2 10 23
/CEA1 11 22
I/O7A0 12 21
I/O6
I/O0 13 20
I/O5
I/O1 14 19
I/O4
I/O2 15 18
I/O3
VSS 16 17
VCCA17 132
A11A4 825
A13A7 528
32 pin
TSOP II/
SOIC
Note
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for a VCC range of 1.65 V–2.2 V),
VCC =3V (for V
CC range of 2.2 V–3.6 V), and VCC = 5 V (for VCC range of 4.5 V–5.5 V), TA = 25 °C.
Document Number: 001-95415 Rev. *E Page 4 of 17
CY62148G MoBL®
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ............................... –65 °C to + 150 °C
Ambient temperature
with power applied .................................. –55 °C to + 125 °C
Supply voltage
to ground potential[3] ............................–0.5 V to Vcc + 0.5 V
DC voltage applied to outputs
in HI-Z state[3]...................................... –0.5 V to VCC + 0.5 V
DC input voltage[3] .............................. –0.5 V to VCC + 0.5 V
Output current into outputs (in low state) .................... 20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ................................. >2001 V
Latch-up current .....................................................>140 mA
Operating Range
Grade Ambient Temperature VCC[4]
Industrial –40 C to +85 C 1.65 V to 2.2 V,
2.2 V to 3.6 V,
4.5 V to 5.5 V
DC Electrical Characteristics
Over the operating range of –40 C to 85 C
Parameter Description Test Conditions 45 ns / 55 ns Unit
Min Typ Max
VOH Output HIGH
voltage
1.65 V to 2.2 V VCC = Min, IOH = –0.1 mA 1.4 – – V
2.2 V to 2.7 V VCC = Min, IOH = –0.1 mA 2 – –
2.7 V to 3.6 V VCC = Min, IOH = –1.0 mA 2.2 – –
4.5 V to 5.5 V VCC = Min, IOH = –1.0 mA 2.4 – –
4.5 V to 5.5 V VCC = Min, IOH = –0.1 mA VCC – 0.5[5] ––
VOL Output LOW
voltage
1.65 V to 2.2 V VCC = Min, IOL = 0.1 mA – – 0.2 V
2.2 V to 2.7 V VCC = Min, IOL = 0.1 mA – – 0.4
2.7 V to 3.6 V VCC = Min, IOL = 2.1 mA – – 0.4
4.5 V to 5.5 V VCC = Min, IOL = 2.1 mA – – 0.4
VIH Input HIGH
voltage
1.65 V to 2.2 V – 1.4 – VCC + 0.2[3] V
2.2 V to 2.7 V – 1.8 – VCC + 0.3[3]
2.7 V to 3.6 V – 2 – VCC + 0.3[3]
4.5 V to 5.5 V – 2.2 – VCC + 0.5[3]
VIL Input LOW
voltage
1.65 V to 2.2 V – –0.2[3] –0.4V
2.2 V to 2.7 V – –0.3[3] –0.6
2.7 V to 3.6 V – –0.3[3] –0.8
4.5 V to 5.5 V – –0.5[3] –0.8
IIX Input leakage current GND < VIN < VCC –1 – +1 A
IOZ Output leakage current GND < VOUT < VCC, Output disabled –1 – +1 A
ICC VCC operating supply current Max VCC, IOUT = 0 mA,
CMOS levels
f = 22.22 MHz
(45 ns)
––20mA
f = 18.18 MHz
(55 ns)
––20mA
f = 1 MHz ––6mA
Notes
3. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
4. Full Device AC operation assumes a 100 μs ramp time from 0 to VCC(min) and 200 μs wait time after VCC stabilization.
5. This parameter is guaranteed by design and not tested.
Document Number: 001-95415 Rev. *E Page 5 of 17
CY62148G MoBL®
ISB1[6] Automatic power down
current – CMOS inputs;
VCC = 2.2 V to 3.6 V and
4.5 V to 5.5 V
CE1 > VCC – 0.2 V or CE2 < 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = fmax (address and data only),
f = 0 (OE, and WE), Max VCC
––8.7A
Automatic power down
current – CMOS inputs
VCC = 1.65 V to 2.2 V
––10
ISB2[6] Automatic power down
current – CMOS inputs
VCC = 2.2 V to 3.6 V and
4.5 V to 5.5 V
CE1 > VCC – 0.2 V or
CE2 < 0.2 V,
VIN > VCC – 0.2 V or
VIN < 0.2 V,
f = 0, Max VCC
25 °C [7] –3.53.7A
40 °C [7] ––4.8
70 °C [7] ––7
85 °C
––8.7
Automatic power down
current – CMOS inputs
VCC = 1.65 V to 2.2 V
CE1 > VCC – 0.2 V or
CE2 < 0.2 V,
VIN > VCC – 0.2 V or
VIN < 0.2 V,
f = 0, Max VCC
25 °C [7] –3.54.3
40 °C [7] ––5
70 °C [7] ––7.5
85 °C – – 10
DC Electrical Characteristics (continued)
Over the operating range of –40 C to 85 C
Parameter Description Test Conditions 45 ns / 55 ns Unit
Min Typ Max
Notes
6. Chip enables (CE must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
7. The ISB2 limits at 25 °C, 40 °C, 70 °C, and typical limit at 85 °C are guaranteed by design and not 100% tested.
Document Number: 001-95415 Rev. *E Page 6 of 17
CY62148G MoBL®
Capacitance
Parameter [8] Description Test Conditions Max Unit
CIN Input capacitance TA = 25 °C, f = 1 MHz, VCC = VCC(typ) 10 pF
COUT Output capacitance 10 pF
Thermal Resistance
Parameter [8] Description Test Conditions 32-pin SOIC 32-pin TSOP II Unit
JA Thermal resistance
(junction to ambient)
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
51.79 79.03 °C/W
JC Thermal resistance
(junction to case)
25.12 17.44 °C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms [9]
V
HIGH
V
CC
OUTPUT
R2
30 pF*
*Including
GND
90%
10% 90%
10%
Rise Time = 1 V/ns Fall Time = 1 V/ns
OUTPUT V
TH
Equivalent to: THÉVENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
jig and sope
Parameters 1.8 V 2.5 V 3.0 V 5.0 V Unit
R1 13500 16667 1103 1800
R2 10800 15385 1554 990
RTH 6000 8000 645 639
VTH 0.80 1.20 1.75 1.77 V
Notes
8. Tested initially and after any design or process changes that may affect these parameters.
9. Full-device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
Document Number: 001-95415 Rev. *E Page 7 of 17
CY62148G MoBL®
Data Retention Characteristics
Over the Operating range
Parameter Description Conditions Min Typ [10] Max Unit
VDR VCC for data retention 1 – – V
ICCDR[11, 12] Data retention current VCC = 1.2 V,
CE1 > VCC 0.2 V or CE2 < 0.2 V,
VIN > VCC 0.2 V or VIN < 0.2 V
––13A
tCDR[13, 14] Chip deselect to data retention
time 0––ns
tR[14] Operation recovery time 45/55 – – ns
Data Retention Waveform
Figure 3. Data Retention Waveform
tCDR tR
VDR=1.0V
DATARETENTIONMODE
VCC(m in) VCC(m in)
VCC
CE
Notes
10. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V–2.2 V), VCC =3V
(for VCC range of 2.2 V–3.6 V), and VCC = 5 V (for VCC range of 4.5 V–5.5 V), TA = 25 °C.
11. Chip enables CE must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
12. ICCDR is guaranteed only after device is first powered up to VCC(min) and then brought down to VDR.
13. These parameters are guaranteed by design.
14. Full-device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
Document Number: 001-95415 Rev. *E Page 8 of 17
CY62148G MoBL®
AC Switching Characteristics
Parameter [15, 16] Description 45 ns 55 ns Unit
Min Max Min Max
Read Cycle
tRC Read cycle time 45 –55 –ns
tAA Address to data valid –45 –55 ns
tOHA Data hold from address change 10 –10 –ns
tACE CE LOW to data valid –45 –55 ns
tDOE OE LOW to data valid –22 –25 ns
tLZOE OE LOW to Low impedance[17] 5 – 5 – ns
tHZOE OE HIGH to HI-Z[17, 18] –18 –18 ns
tLZCE CE LOW to Low impedance[17] 10 –10 –ns
tHZCE CE HIGH to HI-Z[17, 18] –18 –18 ns
tPU CE LOW to power-up 0 – 0 – ns
tPD CE HIGH to power-down –45 –55 ns
Write Cycle [19, 20]
tWC Write cycle time 45 –55 –ns
tSCE CE LOW to write end 35 –45 –ns
tAW Address setup to write end 35 –45 –ns
tHA Address hold from write end 0 – 0 – ns
tSA Address setup to write start 0 – 0 – ns
tPWE WE pulse width 35 –40 –ns
tSD Data setup to write end 25 –25 –ns
tHD Data hold from write end 0 – 0 – ns
tHZWE WE LOW to HI-Z[17, 18] –18 –20 ns
tLZWE WE HIGH to Low impedance[17] 10 –10 –ns
Notes
15. Test conditions assume a signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse
levels of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3 V). Test conditions for the read cycle use output loading shown in AC Test Loads and Waveforms section, unless
specified otherwise.
16. These parameters are guaranteed by design.
17. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
18. tHZOE, tHZCE and tHZWE transitions are measured when the outputs enter a high-impedance state.
19. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL,All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write.
20. The minimum pulse width in Write Cycle No. 3 (WE Controlled, OE LOW) should be equal to sum of tSD and tHZWE.
Document Number: 001-95415 Rev. *E Page 9 of 17
CY62148G MoBL®
Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled) [21, 22]
Figure 5. Read Cycle No. 2 (OE Controlled) [22, 23]
ADDRESS
DATA I / O
VALID DATA OUT
VALID
tRC
tOHA
tAA
PREVIOUS DATAOUT
Notes
21. The device is continuously selected. OE = VIL, CE = VIL.
22. WE is HIGH for Read cycle.
23. Address valid prior to or coincident with CE LOW transition.
Document Number: 001-95415 Rev. *E Page 10 of 17
CY62148G MoBL®
Figure 6. Write Cycle No. 1 (WE Controlled) [24, 25, 26]
Switching Waveforms (continued)
ADDRESS
CE
DATA I/O
tWC
tSCE
tHD
tSD
tBW
BHE/
BLE
tAW tHA
tSA tPWE
tLZWE
tHZWE
WE
DATAIN VALID
Notes
24. WE is HIGH for Read cycle.
25. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write.
26. Data I/O is in a HI-Z state if CE = VIH, or OE = VIH.
Document Number: 001-95415 Rev. *E Page 11 of 17
CY62148G MoBL®
Figure 7. Write Cycle No. 2 (CE Controlled) [27, 28]
Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [27, 28, 29]
Switching Waveforms (continued)
ADDRESS
CE
WE
BHE /
BLE
DATA I/O
OE
tWC
tSCE
tAW
tSA
tPWE
tHA
tBW
tHD
tHZOE
DATAIN VALID
tSD
Notes
27. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write.
28. Data I/O is in HI-Z state if CE = VIH, or OE = VIH
29. The minimum write pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be sum of tHZWE and tSD.
Document Number: 001-95415 Rev. *E Page 12 of 17
CY62148G MoBL®
Truth Table – CY62148G
CE WE OE Inputs/Outputs Mode Power Configuration
HX
[30] X[30] HI-Z Deselect/Power-down Standby (ISB) 512 K × 8
L H L Data Out (I/O0–I/O7)ReadActive (I
CC)512 K × 8
L H H HI-Z Output disabled Active (ICC)512 K × 8
LLX
[30] Data In (I/O0–I/O7) Write Active (ICC)512 K × 8
Note
30. The ‘X’ (Don’t care) state for the chip enables refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
Document Number: 001-95415 Rev. *E Page 13 of 17
CY62148G MoBL®
Ordering Code Definitions
Ordering Information
Speed
(ns)
Voltage
Range Ordering Code
Package
Diagram Package Type Operating
Range
45 2.2 V–3.6 V CY62148G30-45SXI 51-85081 32-pin SOIC (450 Mils) Industrial
CY62148G30-45SXIT 51-85081 32-pin SOIC (450 Mils), Tape and Reel
CY62148G30-45ZSXI 51-85095 32-pin TSOP II
CY62148G30-45ZSXIT 51-85095 32-pin TSOP II, Tape and Reel
4.5 V–5.5 V CY62148G-45SXI 51-85081 32-pin SOIC (450 Mils)
CY62148G-45SXIT 51-85081 32-pin SOIC (450 Mils), Tape and Reel
CY62148G-45ZSXI 51-85095 32-pin TSOP II
CY62148G-45ZSXIT 51-85095 32-pin TSOP II, Tape and Reel
55 1.65 V–2.2 V CY62148G18-55ZSXI 51-85095 32-pin TSOP II
CY62148G18-55ZSXIT 51-85095 32-pin TSOP II, Tape and Reel
X: blank or T
blank = Bulk; T = Tape and Reel
Temperature Range: I = Industrial
Pb-free
Package Type: XX = S or ZS
S = 32-pin SOIC
ZS = 32-pin TSOP II
Speed Grade: XX: 45 or 55
45 = 45 ns; 55 = 55 ns
Voltage Range: XX = 30 or 18 or no character
30 = 3 V typ; 18 = 1.8 V typ; no character = 5 V typ
Process Technology: G = 65 nm
Bus Width: 8 = × 8
Density: 4 = 4-Mbit
Family Code: 621 = MoBL SRAM family
Company ID: CY = Cypress
CY XX XX
621 48GX
-XX IX
Document Number: 001-95415 Rev. *E Page 14 of 17
CY62148G MoBL®
Package Diagrams
Figure 9. 32-pin SOIC (450 Mils) S32.45/SZ32.45 Package Outline, 51-85081
Figure 10. 32-pin TSOP II (20.95 × 11.76 × 1.0 mm) ZS32 Package Outline, 51-85095
51-85081 *E
51-85095 *D
Document Number: 001-95415 Rev. *E Page 15 of 17
CY62148G MoBL®
Acronyms Document Conventions
Units of Measure
Acronym Description
CE chip enable
CMOS complementary metal oxide semiconductor
I/O input/output
OE output enable
SRAM static random access memory
TSOP thin small outline package
VFBGA very fine-pitch ball grid array
WE write enable
Symbol Unit of Measure
°C degree Celsius
MHz megahertz
Amicroamperes
smicroseconds
mA milliamperes
mm millimeters
ns nanoseconds
ohms
%percent
pF picofarads
Vvolts
Wwatts
Document Number: 001-95415 Rev. *E Page 16 of 17
CY62148G MoBL®
Document History Page
Document Title: CY62148G MoBL®, 4-Mbit (512K words × 8 bit) Static RAM with Error-Correcting Code (ECC)
Document Number: 001-95415
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
*B 5054381 NILE 12/17/2015 Changed status from Preliminary to Final.
*C 5082528 NILE 01/12/2016 Updated Ordering Information:
Updated part numbers.
Completing Sunset Review.
*D 5432526 NILE 09/10/2016 Updated Maximum Ratings:
Updated Note 3 (Replaced “2 ns” with “20 ns”).
Updated DC Electrical Characteristics:
Changed minimum value of VIH parameter from 2.0 V to 1.8 V corresponding
to Operating Range “2.2 V to 2.7 V”.
Updated Ordering Information:
Updated part numbers.
Updated to new template.
*E 5979578 AESATMP8 12/01/2017 Updated logo and Copyright.
Document Number: 001-95415 Rev. *E Revised December 1, 2017 Page 17 of 17
© Cypress Semiconductor Corporation, 2015-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
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provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
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CY62148G MoBL®
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