9FG830
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI 1680E—04/04/17
Eight Output Differential Frequency Generator
for PCIe Gen3 and QPI
1
DATASHEET
General Description:
The 9FG830 is a Frequency Timing Generator that provides 8
HCSL differential output pairs. These outputs support PCI-Express
Gen3, and QPI applications. The part supports Spread Spectrum
and synthesizes several additional output frequencies from either
a 14.31818 MHz crystal, a 25 MHz crystal or reference input clock.
The 9FG830 also outputs a copy of the reference clock. Complete
control of the device is available via strapping pins or via the
SMBus interface.
Recommended Application:
8 Output Differential Output Frequency Generator for PCIe Gen3
and QPI
Output Features:
• 8 - 0.7V current mode differential HCSL output pairs
• 1 - 3.3V LVTTL REF output
Features/Benefits:
• Pin-to-Pin with 9FG108D; Easy upgrade to PCIe Gen3
• Generates common frequencies from 14.318 MHz or 25
MHz; single part supports mulitple applications
• Provides copy of reference output; eleminates need for
additional crystal or oscillator
• Three spread spectrum modes: -0.5%, +/-0.25%, and off;
EMI reduction
• Unused outputs may be disabled in Hi-Z; save system
power
• Device may be configured by SMBus and/or strap pins;
can be used in systems without SMBus
Key Specifications:
• Cycle-to-cycle jitter: < 50ps with 25MHz input
• Output-to-output skew: <50ps
• Phase jitter: PCIe Gen3 < 1ps rms
• Phase jitter: QPI 9.6GB/s < 0.2ps rms
• 10 ppm synthesis error with 25MHz input and Spread Off
Functional Block Diagram
STOP
LOGIC
XIN/CLKIN
X2
DIF(7:0)
CONTROL
LOGIC
SPREAD
FS(2:0)
SDATA
SCLK
SEL14M_25M#
DIF_STOP#
PROGRAMMABLE
SPREAD PLL
8
IREF
OSC
REFOUT
OE(7:0)
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI 1680E—04/04/17
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
2
Pin Configuration
Power Groups
VDD GND
34
10,14,19,31,36,40 15,35
N/A 47
48 47
IREF
Analog VDD & GND for PLL Core
Descri
p
tion
Pin Number
REFOUT, Digital Inputs, SMBus
DIF Outputs
Frequency Select Table
SEL14M_25M#
(FS3) FS2 FS1 FS0 OUTPUT(MHz)
0 0 0 0 100.00
0 0 0 1 125.00
0 0 1 0 133.33
0 0 1 1 166.67
0 1 0 0 200.00
0 1 0 1 266.67
0 1 1 0 333.33
0 1 1 1 400.00
1 0 0 0 100.00
1 0 0 1 125.00
1 0 1 0 133.33
1 0 1 1 166.67
1 1 0 0 200.00
1 1 0 1 266.67
1 1 1 0 333.33
1 1 1 1 400.00
XIN/CLKIN 1 48 VDDA
X2 2 47 GNDA
VDD 3 46 IREF
GND 4 45 vFS0
REFOUT 5 44 vFS1
vFS2 6 43 vOE_0
vOE_7 7 42 DIF_0
DIF_7 8 41 DIF_0#
DIF_7# 9 40 VDD
VDD 10 39 DIF_1
DIF_6 11 38 DIF_1#
DIF_6# 12 37 ^OE_1
^OE_6 13 36 VDD
VDD 14 35 GND
GND 15 34 ^OE_2
^OE_5 16 33 DIF_2
DIF_5 17 32 DIF_2#
DIF_5# 18 31 VDD
VDD 19 30 DIF_3
DIF_4 20 29 DIF_3#
DIF_4# 21 28 vOE_3
vOE_4 22 27 ^SEL14M_25M#
SDATA 23 26 vSPREAD
SCLK 24 25 DIF_STOP#
9FG830
^ indicates internal 120K pull up
v indicates internal 120K pull down
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI 1680E—04/04/17
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
3
Pin Description
PIN # PIN NAME PIN TYPE DESCRIPTION
1 XIN/CLKIN IN Crystal input or Reference Clock input
2 X2 OUT Crystal output, Nominally 14.318MHz
3 VDD PWR Power supply, nominal 3.3V
4 GND PWR Ground pin.
5 REFOUT OUT Reference Clock output
6 vFS2 IN Frequency select pin. This pin has an internal 120k pull down resistor
7 vOE_7 IN Active high input for enabling output 7. This pin has a 120kohm pull down.
0 =disable outputs, 1= enable outputs
8 DIF_7 OUT 0.7V differential true clock output
9 DIF_7# OUT 0.7V differential Complementary clock output
10 VDD PWR Power supply, nominal 3.3V
11 DIF_6 OUT 0.7V differential true clock output
12 DIF_6# OUT 0.7V differential Complementary clock output
13 ^OE_6 IN Active high input for enabling output 6. This pin has an internal 120kohm pull up.
0 = disable outputs, 1= enable outputs
14 VDD PWR Power supply, nominal 3.3V
15 GND PWR Ground pin.
16 ^OE_5 IN Active high input for enabling output 5. This pin has an internal 120kohm pull up.
0 = disable outputs, 1= enable outputs
17 DIF_5 OUT 0.7V differential true clock output
18 DIF_5# OUT 0.7V differential Complementary clock output
19 VDD PWR Power supply, nominal 3.3V
20 DIF_4 OUT 0.7V differential true clock output
21 DIF_4# OUT 0.7V differential Complementary clock output
22 vOE_4 IN Active high input for enabling output 4. This pin as an internal 120kohm pull down.
0 =disable outputs, 1= enable outputs
23 SDATA I/O Data pin for SMBus circuitry, 5V tolerant.
24 SCLK IN Clock pin of SMBus circuitry, 5V tolerant.
25 DIF_STOP# IN Active low input to stop differential output clocks.
26 vSPREAD IN Asynchronous, active high input to enable spread spectrum functionality. This pin has
a 120Kohm pull down resistor.
27 ^SEL14M_25M# IN
Select 14.31818 MHz or 25 Mhz input frequency. This pin has an internal 120kohm
pull up resistor.
1 = 14.31818 MHz, 0 = 25 MHz
28 vOE_3 IN
Active high input for enabling output 3. This pin has an internal 120kohm pull down
resistor.
0 =disable outputs, 1= enable outputs
29 DIF_3# OUT 0.7V differential Complementary clock output
30 DIF_3 OUT 0.7V differential true clock output
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI 1680E—04/04/17
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
4
Pin Description (Continued)
31 VDD PWR Power supply, nominal 3.3V
32 DIF_2# OUT 0.7V differential Complementary clock output
33 DIF_2 OUT 0.7V differential true clock output
34 ^OE_2 IN
Active high input for enabling output 2. This pin has in internal 120kohm pull up
resistor.
0 = disable outputs, 1= enable outputs
35 GND PWR Ground pin.
36 VDD PWR Power supply, nominal 3.3V
37 ^OE_1 IN
Active high input for enabling output 1. This pin has an internal 120kohm pull up
resistor.
0 = disable outputs, 1= enable outputs
38 DIF_1# OUT 0.7V differential Complementary clock output
39 DIF_1 OUT 0.7V differential true clock output
40 VDD PWR Power supply, nominal 3.3V
41 DIF_0# OUT 0.7V differential Complementary clock output
42 DIF_0 OUT 0.7V differential true clock output
43 vOE_0 IN
Active high input for enabling output 0. This pin has an internal 120kohm pull down
resistor.
0 =disable outputs, 1= enable outputs
44 vFS1 IN 3.3V Frequency select latched input pin with internal 120kohm pull down resistor.
45 vFS0 IN 3.3V Frequency select latched input pin with internal 120kohm pull down resistor.
46 IREF OUT
This pin establishes the reference current for the differential current-mode output pairs.
This pin requires a fixed precision resistor tied to ground in order to establish the
appropriate current. 475 ohms is the standard value.
47 GNDA PWR Ground pin for the PLL core.
48 VDDA PWR 3.3V power for the PLL core.
Note:
^
indicates internal 120K pull up
v indicates internal 120K pull down
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI 1680E—04/04/17
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
5
Electrical Characteristics - Absolute Maximum Ratings
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
3.3V Core Supply Voltage VDDA 4.6 V 1,2
3.3V Logic Supply Voltage VDD 4.6 V 1,2
Input Low Voltage VIL GND-0.5 V 1
Input High Voltage VIH Except for SMBus interface VDD+0.5V V 1
Input High Voltage VIHSMB SMBus clock and data pins 5.5V V 1
Storage Temperature Ts -65 150 °C1
Junction Temperature Tj 125 °C 1
Input ESD protection ESD prot Human Body Model 2000 V 1
1Guaranteed by desi
g
n and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor
g
uaranteed.
Electrical Characteristics - Input/Supply/Common Parameters
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
TCOM Commmercial range 0 70 °C 1
TIND Industrial range -40 85 °C 1
Input High Voltage VIH
Single-ended inputs, except SMBus, low
threshold and tri-level inputs 2V
DD + 0.3 V 1
Input Low Voltage VIL
Single-ended inputs, except SMBus, low
threshold and tri-level inputs GND - 0.3 0.8 V 1
IIN Single-ended inputs, VIN = GND, VIN = VDD -5 5 uA 1
IINP
Single-ended inputs
VIN = 0 V; Inputs with internal pull-up resistors
VIN = VDD; Inputs with internal pull-down resistors
-200 200 uA 1
SEL14M_25M# = 0 25 MHz 1
SEL14M_25M# = 1 14.31818 MHz 1
Pin Inductance L
p
in 7nH1
CIN Logic Inputs 1.5 5 pF 1
CINXTAL Crystal inputs 6 pF 1
COU
T
Output pin capacitance 6 pF 1
Clk Stabilization TSTAB
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock 2.5 ms 1,2
SS Modulation Frequency fMODIN
Allowable Frequency
(Trian
g
ular Modulation) 30 33 kHz 1
OE# Latency tLATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion 1 3 cycles 1,3
Tdrive_STOP# tDRVDS
DIF output enable after
DIF_STOP# de-assertion 300 us 1,3
Tfall t
F
Fall time of control inputs 5 ns 1,2
Trise t
Rise time of control inputs 5 ns 1,2
SMBus Input Low Voltage VILSMB 0.8 V 1
SMBus Input High Voltage VIHSMB 2.1 VDDSMB V1
SMBus Output Low Voltage VOLSMB @ IPULLUP 0.4 V 1
SMBus Sink Current IPULLUP @ VOL 4mA1
Nominal Bus Voltage VDDSMB 3V to 5V +/- 10% 2.7 5.5 V 1
SCLK/SDATA Rise Time tRSMB (Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1
SCLK/SDATA Fall Time tFSMB (Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1
SMBus Operating
Frequency fMAXSMB Maximum SMBus operating frequency 100 kHz 1
1Guaranteed by desi
g
n and characterization, not 100% tested in production.
2Control input must be monotonic from 20% to 80% of input swin
g
.
Ambient Operating
Temperature
Input Current
3Time from deassertion until out
p
uts are >200 mV
Capacitance
Input Frequency Fin
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI 1680E—04/04/17
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
6
Electrical Characteristics - DIF 0.7V Current Mode Differential Outputs
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%, See Test Loads for loading conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Slew rate Trf Scope averaging on 1 4 V/ns 1, 2, 3
Slew rate matchin
g
∆Trf Slew rate matchin
g
, Scope avera
g
in
g
on 20 %1, 2, 4
Voltage High VHigh 660 850 1
Voltage Low VLow -150 150 1
Max Volta
g
eVmax 1150 1
Min Volta
g
e Vmin -300 1
Vswing Vswing Scope averaging off 300 mV 1, 2
Crossing Voltage (abs) Vcross_abs Scope averaging off 250 550 mV 1, 5
Crossing Voltage (var) ∆-Vcross Scope averaging off 140 mV 1, 6
2 Measured from differential waveform
6 The total variation of all Vcross measurements in a particular system. This is a subset of V_cross_min/max (V_cross absolute)
allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute.
mV
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
Measurement on single ended signal using
absolute value. (Scope avera
g
in
g
off) mV
1Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA.
IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω (100Ω differential impedance).
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4 Matching applies to rising edge rate of Clock / falling edge rate of Clock#. It is measured in a +/-75mV window centered on the
average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscillosco
p
e uses for the ed
g
e rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
Electrical Characteristics - Current Consumption
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%, See Test Loads for loading conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
IDD3.3 VDD, All outputs active @100MHz 250 mA 1
IDDA3. 3OP VDDA, All outputs active @100MHz 28 mA 1
IDD3.3 VDD, All outputs active @400MHz 200 mA 1
IDDA3. 3OP VDDA, All outputs active @400MHz 28 mA 1
IDD3.3DS VDD, All DIF pairs stopped driven 190 mA 1
IDDA3. 3DS VDDA, All DIF pairs stopped driven 28 mA 1
IDD3.3DZ VDD, All DIF pairs stopped Hi-Z 38 mA 1
IDDA3.3DZ VDDA, All DIF pairs stopped Hi-Z 28 mA 1
1Guaranteed by desi
g
n and characterization, not 100% tested in production.
2 IREF = VDD
/
(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.
Operating Supply Current
DIF_STOP# Current
Electrical Characteristics - Output Duty Cycle, Jitter, and Skew Characterisitics
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Duty Cycle tD
C
Measured differentially, PLL Mode 45 55 % 1
Skew, Output to Output tsk3 VT = 50% 50 ps 1
Jitter, Cycle to cycle t
j
c
y
c-c
y
c25M input 50 ps 1,3
Jitter, Cycle to cycle tjcyc-cyc 14.318M input 60 ps 1,3
1Guaranteed by desi
g
n and characterization, not 100% tested in production.
2 IREF = VDD
/
(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.
3 Measured from differential waveform
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI 1680E—04/04/17
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
7
Electrical Characteristics - Phase Jitter Parameters
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%, See Test Loads for loading conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
t
jp
hPCIeG1 PCIe Gen 1 86 ps (p-p) 1,2,3,6
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz 3ps
(rms) 1,2,6
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz) 3.1 ps
(rms) 1,2,6
tjphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz) 1ps
(rms)
1,2,4,5,
6
QPI & SMI
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI) 0.5 ps
(rms) 1,5,6
QPI & SMI
(100MHz, 8.0Gb/s, 12UI) 0.3 ps
(rms) 1,5,6
QPI & SMI
(100MHz, 9.6Gb/s, 12UI) 0.2 ps
(rms) 1,5,6
1 Guaranteed by design and characterization, not 100% tested in production.
6 Applies to all differential outputs
3 Sam
p
le size of at least 100K c
y
cles. This fi
g
ures extra
p
olates to 108
p
s
p
k-
p
k @ 1M c
y
cles for a BER of 1-12.
4 Sub
j
ect to final radification b
y
PCI SIG.
tjphQPI_SMI
5 Calculated from Intel-su
pp
lied Clock Jitter Tool v 1.6.3
Phase Jitter, QPI/SMI
2 See htt
p
://www.
p
cisi
g
.com for com
p
lete s
p
ecs
tjphPCIeG2
Phase Jitter, PCI Express
Electrical Characteristics - REF-14.318/25 MHz
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%; See Test Loads for Loads for loading conditions.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
Long Accuracy ppm see Tperiod min-max values ppm 1,2
Clock period T
p
eriod 14.318MHz output nominal 69.8413 ns 1,2
Clock period T
p
eriod 25.000MHz output nominal 40 ns 1,2
Output High Voltage VOH IOH = -1 mA 2.4 V 1
Output Low Voltage VOL IOL = 1 mA 0.4 V 1
Output High Current IOH VOH @MIN = 1.0 V, VOH@MAX = 3.135 V -29 -23 mA 1
Output Low Current IOL VOL @MIN = 1.95 V, VOL @MAX = 0.4 V 29 27 mA 1
Rise/Fall Time trf1 VOL = 0.4 V, VOH = 2.4 V 0.5 2 ns 1
Duty Cycle dt1 VT = 1.5 V 45 55 % 1
Jitter tjcyc-cyc VT = 1.5 V 100 250 ps 1
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 14.31818 or 25.00 MHz
0
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI 1680E—04/04/17
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
8
Common Recommendations for Differential Routing Dimension or Value Unit Notes
L1 length, route as non-coupled 50ohm trace 0.5 max inch 1
L2 length, route as non-coupled 50ohm trace 0.2 max inch 1
L3 length, route as non-coupled 50ohm trace 0.2 max inch 1
Rs 33 ohm 1
Rt 49.9 ohm 1
Down Device Differential Routing
L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max inch 1
L4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max inch 1
Differential Routing to PCI Express Connector
L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max inch 2
L4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch 2
S R C Ref er en c e Clo c k
HCSL Output Buffer
L1
L1'
Rs
L2
L2'
Rs
L4'
L4
L3L3'
Rt Rt PCI Express
Down Device
REF_CLK Input
Figure 1: Down Device Routing
(Test Load)
HCSL Output Buffer
L1
L1'
Rs
L2
L2'
Rs
L4'
L4
L3L3'
Rt Rt PCI Express
Add-in Board
REF_CLK Input
Figure 2: PCI Express Connector Routing
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI 1680E—04/04/17
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
9
Vdiff Vp-p Vcm R1 R2 R3 R4 Note
0.45v 0.22v 1.08 33 150 100 100
0.58 0.28 0.6 33 78.7 137 100
0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible
0.60 0.3 1.2 33 174 140 100 Standard LVDS
R1a = R1b = R1
R2a = R2b = R2
Alte rnative Term i nation for LVDS and othe r Comm on Differe ntial S i gnal s (Figure 3)
HCSL Output Buffer
L1
L1'
R1b
L2
L2'
R1a
L4'
L4
L3
R2a R2b Down Device
REF_CLK Input
Figure 3
L3'
R3 R4
Component Value Note
R5a, R5b 8.2K 5%
R6a, R6b 1K 5%
Cc 0.1 µF
Vcm 0.350 volts
Ca bl e Conne cte d AC Couple d Appli ca tion (fi gure 4)
PCIe Device
REF_CLK Input
Figure 4
R5a
L4'
L4
3.3 Volts
R5b
R6a R6b
Cc
Cc
9FGxxx REF Output
33
Figure 5. REF Output Test Load
5pF
Zo = 50 ohms
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI 1680E—04/04/17
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
10
Differential Clock Tolerances x1 - 25MHz
Clock Periods - Differential Outputs with Spread Spectrum Disabled
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
-c2c jitter
AbsPer
Min
-SSC
Short-Term
Average
Min
- ppm
Long-Term
Average
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Max
+SSC
Short-
Term
Average
Max
+c2c jitter
AbsPer
Max
0 100.00 9.95000 10.00000 10.00000 10.00000 10.05000 ns 1,2
0 125.00 7.95000 8.00000 8.00000 8.00000 8.05000 ns 1,2
0 133.33 7.45000 7.50000 7.50000 7.50000 7.55000 ns 1,2
10 166.67 5.94994 5.99994 6.00000 6.00006 6.05006 ns 1,2
0 200.00 4.95000 5.00000 5.00000 5.00000 5.05000 ns 1,2
6 266.67 3.69998 3.74998 3.75000 3.75002 3.80002 ns 1,2
10 333.33 2.94997 2.99997 3.00000 3.00003 3.05003 ns 1,2
0 400.00 2.45000 2.50000 2.50000 2.50000 2.55000 ns 1,2
Clock Periods - Differential Outputs with Spread Spectrum Enabled
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
-c2c jitter
AbsPer
Min
-SSC
Short-Term
Average
Min
- ppm
Long-Term
Average
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Max
+SSC
Short-
Term
Average
Max
+c2c jitter
AbsPer
Max
96 99.75 9.94910 9.99910 10.02410 10.02506 10.02603 10.05103 10.10103 ns 1,2
19 124.69 7.94990 7.99990 8.01990 8.02005 8.02020 8.04020 8.09020 ns 1,2
96 133.00 7.44933 7.49933 7.51808 7.51880 7.51952 7.53827 7.58827 ns 1,2
10 166.25 5.94998 5.99998 6.01498 6.01504 6.01510 6.03010 6.08010 ns 1,2
96 199.50 4.94955 4.99955 5.01205 5.01253 5.01301 5.02551 5.07551 ns 1,2
-98 266.00 3.70039 3.75039 3.75977 3.75940 3.75903 3.76841 3.81841 ns 1,2
10 332.50 2.94999 2.99999 3.00749 3.00752 3.00755 3.01505 3.06505 ns 1,2
96 399.00 2.44978 2.49978 2.50603 2.50627 2.50651 2.51276 2.56276 ns 1,2
1Guaranteed by design and characterization, not 100% tested in production.
DIF
2 All Long Term Accuracy specifications are guaranteed with the assumption that the REF output is tuned to the exact target XTAL
frequency.
Notes
Measurement Window
Units
SSC ON
-0.5%
Down
Spread
Center
Freq.
MHz
Notes
Measurement Window
Units
Center
Freq.
MHz
Synthesis
Error
(ppm)
SSC OFF
or SSC +/-
0.25%
Center
Spread
Synthesis
Error
(ppm)
DIF
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI 1680E—04/04/17
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
11
Differential Clock Tolerances x1 - 14.31818MHz
Clock Periods - Differential Outputs with Spread Spectrum Disabled
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
-c2c jitter
AbsPer
Min
-SSC
Short-Term
Average
Min
- ppm
Long-Term
Average
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Max
+SSC
Short-
Term
Average
Ma
x
+c2c jitter
AbsPer
Max
35 100.00 9.94965 9.99965 10.00000 10.00035 10.05035 ns 1,2
-114 125.00 7.95091 8.00091 8.00000 7.99909 8.04909 ns 1,2
35 133.33 7.44974 7.49974 7.50000 7.50026 7.55026 ns 1,2
-104 166.67 5.95062 6.00062 6.00000 5.99937 6.04937 ns 1,2
35 200.00 4.94983 4.99983 5.00000 5.00018 5.05018 ns 1,2
42 266.67 3.69984 3.74984 3.75000 3.75016 3.80016 ns 1,2
-104 333.33 2.95031 3.00031 3.00000 2.99969 3.04969 ns 1,2
35 400.00 2.44991 2.49991 2.50000 2.50009 2.55009 ns 1,2
Clock Periods - Differential Outputs with Spread Spectrum Enabled
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
-c2c jitter
AbsPer
Min
-SSC
Short-Term
Average
Min
- ppm
Long-Term
Average
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Max
+SSC
Short-
Term
Average
Ma
x
+c2c jitter
AbsPer
Max
199 99.75 9.94807 9.99807 10.02307 10.02506 10.02706 10.05206 10.10206 ns 1,2
-100 124.69 7.95085 8.00085 8.02085 8.02005 8.01925 8.03925 8.08925 ns 1,2
199 133.00 7.44855 7.49855 7.51730 7.51880 7.52029 7.53904 7.58904 ns 1,2
10 166.25 5.94998 5.99998 6.01498 6.01504 6.01510 6.03010 6.08010 ns 1,2
199 199.50 4.94903 4.99903 5.01153 5.01253 5.01353 5.02603 5.07603 ns 1,2
-140 266.00 3.70055 3.75055 3.75992 3.75940 3.75887 3.76825 3.81825 ns 1,2
10 332.50 2.94999 2.99999 3.00749 3.00752 3.00755 3.01505 3.06505 ns 1,2
199 399.00 2.44952 2.49952 2.50577 2.50627 2.50676 2.51301 2.56301 ns 1,2
1Guaranteed by desi
g
n and characterization, not 100% tested in production.
Center
Freq.
MHz
Synthesis
Error
(ppm)
SSC OFF
or SSC +/-
0.25%
Center
Spread
Synthesis
Error
(ppm)
DIF
DIF
2 All Long Term Accuracy specifications are guaranteed with the assumption that the REF output is tuned to the exact target XTAL
frequency.
Notes
Measurement Window
Units
SSC ON
-0.5%
Down
Spread
Center
Freq.
MHz
Notes
Measurement Window
Units
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI 1680E—04/04/17
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
12
General SMBus serial interface information for the 9FG830
How to Write:
•Controller (host) sends a start bit.
• Controller (host) sends the write address DC (H)
• IDT clock will
acknowledge
• Controller (host) sends the begining byte location = N
• IDT clock will
acknowledge
• Controller (host) sends the data byte count = X
• IDT clock will
acknowledge
• Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
• IDT clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address DC (H)
• IDT clock will
acknowledge
• Controller (host) sends the begining byte
location = N
• IDT clock will
acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address DD (H)
• IDT clock will
acknowledge
• IDT clock will send the data byte count = X
• IDT clock sends
Byte N + X -1
• IDT clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
IDT (Slave /Re ce iver)
T
WR
ACK
ACK
ACK
ACK
ACK
PstoP bit
X Byte
Index Block Write Operatio n
Slave Address DC(H)
Beginning Byte = N
WRite
starT bit
Con tro l ler (Ho st)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T starT bit
WR WRite
RT Repeat starT
RD ReaD
Beginning Byte N
Byte N + X - 1
N Not acknowledge
PstoP bit
Slave Address DD(H)
Index Block Read Operation
Slave Address DC(H)
Beginning Byte = N
ACK
ACK
Data Byte Count = X
ACK
IDT (Slave /Re ce ive r)
Co ntrol ler (Host)
X Byte
ACK
ACK
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI 1680E—04/04/17
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
13
SMBus Table: Device Control Register, READ/WRITE ADDRESS (DC/DD)
Pin # Name Control Function T
yp
e0 1Default
Bit 7 RW Pin 27
Bit 6 RW Pin 5
Bit 5 RW Pin 44
Bit 4 RW Pin 7
Bit 3 RW Off On Pin 26
Bit 2 RW Hardware
Select
Software
Select 0
Bit 1 RW Driven Hi-Z 0
Bit 0 RW Down Center 0
Notes:
1. These bits reflect the state of the corresponding pins at power up, but may be written to
if Byte 0, bit 2 is set to '1'. FS3 is the SEL14M_25M# pin.
SMBus Table: Output Enable Register
Pin # Name Control Function T
yp
e0 1Default
Bit 7 DIF_7 EN Output Enable RW Disable Enable 1
Bit 6 DIF_6 EN Output Enable RW Disable Enable 1
Bit 5 DIF_5 EN Output Enable RW Disable Enable 1
Bit 4 DIF_4 EN Output Enable RW Disable Enable 1
Bit 3 DIF_3 EN Output Enable RW Disable Enable 1
Bit 2 DIF_2 EN Output Enable RW Disable Enable 1
Bit 1 DIF_1 EN Output Enable RW Disable Enable 1
Bit 0 DIF_0 EN Output Enable RW Disable Enable 1
Note:
SMBus Table: Output Stop Mode Register
Pin # Name Control Function T
yp
e0 1Default
Bit 7 DIF_7 STOP EN Free Run/ Stop Enable RW Free-run Stop-able 0
Bit 6 DIF_6 STOP EN Free Run/ Stop Enable RW Free-run Stop-able 0
Bit 5 DIF_5 STOP EN Free Run/ Stop Enable RW Free-run Stop-able 0
Bit 4 DIF_4 STOP EN Free Run/ Stop Enable RW Free-run Stop-able 0
Bit 3 DIF_3 STOP EN Free Run/ Stop Enable RW Free-run Stop-able 0
Bit 2 DIF_2 STOP EN Free Run/ Stop Enable RW Free-run Stop-able 0
Bit 1 DIF_1 STOP EN Free Run/ Stop Enable RW Free-run Stop-able 0
Bit 0 DIF_0 STOP EN Free Run/ Stop Enable RW Free-run Stop-able 0
44
7
B
y
te 0
27
5
26 Spread Enable1
-
Enable Software Control of Frequency,
Spread Enable (Spread Type always
Software Control)
- DIF_STOP# drive mode
- Spread Type
B
y
te 1
-
-
-
-
-
-
-
-
B
y
te 2
-
-
Byte 1 sets outputs active or inactive, not the conditons set by the OE inputs.
-
-
-
-
See Frequency
Selection Table.
FS31
FS21
FS11
FS01
-
-
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI 1680E—04/04/17
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
14
SMBus Table: Frequency Select Readback Register
Pin # Name Control Function Type 0 1 Default
Bit 7 SEL14M_25M#1State of pin 27 R Pin 27
Bit 6 FS21State of pin 6 R Pin 6
Bit 5 FS11State of pin 44 R Pin 44
Bit 4 FS01State of pin 45 R Pin 45
Bit 3 SPREAD1State of pin 26 R Off On Pin 26
Bit 2 RX
Bit 1 RX
Bit 0 RX
Notes:
1. These bits reflect the state of the corresponding pins, regardless of whether software
programming is enabled or not.
SMBus Table: Vendor & Revision ID Register
Pin # Name Control Function T
yp
e0 1Default
Bit 7 RID3 R - - X
Bit 6 RID2 R - - X
Bit 5 RID1 R - - X
Bit 4 RID0 R - - X
Bit 3 VID3 R - - 0
Bit 2 VID2 R - - 0
Bit 1 VID1 R - - 0
Bit 0 VID0 R - - 1
SMBus Table: DEVICE ID
Pin # Name Control Function T
yp
e0 1Default
Bit 7 DEVID7 R 0
Bit 6 DEVID6 R 0
Bit 5 DEVID5 R 0
Bit 4 DEVID4 R 1
Bit 3 DEVID3 R 0
Bit 2 DEVID2 R 0
Bit 1 DEVID1 R 0
Bit 0 DEVID0 R 0
SMBus Table: Byte Count Register
Pin # Name Control Function T
yp
e0 1Default
Bit 7 BC7 RW - - 0
Bit 6 BC6 RW - - 0
Bit 5 BC5 RW - - 0
Bit 4 BC4 RW - - 0
Bit 3 BC3 RW - - 0
Bit 2 BC2 RW - - 1
Bit 1 BC1 RW - - 1
Bit 0 BC0 RW - - 1
See Frequency
Selection Table.
B
y
te 6
-
-
-
-
-
-
-
Writing to this register
will configure how many
bytes will be read back,
default is 07 = 7 bytes.
-
-
-
-
-
VENDOR ID
-
-
-
-
-
B
y
te 5
-
-
-
B
y
te 4
-
REVISION ID
-
-
-
Reserved Reserved
Reserved Reserved
26
Reserved Reserved
45
44
Byte 3
6
27
Device ID = 10 hex
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI 1680E—04/04/17
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
15
SMBus Table: Reserved Register
Pin # Name Control Function T
yp
e0 1Default
Bit 7 X
Bit 6 X
Bit 5 X
Bit 4 X
Bit 3 X
Bit 2 X
Bit 1 X
Bit 0 X
SMBus Table: Reserved Register
Pin # Name Control Function T
yp
e0 1Default
Bit 7 X
Bit 6 X
Bit 5 X
Bit 4 X
Bit 3 X
Bit 2 X
Bit 1 X
Bit 0 X
SMBus Table: M/N Programming Enable
Pin # Name Control Function T
yp
e0 1Default
Bit 7 M/N_EN PLL M/N Programming
Enable RW Disable Enable 0
Bit 6 OE_Polarity Select Polarity of OE
inputs RW OE# OE 1
Bit 5 REFOUT_En Enables/Disables REF RW Disable Enable 1
Bit 4 0
Bit 3 0
Bit 2 0
Bit 1 0
Bit 0 0
SMBus Table: PLL Frequency Control Register
Pin # Name Control Function T
yp
e0 1Default
Bit 7 PLL N Div8 N Divider Prog bit 8 RW X
Bit 6 PLL N Div9 N Divider Prog bit 9 RW X
Bit 5 PLL M Div5 RW X
Bit 4 PLL M Div4 RW X
Bit 3 PLL M Div3 RW X
Bit 2 PLL M Div2 RW X
Bit 1 PLL M Div1 RW X
Bit 0 PLL M Div0 RW X
B
y
te 10
-
The decimal
representation of M and
N Divider in Byte 11 and
12 will configure the PLL
VCO frequency.
Default at power up =
latch-in or Byte 0 Rom
table. VCO Frequency
= fXTAL x [NDiv(9:0)+8]
/ [MDiv(5:0)+2]
-
-
M Divider Programming
bit (5:0)
-
-
-
-
-
5
Reserved
B
y
te 9
-
-
Reserved
Reserved
Reserved
Reserved
B
y
te 7
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
B
y
te 8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI 1680E—04/04/17
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
16
SMBus Table: PLL Frequency Control Register
Pin # Name Control Function T
yp
e0 1Default
Bit 7 PLL N Div7 RW X
Bit 6 PLL N Div6 RW X
Bit 5 PLL N Div5 RW X
Bit 4 PLL N Div4 RW X
Bit 3 PLL N Div3 RW X
Bit 2 PLL N Div2 RW X
Bit 1 PLL N Div1 RW X
Bit 0 PLL N Div0 RW X
SMBus Table: PLL Spread Spectrum Control Register
Pin # Name Control Function T
yp
e0 1Default
Bit 7 PLL SSP7 RW X
Bit 6 PLL SSP6 RW X
Bit 5 PLL SSP5 RW X
Bit 4 PLL SSP4 RW X
Bit 3 PLL SSP3 RW X
Bit 2 PLL SSP2 RW X
Bit 1 PLL SSP1 RW X
Bit 0 PLL SSP0 RW X
SMBus Table: PLL Spread Spectrum Control Register
Pin # Name Control Function T
yp
e0 1Default
Bit 7 0
Bit 6 PLL SSP14 RW X
Bit 5 PLL SSP13 RW X
Bit 4 PLL SSP12 RW X
Bit 3 PLL SSP11 RW X
Bit 2 PLL SSP10 RW X
Bit 1 PLL SSP9 RW X
Bit 0 PLL SSP8 RW X
B
y
te 11
-The decimal
representation of M and
N Divider in Byte 11 and
12 will configure the PLL
VCO frequency.
Default at power up =
latch-in or Byte 0 Rom
table. VCO Frequency
= fXTAL x [NDiv(9:0)+8]
/ [MDiv(5:0)+2]
-
-
-
-
-
-
-
B
y
te 12
-
-
N Divider Programming
Byte11 bit(7:0) and
Byte10 bit(7:6)
-
-
Spread Spectrum
Programming bit(7:0)
These Spread
Spectrum bits in
Byte 13 and 14 will
program the spread
pecentage of PLL
-
-
-
-
B
y
te 13
- Reserved
-
-
-
Spread Spectrum
Programming bit(14:8)
These Spread
Spectrum bits in
Byte 13 and 14 will
program the spread
pecentage of PLL
-
-
-
-
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI 1680E—04/04/17
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
17
MIN MAX MIN MAX
A 2.41 2.80 .095 .110
A1 0.20 0.40 .008 .016
b 0.20 0.34 .008 .0135
c 0.13 0.25 .005 .010
D
E 10.03 10.68 .395 .420
E1 7.40 7.60 .291 .299
e
h 0.38 0.64 .015 .025
L 0.50 1.02 .020 .040
N
a 0°8°0°8°
VARIATIONS
MIN MAX MIN MAX
48 15.75 16.00 .620 .630
10-0034
Reference Doc.: JEDEC Publication 95, MO-118
300 mil SSOP
N
SEE VARIATIONS SEE VARIATIONS
D mm. D (inch)
SYMBOL
SEE VARIATIONS SEE VARIATIONS
0.635 BASIC 0.025 BASIC
COMMON DIMENSIONS
In Millimeters In Inches
COMMON DIMENSIONS
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI 1680E—04/04/17
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
18
MIN MAX MIN MAX
A -- 1.20 -- .047
A1 0.05 0.15 .002 .006
A2 0.80 1.05 .032 .041
b 0.17 0.27 .007 .011
c 0.09 0.20 .0035 .008
D
E
E1 6.00 6.20 .236 .244
e
L 0.45 0.75 .018 .030
N
α0° 8° 0° 8°
aaa -- 0.10 -- .004
VARIATIONS
MIN MAX MIN MAX
48 12.40 12.60 .488 .496
10 - 0 0 3 9
6.10 mm. Bod
y
, 0.50 mm. Pitch TSSOP
(
240 mil
)
(
20 mil
)
SYMBOL
In Millimeters In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
SEE VARIATIONS SEE VARIATIONS
8.10 BASIC 0.319 BASIC
0.50 BASIC 0.020 BASIC
SEE VARIATIONS SEE VARIATIONS
ND mm. D (inch)
Reference Doc.: JEDEC Publication 95, M O-153
INDEX
AREA
12
N
D
E1 E
SEATING
PLANE
A1
A
A2
e
-C-
--
b
c
L
aaa C
α
Ordering Information
Part / Orde r Num be r S hi pping P acka gi ng Packa ge Te m pe rature
9FG830AFLF Tubes 48-pin SSOP 0 to +70°C
9FG830AFLFT Tape and Reel 48-pin SSOP 0 to +70°C
9FG830AFILF Tubes 48-pin SSOP -40 to +85°C
9FG830AFILFT Tape and Reel 48-pin SSOP -40 to +85°C
9FG830AGLF Tubes 48-pin TSSOP 0 to +70°C
9FG830AGLFT Tape and Reel 48-pin TSSOP 0 to +70°C
9FG830AGILF Tubes 48-pin TSSOP -40 to +85°C
9FG830AGILFT Tape and Reel 48-pin TSSOP -40 to +85°C
“LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
“A” is the device revision designator (wi ll not correlate with the datasheet revision).
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
19
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www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
408-284-6578
www.idt.com/go/support
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or
specifications described herein at any time, without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described
products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained
herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any
particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as
a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure
or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner
does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries.
Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit
www.idt.com/go/glossary. Integrated Device Technology, Inc.. All rights reserved.
Revision History
Rev. Issue Date Originator Description Page #
A 7/13/2010 RDW Initial release. Move to final
B 7/20/2010 RDW
1. Added PPM tables to DS for both 25M and 14.318M inputs
2. Added Test load figures
C 8/25/2010 RDW
1. Updated/reformatted Electrical Tables
2. Corrected Features/Benefits and General Description
3. Updated termination figures to include Fig 5. for REF output Various
D 7/3/2013 D. C.
1. Update OE# Latency min/max values from 1 & 3 cycles to 2 & 5 cycles
respectively.
2. Update VDDA max current from 28 to 30mA for 100MHz and 400MHz.
3. Added typical values to Phase Jitter Parameters table.
Various
E 4/4/2017 RDW 1. Corrected Byte 5 Device ID from 83hex to 10 hex. 14