TPS62177
VIN
EN
SLEEP
AGND
PGND
SW
VOS
PG
FB
NC
4.75 to 28V 3.3V/0.5A
10uH
22uF2.2uF
100k
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TPS6217x 28-V, 0.5-A Step-Down Converter With Sleep Mode
1 Features 3 Description
The TPS6217x is a high efficiency synchronous step-
1 DCS-Control™ Topology down DC/DC converter, based on the DCS-Control™
Input Voltage Range 4.75 V to 28 V topology.
Quiescent Current Typically 4.8 µA (Sleep Mode) With a wide operating input voltage range of 4.75 V
100% Duty Cycle Mode to 28 V, the device is ideally suited for systems
Active Output Discharge powered from multi cell Li-Ion as well as 12 V and
even higher intermediate supply rails, providing up to
Power Good Output 500-mA output current.
Output Current of 500 mA The TPS6217x automatically enters power save
Output Voltage Range 1 VDC to 6 V mode at light loads, to maintain high efficiency across
Switching Frequency of Typically 1 MHz the whole load range. As well, it features a sleep
Seamless Power Save Mode Transition mode to supply applications with advanced power
save modes like ultra low power micro controllers.
Undervoltage Lockout The power good output may be used for power
Short Circuit Protection sequencing and/or power on reset.
Over Temperature Protection The device features a typical quiescent current of 22
Available in 2-mm × 3-mm 10-pin WSON Package µA in normal mode and 4.8 µA in sleep mode. In
sleep mode, the efficiency at very low load currents
2 Applications can be increased by as much as 20%. In shutdown
mode, the shutdown current is less than 2 µA and the
General 12 V / 24 V Point Of Load Supply output is actively discharged.
Ultra Mobile PC, Embedded PC The TPS6217x, available in an adjustable and a fixed
Low Power Supply for Microprocessor output voltage version, is packaged in a small 2-mm
High Efficiency LDO Alternative × 3-mm 10-pin WSON package.
Industrial Sensors Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
TPS6217x WSON (10) 2.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
spacing
Typical Application Schematic Efficiency vs Output Current
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS62175
,
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SLVSB35C OCTOBER 2012REVISED JULY 2015
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Table of Contents
1 Features.................................................................. 19 Application and Implementation ........................ 13
9.1 Application Information............................................ 13
2 Applications ........................................................... 19.2 Typical Application.................................................. 13
3 Description............................................................. 19.3 System Examples ................................................... 23
4 Revision History..................................................... 210 Power Supply Recommendations ..................... 27
5 Device Comparison Table..................................... 311 Layout................................................................... 27
6 Pin Configuration and Functions......................... 311.1 Layout Guidelines ................................................. 27
7 Specifications......................................................... 411.2 Layout Example .................................................... 27
7.1 Absolute Maximum Ratings ...................................... 411.3 Thermal Information.............................................. 28
7.2 ESD Ratings.............................................................. 412 Device and Documentation Support................. 29
7.3 Recommended Operating Conditions....................... 412.1 Device Support...................................................... 29
7.4 Thermal Information.................................................. 412.2 Documentation Support ........................................ 29
7.5 Electrical Characteristics........................................... 512.3 Related Links ........................................................ 29
7.6 Typical Characteristics.............................................. 712.4 Community Resources.......................................... 29
8 Detailed Description.............................................. 812.5 Trademarks........................................................... 29
8.1 Overview................................................................... 812.6 Electrostatic Discharge Caution............................ 29
8.2 Functional Block Diagrams ....................................... 812.7 Glossary................................................................ 30
8.3 Feature Description................................................... 913 Mechanical, Packaging, and Orderable
8.4 Device Functional Modes........................................ 10 Information ........................................................... 30
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (January 2014) to Revision C Page
Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
Changes from Revision A (November 2012) to Revision B Page
Added to SLEEP description in TERMINAL FUNCTIONS table............................................................................................ 3
Changed Sleep Mode Operation section.............................................................................................................................. 11
Changed Micro Controller Power Supply section information and Figure 54....................................................................... 24
Changed Figure 55 .............................................................................................................................................................. 24
Changes from Original (October 2012) to Revision A Page
Added Start-up Mode to High-Side MOSFET Current Limit in ELECTRICAL CHARACTERISTICS..................................... 5
Changed Table 2 ................................................................................................................................................................. 14
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Exposed
Thermal Pad
1
2
3
4
5
10
9
8
7
6
PGND
VIN
EN
NC
FB
VOS
SW
SLEEP
PG
AGND
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5 Device Comparison Table
PART NUMBER OUTPUT VOLTAGE PACKAGE DESIGNATOR CODE PACKAGE MARKING
TPS62175 Adjustable DQC 62175
TPS62177 Fixed, 3.3 V DQC 62177
6 Pin Configuration and Functions
spacing
DQC Package
10-Pin WSON
Top View
spacing
spacing
Pin Functions
PIN (1) I/O DESCRIPTION
NAME NO.
PGND 1 Power ground connection
VIN 2 I Supply voltage for the converter
EN 3 I Enable input (High = enabled, Low = disabled)
NC 4 This pin is recommended to be connected to AGND but can left be floating
Voltage feedback of adjustable version. Connect resistive divider to this pin. TI recommends
FB 5 I connecting FB to AGND for fixed voltage versions for improved thermal performance.
AGND 6 Analog ground connection
PG 7 O Output power good (open drain, requires pullup resistor)
Sleep mode input (High = normal operation, Low = sleep mode operation). Can be operated
SLEEP 8 I dynamically during operation. If sleep mode is not used, connect to VOUT.
Switch node, connected to the internal MOSFET switches. Connect inductor between SW and
SW 9 O output capacitor.
VOS 10 I Output voltage sense pin and connection for the control loop circuitry.
Exposed Must be connected to AGND and PGND. Must be soldered to achieve appropriate power dissipation
Thermal Pad and mechanical reliability.
(1) For more information about connecting pins, see Detailed Description and Application and Implementation sections.
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VIN –0.3 30
Pin voltage(2) EN, SW –0.3 VIN + 0.3 V
FB, PG, VOS, SLEEP, NC –0.3 7
Power good sink PG 10 mA
current Operating junction temperature, TJ–40 125
Temperature °C
Storage temperature, Tstg –65 150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
(2) All voltages are with respect to network ground terminal.
7.2 ESD Ratings VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC specification JESD22-C101, all ±500
pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions MIN NOM MAX UNIT
Supply voltage, VIN 4.75 28 V
Operating free air temperature, TA–40 85 °C
Operating junction temperature, TJ–40 125 °C
7.4 Thermal Information TPS6217x
THERMAL METRIC(1) DQC [WSON] UNIT
10 PINS
RθJA Junction-to-ambient thermal resistance 61.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 65.5 °C/W
RθJB Junction-to-board thermal resistance 22.5 °C/W
ψJT Junction-to-top characterization parameter 1.4 °C/W
ψJB Junction-to-board characterization parameter 22.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 5.3 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5 Electrical Characteristics
Over free-air temperature range (TA= –40°C to 85°C) and VIN = 4.75 V to 28 V. Typical values at VIN = 12 V and TA= 25°C
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
VIN Input voltage range 4.75 28 V
Operating quiescent EN = High, SLEEP = High, IOUT = 0 mA, device not switching
IQ22 36 µA
current
Sleep mode quiescent EN = High, SLEEP = Low, IOUT = 0 mA, device not switching
IQ_SLEEP 4.8 10 µA
current
ISD Shutdown current EN = Low, current into VIN pin 1.5 5 µA
Rising input voltage 4.5 4.6 4.7 V
Undervoltage lockout
VUVLO threshold Falling input voltage 2.9 V
Thermal shutdown Rising junction temperature 150
temperature
TSD °C
Thermal shutdown 20
hysteresis
CONTROL (EN, PG, SLEEP)
High level input
VHthreshold voltage (EN, 0.9 V
SLEEP)
Low level input
VLthreshold voltage (EN, 0.3 V
SLEEP)
Input leakage current
ILKG_EN EN = VIN 5 300 nA
(EN)
Input leakage current
ILKG_SLEEP VSLEEP = 3.3 V 1.4 µA
(SLEEP) Rising (%VOUT) 93% 96% 99%
Power good threshold
VTH_PG voltage Falling (%VOUT) 87% 90% 93%
Power good output low
VOL_PG IPG = –2 mA 0.3 V
voltage
Input leakage current
ILKG_PG VPG = 5 V 5 300 nA
(PG)
POWER SWITCH
High-side MOSFET VIN 6 V 850 1430 mΩ
ON-resistance
RDS(ON) Low-side MOSFET VIN 6 V 320 530 mΩ
ON-resistance Normal operation 800 1000 1200
High-side MOSFET
ILIMF mA
current limit Start-up mode 450 525 600
OUTPUT
VOUT Output voltage range VIN VOUT 1 6 V
(TPS62175)
VREF Internal reference 0.8 V
voltage
IOUT_SLEEP Output current in sleep SLEEP = Low, VOUT = 3.3 V, L = 10 µH 15 mA
mode
Input leakage current
ILKG_FB VFB = 0.8 V 1 100 nA
(FB)
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Electrical Characteristics (continued)
Over free-air temperature range (TA= –40°C to 85°C) and VIN = 4.75 V to 28 V. Typical values at VIN = 12 V and TA= 25°C
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TPS62175 (adjustable PWM mode –1.8% 1.8%
VOUT), VIN VOUT +1 V Power save mode, L VOUT 2.5 V, –1.8% 3%
= 10 µH COUT = 22 µF
VOUT < 2.5 V, 1.8% 3.7%
COUT = 44 µF
Output voltage Sleep mode, IOUT COUT = 22
accuracy(1) 15 mA µF, L = 10 –1.6% 2.9%
µH
VOUT TPS62177 (3.3 V fixed PWM mode –2% 2%
VOUT)Power save mode, COUT = 22 2% 2.9%
µF, L = 10
Sleep mode, IOUT –1.6% 2.7%
µH
15 mA
Output discharge EN = Low 175 Ω
resistance
Load regulation VOUT = 3.3 V, PWM mode operation 0.02 %/A
Line regulation VOUT = 3.3 V, IOUT= 500 mA, PWM mode operation 0.015 %/V
(1) The output voltage accuracy in Power Save and Sleep Mode can be improved by increasing the output capacitor value, reducing the
output voltage ripple (see Application and Implementation section).
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0
100
200
300
400
500
600
700
0.0 3.0 6.0 9.0 12.0 15.0 18.0 21.0 24.0 27.0 30.0
−40°C−10°C25°C
85°C 125°C
Input Voltage (V)
RDSon Low−Side (m)
G001
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.0 3.0 6.0 9.0 12.0 15.0 18.0 21.0 24.0 27.0 30.0
−40°C 25°C
85°C
Input Voltage (V)
Input Current (µA)
G001
0
200
400
600
800
1000
1200
1400
1600
1800
2000
0.0 3.0 6.0 9.0 12.0 15.0 18.0 21.0 24.0 27.0 30.0
−40°C−10°C25°C
85°C 125°C
Input Voltage (V)
RDSon High−Side (m)
G001
0.0
5.0
10.0
15.0
20.0
25.0
30.0
35.0
40.0
45.0
50.0
0.0 3.0 6.0 9.0 12.0 15.0 18.0 21.0 24.0 27.0 30.0
−40°C
25°C
85°C
Input Voltage (V)
Input Current (µA)
G001
0.0
2.0
4.0
6.0
8.0
10.0
0.0 3.0 6.0 9.0 12.0 15.0 18.0 21.0 24.0 27.0 30.0
−40°C 25°C
85°C
Input Voltage (V)
Input Current (µA)
G001
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7.6 Typical Characteristics
Figure 1. Quiescent Current Figure 2. Quiescent Current (Sleep Mode)
Figure 3. Shutdown Current Figure 4. High-Side Switch
Figure 5. Low-Side Switch
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Control Logic
Soft
Start
Thermal
Shutdown UVLO PG Control
Power
Control
Error
Amplifier
Gate
Drive
HS lim
VINPG
PGND
AGND
Comp
+
_
Timer tON, tOFF
DCS - ControlTM
Direct Control
&
Compensation
Comparator
ramp
SW
EN*
VOS
FB
SLEEP* Sleep Control
NC
EN
175
* This pin is connected to a pull down resistor internally
(see Detailed Description section).
VREF
td=1ms
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8 Detailed Description
8.1 Overview
The TPS6217x synchronous switch mode power converters are based on DCS-Control™ (Direct Control with
Seamless Transition into Power Save Mode), an advanced regulation topology, that combines the advantages of
hysteretic, voltage mode, and current mode control including an AC loop directly associated to the output
voltage. This control loop takes information about output voltage changes and feeds it directly to a fast
comparator stage. It sets the switching frequency, which is constant for steady state operating conditions, and
provides immediate response to dynamic load changes. To get accurate DC load regulation, a voltage feedback
loop is used. The internally compensated regulation network achieves fast and stable operation with small
external components and low ESR capacitors. The DCS-Control topology supports pulse width modulation
(PWM) mode for medium and heavy load conditions and a power save mode at light loads. During PWM, it
operates at its nominal switching frequency in continuous conduction mode. This frequency is typically about 1
MHz with a controlled frequency variation depending on the input voltage. If the load current decreases, the
converter enters power save mode to sustain high efficiency down to very light loads. In power save mode the
switching frequency decreases linearly with the load current. Because DCS-Control™ supports both operation
modes within one single building block, the transition from PWM to power save mode is seamless without effects
on the output voltage. Fixed output voltage versions provide smallest solution size and lowest current
consumption, requiring only 3 external components. An internal current limit supports nominal output currents of
up to 500 mA. The TPS6217x offer both excellent DC voltage and superior load transient regulation, combined
with very low output voltage ripple, minimizing interference with RF circuits.
8.2 Functional Block Diagrams
Figure 6. TPS62175 (Adjustable Output Voltage)
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Functional Block Diagrams (continued)
Figure 7. TPS62177 (Fixed Output Voltage)
8.3 Feature Description
8.3.1 Enable/Shutdown (EN)
The device can be switched ON/OFF by pulling the EN pin to High (operation) or Low (shutdown). If EN is pulled
to High, the device starts operation after a delay of about 1 ms (typical). This helps to ensure a monotonic start-
up sequence, which makes the device ideally suited to control the power on sequence of micro controllers.
During shutdown, the internal MOSFETs as well as the entire control circuitry are turned off and the current
consumption is typically 1.5 µA. The EN pin is connected through a 400-kΩpulldown resistor, keeping the logic
level low, if the pin is floating. The resistor is disconnected when EN is set High.
8.3.2 Output Discharge
The output is actively discharged through a 175-Ω(typical) resistor on the VOS pin when the device is turned off
by EN, UVLO or thermal shutdown.
8.3.3 Current Limit and Short Circuit Protection
The TPS6217x devices are protected against heavy load and short circuit events. If a current limit situation is
detected, the device switches off. The off-time is maintained longer as the output voltage becomes lower. At
heavy overloads the low-side MOSFET stays on until the inductor current returns to zero. Then the high-side
MOSFET turns on again (see Figure 50 and Figure 51).
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V
V
t
IN
OUT
ON m1×=
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Feature Description (continued)
8.3.4 Power Good (PG)
The TPS6217x has a built-in power good (PG) function to indicate that the output reached regulation. The PG
signal can be used for start-up sequencing of multiple rails. The PG pin is an open-drain output that requires a
pullup resistor (to any voltage less than 7 V). It can sink 2 mA of current and maintain its specified logic low level
of 0.3 V. It is held low when the device is turned off by EN, UVLO or thermal shutdown.
If the PG pin is not used, it may be left floating or connected to AGND.
8.3.5 Undervoltage Lockout (UVLO)
If the input voltage drops, the undervoltage lockout function prevents misoperation by turning the device off. The
undervoltage lockout threshold is set to 4.6 V (typically) for rising VIN. To cover for possible input voltage drops,
when using high impedance sources or batteries, the falling threshold is set to typically 2.9 V, allowing monotonic
start-up sequence under such conditions. For input voltages below the minimum VIN of 4.75 V and above the
falling UVLO threshold of 2.9 V, the device still functions with a current limit and regulation capability but the
electrical characteristics are no longer specified.
8.3.6 Thermal Shutdown
The junction temperature (TJ) of the device is monitored by an internal temperature sensor. If TJexceeds 150°C
(typical), the device goes into thermal shutdown. Both the high-side and low-side power FETs are turned off and
PG goes Low. When TJdecreases below the hysteresis amount, the converter resumes normal operation,
beginning with soft start. To avoid unstable conditions, a hysteresis of typically 20°C is implemented on the
thermal shutdown temperature.
8.4 Device Functional Modes
8.4.1 Soft Start
The internal soft start circuitry controls the output voltage slope during start-up. This avoids excessive inrush
current and ensures a controlled output voltage rise time. It also prevents unwanted voltage drops from high-
impedance power sources or batteries. When EN is set to High and the device starts switching, VOUT rises with a
slope of typically 10 mV/µs. The internal current limit is reduced to typically 525 mA during start-up. Thereby the
output current is less than 500 mA during that time (see Figure 41). The start-up sequence ends when the device
achieves regulation; then, the device runs with the full current limit of typically 1 A, providing full output current.
The TPS6217x can monotonically start into a prebiased output.
8.4.2 Pulse Width Modulation (PWM) Operation
The TPS6217x operates with pulse width modulation in continuous conduction mode (CCM) with a nominal
switching frequency of about 1 MHz. The switching frequency in PWM is set by an internal timer circuit. The
frequency variation is controlled and depends on VIN and VOUT. The device operates in PWM mode as long the
output current is higher than half the inductor's ripple current. To maintain high efficiency at light loads, the
device enters power save mode at the boundary to discontinuous conduction mode (DCM).
8.4.3 Power Save Mode Operation
The TPS6217x built in power save mode is entered seamlessly, if the load current decreases. This secures a
high efficiency in light load operation by keeping the on-time fixed and reducing the switching frequency by
incorporating pause time. The device remains in power save mode as long as the inductor current is
discontinuous. The on-time, in steady-state PWM operation, can be estimated as:
spacing
(1)
spacing
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ú
û
ù
ê
ë
é-
×
=
L
VV
V
V
t
I
f
OUTIN
OUT
IN
ON
OUT
PSM
2
2
ON
OUTIN
peakLPSM t
L
VV
I×
-
=
)(
)(
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,
TPS62177
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SLVSB35C OCTOBER 2012REVISED JULY 2015
Device Functional Modes (continued)
In case Equation 1 yields a lower value, the device maintain an on-time of about 80 ns to limit switching losses.
This minimum on-time is used in power save mode. While the peak inductor current in Power Save Mode can be
approximated by:
spacing
(2)
spacing
The switching frequency is calculated as follows:
spacing
(3)
spacing
8.4.4 Sleep Mode Operation
In sleep mode operation, the typical quiescent current is reduced from 22 µA to 4.8 µA to significantly increase
the efficiency at load currents of typically less than 1 mA (see Figure 1 and Figure 2). It is designed to be
enabled and disabled during operation by pulling the SLEEP pin High or Low by the host (processor). Ultralow
power micro controllers in deep sleep or hibernating mode may set their output pins floating. Therefore, the
TPS6217x have a pulldown resistor internally connected to the SLEEP pin, to keep a logic low level, when the
sleep input signal goes high impedance. But, if the sleep signal goes directly from logic High to High Impedance,
the low level detection must be ensured considering the leakage of the micro controller's sleep signal. An
external pulldown resistor, on the SLEEP pin, may be required. Connect the SLEEP pin to VOUT, not VIN, to
disable sleep mode, because the pin's voltage rating is limited to 7 V maximum.
The output voltage is regulated with a fixed switching scheme, using a fixed on-time of about twice the minimum
on-time of Equation 1 (compare Figure 48 and Figure 49) and the minimum off-time. A new pulse is initiated
once the output voltage falls below its regulation threshold. Sleep mode is limited with its dynamic response and
current capabilities. However, the device can deliver temporarily more than 15 mA while still in sleep mode, to
allow micro controllers to wake up and drive the sleep signal High, exiting sleep mode.
Continuously operating with a too high current in sleep mode causes the output voltage to drop until the PG pin
goes Low. As a safety feature, the device then returns to normal operation automatically, avoiding a complete
collapse of VOUT. Once the load current decreases again, the device re-enters sleep mode operation. Certainly,
this is not a recommended operation mode and sleep mode should be entered or exited by using the SLEEP pin
logic.
Sleep mode is not entered until soft-start is complete.
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Device Functional Modes (continued)
8.4.5 100% Mode Operation
The duty cycle of the buck converter is given by D = VOUT/VIN and increases as the input voltage comes close to
the output voltage. In this case, the device starts 100% duty cycle operation turning on the high-side switch
100% of the time. The high-side switch stays turned on as long as the output voltage is below the internal
setpoint. This allows the conversion of small input to output voltage differences, for example, for longest
operation time of battery-powered applications.
The minimum input voltage to maintain output voltage regulation can be calculated as:
spacing
where
IOUT is the output current
RDS(on) is the RDS(on) of the high-side FET
RLis the DC resistance of the inductor used (4)
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TPS62175
VIN
EN
SLEEP
AGND
PGND
SW
VOS
PG
FB
NC
4.75 to 28V VOUT/0.5A
10uH
22uF2.2uF
100k
R1
R2
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS6217x is a high-efficiency synchronous step-down DC-DC converter, based on the DCS-Control
topology.
With a wide operating input voltage range of 4.75 V to 28 V, the device is ideally suited for systems powered
from multi cell Li-Ion as well as 12 V and even higher intermediate supply rails, providing up to 500-mA output
current.
9.2 Typical Application
Figure 8. Adjustable 0.5-A Power Supply
9.2.1 Design Requirements
The device operates for an input voltage range of 4.75 V to 28 V. The output voltage is adjustable, using an
external resistive divider, or internally fixed.
The graphs were generated using the setup according to Figure 8.Table 1 shows the list of components used for
the setup.
9.2.2 Detailed Design Procedures
Table 1. List of Components
REFERENCE DESCRIPTION MANUFACTURER
IC 28 V, 0.5-A Step-Down Converter, WSON TPS62175DQC, Texas Instruments
L1 10 uH, (4 × 4 × 1.2) mm LPS4012, Coilcraft
Cin 2.2 µF, 50 V, Ceramic, 0805, X5R Standard
Cout 22 µF, 6.3 V, Ceramic, 0805, X5R Standard
R1 depending on VOUT
R2 depending on VOUT
R3 100 kΩ, Chip, 0603, 1/16 W, 1% Standard
Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: TPS62175 TPS62177
÷
÷
÷
÷
ø
ö
ç
ç
ç
ç
è
æ
×
×
-
×=D
SW
IN
OUT
OUT
LfL
V
V
V
I
(min)
(max)
(max)
1h
h
2
(max)
(max)(max)
L
OUTL
I
II
D
+=
÷
÷
ø
ö
ç
ç
è
æ-= 1
21
REF
OUT
V
V
RR
TPS62175
,
TPS62177
SLVSB35C OCTOBER 2012REVISED JULY 2015
www.ti.com
9.2.2.1 Programming the Output Voltage
While the output voltage of the TPS62175 is adjustable, the TPS62177 is programmed to a fixed output voltage
of 3.3 V. For the fixed output voltage version, the FB pin is pulled low internally by a 400-kΩresistor. TI
recommends connecting the FB pin to AGND to improve thermal resistance. The adjustable version can be
programmed for output voltages from 1 V to 6 V by using a resistive divider. The voltage at the FB pin is
regulated to 800 mV. The value of the output voltage is set by the selection of the resistive divider from
Equation 5. TI recommends choosing resistor values that allow a current of at least 5 uA. Lower resistor values
are recommended to increase noise immunity. For applications requiring lowest current consumption, the use of
the fixed-output voltage version is recommended.
(5)
As a safety feature, the device clamps the output voltage at the VOS pin to typically 7.4 V, if the FB pin gets
opened.
9.2.2.2 External Component Selection
The external components must fulfill the needs of the application, but also the stability criteria of the device's
control loop. The TPS6217x is optimized to work within a wide range of external components. The LC output
filter's inductance and capacitance must be considered together, creating a double pole that is responsible for
the corner frequency of the converter. Table 2 shows the recommended output filter components.
Table 2. Recommended LC Output Filter Combinations(1)
10 µF 22 µF 47 µF 100 µF 200 µF 400 µF
6.8 µH
10 µH (2) √√√
22 µH
33 µH
(1) The values in the table are nominal values. Variations of typically ±20% due to tolerance, saturation and DC bias are assumed.
(2) This LC combination is the standard value and recommended for most applications. For output voltages of 2 V, TI recommends an
output capacitance of at least 2 × 22 uF.
9.2.2.2.1 Output Filter and Loop Stability
The TPS6217x devices are internally compensated and are stable with LC output filter combinations
recommended in Table 2. Further information on other values and loop stability can be found in Optimizing the
TPS62175 Output Filter (SLVA543).
9.2.2.2.2 Inductor Selection
The inductor selection is determined by several effects like inductor ripple current, output ripple voltage, PWM-to-
Power Save Mode transition point and efficiency. In addition, the inductor selected must be rated for appropriate
saturation current and DC resistance (DCR). Equation 6 and Equation 7 calculate the maximum inductor current
under static load conditions.
(6)
spacing
where
ΔILis the peak to peak inductor ripple current
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ηis the converter efficiency (see efficiency figures)
L(min) is the minimum inductor value
fSW is the actual PWM switching frequency (7)
Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation
current of the inductor needed. TI recommends a margin of about 20% to cover possible load transient
overshoot. A larger inductor value is also useful to get lower ripple current, but increases the transient response
time and solution size as well. The inductors listed in Table 3 have been tested with the TPS6217x.
Table 3. List of Inductors
TYPE INDUCTANCE CURRENT (A)(1) DCR (mΩ) DIMENSIONS (LENGTH x MANUFACTURER
(µH]) WIDTH x HEIGHT) mm
LPS4012-103MLC 10 µH, ±20% 1.1 350 (maximum) 4 x 4 × 1.2 Coilcraft
LPS4018-103MLC 10 µH, ±20% 1.3 200 (maximum) 4 x 4 × 1.8 Coilcraft
VLS4012ET-100M 10 µH, ±20% 0.99 190 (typical) 4 x 4 × 1.2 TDK
VLCF4020T- 10 µH, ±20% 0.85 168 (typical) 4 × 4 × 2 TDK
100MR85
74437324100 10 µH, ±20% 1.5 215 (typical) 4.5 × 4.1 × 1.8 Wuerth
744025100 10 µH, ±20% 1 190 (maximum) 2.8 × 2.8 × 2.8 Wuerth
IFSC-1515AH-01 10 µH, ±20% 1.3 135 (typical) 3.8 × 3.8 × 1.8 Vishay
ELL-4LG100MA 10 µH, ±20% 0.8 200 (typical) 3.8 × 3.8 × 1.8 Panasonic
(1) IRMS at 40°C rise or ISAT at 30% drop.
9.2.2.2.3 Output Capacitor Selection
The recommended value for the output capacitor is 22 uF. To maintain low output voltage ripple during large load
transients, for output voltages less than 2 V, TI recommends 2 × 22 µF output capacitors. The architecture of the
TPS6217x allows the use of ceramic output capacitors with low equivalent series resistance (ESR). These
capacitors provide low output voltage ripple and are recommended with an X7R or X5R dielectric. Larger
capacitance values have the advantage of smaller output voltage ripple and a tighter DC output accuracy in
power save mode.
NOTE
In power save mode, the output voltage ripple and accuracy depends on the output
capacitance and the inductor value. The larger the capacitance the lower the output
voltage ripple and the better the output voltage accuracy. The same relation applies to the
inductor value.
9.2.2.2.4 Input Capacitor Selection
Typically, 2.2 µF is sufficient and is recommended, though a larger value reduces input current ripple further. The
input capacitor buffers the input voltage during transient events and also decouples the converter from the
supply. TI recommends a low ESR, multilayer, X5R or X7R dielectric, ceramic capacitor for best filtering, which
should be placed between VIN and PGND as close as possible to those pins.
spacing
spacing
spacing
NOTE
DC Bias effect: High capacitance ceramic capacitors have a DC Bias effect, which has a
strong influence on the final effective capacitance. Therefore, the right capacitor value
must be chosen carefully. Package size and voltage rating in combination with dielectric
material are responsible for differences between the rated capacitor value and the
effective capacitance.
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0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
0.01 0.1 1 10 100 500
VIN=5V
VIN=7.5
VIN=12V VIN=24V
Output Current (mA)
Efficiency (%)
VOUT=3.3V
L=10uH (LPS4012)
Cout=22uF
G001
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
4 6 8 10 12 14 16 18 20 22 24 26 28
IOUT=1mA IOUT=10mA
IOUT=100mA
IOUT=500mA
Input Voltage (V)
Efficiency (%)
VOUT=3.3V
L=10uH (LPS4012)
Cout=22uF
G001
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
0.001 0.01 0.1 1 10 20
VIN=6V
VIN=7.5
VIN=12V VIN=24V
Output Current (mA)
Efficiency (%)
VOUT=5V
L=10uH (LPS4012)
Cout=22uF
G001
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
6 8 10 12 14 16 18 20 22 24 26 28
IOUT=10uA
IOUT=100uA
IOUT=1mA
Input Voltage (V)
Efficiency (%)
VOUT=5V
L=10uH (LPS4012)
Cout=22uF
G001
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
0.01 0.1 1 10 100 500
VIN=6V
VIN=7.5
VIN=12V VIN=24V
Output Current (mA)
Efficiency (%)
VOUT=5V
L=10uH (LPS4012)
Cout=22uF
G001
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
6 8 10 12 14 16 18 20 22 24 26 28
IOUT=1mA IOUT=10mA
IOUT=100mA
IOUT=500mA
Input Voltage (V)
Efficiency (%)
VOUT=5V
L=10uH (LPS4012)
Cout=22uF
G001
TPS62175
,
TPS62177
SLVSB35C OCTOBER 2012REVISED JULY 2015
www.ti.com
9.2.3 Application Curves
VIN=12 V, VOUT = 3.3 V, TJ=25°C, unless otherwise noted
Figure 9. Efficiency vs Load Current Figure 10. Efficiency vs Input Voltage
Figure 11. Efficiency vs Load Current (Sleep Mode) Figure 12. Efficiency vs Input Voltage (Sleep Mode)
Figure 13. Efficiency vs Load Current Figure 14. Efficiency vs Input Voltage
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0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
0.001 0.01 0.1 1 10 20
VIN=5V
VIN=7.5
VIN=12V VIN=24V
Output Current (mA)
Efficiency (%)
VOUT=1.8V
L=10uH (LPS4012)
Cout=22uF
G001
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
4 6 8 10 12 14 16 18 20 22 24 26 28
IOUT=10uA
IOUT=100uA
IOUT=1mA
Input Voltage (V)
Efficiency (%)
VOUT=1.8V
L=10uH (LPS4012)
Cout=22uF
G001
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
0.01 0.1 1 10 100 500
VIN=5V
VIN=7.5V
VIN=12V VIN=24V
Output Current (mA)
Efficiency (%)
VOUT=1.8V
L=10uH (LPS4012)
Cout=22uF
G001
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
4 6 8 10 12 14 16 18 20 22 24 26 28
IOUT=1mA IOUT=10mA IOUT=100mA
IOUT=500mA
Input Voltage (V)
Efficiency (%)
VOUT=1.8V
L=10uH (LPS4012)
Cout=22uF
G001
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
0.001 0.01 0.1 1 10 20
VIN=5V
VIN=7.5
VIN=12V VIN=24V
Output Current (mA)
Efficiency (%)
VOUT=3.3V
L=10uH (LPS4012)
Cout=22uF
G001
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
4 6 8 10 12 14 16 18 20 22 24 26 28
IOUT=10uA
IOUT=100uA IOUT=1mA
Input Voltage (V)
Efficiency (%)
VOUT=3.3V
L=10uH (LPS4012)
Cout=22uF
G001
TPS62175
,
TPS62177
www.ti.com
SLVSB35C OCTOBER 2012REVISED JULY 2015
VIN=12 V, VOUT = 3.3 V, TJ=25°C, unless otherwise noted
Figure 15. Efficiency vs Load Current (Sleep Mode) Figure 16. Efficiency vs Input Voltage (Sleep Mode)
Figure 17. Efficiency vs Load Current Figure 18. Efficiency vs Input Voltage
Figure 19. Efficiency vs Load Current (Sleep Mode) Figure 20. Efficiency vs Input Voltage (Sleep Mode)
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3.20
3.25
3.30
3.35
0.01 0.1 1 10 100 500
VIN=5V VIN=7.5V
VIN=12V
VIN=24V
Output Current (mA)
Output Voltage (V)
VOUT=3.3V
L=2.2uH (LPS4012)
Cout=22uF
G001
3.20
3.25
3.30
3.35
4 7 10 13 16 19 22 25 28
IOUT=1mA IOUT=10mA
IOUT=100mAIOUT=500mA
Input Voltage (V)
Output Voltage (V)
VOUT=3.3V
L=2.2uH (LPS4012)
Cout=22uF
G001
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
0.001 0.01 0.1 1 10 20
VIN=5V
VIN=7.5
VIN=12V VIN=24V
Output Current (mA)
Efficiency (%)
VOUT=1V
L=10uH (LPS4012)
Cout=22uF
G001
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
4 6 8 10 12 14 16 18 20 22 24 26 28
IOUT=10uA
IOUT=100uA
IOUT=1mA
Input Voltage (V)
Efficiency (%)
VOUT=1V
L=10uH (LPS4012)
Cout=22uF
G001
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
0.01 0.1 1 10 100 500
VIN=5V
VIN=7.5
VIN=12V
VIN=24V
Output Current (mA)
Efficiency (%)
VOUT=1V
L=10uH (LPS4012)
Cout=2x22uF
G001
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
4 6 8 10 12 14 16 18 20 22 24 26 28
IOUT=1mA IOUT=10mA
IOUT=100mA IOUT=500mA
Input Voltage (V)
Efficiency (%)
VOUT=1V
L=10uH (LPS4012)
Cout=2x22uF
G001
TPS62175
,
TPS62177
SLVSB35C OCTOBER 2012REVISED JULY 2015
www.ti.com
VIN=12 V, VOUT = 3.3 V, TJ=25°C, unless otherwise noted
Figure 21. Efficiency vs Load Current Figure 22. Efficiency vs Input Voltage
Figure 23. Efficiency vs Load Current (Sleep Mode) Figure 24. Efficiency vs Input Voltage (Sleep Mode)
Figure 25. Output Voltage Accuracy (Load Regulation) Figure 26. Output Voltage Accuracy (Line Regulation)
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SLEEP ON
SLEEP OFF
SLEEP ON
SLEEP ON
SLEEP OFF
SLEEP ON
0
200
400
600
800
1000
4 6 8 10 12 14 16 18 20 22 24 26 28
−40°C25°C 85°C
Input Voltage (V)
Output Current (mA)
VOUT=3.3V
L=10uH (LPS4012)
Cout=22uF
G000
0
0.5
1
1.5
0 100 200 300 400 500
Output Current (mA)
Switching Frequency (MHz)
VIN=12V, VOUT=3.3V
L=10uH (LPS4012)
Cout=22uF
G000
0
0.5
1
1.5
4 6 8 10 12 14 16 18 20 22 24 26 28
IOUT=10mA
IOUT=500mA
Input Voltage (V)
Switching Frequency (MHz)
VOUT=3.3V
L=10uH (LPS4012)
Cout=22uF
G000
TPS62175
,
TPS62177
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SLVSB35C OCTOBER 2012REVISED JULY 2015
VIN=12 V, VOUT = 3.3 V, TJ=25°C, unless otherwise noted
Figure 27. Switching Frequency Figure 28. Switching Frequency
Figure 29. Maximum Output Current Figure 30. Sleep Mode Entry/Exit, IOUT = 1 mA
Figure 32. Load Transient Response, PWM Mode, IOUT (200
Figure 31. Sleep Mode Entry/Exit, IOUT = 10 mA mA to 500 mA)
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VIN=12 V, VOUT = 3.3 V, TJ=25°C, unless otherwise noted
Figure 33. Load Transient Response, PWM Mode, IOUT (200 Figure 34. Load Transient Response, PWM Mode, IOUT (200
mA to 500 mA), Rising Edge mA to 500 mA), Falling Edge
Figure 36. Load Transient Response, Power Save Mode,
Figure 35. Load Transient Response, Power Save Mode, IOUT (50 mA to 500 mA), Rising Edge
IOUT (50 mA to 500 mA)
Figure 37. Load Transient Response, Power Save Mode, Figure 38. Line Transient Response, PWM Mode, VIN (6 V
IOUT (50 mA to 500 mA), Falling Edge to 12 V), IOUT = 500 mA
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VIN=12 V, VOUT = 3.3 V, TJ=25°C, unless otherwise noted
Figure 39. Line Transient Response, Power Save Mode, VIN Figure 40. Start-Up (PWM Mode), IOUT = 250 mA
(6 V to 12 V), IOUT = 10 mA
Figure 41. Start-Up Current Limit, RLOAD = 6.6 ΩFigure 42. Start-Up (Sleep Mode), IOUT = 10 mA
Figure 44. Typical Operation in PWM Mode, IOUT = 250 mA
Figure 43. Output Discharge Function (No Load)
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VIN=12 V, VOUT = 3.3 V, TJ=25°C, unless otherwise noted
Figure 45. Typical Operation in Power Save Mode, IOUT =Figure 46. Typical Operation in Power Save Mode, IOUT = 1
75 mA mA
Figure 47. Typical Operation in Sleep Mode, IOUT = 1 mA Figure 48. Typical Operation in Power Save Mode, IOUT = 1
mA (Single Pulse)
Figure 50. Short Circuit While Running
Figure 49. Typical Operation in Sleep Mode, IOUT = 1 mA
(Single Pulse)
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VIN=12 V, VOUT = 3.3 V, TJ=25°C, unless otherwise noted
Figure 51. Short Circuit From Start-Up Figure 52. Triangular Load Sweep With Mode Transitions
(Power Save Mode - PWM Mode - Power Save Mode)
Figure 53. Triangular Load Sweep With Mode Transitions (Power Save Mode - PWM Mode - Power Save Mode), VIN = 24 V
9.3 System Examples
9.3.1 Microcontroller Power Supply
The TPS6217x can be used advantageously as the power supply rail for microcontrollers with low current power
save modes. Figure 54 shows the connection of TPS62177 to the Tiva C Series TM4C123x ARM Cortex™ - M4
MCUs (TM4C123x MCUs), using its hibernate mode signal to control sleep mode operation. More information is
found in the Application Report, Powering Tiva™ C Series Microcontrollers Using the High Efficiency DCS-
Control™ Topology (SPMA066).
spacing
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Product Folder Links: TPS62175 TPS62177
VIN
EN
SLEEP
NC
AGND
SW
VOS
PG
FB
PGND
10µH
2.2uF
R2
R1
47uF
TPS62175 100k
VIN
-VOUT
TPS62177
VIN
EN
NC
AGND
PGND
SW
VOS
PG
SLEEP
FB
4.75 to 28 V 10µH
22µF
2.2µF
100k
Tiva C Series MCU
VBAT
VDD
VDDA
HIB
2x0.01µF4x0.1µF2x1µF
0.1µF1µF
ETP
Decoupling Caps
3.3V
Lithium Battery 0.1µF
TPS62175
,
TPS62177
SLVSB35C OCTOBER 2012REVISED JULY 2015
www.ti.com
System Examples (continued)
Figure 54. Microcontroller Power Supply With Sleep Mode
spacing
9.3.2 Inverting Power Supply
The TPS6217x can be used as inverting power supply by rearranging external circuitry as shown in Figure 55.
As the former GND node now represents a voltage level below system ground, the voltage difference between
VIN and VOUT must be limited to the maximum operating voltage of 28 V.
spacing
Figure 55. Inverting Buck-Boost Converter
spacing
More information about using TPS62175 as inverting buck-boost converter can be found in the Application Note,
Using the TPS62175 in an Inverting Buck Boost Topology (SLVA542).
9.3.3 TPS62175 Adjustable Output Voltages
The following example circuits show typical schematics for commonly used output voltage values using the
adjustable device version TPS62175.
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Product Folder Links: TPS62175 TPS62177
TPS62175
VIN
EN
SLEEP
AGND
PGND
SW
VOS
PG
FB
NC
4.75 to 28V 1.8V/0.5A
10uH
22uF2.2uF
100k
200k
160k
TPS62175
VIN
EN
SLEEP
AGND
PGND
SW
VOS
PG
FB
NC
4.75 to 28V 2.5V/0.5A
10uH
22uF2.2uF
100k
390k
110k
TPS62175
VIN
EN
SLEEP
AGND
PGND
SW
VOS
PG
FB
NC
5 to 28V 5V/0.5A
10uH
22uF2.2uF
100k
787k
150k
TPS62175
,
TPS62177
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SLVSB35C OCTOBER 2012REVISED JULY 2015
System Examples (continued)
9.3.3.1 5-V / 0.5-A Power Supply
Figure 56. 5-V / 0.5-A Power Supply
9.3.3.2 2.5-V / 0.5-A Power Supply
Figure 57. 2.5-V / 0.5-A Power Supply
9.3.3.3 1.8-V / 0.5-A Power Supply
Figure 58. 1.8-V / 0.5-A Power Supply
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TPS62177
VIN
EN
SLEEP
AGND
PGND
SW
VOS
PG
FB
NC
4.75 to 28V 3.3V/0.5A
10uH
22uF2.2uF
100k
TPS62175
VIN
EN
SLEEP
AGND
PGND
SW
VOS
PG
FB
NC
4.75 to 28V 1V/0.5A
10uH
22uF2.2uF
100k
30k
120k
TPS62175
VIN
EN
SLEEP
AGND
PGND
SW
VOS
PG
FB
NC
4.75 to 28V 1.2V/0.5A
10uH
22uF2.2uF
100k
75k
150k
TPS62175
,
TPS62177
SLVSB35C OCTOBER 2012REVISED JULY 2015
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System Examples (continued)
9.3.3.4 1.2-V / 0.5-A Power Supply
Figure 59. 1.2-V / 0.5-A Power Supply
9.3.3.5 1-V / 0.5-A Power Supply
Figure 60. 1-V / 0.5-A Power Supply
9.3.4 TPS62177 Fixed 3.3-V / 0.5-A Power Supply
The following example circuit shows the typical schematic for fixed output voltage using the device version
TPS62177.
Figure 61. 3.3-V / 0.5-A Power Supply
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L
COUT
COUT
CIN
R2
R1
AGND
PGND
VIN
VOUT
TPS62175
,
TPS62177
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SLVSB35C OCTOBER 2012REVISED JULY 2015
10 Power Supply Recommendations
The TPS6217x device family has no special requirements for its input power supply. The input power supply's
output current needs to be rated according to the supply voltage, output voltage and output current of the
TPS6217x.
11 Layout
11.1 Layout Guidelines
The input capacitor needs to be placed as close as possible to the IC pins (VIN, PGND). The inductor should be
placed close to the SW pin and connect directly to the output capacitor - minimizing the loop area between the
SW pin, inductor, output capacitor and PGND pin. Also, sensitive nodes like FB and VOS should be connected
with short wires, not nearby high dv/dt signals (for example, SW). The feedback resistors, R1and R2, should be
placed close to the IC and connect directly to the AGND and FB pins.
A proper layout is critical for the operation of a switch mode power supply, even more at high switching
frequencies. Therefore the PCB layout of the TPS6217x demands careful attention to ensure operation and to
get the performance specified. A poor layout can lead to issues like poor regulation (both line and load), stability
and accuracy weaknesses, increased EMI radiation and noise sensitivity. See Figure 62 for the recommended
layout of the TPS62175, which is implemented on the EVM. Information can be found in the EVM Users Guide,
TPS62175EVM-098 Evaluation Module (SLVU743). Alternatively, the EVM Gerber data are available for
download here, SLVC453.
11.2 Layout Example
Figure 62. Layout Example Recommendation
The exposed thermal pad must be soldered to AGND and on the circuit board for mechanical reliability and to
achieve appropriate power dissipation.
Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Links: TPS62175 TPS62177
TPS62175
,
TPS62177
SLVSB35C OCTOBER 2012REVISED JULY 2015
www.ti.com
11.3 Thermal Information
The TPS6217x is designed for a maximum operating junction temperature (TJ) of 125°C. Therefore the maximum
output power is limited by the power losses. Because the thermal resistance of the package is given, the size of
the surrounding copper area and a proper thermal connection of the IC can reduce the thermal resistance. To
get an improved thermal behavior, TI recommends using top layer metal to connect the device with wide and
thick metal lines (see Figure 62). Internal ground layers can connect to vias directly under the IC for improved
thermal performance.
For more details on how to use the thermal parameters, see the application notes: Thermal Characteristics
Application Note, Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs (SZZA017),
and Semiconductor and IC Package Thermal Metrics (SPRA953).
28 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: TPS62175 TPS62177
TPS62175
,
TPS62177
www.ti.com
SLVSB35C OCTOBER 2012REVISED JULY 2015
12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
Refer to the following documents for more information:
Optimizing the TPS62175 Output Filter,SLVA543
Powering Tiva™ C Series Microcontrollers Using the High Efficiency DCS-Control™ Topology,SPMA066
Using the TPS62175 in an Inverting Buck Boost Topology,SLVA542
TPS62175EVM-098 Evaluation Module,SLVU743
Semiconductor and IC Package Thermal Metrics,SPRA953
Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs,SZZA017
12.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY
TPS62175 Click here Click here Click here Click here Click here
TPS62177 Click here Click here Click here Click here Click here
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
DCS-Control, E2E are trademarks of Texas Instruments.
ARM Cortex is a trademark of ARM Limited.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Links: TPS62175 TPS62177
TPS62175
,
TPS62177
SLVSB35C OCTOBER 2012REVISED JULY 2015
www.ti.com
12.7 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
30 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: TPS62175 TPS62177
TPS62175
,
TPS62177
www.ti.com
SLVSB35C OCTOBER 2012REVISED JULY 2015
Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 31
Product Folder Links: TPS62175 TPS62177
TPS62175
,
TPS62177
SLVSB35C OCTOBER 2012REVISED JULY 2015
www.ti.com
32 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: TPS62175 TPS62177
TPS62175
,
TPS62177
www.ti.com
SLVSB35C OCTOBER 2012REVISED JULY 2015
Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 33
Product Folder Links: TPS62175 TPS62177
PACKAGE OPTION ADDENDUM
www.ti.com 5-Mar-2015
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPS62175DQCR ACTIVE WSON DQC 10 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 62175
TPS62175DQCT ACTIVE WSON DQC 10 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 62175
TPS62177DQCR ACTIVE WSON DQC 10 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 62177
TPS62177DQCT ACTIVE WSON DQC 10 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 62177
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
PACKAGE OPTION ADDENDUM
www.ti.com 5-Mar-2015
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS62175DQCR WSON DQC 10 3000 180.0 8.4 2.25 3.25 1.05 4.0 8.0 Q1
TPS62175DQCT WSON DQC 10 250 180.0 8.4 2.25 3.25 1.05 4.0 8.0 Q1
TPS62177DQCR WSON DQC 10 3000 180.0 8.4 2.25 3.25 1.05 4.0 8.0 Q1
TPS62177DQCT WSON DQC 10 250 180.0 8.4 2.25 3.25 1.05 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Mar-2015
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS62175DQCR WSON DQC 10 3000 210.0 185.0 35.0
TPS62175DQCT WSON DQC 10 250 210.0 185.0 35.0
TPS62177DQCR WSON DQC 10 3000 210.0 185.0 35.0
TPS62177DQCT WSON DQC 10 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Mar-2015
Pack Materials-Page 2
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