X1227S8T1 - Xicor, Inc. - Datasheet.Directory

REV 1.1.5 8/2/01

Characteristics subject to change without notice.

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Preliminary Information

BLOCK DIAGRAM

Oscillator Frequency Timer

Logic

Divider Calendar

32.768kHz

Control/

Registers

1Hz Time

Keeping

Registers

Alarm Regs

Compare

Mask

RESET

Control

Decode

Logic

Alarm

(EEPROM)

SCL

SDA

Serial

Interface

Decoder

EEPROM

Array

Watchdog

Timer

Low Voltage

Reset

Registers

Status

(SRAM)

4k (512 x 8)

X1227

2-Wire RTC

Real Time Clock/Calendar/CPU Supervisor with EEPROM

FEATURES

• 2 polled alarms

—Settable on the second, minute, hour, day,

month, or day of the week

• Selectable watchdog timer (0.25s, 0.75s, 1.75s, off)

• Power on reset (250ms)

• Low voltage reset

• 2-wire interface interoperable with I

—400kHz data transfer rate

• Secondary power supply input with internal

switch-over circuitry

• On-chip oscillator compensation

• 512 x 8 bits of EEPROM

—64-byte page write mode

—3-bit Block Lock

™

protection

• Low-power CMOS

—<1µA operating current

—<3mA active current–EEPROM program

—<400µA active current–EEPROM read

• Typical nonvolatile write cycle time: 5ms

• High reliability

• Small package options

—8-lead SOIC, 8-lead TSSOP

DESCRIPTION

The X1227 is a Real Time Clock with clock/calendar CPU

Supervisor circuits and two polled alarms. The dual port

clock and alarm registers allow the clock to operate,

without loss of accuracy, even during read and write

operations.

The clock/calendar provides functionality that is con-

trollable and readable through a set of registers. The

clock, using a low-cost 32.768kHz crystal input, accu-

rately tracks the time in seconds, minutes, hours, date,

day, month and years. It has leap year correction,

automatic adjustment up to the year 2096.

The X1227 provides a watchdog timer with 3 selectable

time out periods and off. The watchdog activates a

RESET pin when it expires. The reset also goes active

when V

drops below a ﬁxed trip point. There are two

alarms where a match is monitored by polling status bits.

The device offers a backup power input pin. This V

BACK

pin allows the device to be backed up by a non-

rechargeable battery.

The X1227 provides a 4Kbit EEPROM array, giving a

safe, secure memory for critical user and conﬁguration

data. This memory is unaffected by complete failure of

the main and backup supplies.

X1227 – Preliminary Information

Characteristics subject to change without notice.

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PIN DESCRIPTIONS

Serial Clock (SCL)

The SCL input is used to clock all data into and out of

the device. The input buffer on this pin is always active

(not gated).

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into and

out of the device. It has an open drain output and may

be wire ORed with other open drain or open collector

outputs. The input buffer is always active (not gated).

An open drain output requires the use of a pull-up

resistor. The output circuitry controls the fall time of the

output signal with the use of a slope controlled pull-

down. The circuit is designed for 400kHz 2-wire inter-

face speeds.

BACK

This input provides a backup supply voltage to the

device. V

BACK

supplies power to the device in the

event the V

supply fails.

RESET Output—RESET

This is a reset signal output. This signal notiﬁes a host

processor that the watchdog time period has expired or

that the voltage has dropped below a ﬁxed V

TRIP

threshold. It is an open drain active LOW output. If the

output is unused either pull up with 5k

Ω

or tie to V

X1, X2

The X1 and X2 pins are the input and output, respec-

tively, of an inverting ampliﬁer that can be conﬁgured

for use as an on-chip oscillator. A 32.768kHz quartz

crystal is required. The recommended crystal is a Citizen

CFS206-32.768KDZF. The crystal supplies a timebase

for a clock/oscillator. Internal compensation circuitry is

included to form a complete oscillator circuit.

Figure 1. Recommended Crystal Connection

POWER CONTROL OPERATION

The Power control circuit accepts a V

and a V

BACK

input. The power control circuit will switch to V

BACK

when V

< V

BACK

- 0.2V. It will switch back to V

when V

exceeds V

BACK

Figure 2. Power Control

REAL TIME CLOCK OPERATION

The Real Time Clock (RTC) uses an external,

32.768kHz quartz crystal to maintain an accurate inter-

nal representation of the year, month, day, date, hour,

minute, and seconds. The RTC has leap-year correc-

tion and century byte. The clock also corrects for

months having fewer than 31 days and has a bit that

controls 24-hour or AM/PM format. When the X1227

powers up after the loss of both V

and V

BACK

, the

clock will not increment until at least one byte is written

to the clock register.

Reading the Real Time Clock

The RTC is read by initiating a Read command and

specifying the address corresponding to the register of

the Real Time Clock. The RTC Registers can then be

read in a Sequential Read Mode. Since the clock runs

continuously and a read takes a ﬁnite amount of time,

there is the possibility that the clock could change dur-

ing the course of a read operation. In this device, the

time is latched by the read command (falling edge of

the clock on the ACK bit prior to RTC data output) into a

separate latch to avoid time changes during the read

operation. The clock continues to run. Alarms occurring

during a read are unaffected by the read operation.

X1227

VBACK

VCC

RESET

SCL

SDA

VSS

8-Pin TSSOP

X1227

X2 VBACK

VCC

RESET SCL

SDA

VSS

8-Pin SOIC

VBACK

VCC = VBACK -0.2V

Internal

Voltage

VCC

X1227

– Preliminary Information

Characteristics subject to change without notice.

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Writing to the Real Time Clock

The time and date may be set by writing to the RTC

registers. To avoid changing the current time by an

uncompleted write operation, the current time value is

loaded into a separate buffer at the falling edge of the

clock on the ACK bit before the RTC data input bytes.

The clock continues to run. The new serial input data

replaces the values in the buffer. This new RTC value

is loaded back into the RTC Register by a stop bit at

the end of a valid write sequence. An invalid write

operation aborts the time update procedure and the

contents of the buffer are discarded. After a valid write

operation the RTC will reﬂect the newly loaded data

beginning with the ﬁrst “one second” clock cycle after

the stop bit. The RTC continues to update the time

while an RTC register write is in progress and the RTC

continues to run during any nonvolatile write

sequences. A single byte may be written to the RTC

without affecting the other bytes.

CLOCK/CONTROL REGISTERS (CCR)

The Control/Clock Registers are located in an area

separate from the EEPROM array and are only acces-

sible following a slave byte of “1101111x” and reads or

writes to addresses [0000h:003Fh].

CCR Access

The contents of the CCR can be modiﬁed by perform-

ing a byte or a page write operation directly to any

address in the CCR. Prior to writing to the CCR

(except the status register), however, the WEL and

RWEL bits must be set using a two step process (See

section “Writing to the Clock/Control Registers.”)

The CCR is divided into 5 sections. These are:

1. Alarm 0 (8 bytes)

2. Alarm 1 (8 bytes)

3. Control (4 bytes)

4. Real Time Clock (8 bytes)

5. Status (1 byte)

Sections 1) through 3) are nonvolatile and Sections 4)

and 5) are volatile. Each register is read and written

through buffers. The nonvolatile portion (or the counter

portion of the RTC) is updated only if RWEL is set and

only after a valid write operation and stop bit. A

sequential read or page write operation provides

access to the contents of only one section of the CCR

per operation. Access to another section requires a

new operation. Continued reads or writes, once reach-

ing the end of a section, will wrap around to the start of

the section. A read or page write can begin at any

address in the CCR.

Section 5) is a volatile register. It is not necessary to

set the RWEL bit prior to writing the status register.

Section 5) supports a single byte read or write only.

Continued reads or writes from this section terminates

the operation.

The state of the CCR can be read by performing a ran-

dom read at any address in the CCR at any time. This

returns the contents of that register location. Addi-

tional registers are read by performing a sequential

read. The read instruction latches all Clock registers

into a buffer, so an update of the clock does not

change the time being read. A sequential read of the

CCR will not result in the output of data from the mem-

ory array. At the end of a read, the master supplies a

stop condition to end the operation and free the bus.

After a read of the CCR, the address remains at the

previous address +1 so the user can execute a current

address read of the CCR and continue reading the

next Register.

ALARM REGISTERS

There are two alarm registers whose contents mimic

the contents of the RTC register, but add enable bits

and exclude the 24-hour time selection bit. The enable

bits specify which registers to use in the comparison

between the Alarm and Real Time Registers. For

example:

– The user can set the X1227 to alarm every Wednes-

day at 8:00AM by setting the EDWn, the EHRn and

EMNn enable bits to ‘1’ and setting the DWAn, HRAn

and MNAn Alarm registers to 8:00AM Wednesday.

– A daily alarm for 9:30PM results when the EHRn

and EMNn enable bits are set to ‘1’ and the HRAn

and MNAn registers set 9:30PM.

– Setting the EMOn bit in combination with other

enable bits and a speciﬁc alarm time, the user can

establish an alarm that triggers at the same time

once a year.

When there is a match, an alarm ﬂag is set. The occur-

rence of an alarm can only be determined by polling

the AL0 and AL1 bits.

The alarm enable bits are located in the MSB of the

particular register. When all enable bits are set to ‘0’,

there are no alarms.

X1227 – Preliminary Information

Characteristics subject to change without notice.

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Table 1. Clock/Control Memory Map

Addr. Type Reg

Name

Bit Range

Default

76543210

(optional)

003F Status SR BAT AL1 AL0 0 0 RWEL WEL RTCF 01h

0037 RTC

(SRAM)

Y2K 0 0 Y2K21 Y2K20 Y2K13 0 0 Y2K10 19/20 20h

0036 DW 0 0 0 0 0 DY2 DY1 DY0 0-6 00h

0035 YR Y23 Y22 Y21 Y20 Y13 Y12 Y11 Y10 0-99 00h

0034 MO 0 0 0 G20 G13 G12 G11 G10 1-12 00h

0033 DT 0 0 D21 D20 D13 D12 D11 D10 1-31 00h

0032 HR MIL 0 H21 H20 H13 H12 H11 H10 0-23 00h

0031 MN 0 M22 M21 M20 M13 M12 M11 M10 0-59 00h

0030 SC 0 S22 S21 S20 S13 S12 S11 S10 0-59 00h

0013 Control

(EEPROM)

DTR 0 0 0 0 0 DTR2 DTR1 DTR0 00h

0012 ATR 0 0 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 00h

0011 INT Unused

0010 BL BP2 BP1 BP0 WD1 WD0 0 0 0 00h

000F Alarm1

(EEPROM)

Y2K1 0 0 A1Y2K21 A1Y2K20 A1Y2K13 0 0 A1Y2K10 19/20 20h

000E DWA1 EDW1 0 0 0 0 DY2 DY1 DY0 0-6 00h

000D YRA1 Unused - Default = RTC Year value (No EEPROM) - Future expansion

000C MOA1 EMO1 0 0 A1G20 A1G13 A1G12 A1G11 A1G10 1-12 00h

000B DTA1 EDT1 0 A1D21 A1D20 A1D13 A1D12 A1D11 A1D10 1-31 00h

000A HRA1 EHR1 0 A1H21 A1H20 A1H13 A1H12 A1H11 A1H10 0-23 00h

0009 MNA1 EMN1 A1M22 A1M21 A1M20 A1M13 A1M12 A1M11 A1M10 0-59 00h

0008 SCA1 ESC1 A1S22 A1S21 A1S20 A1S13 A1S12 A1S11 A1S10 0-59 00h

0007 Alarm0

(EEPROM)

Y2K0 0 0 A0Y2K21 A0Y2K20 A0Y2K13 0 0 A0Y2K10 19/20 20h

0006 DWA0 EDW0 0 0 0 0 DY2 DY1 DY0 0-6 00h

0005 YRA0 Unused - Default = RTC Year value (No EEPROM) - Future expansion

0004 MOA0 EMO0 0 0 A0G20 A0G13 A0G12 A0G11 A0G10 1-12 00h

0003 DTA0 EDT0 0 A0D21 A0D20 A0D13 A0D12 A0D11 A0D10 1-31 00h

0002 HRA0 EHR0 0 A0H21 A0H20 A0H13 A0H12 A0H11 A0H10 0-23 00h

0001 MNA0 EMN0 A0M22 A0M21 A0M20 A0M13 A0M12 A0M11 A0M10 0-59 00h

0000 SCA0 ESC0 A0S22 A0S21 A0S20 A0S13 A0S12 A0S11 A0S10 0-59 00h

REAL TIME CLOCK REGISTERS

Year 2000 (Y2K)

The X1227 has a century byte that “rolls over” from 19

to 20 when the years byte changes from 99 to 00. The

Y2K byte can contain only the values of 19 or 20.

Day of the Week Register (DW)

This register provides a Day of the Week status and

uses three bits DY2 to DY0 to represent the seven

days of the week. The counter advances in the cycle

0-1-2-3-4-5-6-0-1-2-... The assignment of a numerical

value to a speciﬁc day of the week is arbitrary and may

be decided by the system software designer. The

Clock Default values deﬁne 0 = Sunday.

X1227

– Preliminary Information

Characteristics subject to change without notice.

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Clock/Calendar Register (YR, MO, DT, HR, MN, SC)

These registers depict BCD representations of the

time. As such, SC (Seconds) and MN (Minutes) range

from 0 to 59, HR (Hour) is 1 to 12 with an AM or PM

indicator (H21 bit) or 0 to 23 (with MIL=1), DT (Date) is

1 to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99.

24 Hour Time

If the MIL bit of the HR register is 1, the RTC uses a

24-hour format. If the MIL bit is 0, the RTC uses a 12-

hour format and bit H21 functions as an AM/PM indi-

cator with a ‘1’ representing PM. The clock defaults to

Standard Time with H21=0.

Leap Years

Leap years add the day February 29 and are deﬁned

as those years that are divisible by 4. Years divisible by

100 are not leap years, unless they are also divisible

by 400. This means that the year 2000 is a leap year,

the year 2100 is not. The X1227 does not correct for

the leap year in the year 2100.

STATUS REGISTER (SR)

The Status Register is located in the RTC area at

address 003Fh. This is a volatile register only and is

used to control the WEL and RWEL write enable

latches, read two power status and two alarm bits. This

Control Registers (CCR).

Table 2. Status Register (SR)

BAT: Battery Supply—Volatile

This bit set to “1” indicates that the device is operating

from V

BACK

, not V

. It is a read only bit and is set/

reset by hardware.

AL1, AL0: Alarm bits—Volatile

These bits announce if either alarm 1 or alarm 2 match

the real time clock. If there is a match, the respective

bit is set to ‘1’. The falling edge of the last data bit in a

SR Read operation resets the ﬂags. Note: Only the AL

bits that are set when an SR read starts will be reset.

An alarm bit that is set by an alarm occurring during an

SR read operation will remain set after the read opera-

tion is complete.

RWEL: Register Write Enable Latch—Volatile

This bit is a volatile latch that powers up in the LOW

(disabled) state. The RWEL bit must be set to “1” prior

to any writes to the Clock/Control Registers. Writes to

RWEL bit do not cause a nonvolatile write cycle, so the

device is ready for the next operation immediately after

the stop condition. A write to the CCR requires both

the RWEL and WEL bits to be set in a speciﬁc

sequence.

WEL: Write Enable Latch—Volatile

The WEL bit controls the access to the CCR and

memory array during a write operation. This bit is a

volatile latch that powers up in the LOW (disabled)

state. While the WEL bit is LOW, writes to the CCR or

any array address will be ignored (no acknowledge will

be issued after the Data Byte). The WEL bit is set by

writing a “1” to the WEL bit and zeroes to the other bits

of the Status Register. Once set, WEL remains set

until either reset to 0 (by writing a “0” to the WEL bit

and zeroes to the other bits of the Status Register) or

until the part powers up again. Writes to WEL bit do

not cause a nonvolatile write cycle, so the device is

ready for the next operation immediately after the stop

condition.

RTCF: Real Time Clock Fail Bit—Volatile

This bit is set to a ‘1’ after a total power failure. This is

a read only bit that is set by hardware when the device

powers up after having lost all power to the device.

The bit is set regardless of whether V

or V

BACK

applied ﬁrst. The loss of one or the other supplies does

not result in setting the RTCF bit. The ﬁrst valid write to

the RTC (writing one byte is sufﬁcient) resets the

RTCF bit to ‘0’.

Unused Bits

These devices do not use bits 3 or 4, but must have a

zero in these bit positions. The Data Byte output dur-

ing a SR read will contain zeros in these bit locations.

CONTROL REGISTER

Block Protect Bits—BP2, BP1, BP0—(Nonvolatile)

The Block Protect Bits, BP2, BP1 and BP0, determine

which blocks of the array are write-protected. A write

to a protected block of memory is ignored. The block

protect bits will prevent write operations to one of eight

segments of the array. The partitions are described in

Table 3 .

Addr 7 6 5 4 3 2 1 0

003Fh BAT AL1 AL0 0 0 RWEL WEL RTCF

Default 0 0 0 0 0 0 0 1

X1227 – Preliminary Information

Characteristics subject to change without notice.

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Table 3. Block Protect Bits

Watchdog Timer Control Bits

The bits WD1 and WD0 control the period of the

Watchdog Timer. See Table 4 for options.

Table 4. Watchdog Timer Time Out Options

Digital Trimming Register (DTR)—DTR2, DTR1 and

DTR0 (Nonvolatile)

The digital trimming bits

DTR2

DTR1

and

DTR0

adjust the number of count per second and average

the ppm error to achieve a better time over a long

period.

DTR2

is a sign bit when equal to 1 means posi-

tive ppm and 0 means negative ppm compensation. A

range from -30ppm to +30ppm can be represented by

using the three bits.

Table 5. Digital Trimming Registers

Analog Trimming Register (ATR)—ATR5, ATR4...

and ATR0 (Nonvolatile)

Six analog trimming bits from

ATR5

ATR0

are pro-

vided to adjust the on-chip loading capacitance range.

The effective load capacitance ranges from 5.25pF to

18.75pF. Each bit has different weight for capacitance

adjustment. This will allow 6pF or 12.5pF crystal being

used and widen the selection. In addition, using a Citi-

zen CSF-206 crystal with different ATR bits combina-

tions, it provides an estimated ppm range from

+116ppm to -37ppm to the nominal frequency com-

pensation. The combination of digital and analog trim-

ming can give up to +146ppm adjustment.

The on-chip capacitance can be calculated as follows:

ATR

= [(ATR value, decimal) x 0.25pF] + 11.0pF

Note that the ATR values are in two’s complement,

with ATR(000000) = 11.0pF, so the entire range runs

from 3.25pF to 18.75pF in 0.25pF steps.

The total load capacitance seen by the crystal will

include approximately 2pF of package and board

capacitance in addition to the ATR value.

BP2

BP1

BP0

Protected Addresses

X1227 Array Lock

0 0 0 None None

001 180

- 1FF

Upper 1/4

010 100

- 1FF

Upper 1/2

011 000

- 1FF

Full Array

100 000

- 03F

First Page

101 000

- 07F

First 2 pgs

110 000

- 0FF

First 4 pgs

111 000

- 1FF

First 8 pgs

WD1 WD0 Watchdog Time Out Period

0 0 1.75 seconds

0 1 750 milliseconds

1 0 250 milliseconds

1 1 Disabled

DTR Register

Estimated PPMDTR2 DTR1 DTR0

000 -0

0 1 0 -10

0 0 1 -20

0 1 1 -30

100 +0

1 1 0 +10

1 0 1 +20

1 1 1 +30

X1227

– Preliminary Information

Characteristics subject to change without notice.

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WRITING TO THE CLOCK/CONTROL REGISTERS

Changing any of the nonvolatile bits of the clock/control

– Write a 02h to the Status Register to set the Write

Enable Latch (WEL). This is a volatile operation, so

there is no delay after the write. (Operation pre-

ceeded by a start and ended with a stop).

– Write a 06h to the Status Register to set both the

bit. This is also a volatile cycle. The zeros in the data

byte are required. (Operation preceeded by a start

and ended with a stop).

– Write one to 8 bytes to the Clock/Control Registers

with the desired clock, alarm, or control data. This

sequence starts with a start bit, requires a slave byte

of “11011110” and an address within the CCR and is

terminated by a stop bit. A write to the CCR changes

EEPROM values so these initiate a nonvolatile write

cycle and will take up to 10ms to complete. Writes to

undeﬁned areas have no effect. The RWEL bit is

reset by the completion of a nonvolatile write cycle,

so the sequence must be repeated to again initiate

another change to the CCR contents. If the

sequence is not completed for any reason (by send-

ing an incorrect number of bits or sending a start

instead of a stop, for example) the RWEL bit is not

reset and the device remains in an active mode.

– Writing all zeros to the status register resets both the

WEL and RWEL bits.

– A read operation occurring between any of the previ-

ous operations will not interrupt the register write

operation.

– The RWEL and WEL bits can be reset by writing a 0

to the Status Register.

POWER ON RESET

Application of power to the X1227 activates a Power

On Reset Circuit that pulls the RESET pin active. This

signal provides several beneﬁts.

– It prevents the system microprocessor from starting

to operate with insufﬁcient voltage.

– It prevents the processor from operating prior to sta-

bilization of the oscillator.

– It allows time for an FPGA to download its conﬁgura-

tion prior to initialization of the circuit.

– It prevents communication to the EEPROM, greatly

reducing the likelihood of data corruption on power

up.

When V

exceeds the device V

TRIP

threshold value

for 250ms the circuit releases RESET

, allowing the

system to begin operation.

WATCHDOG TIMER OPERATION

The watchdog timer is selectable. By writing a value to

WD1 and WD0, the watchdog timer can be set to 3 dif-

ferent time out periods or off. When the Watchdog

timer is set to off, the watchdog circuit is conﬁgured for

low power operation.

Watchdog Timer Restart

The Watchdog Timer is restarted by a falling edge of

SDA when the SCL line is high and followed by a stop

bit. This is also referred to as start condition. The

restart signal restarts the watchdog timer counter,

resetting the period of the counter back to the maxi-

mum. If another start fails to be detected prior to the

watchdog timer expiration, then the RESET pin

becomes active. In the event that the restart signal

occurs during a reset time out period, the restart will

have no effect. When using a single START to refresh

watchdog timer, a STOP bit should be followed to reset

the device back to stand-by mode.

LOW VOLTAGE RESET OPERATION

When a power failure occurs, and the voltage to the

part drops below a ﬁxed VTRIP voltage, a reset pulse is

issued to the host microcontroller. The circuitry moni-

tors the VCC line with a voltage comparator which

senses a preset threshold voltage. Power up and

power down waveforms are shown in Figure 4. The

Low Voltage Reset circuit is to be designed so the

RESET signal is valid down to 1.0V.

When the low voltage reset signal is active, the operation

of any in progress nonvolatile write cycle is unaffected,

allowing a nonvolatile write to continue as long as possi-

ble (down to the power on reset voltage). The low voltage

reset signal, when active, terminates in progress commu-

nications to the device and prevents new commands, to

reduce the likelihood of data corruption.

X1227 – Preliminary Information

Characteristics subject to change without notice. 8 of 25

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Figure 3. Watchdog Restart/Time Out

Figure 4. Power On Reset and Low Voltage Reset

tRSP<tWDO tRST

RESET

SDA

tRSP

Note: All inputs are ignored during the active reset period (tRST).

tRST

SCL

tRSP>tWDO

Start Stop Start

VCC

VTRIP

RESET

tPURST tPURST

tRPD

VRVALID

VCC THRESHOLD RESET PROCEDURE

The X1227 is shipped with a standard VCC threshold

(VTRIP) voltage. This value will not change over normal

operating and storage conditions. However, in applica-

tions where the standard VTRIP is not exactly right, or if

higher precision is needed in the VTRIP value, the

X1227 threshold may be adjusted. The procedure is

described below, and uses the application of a nonvolatile

write control signal.

Setting the VTRIP Voltage

It is necessary to reset the trip point before setting the

new value.

To set the new VTRIP voltage, apply the desired VTRIP

threshold voltage to the VCC pin and tie the RESET pin

to the programming voltage VP

. Then write data 00h to

address 01h. The stop bit following a valid write opera-

tion initiates the VTRIP programming sequence. Bring

RESET to VCC to complete the operation. Note: this

operation also writes 00h to address 01h of the

EEPROM array.

X1227 – Preliminary Information

Characteristics subject to change without notice. 9 of 25

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Figure 5. Set VTRIP Level Sequence (VCC = desired VTRIP value.)

SCL

SDA

01h

RESET VP = 15V

00h

01234567 01234567 01234567 01234567

AEh 00h

VCC

Note: BP0, BP1, BP2 must be disabled.

Resetting the VTRIP Voltage

This procedure is used to set the VTRIP to a “native”

voltage level. For example, if the current VTRIP is 4.4V

and the new VTRIP must be 4.0V, then the VTRIP must

be reset. When VTRIP is reset, the new VTRIP is some-

thing less than 1.7V. This procedure must be used to

set the voltage to a lower value.

To reset the new VTRIP voltage, apply more than 3V to

the VCC pin and tie the RESET pin to the programming

voltage VP

. Then write 00h to address 03h. The stop bit

of a valid write operation initiates the VTRIP program-

ming sequence. Bring RESET to VCC to complete the

operation. Note: this operation also writes 00h to

address 03h of the EEPROM array.

For best accuracy in setting VTRIP

, it is advised that the

following sequence be used.

1.Program VTRIP as above.

2.Measure resulting VTRIP by measuring the VCC

value where a RESET occurs. Calculate Delta =

(Desired – Measured) VTRIP value.

3.Perform a VTRIP program using the following formula

to set the voltage of the RESET pin:

VRESET = (Desired Value – Delta) + 0.25V

Figure 6. Reset VTRIP Level Sequence (VCC > 3V)

01234567

SCL

SDA

AEh

01234567

03h

RESET VP = 15V

00h

01234567 01234567

00h

VCC

Note: BP0, BP1, BP2 must be disabled.

SERIAL COMMUNICATION

Interface Conventions

The device supports a bidirectional bus oriented proto-

col. The protocol deﬁnes any device that sends data

onto the bus as a transmitter, and the receiving device

as the receiver. The device controlling the transfer is

called the master and the device being controlled is

called the slave. The master always initiates data

transfers, and provides the clock for both transmit and

receive operations. Therefore, the devices in this family

operate as slaves in all applications.

Clock and Data

Data states on the SDA line can change only during

SCL LOW. SDA state changes during SCL HIGH are

reserved for indicating start and stop conditions. See

Figure 7.

X1227 – Preliminary Information

Characteristics subject to change without notice. 10 of 25

REV 1.1.5 8/2/01 www.xicor.com

Figure 7. Valid Data Changes on the SDA Bus

SCL

SDA

Data Stable Data Change Data Stable

Start Condition

All commands are preceded by the start condition,

which is a HIGH to LOW transition of SDA when SCL is

HIGH. The device continuously monitors the SDA and

SCL lines for the start condition and will not respond to

any command until this condition has been met. See

Figure 8.

Stop Condition

All communications must be terminated by a stop con-

dition, which is a LOW to HIGH transition of SDA when

SCL is HIGH. The stop condition is also used to place

the device into the Standby power mode after a read

sequence. A stop condition can only be issued after the

transmitting device has released the bus. See Figure 7.

Acknowledge

Acknowledge is a software convention used to indicate

successful data transfer. The transmitting device, either

master or slave, will release the bus after transmitting

eight bits. During the ninth clock cycle, the receiver will

pull the SDA line LOW to acknowledge that it received

the eight bits of data. Refer to Figure 9.

Figure 8. Valid Start and Stop Conditions

SCL

SDA

Start Stop

The device will respond with an acknowledge after rec-

ognition of a start condition and if the correct Device

Identiﬁer and Select bits are contained in the Slave

Address Byte. If a write operation is selected, the

device will respond with an acknowledge after the

receipt of each subsequent eight bit word. The device

will acknowledge all incoming data and address bytes,

except for:

– The Slave Address Byte when the Device Identiﬁer

and/or Select bits are incorrect

– All Data Bytes of a write when the WEL in the Write

Protect Register is LOW

– The 2nd Data Byte of a Status Register Write Opera-

tion (only 1 data byte is allowed)

In the read mode, the device will transmit eight bits of

data, release the SDA line, then monitor the line for an

acknowledge. If an acknowledge is detected and no

stop condition is generated by the master, the device

will continue to transmit data. The device will terminate

further data transmissions if an acknowledge is not

detected. The master must then issue a stop condition

to return the device to Standby mode and place the

device into a known state.

X1227 – Preliminary Information

Characteristics subject to change without notice. 11 of 25

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DEVICE ADDRESSING

Following a start condition, the master must output a

Slave Address Byte. The ﬁrst four bits of the Slave

Address Byte specify access to either the EEPROM

array or to the CCR. Slave bits ‘1010’ access the

EEPROM array. Slave bits ‘1101’ access the CCR.

Bit 3 through Bit 1 of the slave byte specify the device

select bits. These are set to ‘111’.

The last bit of the Slave Address Byte deﬁnes the oper-

ation to be performed. When this R/W bit is a one, then

a read operation is selected. A zero selects a write

operation. Refer to Figure 18.

After loading the entire Slave Address Byte from the

SDA bus, the X1228 compares the device identiﬁer

and device select bits with ‘1010111’ or ‘1101111’.

Upon a correct compare, the device outputs an

acknowledge on the SDA line.

Following the Slave Byte is a two byte word address.

The word address is either supplied by the master

device or obtained from an internal counter. On power

up the internal address counter is set to address 0h, so

a current address read of the EEPROM array starts at

address 0. When required, as part of a random read,

the master must supply the 2 Word Address Bytes as

shown below.

In a random read operation, the slave byte in the

“dummy write” portion must match the slave byte in the

“read” section. That is if the random read is from the

array the slave byte must be 1010111x in both

instances. Similarly, for a random read of the Clock/

Control Registers, the slave byte must be 1101111x in

both places.

Slave Address, Word Address, and Data Bytes (64 Byte pages)

Slave Address Byte

Byte 0

D7 D6 D5 D2D4 D3 D1 D0

A0A7 A2A4 A3 A1

Data Byte

Byte 3

A6 A5

00 0 A10 A9 A80

11R/W

Device Identifier

Array

CCR

High Order Word Address

Byte 1

Low Order Word Address

Byte 2

X1227 – Preliminary Information

Characteristics subject to change without notice. 12 of 25

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Figure 9. Acknowledge Response From Receiver

SCL from

Master

Data Output

from Transmitter

Data Output

from Receiver

81 9

Start Acknowledge

WRITE OPERATIONS

Byte Write

For a write operation, the device requires the Slave

Address Byte and the Word Address Bytes. This gives

the master access to any one of the words in the array

or CCR. (Note: Prior to writing to the CCR, the master

must write a 02h, then 06h to the status register in two

preceding operations to enable the write operation.

See “Writing to the Clock/Control Registers” on page

6.) Upon receipt of each address byte, the X1227

responds with an acknowledge. After receiving both

address bytes the X1227 awaits the eight bits of data.

After receiving the 8 data bits, the X1227 again

responds with an acknowledge. The master then termi-

nates the transfer by generating a stop condition. The

X1227 then begins an internal write cycle of the data to

the nonvolatile memory. During the internal write cycle,

the device inputs are disabled, so the device will not

respond to any requests from the master. The SDA out-

put is at high impedance. See Figure 10.

Figure 10. Byte Write Sequence

Figure 11. Writing 30 bytes to a 64-byte memory page starting at address 40.

Slave

Address

Word

Address 1

Data

SDA Bus

Signals From

The Slave

Signals from

the Master

Word

Address 0

1111 0 0000

Address

23 Bytes

7 Bytes

Address

= 6

Address Pointer

Ends Here

Addr = 7

X1227 – Preliminary Information

Characteristics subject to change without notice. 13 of 25

REV 1.1.5 8/2/01 www.xicor.com

A write to a protected block of memory is ignored, but

will still receive an acknowledge. At the end of the write

command, the X1227 will not initiate an internal write

cycle, and will continue to ACK commands.

Page Write

The X1227 has a page write operation. It is initiated in

the same manner as the byte write operation; but

instead of terminating the write cycle after the ﬁrst data

byte is transferred, the master can transmit up to 63

more bytes to the memory array and up to 7 more

bytes to the clock/control registers. (Note: Prior to writ-

ing to the CCR, the master must write a 02h, then 06h

to the status register in two preceding operations to

enable the write operation. See “Writing to the Clock/

Control Registers” on page 6.)

After the receipt of each byte, the X1227 responds with

an acknowledge, and the address is internally incrimi-

nated by one. When the counter reaches the end of the

page, it “rolls over” and goes back to the ﬁrst address

on the same page. This means that the master can

write 64 bytes to a memory array page or 8 bytes to a

CCR section starting at any location on that page. If

the master begins writing at location 40 of the memory

and loads 30 bytes, then the ﬁrst 23 bytes are written

to addresses 40 through 63, and the last 7 bytes are

written to columns 0 through 6. Afterwards, the

address counter would point to location 7 on the page

that was just written. If the master supplies more than

the maximum bytes in a page, then the previously

loaded data is over written by the new data, one byte at

a time.

The master terminates the Data Byte loading by issu-

ing a stop condition, which causes the X1227 to begin

the nonvolatile write cycle. As with the byte write oper-

ation, all inputs are disabled until completion of the

internal write cycle. Refer to Figure 12 for the address,

acknowledge, and data transfer sequence.

Stops and Write Modes

Stop conditions that terminate write operations must

be sent by the master after sending at least 1 full data

byte and it’s associated ACK signal. If a stop is issued

in the middle of a data byte, or before 1 full data byte +

ACK is sent, then the X1227 resets itself without per-

forming the write. The contents of the array are not

affected.

Figure 12. Page Write Sequence

Figure 13. Current Address Read Sequence

Word

Address 0

Slave

Address

Word

Address 1

Data

(n)

SDA Bus

Signals from

the Slave

Signals from

the Master

Data

(1)

(1 ≤ n ≤ 64)

1111 00000

Slave

Address

Data

SDA Bus

Signals from

the Slave

Signals from the

Master

11111

X1227 – Preliminary Information

Characteristics subject to change without notice. 14 of 25

REV 1.1.5 8/2/01 www.xicor.com

Acknowledge Polling

Disabling of the inputs during nonvolatile write cycles

can be used to take advantage of the typical 5mS write

cycle time. Once the stop condition is issued to indi-

cate the end of the master’s byte load operation, the

X1227 initiates the internal nonvolatile write cycle.

Acknowledge polling can begin immediately. To do this,

the master issues a start condition followed by the

Slave Address Byte for a write or read operation. If the

X1227 is still busy with the nonvolatile write cycle then

no ACK will be returned. When the X1227 has com-

pleted the write operation, an ACK is returned and the

host can proceed with the read or write operation.

Refer to the ﬂow chart in Figure 14.

Read Operations

There are three basic read operations: Current

Address Read, Random Read, and Sequential Read.

Current Address Read

Internally the X1227 contains an address counter that

maintains the address of the last word read incrimi-

nated by one. Therefore, if the last read was to address

n, the next read operation would access data from

address n+1. On power up, the sixteen bit address is

initialized to 0h. In this way, a current address read

immediately after the power on reset can download the

entire contents of memory starting at the ﬁrst loca-

tion.Upon receipt of the Slave Address Byte with the R/

W bit set to one, the X1227 issues an acknowledge,

then transmits eight data bits. The master terminates

the read operation by not responding with an acknowl-

edge during the ninth clock and issuing a stop condi-

tion. Refer to Figure 12 for the address, acknowledge,

and data transfer sequence.

Figure 14. Acknowledge Polling Sequence

It should be noted that the ninth clock cycle of the read

operation is not a “don’t care.” To terminate a read

operation, the master must either issue a stop condi-

tion during the ninth cycle or hold SDA HIGH during

the ninth clock cycle and then issue a stop condition.

ACK

returned?

Issue Slave

Address Byte

(Read or Write)

Byte load completed

by issuing STOP.

Enter ACK Polling

Issue STOP

Issue START

YES

Issue STOP

Continue normal

Read or Write

command

sequence

PROCEED

YES

nonvolatile write

Cycle complete.

Continue command

sequence?

X1227 – Preliminary Information

Characteristics subject to change without notice. 15 of 25

REV 1.1.5 8/2/01 www.xicor.com

Random Read

Random read operations allows the master to access

any location in the X1227. Prior to issuing the Slave

Address Byte with the R/W bit set to one, the master

must ﬁrst perform a “dummy” write operation.

The master issues the start condition and the slave

address byte, receives an acknowledge, then issues

the word address bytes. After acknowledging receipt of

each word address byte, the master immediately

issues another start condition and the slave address

byte with the R/W bit set to one. This is followed by an

acknowledge from the device and then by the eight bit

data word. The master terminates the read operation

by not responding with an acknowledge and then issu-

ing a stop condition. Refer to Figure 15 for the address,

acknowledge, and data transfer sequence.

In a similar operation called “Set Current Address,” the

device sets the address if a stop is issued instead of

the second start shown in Figure 15. The X1227 then

goes into standby mode after the stop and all bus

activity will be ignored until a start is detected. This

operation loads the new address into the address

counter. The next Current Address Read operation will

read from the newly loaded address. This operation

could be useful if the master knows the next address it

needs to read, but is not ready for the data.

Sequential Read

Sequential reads can be initiated as either a current

address read or random address read. The ﬁrst data

byte is transmitted as with the other modes; however,

the master now responds with an acknowledge, indi-

cating it requires additional data. The device continues

to output data for each acknowledge received. The mas-

ter terminates the read operation by not responding with

an acknowledge and then issuing a stop condition.

Figure 15. Random Address Read Sequence

Slave

Address Word

Address 1

Slave

Address

Data

SDA Bus

Signals from

the Slave

Signals from the

Master

Word

Address 0

111100000 1111

The data output is sequential, with the data from

address n followed by the data from address n + 1. The

address counter for read operations increments

through all page and column addresses, allowing the

entire memory contents to be serially read during one

operation. At the end of the address space the counter

“rolls over” to the start of the address space and the

X1227 continues to output data for each acknowledge

received. Refer to Figure 16 for the acknowledge and

data transfer sequence.

X1227 – Preliminary Information

Characteristics subject to change without notice. 16 of 25

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ABSOLUTE MAXIMUM RATINGS

Temperature under bias .................... -65°C to +135°C

Storage temperature ......................... -65°C to +150°C

Voltage on any pin (respect to ground).. -1.0V to 7.0V*

DC output current................................................ 5 mA

Lead temperature (soldering, 10 sec) ............... 300°C

*The voltage on the RESET pin is allowed to go to

+15V maximum for VTRIP programming purposes

only.

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

This is a stress rating only; functional operation of the

device (at these or any other conditions above those

indicated in the operational sections of this speciﬁca-

tion) is not implied. Exposure to absolute maximum rat-

ing conditions for extended periods may affect device

reliability.

DC OPERATING CHARACTERISTICS Temperature = -40°C to +85°C, unless otherwise stated.

Symbol Parameter Conditions Min. Typ. Max. Unit Notes

VCC Main Power Supply 2.7 5.5 V

VBACK Backup Power Supply 1.8 5.5 V

VCB Switch to Backup Supply VBACK – 0.1 VBACK + 0.2 V 4

VBC Switch to Main Supply VBACK VBACK + 0.2 V 4

ICC1 Active Supply Current VCC = 2.7V 400 µA 1, 5, 8, 15

VCC = 5.5V 800 µA

ICC2 Program Supply Current

(nonvolatile)

VCC = 2.7V 1.5 mA 2, 5, 8, 15

VCC = 5.5V 3.0 mA

ICC3 Main Timekeeping

Current

VCC = 2.7V 1.5 5.0 µA 3, 8, 9, 16, 17

VCC = 5.5V 1.5 10.0 µA

IBACK1 Backup Timekeeping

Current

VBACK = 1.8V 1.0 1.5 µA 3, 7, 10, 16, 17

VBACK = 3.3V 1.5 2.0 µA

VBACK = 5.5V 1.5 10.0 µA

ILI Input Leakage Current 10 µA 11

ILO Output Leakage Current 10 µA 11

VIL Input LOW Voltage -0.5 VCC x 0.2 or

VBACK x 0.2

V 4, 14

VIH Input HIGH Voltage VCC x 0.7 or

VBACK x 0.7

VCC + 0.5

VBACK + 0.5

V 4, 14

VHYS Schmitt Trigger Input

Hysteresis

VCC related level VCC x 0.7 or

VBACK x 0.7

V14

VOL Output LOW Voltage VCC = 2.7V 0.4 V 12

VCC = 5.5V 0.4

VOH Output LOW Voltage VCC = 2.7V 1.6 V 13

VCC = 5.5V 2.4

X1227 – Preliminary Information

Characteristics subject to change without notice. 17 of 25

REV 1.1.5 8/2/01 www.xicor.com

Notes:

(1) The device enters the Active state after any start, and remains active: for 9 clock cycles if the Device Select Bits in the Slave

Address Byte are incorrect or until 200ns after a stop ending a read or write operation.

(2) The device enters the Program state 200ns after a stop ending a write operation and continues for tWC.

(3) The device goes into the Timekeeping state 200ns after any stop, except those that initiate a nonvolatile write cycle; tWC after a stop

that initiates a nonvolatile write cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the

Slave Address Byte.

(4) For reference only and not tested.

(5) VIL = VCC x 0.1, VIH = VCC x 0.9, fSCL = 400kHz, SDA = Open

(6) VIL = VCC x 0.1, VIH = VCC x 0.9, fSCL = 400kHz, fSDA = 400kHz, VCC = 1.22 x VCC Min

(7) VCC = 0V

(8) VBACK = 0V

(9) VSDA = VSCL = VCC, Others = GND or VCC

(10)VSDA = VSCL = VBACK, Others = GND or VBACK

(11)VSDA = GND to VCC, VCLK = GND or VCC

(12)IOL = 3.0mA at 5V, 1.5mA at 2.7V

(13)IOH = -1.0mA at 5V, -0.4mA at 2.7V

(14)Threshold voltages based on the higher of VCC or VBACK.

(15)Driven by external 32.768kHz square wave oscillator on X1, X2 open.

(16)Using recommended crystal and oscillator network applied to X1 and X2 (25°C). Periodically sampled and not 100% tested.

(17)Average Supply Current. Instantaneous peaks may exceed the average.

Capacitance TA = 25°C, f = 1.0 MHz, VCC = 5V

Note: (1) This parameter is periodically sampled and not 100% tested.

Symbol Parameter Max. Units Test Conditions

COUT(1) Output Capacitance (SDA, IRQ)10pF V

OUT = 0V

CIN(1) Input Capacitance (SCL) 10 pF VIN = 0V

AC CHARACTERISTICS

AC Test Conditions

Figure 16. Standard Output Load for testing the

device with VCC = 5.0V

Input pulse levels VCC x 0.1 to VCC x 0.9

Input rise and fall times 10ns

Input and output timing levels VCC x 0.5

Output load Standard output load

SDA

1533Ω

100pF

5.0V

For VOL= 0.4V

and IOL = 3 mA

Equivalent AC Output Load Circuit for VCC = 5V

X1227 – Preliminary Information

Characteristics subject to change without notice. 18 of 25

REV 1.1.5 8/2/01 www.xicor.com

AC SPECIFICATIONS TA = -55°C to +125°C, VCC = +2.7V to +5.5V, unless otherwise speciﬁed.

Notes: (1) Typical values are for TA = 25°C and VCC = 5.0V

(2) This parameter is periodically sampled and not 100% tested.

(3) Cb = total capacitance of one bus line in pF.

TIMING DIAGRAMS

Bus Timing

Symbol Parameter Min. Max. Unit

fSCL SCL Clock Frequency 0 400 kHz

tIN Pulse width Suppression Time at inputs 50 ns

tAA SCL LOW to SDA Data Out Valid 0.1 0.9 µs

tBUF Time the bus must be free before a new transmission can start 1.3 µs

tLOW Clock LOW Time 1.3 µs

tHIGH Clock HIGH Time 0.6 µs

tSU:STA Start Condition Setup Time 0.6 µs

tHD:STA Start Condition Hold Time 0.6 µs

tSU:DAT Data In Setup Time 100 ns

tHD:DAT Data In Hold Time 0 µs

tSU:STO Stop Condition Setup Time 0.6 µs

tDH Data Output Hold Time 50 ns

tR(2) SDA and SCL Rise Time 20 +.1Cb(3) 300 ns

tF(2) SDA and SCL Fall Time 20 +.1Cb(3) 300 ns

Cb(2) Capacitive load for each bus line 400 pF

tSU:STO

tDH

tHIGH

tSU:ST tHD:STA

tHD:DAT

tSU:DAT

SCL

SDA IN

SDA OUT

tFtLOW

tBUF

tAA

X1227 – Preliminary Information

Characteristics subject to change without notice. 19 of 25

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Write Cycle Timing

Power Up Timing

Notes: (1) Delays are measured from the time VCC is stable until the speciﬁed operation can be initiated. These parameters are periodically

sampled and not 100% tested.

(2) Typical values are for TA = 25°C and VCC = 5.0V

Nonvolatile Write Cycle Timing

Note: (1) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle.

It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.

Symbol Parameter Min. Max. Unit

tPUR(1) Time from Power Up to Read 1 ms

tPUW(1) Time from Power Up to Write 5 ms

Symbol Parameter Min. Typ.(1) Max. Unit

tWC(1) Write Cycle Time 2 10 ms

SCL

SDA

tWC

8th Bit of Last Byte ACK

Stop

Condition

Start

Condition

X1227 – Preliminary Information

Characteristics subject to change without notice. 20 of 25

REV 1.1.5 8/2/01 www.xicor.com

WATCHDOG TIMER/LOW VOLTAGE RESET OPERATING CHARACTERISTICS

Watchdog/Low Voltage Reset Parameters

VTRIP Programming Timing Diagram

Symbols Parameters Min. Typ. Max. Unit

VPTRIP Programmed Reset Trip Voltage

X1227-4.5A

X1227

X1227-2.7A

X1227-2.7

4.49

4.25

2.76

2.57

4.68

4.38

2.85

2.65

4.77

4.51

2.94

2.73

tRPD VCC Detect to RST LOW (RST HIGH) 500 ns

tPURST1 Power Up Reset Time Out Delay 100 200 400 ms

tFVCC Fall Time 10 µs

tRVCC Rise Time 10 µs

tWDO Watchdog Timer Period:

WD1=0, WD0=0

WD1=0, WD0=1

WD1=1, WD0=0

1.7

725

225

1.75

750

250

1.8

775

275

tRST1 Watchdog Reset Time Out Delay 225 250 275 ms

tRSP 2-Wire interface 1 µs

VRVALID Reset Valid VCC 1.0 V

01234567 01234567 01234567 01234567

VCC

(VTRIP)

tVPH

tVPS tVPO

tRP

SCL

SDA

AEh 03h/01h

RESET VP = 15V

00h00h

VCC

tTSU tTHD

VTRIP

X1227 – Preliminary Information

Characteristics subject to change without notice. 21 of 25

REV 1.1.5 8/2/01 www.xicor.com

VTRIP Programming Parameters

Parameter Description Min. Max. Units

tVPS VTRIP Program Enable Voltage Setup time 1 µs

tVPH VTRIP Program Enable Voltage Hold time 1 µs

tTSU VTRIP Setup time 1 µs

tTHD VTRIP Hold (stable) time 10 ms

tWC VTRIP Write Cycle Time 10 ms

tVPO VTRIP Program Enable Voltage Off time (Between successive adjustments) 0 µs

tRP VTRIP Program Recovery Period (Between successive adjustments) 10 ms

VPProgramming Voltage 14 15 V

VTRAN VTRIP Programmed Voltage Range 1.7 5.0 V

Vta VTRIP Program Voltage accuracy [(VCC applied—Vta1)—VTRIP. Programmed at

25°C.)

-25 +25 mV

Vtr VTRIP Program Voltage repeatability (Successive program operations.

Programmed at 25°C.)

-25 +25 mV

Vtv VTRIP Program variation after programming (0-75°C). (Programmed at 25°C.) -25 +25 mV

VTRIP Programming parameters are periodically sampled and are not 100% tested.

X1227 – Preliminary Information

Characteristics subject to change without notice. 22 of 25

REV 1.1.5 8/2/01 www.xicor.com

PACKAGING INFORMATION

0.150 (3.80)

0.158 (4.00)

0.228 (5.80)

0.244 (6.20)

0.014 (0.35)

0.019 (0.49)

Pin 1

Pin 1 Index

0.010 (0.25)

0.020 (0.50)

0.050 (1.27)

0.188 (4.78)

0.197 (5.00)

0.004 (0.19)

0.010 (0.25)

0.053 (1.35)

0.069 (1.75)

(4X) 7°

0.016 (0.410)

0.037 (0.937)

0.0075 (0.19)

0.010 (0.25)

0° - 8°

X 45°

8-Lead Plastic, SOIC, Package Code S8

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

0.250"

0.050"Typical

0.050"

Typical

0.030"

Typical

8 PlacesFOOTPRINT

X1227 – Preliminary Information

Characteristics subject to change without notice. 23 of 25

REV 1.1.5 8/2/01 www.xicor.com

PACKAGING INFORMATION

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

8-Lead Plastic, TSSOP, Package Code V8

See Detail “A”

.031 (.80)

.041 (1.05)

.169 (4.3)

.177 (4.5) .252 (6.4) BSC

.025 (.65) BSC

.114 (2.9)

.122 (3.1)

.002 (.05)

.006 (.15)

.047 (1.20)

.0075 (.19)

.0118 (.30)

0° – 8°

.010 (.25)

.019 (.50)

.029 (.75)

Gage Plane

Seating Plane

Detail A (20X)

(4.16) (7.72)

(1.78)

(0.42)

(0.65)

All Measurements Are Typical

X1227 – Preliminary Information

Characteristics subject to change without notice. 24 of 25

REV 1.1.5 8/2/01 www.xicor.com

Ordering Information

VCC Range VTRIP Package Operating Temperature Range Part Number

2.7 – 5.5V 4.63V ± 3% 8L SOIC 0–70°C X1227S8-4.5A

-40–85°C X1227S8I-4.5A

2.7 – 5.5V 4.63V ± 3% 8L TSSOP 0–70°C X1227V8-4.5A

-40–85°C X1227V8I-4.5A

2.7 – 5.5V 4.38V ± 3% 8L SOIC 0–70°C X1227S8

-40–85°C X1227S8I

2.7 – 5.5V 4.38V ± 3% 8L TSSOP 0–70°C X1227V8

-40–85°C X1227V8I

2.7 – 5.5V 2.85V ± 3% 8L SOIC 0–70°C X1227S8-2.7A

-40–85°C X1227S8I-2.7A

2.7 – 5.5V 2.85V ± 3% 8L TSSOP 0–70°C X1227V8-2.7A

-40–85°C X1227V8I-2.7A

2.7 – 5.5V 2.65V ± 3% 8L SOIC 0–70°C X1227S8-2.7

-40–85°C X1227S8I-2.7

2.7 – 5.5V 2.65V ± 3% 8L TSSOP 0–70°C X1227V8-2.7

-40–85°C X1227V8I-2.7

Note: For appropriate volume, any VTRIP value from 2.6 to 4.7V may be ordered via Xicor’s Customer Speciﬁcation Program (CSPEC).

X1227 – Preliminary Information

Characteristics subject to change without notice. 25 of 25

REV 1.1.5 8/2/01 www.xicor.com

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemniﬁcation provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,

express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.

Xicor, Inc. makes no warranty of merchantability or ﬁtness for any purpose. Xicor, Inc. reserves the right to discontinue production and change speciﬁcations and prices

at any time and without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.

COPYRIGHTS AND TRADEMARKS

Xicor, Inc., the Xicor logo, E2POT, XDCP, XBGA, AUTOSTORE, Direct Write cell, Concurrent Read-Write, PASS, MPS, PushPOT, Block Lock, IdentiPROM,

E2KEY, X24C16, SecureFlash, and SerialFlash are all trademarks or registered trademarks of Xicor, Inc. All other brand and product names mentioned herein are

used for identification purposes only, and are trademarks or registered trademarks of their respective holders.

U.S. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;

4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;

5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection

and correction, redundancy and back-up features to prevent such an occurrence.

Xicor’s products are not authorized for use in critical components in life support devices or systems.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to

perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a signiﬁcant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or effectiveness.

Part Mark Information

8-Lead TSSOP

EYWW

XXXXX

1227AL = 4.5 to 5.5V, 0 to +70°C, VTRIP = 4.63V ± 3%

1227AM = 4.5 to 5.5V, -40 to +85°C, VTRIP = 4.63V ± 3%

1227 = 4.5 to 5.5V, 0 to +70°C, VTRIP = 4.38V ± 3%

1227I = 4.5 to 5.5V, -40 to +85°C, VTRIP = 4.38V ± 3%

1227AN = 2.7 to 5.5V, 0 to +70°C, VTRIP = 2.85V ± 3%

1227AP = 2.7 to 5.5V, -40 to +85°C, VTRIP = 2.85V ± 3%

1227F = 2.7 to 5.5V, 0 to +70°C, VTRIP = 2.65V ± 3%

1227G = 2.7 to 5.5V, -40 to +85°C, VTRIP = 2.65V ± 3%

8-Lead SOIC

X1227 X

Blank = 8-Lead SOIC

AL = 4.5 to 5.5V, 0 to +70°C, VTRIP = 4.63V ± 3%

AM = 4.5 to 5.5V, -40 to +85°C, VTRIP = 4.63V ± 3%

Blank = 4.5 to 5.5V, 0 to +70°C, VTRIP = 4.38V ± 3%

I = 4.5 to 5.5V, -40 to +85°C, VTRIP = 4.38V ± 3%

AN = 2.7 to 5.5V, 0 to +70°C, VTRIP = 2.85V ± 3%

AP = 2.7 to 5.5V, -40 to +85°C, VTRIP = 2.85V ± 3%

F = 2.7 to 5.5V, 0 to +70°C, VTRIP = 2.65V ± 3%

G = 2.7 to 5.5V, -40 to +85°C, VTRIP = 2.65V ± 3%

Draft Copy

Real Time Clock Errata Sheet

INTRODUCTION

Initial production parts of the Real Time Clock (RTC) product family will have some specifications which

are slightly different than shown in the preliminary data sheet. Following is a list of these changes and

some supplementary information.

The following RTC products are affected by some or all of the following changes. If a particular part is

affected, it will be listed under that section.

X1226, X1227, X1228 (RTC with CPU Supervisor, on-chip Oscillator Compensation and EEPROM)

1. ICC3 and IBACK1 Timekeeping Currents (all products)

Description: The data sheet limits for ICC3 and IBACK1 have changed and are shown below. An

additional specification for Backup supply current at 3.3V is included in support of typical lithium battery

systems. The supporting notes for the specifications also change as shown.

Type of Change: Data sheet only

Data sheet Impact: See updated section below

Notes:

(3) The device goes into timekeeping state 200ns after any stop, except those that initiate a nonvolatile

write cycle; tWC after a stop that initiates a nonvolatile write cycle; or 9 clock cycles after any start that is

not followed by the correct Device Select Bits in the Slave Address Byte.

(7) VCC = 0V

(8) VBACK = 0V

(9) VSDA = VSCL = VCC, Others = GND or VCC

(10) VSDA = VSCL = GND, Others = GND or VCC

(16) Using recommended crystal applied to X1 and X2 (25¡C).

Periodically sampled and not 100% tested.

(17) Average supply current. Does not include instantaneous peaks.

Supplemental Information: The Main and Backup timekeeping currents are slightly higher than shown in

the preliminary data sheet. The switch to the Backup Supply is only conditional on the relative value of

Vcc to VBACK. Therefore Vcc MUST be greater than VBACK, or Vcc=0 to meet the IBACK specification. If

Vcc < VBACK but not 0V, the chip will operate from the VBACK supply (in normal, not back up mode) which

can draw IBACK in excess of the stated maximum.

2. Serial Bus I/O Capacitance (all products)

Description: The data sheet limits for Cout and Cin have changed and are shown below.

Type of Change: Data sheet only

Data sheet Impact: See updated section below

Symbol Parameter Conditions Min Typ Max Units Notes

COUT Output Capacitance (SDA, IRQ) VCC = 2.7V 10.0 pF 1

CIN Input Capacitance (SCL) VCC = 2.7V 10.0 pF 1

Symbol Parameter Conditions Min Typ Max Units Notes

ICC3 Main Timekeeping Current VCC = 2.7V 1.5 5.0 uA 3,8,9,16,17

VCC = 5.5V 1.5 10.0 uA

IBACK1 Backup Timekeeping Current VBACK = 1.8V 1.0 1.5 uA 3,7,10,16,

VBACK = 3.3V 1.0 2.0 uA 17

VBACK = 5.5V 1.5 10.0 uA Max at 85oC

Note:

(1) This parameter is periodically sampled and not 100% tested

Supplemental Information: The Values shown here reflect the actual measured values of the device.

This change will not affect serial bus communications since the values are within major serial bus

specifications.

3. Temperature Specifications (all products)

Description: Industrial grade crystals are required for operation over the industrial temperature range.

Type of Change: No change, advisory only.

Data sheet Impact: None

Supplemental Information: Many commercially available crystals including those mentioned in the data

sheet are specified for -10 to +60oC. The customer must be sure to select a crystal which meets their

specific temperature range.

4. Analog Trimming Register (ATR) Values (all products)

Description: The range of ATR values shown in the data sheet table for load capacitance will vary with

package and board layout. There is a new table with different values.

Type of Change: Data sheet change.

Data sheet Impact: The ATR table will change in the Applications section.

Supplemental Information: A table is shown in the data sheet listing the internal load capacitance values

and the expected PPM change with a typical production crystal deleted, instead the customer will be able to

estimate the capacitance based on the chip capacitance, estimated package capacitance, and approximate

board capacitance (usually very small). The formula for calculating the chip capacitance is as follows:

CATR = [(ATR decimal Value) x 0.25pF]+ 11.0pF

Note that the ATR register values are two s complement (6 bits long), beginning with ATR(000000) =

11.0pF, so the entire range runs from 3.0 pF to 18.75pF in 0.25pF steps.

There will be a formula for the calculation of the frequency deviation with ATR setting for a given crystal

with known parameters. This formula will be published pending final verification.

5. PHZ pin (X1226 and X1228)

Description: Operation of the PHZ pin needs clarification from what is shown on the data sheet.

Type of Change: No change, advisory only.

Data sheet Impact: None. Applications advisory.

Supplemental Information: The X1226 PHZ pin is an open drain output. The recommended value for the

resistor pullup is 5k ohms to VCC. If unused need either pull up with a resistor to Vcc or tie to ground. PHZ

will cause excessive IBACK current draw if enabled on VCC power down. VBACK must be < VTRIP to disable

PHZ with VCC off. The X1228 PHZ pin is a CMOS output.

Great care should be taken in the placement of the oscillator and the layout of the circuit so that there is

plenty of ground plane around the device, and that the resistor pullup and copper trace for PHZ does not

cross the X1 and X2 pins. Long Traces from the X1 and X2 pins to the crystal are to be avoided.

6. RESET/ pin (X1227 and X1228)

Description: Operation of the RESET/ pin needs clarification from what is shown on the data sheet.

Type of Change: No change, advisory only.

Data sheet Impact: None. Supplemental information only.

Supplemental Information: The X1227 and X1228 RESET/ pin is an open drain output. The

recommended value for the resistor pullup is 5k ohms to Vcc. If unused tie it to ground.

Great care should be taken in the placement of the oscillator and the layout of the circuit so that there is

plenty of ground plane around the device, and that the resistor pullup and copper trace for PHZ does not

cross the X1 and X2 pins.

7. Switch to Backup Supply (VBACK) (All products)

Description: The conditions for switching to VBACK are different than is what is shown in the

specification table, and additional information on Backup supply switching is needed.

Type of Change: Data sheet only.

Data sheet Impact: Specification table changes, see below.

Note:

(4) For reference only and not tested

Supplemental Information: The switch to the Backup Supply depends on the values of both VCC and

VBACK. The state of Vcc MUST be either > VBACK or Vcc=0 to meet the IBACK specification. If VCC <

VBACK but not 0V, the chip will operate from the VBACK supply (NOT in backup mode) which can cause

IBACK current in excess of the stated maximum.

The specification for switching over to the backup supply includes hysteresis. Switching back to the main

supply can occur without hysteresis.

8. Input High Voltage (All products)

Description: The limits for Input High voltage change in the specification table.

Type of Change: Data sheet change.

Data sheet Impact: Specification Table Changes.

Notes:

(4) For reference only and not tested

(14) Threshold Voltages based on the higher of VCC or VBACK

Supplemental Information: The limits now used are appropriate for designers to consider when supply

voltage changes, as in battery backup mode.

9. VTRIP Programming (X1227, X1228)

Description: The procedure for programming VTRIP is not completely described in the data sheet.

Type of Change: Data sheet change. New information which will become part of the data sheet.

Data sheet Impact: Applications information in the data sheet will change.

Supplemental Information: There is a specific procedure to use when progamming the VTRIP value,

otherwise the resulting VTRIP value will be offset from the desired setting. The recommended procedure is

as follows:

1. Perform a VTRIP level set per the sequence in the data sheet. (Note: if the new VTRIP level is less than

the current level, a VTRIP Reset sequence must be performed as shown in the data sheet).

2. Verify VTRIP setting by measuring where VTRIP occurs (done by decrementing Vcc and monitoring

RST/ pin, if it exists). Note the difference in the measured value versus the desired value (VMEASURED —

VDESIRED = VERROR)

3. Reprogram VTRIP using the following formula to set the voltage on the Reset/ pin:

VRESET/ = (VDESIRED + VERROR) + 0.025V

The resulting voltage will settle very close to the desired VTRIP voltage within 24 hours.

10. IBACK Current on Power Down (X1226)

Description: The battery backup supply current will be affected by the state of the serial bus pins when

VCC is lost.

Type of Change: No change, advisory only. Final production parts will have this issue corrected.

Symbol Parameter Conditions Min Typ Max Units Notes

VIHInput HIGH Voltage

VCC x 0.7 or

VBACK x 0.7

VCC + 0.5 or

VBACK + 0.5 V 4,14

Symbol Parameter Conditions Min Typ Max Units Notes

VCB Switch to Backup Supply VBACK -.1 VBACK +.2 V4

VBC Switch to Main Supply VBACK VBACK +.2 V4

Data sheet Impact: None.

Supplemental Information: When the SDA and SCL pins are in a particular state (after a start

sequence), and Vcc drops below the VTRIP threshold with a battery connected to VBACK, then the device will

exceed the maximum IBACK specification stated on the data sheet. The timing diagram below describes this

condition:

Valid Start sequence

SCL

SDA

VCC

The serial bus is active from Start until Stop. If the serial bus is active when Vcc is removed, an excess

~4.5 A will be observed on VBACK.

VTRIP