S-25C512A0I-T8T1U4 - SEIKO INSTRUMENTS

S-25C512A

www.sii-ic.com SPI SERIAL E2PROM

Seiko Instruments Inc. 1

The S-25C512A is a SPI serial E2PROM which operates at high speed, with low current consumption and the wide range

operation. The S-25C512A has the capacity of 512 K-bit and the organization of 65536 words × 8-bit. Page write and

sequential read are available.

 Features

• Operating voltage range Read: 1.6 V to 5.5 V

Write: 1.7 V to 5.5 V

• Operation frequency: 10.0 MHz (VCC = 2.5 V to 5.5 V)

• Write time: 5.0 ms max.

• SPI mode (0, 0) and (1, 1)

• Page write: 128 bytes / page

• Sequential read

• Write protect: Software, Hardware

Protect area: 25%, 50%, 100%

• Monitors write to the memory by a status register

• Function to prevent malfunction by monitoring clock pulse

• Write protect function during the low power supply voltage

• CMOS schmitt input (CS , SCK, SI, WP , HOLD)

• Endurance: 106cycles / unit*1 (Ta = +25°C)

• Data retention: 100 years (Ta = +25°C)

• Memory capacity: 512 K-bit

• Initial shipment data: FFh, SRWD = 0, BP1 = 0, BP0 = 0

• Lead-free (Sn 100%), halogen-free*2

*1. For each unit (unit: the 4 bytes with the same address of A15 to A2)

*2. Refer to “ Product Name Structure” for details.

 Packages

• 8-Pin SOP (JEDEC)

• 8-Pin TSSOP

Caution This product is intended to use in general electronic devices such as consumer electronics, office

equipment, and communications devices. Before using the product in medical equipment or

automobile equipment in cluding car audio, keyless entry and engine control uni t, contact to SII is

indispensable.

SPI SERIAL E2PROM

S-25C512A Rev.2.1_00_S

Seiko Instruments Inc.

 Pin Configurations

1. 8-Pin SOP (JEDEC)

2. 8-Pin TSSOP

Remark Refer to the “Package drawings” for the details.

8-Pin SOP (JEDEC)

Top view Table 1

Pin No. Symbol Description

1 CS*1 Chip select input

2 SO Serial data output

3 WP *1 Write protect input

4 GND Ground

5 SI*1 Serial data input

6 SCK*1 Serial clock input

7 HOLD*1 Hold input

8 VCC Power supply

*1. Do not use it in high impedance.

Figure 1

S-25C512A0I-J8T1U4

8-Pin TSSOP

Top view Table 2

Pin No. Symbol Description

1 CS*1 Chip select input

2 SO Serial data output

3 WP *1 Write protect input

4 GND Ground

5 SI*1 Serial data input

6 SCK*1 Serial clock input

7 HOLD*1 Hold input

8 VCC Power supply

*1. Do not use it in high impedance.

Figure 2

S-25C512A0I-T8T1U4

SPI SERIAL E2PROM

Rev.2.1_00_S S-25C512A

Seiko Instruments Inc. 3

 Block Diagram

Mode

Decoder

Status RegisterAddress Register

Data Register

HOLD

SCK

VCC

GND

Memory

Cell

Array

Status

Memory Cell Array

Voltage Detector

Read Circuit

Clock Counter

Y Decoder

X Decoder

Input Control Circuit

Output

Control

Circuit

Step-up Circuit

Page Latch

Figure 3

SPI SERIAL E2PROM

S-25C512A Rev.2.1_00_S

Seiko Instruments Inc.

 Absolute Maximum Ratings

Table 3

Item Symbol Absolute Maximum Rating Unit

Power supply voltage VCC −0.3 to + 6.5 V

Input voltage VIN −0.3 to + 6.5 V

Output voltage VOUT −0.3 to VCC + 0.3 V

Operation ambient temperature Topr −40 to +85 °C

Storage temperature Tstg −65 to +150 °C

Caution The absolute maximum ratings are rated values exceeding which the product could suffer

physical damage. These values must therefore not be exceeded under any conditions.

 Recommended Operating Conditions

Table 4 Ta = −40°C to +85°C

Item Symbol Condition

Min. Max.

Unit

Read Operation 1.6 5.5 V

Power supply voltage VCC Write Operation 1.7 5.5 V

VCC = 1.8 V to 5.5 V 0.7 × VCC V

CC + 1.0 V

High level input voltage VIH VCC = 1.6 V to 1.8 V 0.8 × VCC V

CC + 1.0 V

VCC = 1.8 V to 5.5 V −0.3 0.3 × VCC V

Low level input voltage VIL VCC = 1.6 V to 1.8 V −0.3 0.2 × VCC V

 Pin Capacitance

Table 5 (Ta = +25°C, f = 1.0 MHz, VCC = 5.0 V)

Item Symbol Condition Min. Max. Unit

Input capacitance CIN VIN = 0 V (CS , SCK, SI, WP , HOLD) − 8 pF

Output capacitance COUT VOUT = 0 V (SO) − 10 pF

 Endurance

Table 6

Item Symbol Operation Ambient Temperature Min. Max. Unit

Endurance NW Ta = +25°C 106 − cycles / unit*1

*1. For each unit (unit: the 4 bytes with the same address of A15 to A2)

 Data Retention

Table 7

Item Symbol Operation Ambient Temperature Min. Max. Unit

Data retention − Ta = +25°C 100 − year

SPI SERIAL E2PROM

Rev.2.1_00_S S-25C512A

Seiko Instruments Inc. 5

 DC Electrical Characteristics

Table 8 Ta = −40°C to +85°C

VCC = 1.6 V to 1.8 V

fSCK = 2.0 MHz VCC = 1.8 V to 2.5 V

fSCK = 5.0 MHz VCC = 2.5 V to 5.5 V

fSCK = 10.0 MHz

Item Symbol Condition

Min. Max. Min. Max. Min. Max.

Unit

Current consumption (READ) ICC1 No load at

SO pin − 2.5 − 2.5 − 4.0 mA

Table 9 Ta = −40°C to +85°C

VCC = 1.7 V to 1.8 V

fSCK = 2.0 MHz VCC = 1.8 V to 2.5 V

fSCK = 5.0 MHz VCC = 2.5 V to 5.5 V

fSCK = 10.0 MHz

Item Symbol Condition

Min. Max. Min. Max. Min. Max.

Unit

Current consumption (WRITE) ICC2 No load at

SO pin − 4.0 − 4.0 − 4.0 mA

Table 10 Ta = −40°C to +85°C

VCC = 1.6 V to 1.8 V VCC = 1.8 V to 2.5 V VCC = 2.5 V to 5.5 V

Item

Symbol Condition

Min. Max. Min. Max. Min. Max.

Unit

Standby current

consumption ISB

CS = VCC,

SO = Open

Other inputs are

VCC or GND

− 3.0 − 4.0 − 8.0 μA

Input leakage current ILI V

IN = GND to VCC − 1.0 − 1.0 − 1.0 μA

Output leakage current ILO V

OUT = GND to VCC − 1.0 − 1.0 − 1.0 μA

VOL1 I

OL = 2.0 mA − − − 0.4 − 0.4 V Low level

output voltage VOL2 I

OL = 1.5 mA − 0.4 − 0.4 − 0.4 V

VOH1 I

OH = −2.0 mA − − 0.8 × VCC − 0.8 × VCC − V

High level

output voltage VOH2 I

OH = −0.4 mA 0.8 × VCC − 0.8 × VCC − 0.8 × VCC − V

SPI SERIAL E2PROM

S-25C512A Rev.2.1_00_S

Seiko Instruments Inc.

 AC Electrical Characteristics

Table 11 Measurement Conditions

Input pulse voltage 0.2 × VCC to 0.8 × VCC

Output reference voltage 0.5 × VCC

Output load 100 pF

Table 12 Ta = −40°C to +85°C

VCC = 1.6 V to 1.8 V VCC = 1.8 V to 2.5 V VCC = 2.5 V to 5.5 V

Item Symbol

Min. Max. Min. Max. Min. Max.

Unit

SCK clock frequency fSCK − 2.0 − 5.0 − 10.0 MHz

CS setup time during CS falling tCSS.CL 150 − 90 − 30 − ns

CS setup time during CS rising tCSS.CH 150 − 90 − 30 − ns

CS deselect time tCDS 200 − 90 − 40 − ns

CS hold time during CS falling tCSH.CL 200 − 90 − 30 − ns

CS hold time during CS rising tCSH.CH 150 − 90 − 30 − ns

SCK clock time “H” *1 tHIGH 200 − 90 − 40 − ns

SCK clock time “L” *1 tLOW 200 − 90 − 40 − ns

Rising time of SCK clock *2 tRSK − 1 − 1 − 1 μs

Falling time of SCK clock *2 tFSK − 1 − 1 − 1 μs

SI data input setup time tDS 50 − 20 − 10 − ns

SI data input hold time tDH 60 − 30 − 10 − ns

SCK “L” hold time

during HOLD ri sin g tSKH.HH 150 − 70 − 30 − ns

SCK “L” hold time

during HOLD fa lling tSKH.HL 100 − 40 − 30 − ns

SCK “L” setup time

during HOLD fa lling tSKS.HL 0 − 0 − 0 − ns

SCK “L” setup time

during HOLD ri sin g tSKS.HH 0 − 0 − 0 − ns

Disable time of SO output *2 tOZ − 200 − 100 − 40 ns

Delay time of SO output tOD − 150 − 70 − 40 ns

Hold time of SO output tOH 0 − 0 − 0 − ns

Rising time of SO output *2 tRO − 100 − 40 − 40 ns

Falling time of SO output *2 tFO − 100 − 40 − 40 ns

Disable time of SO output

during HOLD fa lling *2 tOZ.HL − 200 − 100 − 40 ns

Delay time of SO output

during HOLD ri sin g *2 tOD.HH − 150 − 50 − 40 ns

WP setup time tWS1 0 − 0 − 0 − ns

WP hold time tWH1 0 − 0 − 0 − ns

WP release / setup time tWS2 0 − 0 − 0 − ns

WP release / hold time tWH2 60 − 30 − 30 − ns

*1. The clock cycle of the SCK clock (frequency fSCK) is 1 / fSCK μs. This clock cycle is determined by a combination of

several AC characteristics. Note that the clock cycle cannot be set as (1 / fSCK) = tLOW (min.) + tHIGH (min.) by minimizing

the SCK clock cycle time.

*2. These are values of sample and not 100% tested.

SPI SERIAL E2PROM

Rev.2.1_00_S S-25C512A

Seiko Instruments Inc. 7

Table 13 Ta = −40°C to +85°C

VCC = 1.7 V to 5.5 V

Item Symbol

Min. Max.

Unit

Write time tPR − 5.0 ms

CSH.CL

SCK

CSS.CL

MSB IN LSB IN

CSH.CH

CSS.CH

CDS

FSK

RSK

High-Z

Figure 4 Serial Input Timing

SCK

HOLD

tSKH.HL

tOZ.HL tOD.HH

tSKH.HH

tSKS.HL

tSKS.HH

Figure 5 Hold Timing

SPI SERIAL E2PROM

S-25C512A Rev.2.1_00_S

Seiko Instruments Inc.

SCK

HIGH

LOW

SCK

ADDR

LSB IN

LSB OUT

Figure 6 Serial Output Timing

WH1

WS1

Figure 7 Valid Timing in Write Protect

WH2

WS2

Figure 8 Invalid Timing in Write Protect

SPI SERIAL E2PROM

Rev.2.1_00_S S-25C512A

Seiko Instruments Inc. 9

 Pin Functions

1. CS (Chip select input) pin

This is an input pin to set a chip in the select status. In the “H” input level, the device is in the non-select status and its

output is high impedance. The device is in standby as long as it is not in Write inside. The device goes in active by

setting the chip select to “L”. Input any instruction code after power-on and a falling of chip select.

2. SI (Serial data input) pin

This pin is to input serial data. This pin receives an instruction code, an address and Wr ite data. This pin latches data

at rising edge of serial clock.

3. SO (Serial data output) pin

This pin is to output serial data. The data output changes according to falling edge of serial clock.

4. SCK (Serial clock input) pin

This is a clock input pin to set the timing of serial data. An instruction code, an address and Write data are received at

a rising edge of clock. Data is output during falling edge of clock.

5. WP (Write protect input) pin

Write protect is purposed to protect the area size against the Write instruction (BP1, BP0 in the status register). Fix

this pin “H” or “L” not to set it in the floating state.

Refer to “ Protect Operation” for details.

6. HOLD (HOLD input) pin

This pin is used to pause serial communications without setting the device in the non-select status.

In the hold status, the serial output goes in high impedance, the serial input and the serial clock go in “Don’t care”.

During the hold operation, be sure to set the device in active by setting the chip select (CS pin) to “L”.

Refer to “ Hold Operation” for details.

 Initial Shipment Data

Initial shipment data of all addresses is “FFh”.

Moreover, initial shipment data of the status register nonvolatile memory is as follows.

• SRWD = 0

• BP1 = 0

• BP0 = 0

 ECC Function (Error correction function)

S-25C512A Series adds 6 ECC bits for error correction to each 4 bytes with the same address of A15 to A2. The ECC

function can make correction and output correct data even if wrong data of 1 bit is in the 4 bytes when reading.

In addition, the S-25C512A Series rewrites the 4 bytes used as the rewriting mini mum unit and 6 ECC bits if only 1 byte

data is input.

Therefore, it is recommended to rewrite data of each 4 bytes with the same address of A15 to A2 in order to get the

maximum endurance in the application in which the data is rewrote frequently.

SPI SERIAL E2PROM

S-25C512A Rev.2.1_00_S

Seiko Instruments Inc.

 Instruction Set

Table 14 is the list of instruction for the S-25C512A. The instruction is able to be input by changing the CS pin “H” to

“L”. Input the instruction in the MSB first. Each instruction code is organized with 1-byte as shown below. If the S-

25C512A receives any invalid instruction code, the device goes in the non-select status.

Table 14 Instruction Set

Instruction code Address Data

Instruction Operation

SCK Input Clock

1 to 8 SCK Input Clock

9 to 16 SCK Input Clock

17 to 24 SCK Input Clock

25 to 32

WREN Write enable 0000 0110 − − −

WRDI Write disable 0000 0100 − − −

RDSR Read the status register 0000 0101 b7 to b0 output *1 − −

WRSR Write in the status register 0000 0001 b7 to b0 input − −

READ Read memory data 0000 0011 A15 to A8 A7 to A0 D7 to D0 output *2

WRITE Write memory data 0000 0010 A15 to A8 A7 to A0 D7 to D0 input

*1. Sequential data reading is possible.

*2. After outputting data in the specified address, data in the following address is output.

SPI SERIAL E2PROM

Rev.2.1_00_S S-25C512A

Seiko Instruments Inc. 11

 Operation

1. Status register

The status register’s organization is below. The status register can Write and Read by a specific instruction.

SRWD 0

b7 b6

BP1

BP0

WEL

WIP

Status Register Write Disable Block Protect Write Enable Latch

Write In Progress

Figure 9 Organization of Status Register

The status / control bits of the status register as follows.

1. 1 SRWD (b7) : Status Register Write Disable

Bit SRWD operates in conjunction with the Write protect signal (WP ). With a combination of bit SRWD and signal

WP (SRWD = “1”, WP = “L”), this device goes in Hardware Protect status. In this case, the bits composed of the

nonvolatile bit in the status register (SRWD, BP1, BP0) go in Read Only, so that the WRSR instruction is not be

performed.

1. 2 BP1, BP0 (b3, b2) : Block Protect

Bit BP1 and BP0 are composed of the nonvolatile memory. The area size of Software Protect against WRITE

instruction is defined by them. Rewriting these bits is possible by the WRSR instruction. To protect the memory area

against the WRITE instruction, set either or both of bit BP1 and BP0 to “1”. Rewriting bit BP1 and BP0 is possible

unless they are in Hardware Protect mode. Refer to “ Protect Operation” for details of “Block Protect”.

1. 3 WEL (b1) : Write Enable Latch

Bit WEL shows the status of internal Write Enable Latch. Bit WEL is set by the WREN instruction only. If bit WEL is

“1”, this is the status that Write Enable Latch is set. If bit WEL is “0”, Write Enable Latch is in reset, so that the

device does not receive the WRITE or WRSR instruction. Bit WEL is reset after these operations;

• The power supply voltage is dropping

• Power-on

• After performing WRDI

• After the Write operation by the WRSR instruction has completed

• After the Write operation by the WRITE instruction has completed

SPI SERIAL E2PROM

S-25C512A Rev.2.1_00_S

Seiko Instruments Inc.

1. 4 WIP (b0) : Write in Progress

Bit WIP is Read Only and shows whether the internal memory is in the Write operation or not by the WRITE or

WRSR instruction. Bit WIP is “1” during the Write operation but “0” during any other status. Figure 10 shows the

usage example.

000 000 000 00

WEL, WIP WEL, WIP WEL, WIP

RDSR instruction RDSR instruction RDSR instruction

RDSR RDSR RDSR

11 11

WRITE or WRSR instruction

D2 D1D0

Figure 10 Usage Examp le of WEL, WIP Bits during Write

SPI SERIAL E2PROM

Rev.2.1_00_S S-25C512A

Seiko Instruments Inc. 13

2. Write enable (WREN)

Before writing data (WRITE and WRSR), be sure to set bit Write Enable Latch (WEL). This instruction is to set bit

WEL. Its operation is below.

After selecting the device by the chip select (CS ), input the instruction code from serial data input (SI). To set bit WEL,

set the device in the non-select status by CS at the 8th clock of the serial clock (SCK). To cancel the WREN

instruction, input the clock different from a specified value (n = 8 clocks) while CS is in “L”.

SCK

Instruction

High-Z

12345678

High / Low

Figure 11 WREN Operation

SPI SERIAL E2PROM

S-25C512A Rev.2.1_00_S

Seiko Instruments Inc.

3. Write disable (WRDI)

The WRDI instruction is one of ways to reset bit Write Enable Latch (WEL). After selecting the device by the chip select

(CS ), input the instruction code from serial data input (SI).

To reset bit WEL, set the device in the non-select status by CS at the 8th clock of the serial clock.

To cancel the WRDI instruction, input the clock different from a specified value (n = 8 clocks) while CS is in “L”. Bit

WEL is reset after the operations shown below.

• The power supply voltage is dropping

• Power-on

• After performing WRDI

• After the completion of Write operation by the WRSR instruction

• After the completion of Write operation by the WRITE instruction

SCK

Instruction

High-Z

12345678

High / Low

Figure 12 WRDI Operation

SPI SERIAL E2PROM

Rev.2.1_00_S S-25C512A

Seiko Instruments Inc. 15

4. Read the status register (RDSR)

Reading data in the status register is possible by the RDSR instruction. During the Write operation, it is possible to

confirm the progress by checking bit WIP.

Set the chip select (CS ) “L” first. After that, input the instruction code from serial data input (SI). The status of bit in the

status register is output from serial data output (SO). Sequential Read is available for the status register. To stop the

Read cycle, set CS to “H”.

It is possible to read the status register always. The bits in it are valid and can be read by RDSR even in the Write

cycle.

However, during the Write cycle in progress, the nonvolatile bits SRWD, BP1, BP0 are fixed in a certain value. These

updated values of bit can be obtained by inputting another new RDSR instruction after the Write cycle has completed.

Contrarily, two of Read Only bits WEL and WIP are being updated while the Write cycle is in progress.

SCK

Instruction

High-Z

12345678

High / Low

9 10111213141516

Outputs Data in the Status Register

b7 b6 b5 b7b0b1b2b3b4

Figure 13 RDSR Operation

SPI SERIAL E2PROM

S-25C512A Rev.2.1_00_S

Seiko Instruments Inc.

5. Write in the status register (WRSR)

The values of status register (SRWD, BP1, BP0) can be rewritten by inputting the WRSR instruction. But b6, b5, b4,

b1, b0 of status register cannot be rewritten. b6 to 4 are always data “0” when reading the status register.

Before inputting the WRSR instruction, set bit WEL by the WREN instruction. The operation of WRSR is shown below.

Set the chip select (CS ) “L” first. After that, input the instruction code and data from serial data input (SI). To start

WRSR Write (tPR), set the chip select (CS ) to “H” after inputting data or before inputting a rising of the next serial

clock. It is possible to confirm the operation status by reading the value of bit WIP during WRSR Write. Bit WIP is “1”

during Write, “0” during any other status. Bit WEL is reset when Write is completed.

With the WRSR instruction, the values of BP1 and BP0; which determine the area size the users can handle as the

Read Only memory; can be changed. Besides bit SRWD can be set or reset by the WRSR instruction depending on

the status of Write protect WP . With a combination of bit SRWD and Write protect WP , the device can be set in

Hardware Protect mode (HPM). In this case, the WRSR instruction is not be performed (Refer to “ Protect

Operation”).

Bit SRWD and BP1, BP0 keep the value which is the one prior to the WRSR instruction during the WRSR instruction.

The newly updated value is changed when the WRSR instruction has completed.

To cancel the WRSR instruction, input the clock different from a specified value (n = 16 clocks) while CS is in “L”.

SCK

Instruction

High-Z

12345678

High / Low

9 10111213141516

Inputs Data in the Status Register

b7 b6 b5 b0b1b2b3b4

Figure 14 WRSR Operation

SPI SERIAL E2PROM

Rev.2.1_00_S S-25C512A

Seiko Instruments Inc. 17

6. Read memory data (READ)

The READ operation is shown below. Input the instruction code and the address from serial data input (SI) after

inputting “L” to the chip select ( CS ). The input address is loaded to the internal address counter, and data in the

address is output from the serial data output (SO).

Next, by inputting the serial clock (SCK) keeping the chip select (CS) in “L”, the address is automatically incremented

so that data in the following address is sequentially output. The address counter rolls over to the first address by

increment in the last address.

To finish the Read cycle, set CS to “H”. It is possible to raise the chip select always during the cycle. During Write, the

READ instruction code is not be accepted or operated.

SCK

Instruction

High-Z

12345678

High / Low

91011 2122232425

16-bit Address

A15 A14 A13 A0A1A2A3

Outputs the First Byte

D4D5D6D7

26 27 28 29 30 31 32

D0D1D2D3 D7

Outputs

the Second

Figure 15 READ Operation

SPI SERIAL E2PROM

S-25C512A Rev.2.1_00_S

Seiko Instruments Inc.

7. Write memory data (WRITE)

Figure 16 shows the timing chart when inputting 1-byte data. Input the instruction code, the address and data from

serial data input (SI) after inputting “L” to the chip select (CS ). To start WRITE (tPR), set the chip select (CS ) to “H”

after inputting data or before inputting a rising of the next serial clock. Bit WIP and WEL are reset to “0” when Write has

completed.

The S-25C512A can Page Write of 128 bytes. Its function to transmit data is as same as Byte Write basically, but it

operates Page Write by receiving sequential 8-bit Write data as much data as page size has. Input the instruction

code, the address and data from serial data input (SI) after inputting “L” in CS , as the WRITE operation (page) shown

in Figure 17. Input the next data while keeping CS in “L”. After that, repeat inputting data of 8-bit sequentially. At the

end, by setting CS to “H”, the WRITE operation starts (tPR).

7 of the lower bits in the address are automatically incremented every time when receiving Write data of 8-bit. Thus,

even if Write data exceeds 128 bytes, the higher bits in the address do not change. And 7 of lower bits in the address

roll over so that Write data which is previously input is overwritten.

These are cases when the WRITE instruction is not accepted or operated.

• Bit WEL is not set to “1” (not set to “1” beforehand immediately before the WRITE instruction)

• During Write

• The address to be written is in the protect area by BP1 and BP0.

To cancel the WRITE instruction, input the clock different from a specified value (n = 24 + m × 8 clocks) while CS is in

“L”.

SCK

Instruction

High-Z

12345678

High / Low

91011 2122232425

16-bit Address

A15 A14 A13 A0A1A2A3

Data Byte 1

D4D5D6D7

26 27 28 29 30 31 32

D0D1D2D3

Figure 16 WRITE Operation (1 Byte)

SPI SERIAL E2PROM

Rev.2.1_00_S S-25C512A

Seiko Instruments Inc. 19

SCK

Instruction

High-Z

12345678

High / Low

9 1011 22232425

16-bit Address (n)

A15 A14 A13

A0A1A2

Data Byte (n) Data Byte (n + x)

D4D5D6D7

26 27 28 29 30 31 32

D0D1D2D3 D0D1D2D3

Figure 17 WRITE Operation (Pag e)

SPI SERIAL E2PROM

S-25C512A Rev.2.1_00_S

Seiko Instruments Inc.

 Protect Operation

Table 15 shows the block settings of Write protect. Table 16 shows the protect operation for the device. As long as bit

SRWD, the Status Register Write Disable bit, in the status register is reset to “0” (it is in reset before the shipment), the

value of status register can be changed.

These are two statues when bit SRW D is set to “1”.

• Write in the status register is possible; Write protect ( WP ) is in “H”.

• Write in the status register is impossible; Write protect ( WP ) is in “L”. T herefore the Write protect area which is set

by protect bit (BP1, BP0) in the status register cannot be changed.

These operations are to set Hardware Protect (HPM).

• After setting bit SRWD, set Write protect (WP ) to “L”.

• Set bit SRWD completed setting Write protect ( WP ) to “L”.

Figure 7 and 8 show the Valid timing in Write protect and Invalid timing in Write protect during the cycle Write to the

status register.

By inputting “H” to Write protect ( WP ), Hardware Protect (HPM) is released. If the Write protect ( WP ) is “H”,

Hardware Protect (HPM) does not function, Software Protect (SPM) which is set by the protect bits in the status

Table 15 Block Settings of W rite Pro tect

Status Register

BP1 BP0

Area of Write Protect Address of Write Protect Block

0 0 0 % None

0 1 25 % C000h to FFFFh

1 0 50 % 8000h to FFFFh

1 1 100 % 0000h to FFFFh

Table 16 Protect Operation

Mode WP Pin Bit SRWD Bit WEL Write Protect Block General Block Status Register

1 X 0 Write disable Write disable Write disable

1 X 1 Write disable Write enable Write enable

X 0 0 Write disable Write disable Write disable

Software Protect

(SPM) X 0 1 Write disable Write enable Write enable

0 1 0 Write disable Write disable Write disable Hardware Protect

(HPM) 0 1 1 Write disable Write enable Write disable

Remark X = Don’t care

SPI SERIAL E2PROM

Rev.2.1_00_S S-25C512A

Seiko Instruments Inc. 21

 Hold Operation

The hold operation is used to pause serial communications without setting the device in the non-select status. In the

hold status, the serial data output goes in high impedance, and both of the serial data input and the serial clock go in

“Don’t care”. Be sure to set the chip select (CS ) to “L” to set the device in the select status during the hold status.

Generally, during the hold status, the device holds the select status. But if setting the device in the non-select status,

the users can finish the operation even in progress.

Figure 18 shows the hold operation. Set Hold (HOLD) to “L” when the serial clock (SCK) is in “L”, Hold (HOLD ) is

switched at the same time the hold status starts. If setting Hold (HOLD) to “H”, Hold (HOLD) is switched at the same

time the hold status ends.

Set Hold (HOLD) to “L” when the serial clock (SCK) is in “H”; the hold status starts when the serial clock goes in “L”

after Hold (HOLD ) is switched. If setting Hold (HOLD) to “H”, the hold status ends when the serial clock goes in “L”

after Hold (HOLD) is switched.

SCK

HOLD

Hold status Hold status

Figure 18 Hold Operation

SPI SERIAL E2PROM

S-25C512A Rev.2.1_00_S

Seiko Instruments Inc.

 Write Protect Function during the Low Power Supply Voltage

The S-25C512A has a built-in detection circuit which operates with the low power supply voltage. The S-25C512A

cancels the Write operation (WRITE, WRSR) when the power supply voltage drops and power-on, at the same time,

goes in the Write protect status (WRDI) automatically to reset bit WEL. Its detection and release voltages are 1.50 V

typ. (Refer to Figure 19).

To operate Write, after the power supply voltage dropped once but rose to the voltage level which allows Write again,

be sure to set the Write Enable Latch bit (WEL) before operating Write (WRITE, WRSR).

In the Write operation, data in the address written during the low power supply voltage is not assured.

Cancel the Write instruction

Set in Write protect (WRDI) automatically

Release voltage (+V

DET

)

1.50 V typ.

Detection voltage (−V

DET

)

1.50 V typ.

Power supply voltage

Figure 19 Operation during Low Pow er Supply Voltage

 Input Pin and Output Pin

1. Connection of input pin

All input pins in the S-25C512A have the CMOS structure. Do not set these pins in high impedance during operation

when you design. Especially, set the CS input in the non-select status “H” during power-on/off and standby. The error

Write does not occur as long as the CS pin is in the non-select status “H”. Set the CS pin to VCC via a resistor (the

pull-up resistor of 10 kΩ to 100 kΩ).

If the CS pin and the SCK pin change from “L” to “H” simultaneously, data may be input from the SI pin.

To prevent the error for sure, it is recommended to pull down the SCK pin to GND. In addition, it is recommended to

pull up the SI pin, the WP pin and the HOLD pin to VCC, or pull down these pins to GND, respectively. Connecting the

WP pin and the HOLD pin to VCC directly is also possible when these pins are not in use.

2. Equivalent circuit of input pin and output pin

Figure 20 and 21 show the equivalent circuits of input pins in the S-25C512A. A pull-up and pull-down elements are

not included in each input pin, pay attention not to set it in the floating state when you design.

Figure 22 shows the equivalent circuit of the output pin. This pin has the tri-state output of “H” level / “L” level / high

impedance.

SPI SERIAL E2PROM

Rev.2.1_00_S S-25C512A

Seiko Instruments Inc. 23

2. 1 Input pin

CS, SCK

Figure 20 CS , SCK Pin

SI, WP, HOLD

Figure 21 SI, WP , HOLD Pin

2. 2 Output pin

Figure 22 SO Pin

3. Precautions for use

• Absolute maximum ratings: Do not operate these ICs in excess of the absolute maximum ratings (as listed on the

data sheet). Exceeding the supply voltage rating can cause latch-up.

• Operations with moisture on the S-25C512A pins may occur malfunction by short-circuit between pins. Especially, in

occasions like picking the S-25C512A up from low temperature tank during the evaluation. Be sure that not remain

frost on the S-25C512A’s pins to prevent malfunction by short-circuit.

Also attention should be paid in using on environment, which is easy to dew for the same reason.

SPI SERIAL E2PROM

S-25C512A Rev.2.1_00_S

Seiko Instruments Inc.

 Precautions

• Set a by-pass capacitor of about 0.1 μF between the VCC and GND pin for stabilization.

• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic

protection circuit.

• SII claims no responsibility for any and all disputes arising out of or in connection with any infringement of the

products including this IC upon patents owned by a third party.

 Product Name Structure

1. Product name

S-25C512A 0I − xxxx U 4

Product name

S-25C512A : 512 K-bit

Fixed

Package name (abbreviation) and IC packing specification

J8T1: 8-Pin SOP (JEDEC), Tape

T8T1: 8-Pin TSSOP, Tape

Environmental code

U: Lead-free (Sn 100%), halogen-free

2. Packages

Drawing Code

Package Name Package Tape Reel

8-Pin SOP (JEDEC) FJ008-Z-P-SD FJ008-Z-C-SD FJ008-Z-R-SD

8-Pin TSSOP FT008-Z-P-SD FT008-Z-C-SD FT008-Z-R-SD

No. FJ008-Z-P-SD-2.0

No.

TITLE

SCALE

UNIT mm

SOP8J-Z-PKG Dimensions

Seiko Instruments Inc.

FJ008-Z-P-SD-2.0

0.4

1.27

0.20±0.05

5.02

+0.20

-0.35

+0.11

-0.07

No.

TITLE

SCALE

UNIT mm

ø1.5 min.

ø1.55±0.05 0.3±0.05

2.1±0.1

8.0±0.1

6.5

2.0±0.05

Seiko Instruments Inc.

Feed direction

4.0±0.1(10 pitches:40.0±0.2)

SOP8J-Z-Carrier Tape

No. FJ008-Z-C-SD-1.0

FJ008-Z-C-SD-1.0

+0.30

-0.25

No.

TITLE

UNIT mm

SCALE QTY. 4,000

13.4±1.0

2±0.5

ø13±0.2

ø21±0.8

Seiko Instruments Inc.

Enlarged drawing in the central part

SOP8J-Z-Reel

No. FJ008-Z-R-SD-1.0

FJ008-Z-R-SD-1.0

17.5±1.5

No.

TITLE

SCALE

UNIT mm

Seiko Instruments Inc.

TSSOP8-Z-PKG Dimensions

No. FT008-Z-P-SD-1.0

FT008-Z-P-SD-1.0

0.15±0.07

3.00

0.65

0.2±0.1

+0.3

-0.2

No.

TITLE

SCALE

UNIT mm

Seiko Instruments Inc.

ø1.55±0.05

2.0±0.05

8.0±0.1 ø1.55 +0.2

-0.05

0.3±0.05

4.0±0.1

Feed direction

TSSOP8-Z-Carrier Tape

No. FT008-Z-C-SD-1.0

FT008-Z-C-SD-1.0

+0.4

-0.2

6.6

No.

TITLE

SCALE

UNIT mm

Seiko Instruments Inc.

Enlarged drawing in the central part

No. FT008-Z-R-SD-1.0

2±0.5

ø13±0.2

ø21±0.8

13.4±1.0

17.5±1.0

4,000

QTY.

TSSOP8-Z-Reel

FT008-Z-R-SD-1.0

www.sii-ic.com

• The information described herein is subject to change without notice.

• Seiko Instruments Inc. is not responsible for any problems caused by circuits or diagrams described herein

whose related industrial properties, patents, or other rights belong to third parties. The application circuit

examples explain typical applications of the products, and do not guarantee the success of any specific

mass-production design.

• When the products described herein are regulated products subject to the Wassenaar Arrangement or other

agreements, they may not be exported without authorization from the approp riate governmental authority.

• Use of the information described herein for other purposes and/or reproduction or copying without the

express permissi on of Seiko Instruments Inc. is strictly prohibited.

• The products described herein cannot be used as part of any device or equipment affecting the human

body, such as exercise equipment, medical equipment, security systems, gas equipment, or any apparatus

installed in airplanes and other vehicle s, without prior written permission of Seiko Instruments Inc.

• The products described herein are not designed to be radiation-proof.

• Although Seiko Instruments Inc. exerts the greatest possible effort to ensure high quality and reliability, the

failure or malfunction of semiconductor products may occur. The user of these products should therefore

give thorough consideration to safety design, including redundancy, fire-prevention measures, and

malfunction prevention, to prevent any accidents, fires, or comm unity damage that may ensue.