MKE06Z128VLD4 - NXP SEMICONDUCTORS

MKE06P80M48SF0

KE06 Sub-Family Data Sheet

Supports the following:

MKE06Z64VLD4(R),

MKE06Z128VLD4(R),

MKE06Z64VQH4(R),

MKE06Z128VQH4(R),

MKE06Z64VLH4(R),

MKE06Z128VLH4(R),

MKE06Z64VLK4(R), and

MKE06Z128VLK4(R)

Key features

• Operating characteristics

– Voltage range: 2.7 to 5.5 V

– Flash write voltage range: 2.7 to 5.5 V

– Temperature range (ambient): -40 to 105°C

• Performance

– Up to 48 MHz ARM® Cortex-M0+ core

– Single cycle 32-bit x 32-bit multiplier

– Single cycle I/O access port

• Memories and memory interfaces

– Up to 128 KB flash

– Up to 16 KB RAM

• Clocks

– Oscillator (OSC) - supports 32.768 kHz crystal or 4

MHz to 24 MHz crystal or ceramic resonator; choice

of low power or high gain oscillators

– Internal clock source (ICS) - internal FLL with

internal or external reference, 37.5 kHz pre-trimmed

internal reference for 48 MHz system clock

– Internal 1 kHz low-power oscillator (LPO)

• System peripherals

– Power management module (PMC) with three power

modes: Run, Wait, Stop

– Low-voltage detection (LVD) with reset or interrupt,

selectable trip points

– Watchdog with independent clock source (WDOG)

– Programmable cyclic redundancy check module

(CRC)

– Serial wire debug interface (SWD)

– Aliased SRAM bitband region (BIT-BAND)

– Bit manipulation engine (BME)

• Security and integrity modules

– 80-bit unique identification (ID) number per chip

• Human-machine interface

– Up to 71 general-purpose input/output (GPIO)

– Two 32-bit keyboard interrupt modules (KBI)

– External interrupt (IRQ)

• Analog modules

– One up to 16-channel 12-bit SAR ADC, operation in

Stop mode, optional hardware trigger (ADC)

– Two analog comparators containing a 6-bit DAC

and programmable reference input (ACMP)

• Timers

– One 6-channel FlexTimer/PWM (FTM)

– Two 2-channel FlexTimer/PWM (FTM)

– One 2-channel periodic interrupt timer (PIT)

– One pulse width timer (PWT)

– One real-time clock (RTC)

• Communication interfaces

– Two SPI modules (SPI)

– Up to three UART modules (UART)

– Two I2C modules (I2C)

– One MSCAN module (MSCAN)

• Package options

– 80-pin LQFP

– 64-pin QFP/LQFP

– 44-pin LQFP

NXP Semiconductors Document Number MKE06P80M48SF0

Data Sheet: Technical Data Rev. 4, 07/2016

NXP reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products.

KE06 Sub-Family Data Sheet, Rev. 4, 07/2016

2 NXP Semiconductors

Table of Contents

1 Ordering parts.......................................................................................4

1.1 Determining valid orderable parts............................................... 4

2 Part identification................................................................................. 4

2.1 Description...................................................................................4

2.2 Format..........................................................................................4

2.3 Fields............................................................................................4

2.4 Example....................................................................................... 5

3 Parameter classification........................................................................5

4 Ratings..................................................................................................6

4.1 Thermal handling ratings.............................................................6

4.2 Moisture handling ratings............................................................ 6

4.3 ESD handling ratings...................................................................6

4.4 Voltage and current operating ratings..........................................7

5 General................................................................................................. 7

5.1 Nonswitching electrical specifications........................................ 7

5.1.1 DC characteristics.......................................................... 7

5.1.2 Supply current characteristics........................................ 14

5.1.3 EMC performance..........................................................15

5.2 Switching specifications.............................................................. 16

5.2.1 Control timing................................................................16

5.2.2 FTM module timing.......................................................17

5.3 Thermal specifications.................................................................18

5.3.1 Thermal operating requirements.................................... 18

5.3.2 Thermal characteristics.................................................. 19

6 Peripheral operating requirements and behaviors................................ 20

6.1 Core modules............................................................................... 20

6.1.1 SWD electricals .............................................................20

6.2 External oscillator (OSC) and ICS characteristics.......................21

6.3 NVM specifications..................................................................... 23

6.4 Analog..........................................................................................24

6.4.1 ADC characteristics....................................................... 24

6.4.2 Analog comparator (ACMP) electricals.........................27

6.5 Communication interfaces........................................................... 27

6.5.1 SPI switching specifications.......................................... 27

6.5.2 MSCAN......................................................................... 30

7 Dimensions...........................................................................................31

7.1 Obtaining package dimensions.................................................... 31

8 Pinout................................................................................................... 31

8.1 Signal multiplexing and pin assignments.................................... 31

8.2 Device pin assignment.................................................................34

9 Revision history....................................................................................37

KE06 Sub-Family Data Sheet, Rev. 4, 07/2016

NXP Semiconductors 3

Ordering parts

1.1 Determining valid orderable parts

Valid orderable part numbers are provided on the web. To determine the orderable part

numbers for this device, go to nxp.com and perform a part number search for the

following device numbers: KE06Z.

Part identification

2.1 Description

Part numbers for the chip have fields that identify the specific part. You can use the

values of these fields to determine the specific part you have received.

2.2 Format

Part numbers for this device have the following format:

Q KE## A FFF R T PP CC N

2.3 Fields

This table lists the possible values for each field in the part number (not all combinations

are valid):

Field Description Values

Q Qualification status • M = Fully qualified, general market flow

• P = Prequalification

KE## Kinetis family • KE06

A Key attribute • Z = M0+ core

FFF Program flash memory size • 128 = 128 KB

R Silicon revision • (Blank) = Main

• A = Revision after main

T Temperature range (°C) • V = –40 to 105

PP Package identifier • LD = 44 LQFP (10 mm x 10 mm)

Table continues on the next page...

Ordering parts

KE06 Sub-Family Data Sheet, Rev. 4, 07/2016

4 NXP Semiconductors

Field Description Values

• QH = 64 QFP (14 mm x 14 mm)

• LH = 64 LQFP (10 mm x 10 mm)

• LK = 80 LQFP (14 mm x 14 mm)

CC Maximum CPU frequency (MHz) • 4 = 48 MHz

N Packaging type • R = Tape and reel

• (Blank) = Trays

2.4 Example

This is an example part number:

MKE06Z128VLK4

3Parameter classification

The electrical parameters shown in this supplement are guaranteed by various methods.

To give the customer a better understanding, the following classification is used and the

parameters are tagged accordingly in the tables where appropriate:

Table 1. Parameter classifications

P Those parameters are guaranteed during production testing on each individual device.

C Those parameters are achieved by the design characterization by measuring a statistically relevant sample size

across process variations.

T Those parameters are achieved by design characterization on a small sample size from typical devices under

typical conditions unless otherwise noted. All values shown in the typical column are within this category.

D Those parameters are derived mainly from simulations.

NOTE

The classification is shown in the column labeled “C” in the

parameter tables where appropriate.

Parameter classification

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NXP Semiconductors 5

Ratings

4.1 Thermal handling ratings

Symbol Description Min. Max. Unit Notes

TSTG Storage temperature –55 150 °C 1

TSDR Solder temperature, lead-free — 260 °C 2

1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.

2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

4.2 Moisture handling ratings

Symbol Description Min. Max. Unit Notes

MSL Moisture sensitivity level — 3 — 1

1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

4.3 ESD handling ratings

Symbol Description Min. Max. Unit Notes

VHBM Electrostatic discharge voltage, human body model –6000 +6000 V 1

VCDM Electrostatic discharge voltage, charged-device model –500 +500 V 2

ILAT Latch-up current at ambient temperature of 125°C –100 +100 mA 3

1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body

Model (HBM).

2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.

3. Determined according to JEDEC Standard JESD78D, IC Latch-up Test.

• Test was performed at 125 °C case temperature (Class II).

• I/O pins pass ±100 mA I-test with IDD current limit at 400 mA.

• I/O pins pass +50/-100 mA I-test with IDD current limit at 1000 mA.

• Supply groups pass 1.5 Vccmax.

• RESET pin was only tested with negative I-test due to product conditioning requirement.

Ratings

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6 NXP Semiconductors

4.4 Voltage and current operating ratings

Absolute maximum ratings are stress ratings only, and functional operation at the

maxima is not guaranteed. Stress beyond the limits specified in the following table may

affect device reliability or cause permanent damage to the device. For functional

operating conditions, refer to the remaining tables in this document.

This device contains circuitry protecting against damage due to high static voltage or

electrical fields; however, it is advised that normal precautions be taken to avoid

application of any voltages higher than maximum-rated voltages to this high-impedance

circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate

logic voltage level (for instance, either VSS or VDD) or the programmable pullup resistor

associated with the pin is enabled.

Table 2. Voltage and current operating ratings

Symbol Description Min. Max. Unit

VDD Digital supply voltage –0.3 6.0 V

IDD Maximum current into VDD — 120 mA

VIN Input voltage except true open drain pins –0.3 VDD + 0.31V

Input voltage of true open drain pins –0.3 6 V

IDInstantaneous maximum current single pin limit (applies to all

port pins)

–25 25 mA

VDDA Analog supply voltage VDD – 0.3 VDD + 0.3 V

1. Maximum rating of VDD also applies to VIN.

General

Nonswitching electrical specifications

5.1.1 DC characteristics

This section includes information about power supply requirements and I/O pin

characteristics.

Table 3. DC characteristics

Symbol C Descriptions Min Typical1Max Unit

— — Operating voltage — 2.7 — 5.5 V

Table continues on the next page...

5.1

General

KE06 Sub-Family Data Sheet, Rev. 4, 07/2016

NXP Semiconductors 7

Table 3. DC characteristics (continued)

Symbol C Descriptions Min Typical1Max Unit

VOH P Output

high

voltage

All I/O pins, except PTA2

and PTA3, standard-

drive strength

5 V, Iload = –5 mA VDD – 0.8 — — V

C 3 V, Iload = –2.5 mA VDD – 0.8 — — V

P High current drive pins,

high-drive strength25 V, Iload = –20 mA VDD – 0.8 — — V

C 3 V, Iload = –10 mA VDD – 0.8 — — V

IOHT D Output

high

current

Max total IOH for all ports 5 V — — –100 mA

3 V — — –60

VOL P Output

low

voltage

All I/O pins, standard-

drive strength

5 V, Iload = 5 mA — — 0.8 V

C 3 V, Iload = 2.5 mA — — 0.8 V

P High current drive pins,

high-drive strength25 V, Iload =20 mA — — 0.8 V

C 3 V, Iload = 10 mA — — 0.8 V

IOLT D Output

low

current

Max total IOL for all ports 5 V — — 100 mA

3 V — — 60

VIH P Input

high

voltage

All digital inputs 4.5≤VDD<5.5 V 0.65 × VDD — — V

2.7≤VDD<4.5 V 0.70 × VDD — —

VIL P Input low

voltage

All digital inputs 4.5≤VDD<5.5 V — — 0.35 ×

VDD

2.7≤VDD<4.5 V — — 0.30 ×

VDD

Vhys C Input

hysteresi

All digital inputs — 0.06 × VDD — — mV

|IIn| P Input

leakage

current

Per pin (pins in high

impedance input mode)

VIN = VDD or VSS — 0.1 1 µA

|IINTOT| C Total

leakage

combine

d for all

port pins

Pins in high impedance

input mode

VIN = VDD or VSS — — 2 µA

RPU P Pullup

resistors

All digital inputs, when

enabled (all I/O pins

other than PTA2 and

PTA3)

— 30.0 — 50.0 kΩ

RPU3P Pullup

resistors

PTA2 and PTA3 pins — 30.0 — 60.0 kΩ

IIC D DC

injection

current4,

5, 6

Single pin limit VIN < VSS, VIN >

VDD

-2 — 2 mA

Total MCU limit, includes

sum of all stressed pins

-5 — 25

CIn C Input capacitance, all pins — — — 7 pF

VRAM C RAM retention voltage — 2.0 — — V

1. Typical values are measured at 25 °C. Characterized, not tested.

Nonswitching electrical specifications

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8 NXP Semiconductors

2. Only PTB4, PTB5, PTD0, PTD1, PTE0, PTE1, PTH0 (64-pin and 80-pin packages only), and PTH1 (64-pin and 80-pin

packages only) support high current output.

3. The specified resistor value is the actual value internal to the device. The pullup value may appear higher when measured

externally on the pin.

4. All functional non-supply pins, except for PTA2 and PTA3, are internally clamped to VSS and VDD. PTA2 and PTA3 are true

open drain I/O pins that are internally clamped to VSS.

5. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,

calculate resistance values for positive and negative clamp voltages, then use the larger value.

6. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current

conditions. If the positive injection current (VIn > VDD) is higher than IDD, the injection current may flow out of VDD and could

result in external power supply going out of regulation. Ensure that external VDD load will shunt current higher than

maximum injection current when the MCU is not consuming power, such as when no system clock is present, or clock rate

is very low (which would reduce overall power consumption).

Table 4. LVD and POR specification

Symbol C Description Min Typ Max Unit

VPOR D POR re-arm voltage11.5 1.75 2.0 V

VLVDH C Falling low-voltage detect

threshold—high range (LVDV

= 1)2

4.2 4.3 4.4 V

VLVW1H C Falling low-

voltage

warning

threshold—

high range

Level 1 falling

(LVWV = 00)

4.3 4.4 4.5 V

VLVW2H C Level 2 falling

(LVWV = 01)

4.5 4.5 4.6 V

VLVW3H C Level 3 falling

(LVWV = 10)

4.6 4.6 4.7 V

VLVW4H C Level 4 falling

(LVWV = 11)

4.7 4.7 4.8 V

VHYSH C High range low-voltage

detect/warning hysteresis

— 100 — mV

VLVDL C Falling low-voltage detect

threshold—low range (LVDV

= 0)

2.56 2.61 2.66 V

VLVW1L C Falling low-

voltage

warning

threshold—

low range

Level 1 falling

(LVWV = 00)

2.62 2.7 2.78 V

VLVW2L C Level 2 falling

(LVWV = 01)

2.72 2.8 2.88 V

VLVW3L C Level 3 falling

(LVWV = 10)

2.82 2.9 2.98 V

VLVW4L C Level 4 falling

(LVWV = 11)

2.92 3.0 3.08 V

VHYSDL C Low range low-voltage detect

hysteresis

— 40 — mV

VHYSWL C Low range low-voltage

warning hysteresis

— 80 — mV

VBG P Buffered bandgap output 31.14 1.16 1.18 V

1. Maximum is highest voltage that POR is guaranteed.

2. Rising thresholds are falling threshold + hysteresis.

3. voltage Factory trimmed at VDD = 5.0 V, Temp = 25 °C

Nonswitching electrical specifications

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NXP Semiconductors 9

IOH(mA)

VDD-VOH(V)

Figure 1. Typical VDD-VOH Vs. IOH (standard drive strength) (VDD = 5 V)

IOH(mA)

VDD-VOH(V)

Figure 2. Typical VDD-VOH Vs. IOH (standard drive strength) (VDD = 3 V)

Nonswitching electrical specifications

KE06 Sub-Family Data Sheet, Rev. 4, 07/2016

10 NXP Semiconductors

IOH(mA)

VDD-VOH(V)

Figure 3. Typical VDD-VOH Vs. IOH (high drive strength) (VDD = 5 V)

IOH(mA)

VDD-VOH(V)

Figure 4. Typical VDD-VOH Vs. IOH (high drive strength) (VDD = 3 V)

Nonswitching electrical specifications

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NXP Semiconductors 11

IOL(mA)

VOL(V)

Figure 5. Typical VOL Vs. IOL (standard drive strength) (VDD = 5 V)

IOL(mA)

VOL(V)

Figure 6. Typical VOL Vs. IOL (standard drive strength) (VDD = 3 V)

Nonswitching electrical specifications

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12 NXP Semiconductors

IOL(mA)

VOL(V)

Figure 7. Typical VOL Vs. IOL (high drive strength) (VDD = 5 V)

IOL(mA)

VOL(V)

Figure 8. Typical VOL Vs. IOL (high drive strength) (VDD = 3 V)

Nonswitching electrical specifications

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NXP Semiconductors 13

5.1.2 Supply current characteristics

This section includes information about power supply current in various operating modes.

Table 5. Supply current characteristics

C Parameter Symbol Core/Bus

Freq

VDD (V) Typical1Max2Unit Temp

C Run supply current FEI

mode, all modules clocks

enabled; run from flash

RIDD 48/24 MHz 5 11.1 — mA -40 to 105 °C

C 24/24 MHz 8 —

C 12/12 MHz 5 —

C 1/1 MHz 2.4 —

C 48/24 MHz 3 11 —

C 24/24 MHz 7.9 —

C 12/12 MHz 4.9 —

1/1 MHz 2.3 —

C Run supply current FEI

mode, all modules clocks

disabled and gated; run

from flash

RIDD 48/24 MHz 5 7.8 — mA -40 to 105 °C

C 24/24 MHz 5.5 —

C 12/12 MHz 3.8 —

C 1/1 MHz 2.3 —

C 48/24 MHz 3 7.7 —

C 24/24 MHz 5.4 —

C 12/12 MHz 3.7 —

C 1/1 MHz 2.2 —

C Run supply current FBE

mode, all modules clocks

enabled; run from RAM

RIDD 48/24 MHz 5 14.7 — mA -40 to 105 °C

P 24/24 MHz 9.8 14.9

C 12/12 MHz 6 —

C 1/1 MHz 2.4 —

C 48/24 MHz 3 14.6 —

P 24/24 MHz 9.6 12.8

C 12/12 MHz 5.9 —

C 1/1 MHz 2.3 —

C Run supply current FBE

mode, all modules clocks

disabled and gated; run

from RAM

RIDD 48/24 MHz 5 11.4 — mA -40 to 105 °C

P 24/24 MHz 7.7 12.5

C 12/12 MHz 4.7 —

C 1/1 MHz 2.3 —

C 48/24 MHz 3 11.3 —

P 24/24 MHz 7.6 9.5

C 12/12 MHz 4.6 —

1/1 MHz 2.2 —

Table continues on the next page...

Nonswitching electrical specifications

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14 NXP Semiconductors

Table 5. Supply current characteristics (continued)

C Parameter Symbol Core/Bus

Freq

VDD (V) Typical1Max2Unit Temp

C Wait mode current FEI

mode, all modules clocks

enabled

WIDD 48/24 MHz 5 8.4 — mA -40 to 105 °C

P 24/24 MHz 6.5 7.2

C 12/12 MHz 4.3 —

C 1/1 MHz 2.4 —

C 48/24 MHz 3 8.3 —

P 24/24 MHz 6.4 7

C 12/12 MHz 4.2 —

C 1/1 MHz 2.3 —

P Stop mode supply current

no clocks active (except 1

kHz LPO clock)3

SIDD — 5 2 105 µA -40 to 105 °C

P — 3 1.9 95 -40 to 105 °C

C ADC adder to Stop

ADLPC = 1

ADLSMP = 1

ADCO = 1

MODE = 10B

ADICLK = 11B

— — 5 86 — µA -40 to 105 °C

C 3 82 —

C ACMP adder to Stop — — 5 12 — µA -40 to 105 °C

C 3 12 —

C LVD adder to Stop4— — 5 130 — µA -40 to 105 °C

C 3 125 —

1. Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.

2. The Max current is observed at high temperature of 105 °C.

3. RTC adder cause <1 µA IDD increase typically, RTC clock source is 1 kHz LPO clock.

4. LVD is periodically woken up from Stop by 5% duty cycle. The period is equal to or less than 2 ms.

5.1.3 EMC performance

Electromagnetic compatibility (EMC) performance is highly dependent on the

environment in which the MCU resides. Board design and layout, circuit topology

choices, location and characteristics of external components as well as MCU software

operation play a significant role in EMC performance. The system designer must consult

the following applications notes, available on nxp.com for advice and guidance

specifically targeted at optimizing EMC performance.

• AN2321: Designing for Board Level Electromagnetic Compatibility

• AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS

Microcontrollers

• AN1263: Designing for Electromagnetic Compatibility with Single-Chip

Microcontrollers

Nonswitching electrical specifications

KE06 Sub-Family Data Sheet, Rev. 4, 07/2016

NXP Semiconductors 15

• AN2764: Improving the Transient Immunity Performance of Microcontroller-Based

Applications

• AN1259: System Design and Layout Techniques for Noise Reduction in MCU-

Based Systems

5.1.3.1 EMC radiated emissions operating behaviors

Table 6. EMC radiated emissions operating behaviors for 80-pin LQFP package

Symbol Description Frequency

band (MHz)

Typ. Unit Notes

VRE1 Radiated emissions voltage, band 1 0.15–50 6 dBμV 1, 2

VRE2 Radiated emissions voltage, band 2 50–150 6 dBμV

VRE3 Radiated emissions voltage, band 3 150–500 11 dBμV

VRE4 Radiated emissions voltage, band 4 500–1000 5 dBμV

VRE_IEC IEC level 0.15–1000 N3—2, 4

1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150

kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of

Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband

TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported

emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the

measured orientations in each frequency range.

2. VDD = 5.0 V, TA = 25 °C, fOSC = 8 MHz (crystal), fSYS = 40 MHz, fBUS = 20 MHz

3. IEC/SAE Level Maximums: N≤12 dBµV, M≤18 dBµV, K≤30 dBµV, I ≤36 dBµV, H≤42 dBµV.

4. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband

TEM Cell Method

Switching specifications

5.2.1 Control timing

Table 7. Control timing

Num C Rating Symbol Min Typical1Max Unit

1 D System and core clock fSys DC — 48 MHz

2 P Bus frequency (tcyc = 1/fBus) fBus DC — 24 MHz

3 P Internal low power oscillator frequency fLPO 0.67 1.0 1.25 KHz

4 D External reset pulse width2textrst 1.5 ×

tcyc

— — ns

5 D Reset low drive trstdrv 34 × tcyc — — ns

6 D IRQ pulse width Asynchronous

path2tILIH 100 — — ns

D Synchronous path3tIHIL 1.5 × tcyc — — ns

Table continues on the next page...

5.2

Switching specifications

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16 NXP Semiconductors

Table 7. Control timing (continued)

Num C Rating Symbol Min Typical1Max Unit

7 D Keyboard interrupt pulse

width

Asynchronous

path2tILIH 100 — — ns

D Synchronous path tIHIL 1.5 × tcyc — — ns

8 C Port rise and fall time -

Normal drive strength

(load = 50 pF)4

— tRise — 10.2 — ns

C tFall — 9.5 — ns

C Port rise and fall time -

high drive strength (load =

50 pF)4

— tRise — 5.4 — ns

C tFall — 4.6 — ns

1. Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated.

2. This is the shortest pulse that is guaranteed to be recognized as a RESET pin request.

3. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or

may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.

4. Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range -40 °C to 105 °C.











 

textrst

RESET_b pin

Figure 9. Reset timing

tIHIL

KBIPx

tILIH

IRQ/KBIPx

Figure 10. KBIPx timing

5.2.2 FTM module timing

Synchronizer circuits determine the shortest input pulses that can be recognized or the

fastest clock that can be used as the optional external source to the timer counter. These

synchronizers operate from the current bus rate clock.

Table 8. FTM input timing

C Function Symbol Min Max Unit

D Timer clock

frequency

fTimer fBus fSys Hz

D External clock

frequency

fTCLK 0 fTimer/4 Hz

Table continues on the next page...

Switching specifications

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NXP Semiconductors 17

Table 8. FTM input timing (continued)

C Function Symbol Min Max Unit

D External clock

period

tTCLK 4 — tTimer, 1

D External clock high

time

tclkh 1.5 — tTimer1

D External clock low

time

tclkl 1.5 — tTimer1

D Input capture pulse

width

tICPW 1.5 — tTimer1

1. tTimer = 1/fTimer











 

tTCLK

tclkh

tclkl

TCLK

Figure 11. Timer external clock











 

tICPW

FTMCHn

tICPW

FTMCHn

Figure 12. Timer input capture pulse

Thermal specifications

5.3.1 Thermal operating requirements

Table 9. Thermal operating requirements

Symbol Description Min. Max. Unit Notes

TJDie junction temperature –40 125 °C

TAAmbient temperature –40 105 °C 1

1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to

determine TJ is: TJ = TA + θJA x chip power dissipation

5.3

Thermal specifications

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18 NXP Semiconductors

5.3.2 Thermal characteristics

This section provides information about operating temperature range, power dissipation,

and package thermal resistance. Power dissipation on I/O pins is usually small compared

to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-

determined rather than being controlled by the MCU design. To take PI/O into account in

power calculations, determine the difference between actual pin voltage and VSS or VDD

and multiply by the pin current for each I/O pin. Except in cases of unusually high pin

current (heavy loads), the difference between pin voltage and VSS or VDD will be very

small.

Table 10. Thermal attributes

Board type Symbol Description 64

LQFP

64 QFP 44

LQFP

Unit Notes

Single-layer (1S) RθJA Thermal resistance, junction

to ambient (natural

convection)

71 61 75 57 °C/W 1, 2

Four-layer (2s2p) RθJA Thermal resistance, junction

to ambient (natural

convection)

53 47 53 44 °C/W 1, 3

Single-layer (1S) RθJMA Thermal resistance, junction

to ambient (200 ft./min. air

speed)

59 50 62 47 °C/W 1, 3

Four-layer (2s2p) RθJMA Thermal resistance, junction

to ambient (200 ft./min. air

speed)

46 41 47 38 °C/W 1, 3

— RθJB Thermal resistance, junction

to board

35 32 34 28 °C/W 4

— RθJC Thermal resistance, junction

to case

20 23 20 15 °C/W 5

—ΨJT Thermal characterization

parameter, junction to

package top outside center

(natural convection)

5 8 5 3 °C/W 6

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site

(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board

thermal resistance.

2. Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.

3. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured

on the top surface of the board near the package.

5. Thermal resistance between the die and the solder pad on the bottom of the package. Interface resistance is ignored.

6. Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization.

The average chip-junction temperature (TJ) in °C can be obtained from:

TJ = TA + (PD × θJA)

Thermal specifications

KE06 Sub-Family Data Sheet, Rev. 4, 07/2016

NXP Semiconductors 19

Where:

TA = Ambient temperature, °C

θJA = Package thermal resistance, junction-to-ambient, °C/W

PD = Pint + PI/O

Pint = IDD × VDD, Watts - chip internal power

PI/O = Power dissipation on input and output pins - user determined

For most applications, PI/O << Pint and can be neglected. An approximate relationship

between PD and TJ (if PI/O is neglected) is:

PD = K ÷ (TJ + 273 °C)

Solving the equations above for K gives:

K = PD × (TA + 273 °C) + θJA × (PD)2

where K is a constant pertaining to the particular part. K can be determined by measuring

PD (at equilibrium) for an known TA. Using this value of K, the values of PD and TJ can

be obtained by solving the above equations iteratively for any value of TA.

6Peripheral operating requirements and behaviors

6.1 Core modules

6.1.1 SWD electricals

Table 11. SWD full voltage range electricals

Symbol Description Min. Max. Unit

Operating voltage 2.7 5.5 V

J1 SWD_CLK frequency of operation

• Serial wire debug

MHz

J2 SWD_CLK cycle period 1/J1 — ns

J3 SWD_CLK clock pulse width

• Serial wire debug

—

J4 SWD_CLK rise and fall times — 3 ns

J9 SWD_DIO input data setup time to SWD_CLK rise 10 — ns

J10 SWD_DIO input data hold time after SWD_CLK rise 3 — ns

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Peripheral operating requirements and behaviors

KE06 Sub-Family Data Sheet, Rev. 4, 07/2016

20 NXP Semiconductors

Table 11. SWD full voltage range electricals (continued)

Symbol Description Min. Max. Unit

J11 SWD_CLK high to SWD_DIO data valid — 35 ns

J12 SWD_CLK high to SWD_DIO high-Z 5 — ns

J3 J3

J4 J4

SWD_CLK (input)

Figure 13. Serial wire clock input timing

J11

J12

J11

J9 J10

Input data valid

Output data valid

SWD_CLK

SWD_DIO

Figure 14. Serial wire data timing

6.2 External oscillator (OSC) and ICS characteristics

Table 12. OSC and ICS specifications (temperature range = -40 to 105 °C ambient)

Num C Characteristic Symbol Min Typical1Max Unit

1 C Crystal or

resonator

frequency

Low range (RANGE = 0) flo 31.25 32.768 39.0625 kHz

C High range (RANGE = 1) fhi 4 — 24 MHz

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Peripheral operating requirements and behaviors

KE06 Sub-Family Data Sheet, Rev. 4, 07/2016

NXP Semiconductors 21

Table 12. OSC and ICS specifications (temperature range = -40 to 105 °C ambient)

(continued)

Num C Characteristic Symbol Min Typical1Max Unit

2 D Load capacitors C1, C2 See Note2

3 D Feedback

resistor

Low Frequency, Low-Power

Mode3RF— — — MΩ

Low Frequency, High-Gain

Mode

— 10 — MΩ

High Frequency, Low-

Power Mode

— 1 — MΩ

High Frequency, High-Gain

Mode

— 1 — MΩ

4 D Series resistor -

Low Frequency

Low-Power Mode 3RS— 0 — kΩ

High-Gain Mode — 200 — kΩ

5 D Series resistor -

High Frequency

Low-Power Mode3RS— 0 — kΩ

D Series resistor -

High

Frequency,

High-Gain Mode

4 MHz — 0 — kΩ

D 8 MHz — 0 — kΩ

D 16 MHz — 0 — kΩ

6 C Crystal start-up

time low range

= 32.768 kHz

crystal; High

range = 20 MHz

crystal4,5

Low range, low power tCSTL — 1000 — ms

C Low range, high gain — 800 — ms

C High range, low power tCSTH — 3 — ms

C High range, high gain — 1.5 — ms

7 T Internal reference start-up time tIRST — 20 50 µs

8 P Internal reference clock (IRC) frequency trim

range

fint_t 31.25 — 39.0625 kHz

9 P Internal

reference clock

frequency,

factory trimmed,

T = 25 °C, VDD = 5 V fint_ft — 37.5 — kHz

10 P DCO output

frequency range

FLL reference = fint_t, flo,

or fhi/RDIV

fdco 40 — 50 MHz

11 P Factory trimmed

internal

oscillator

accuracy

T = 25 °C, VDD = 5 V Δfint_ft -0.5 — 0.5 %

12 C Deviation of IRC

over

temperature

when trimmed

at T = 25 °C,

VDD = 5 V

Over temperature range

from -40 °C to 105°C

Δfint_t -1 — 0.5 %

Over temperature range

from 0 °C to 105°C

Δfint_t -0.5 — 0.5

13 C Frequency

accuracy of

DCO output

using factory

trim value

Over temperature range

from -40 °C to 105°C

Δfdco_ft -1.5 — 1 %

Over temperature range

from 0 °C to 105°C

Δfdco_ft -1 — 1

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Peripheral operating requirements and behaviors

KE06 Sub-Family Data Sheet, Rev. 4, 07/2016

22 NXP Semiconductors