M25P20-VMP6T - STMicroelectronics

1/34December 2002

M25P20

2 Mbit, Low Voltage, Serial Flash Memory

With 25 MHz SPI Bus Interface

FEATURES SUMMARY

■2 Mbit of Flash Memory

■Page Program (up to 256 Bytes) in 1.5ms

(typical)

■Sector Erase (512 Kbit) in 2 s (typical)

■Bu lk Eras e (2 M b i t) in 3 s ( ty pic a l )

■2.7 V to 3.6 V Single Suppl y Voltage

■SPI Bus Compatible Serial Interface

■25 MHz Clock Rat e (maximum)

■Deep Power-down Mode 1 µA (typ ica l)

■Electronic Signature (11h)

■More than 100,000 Erase/Program Cycles per

Sector

■More than 20 Year Data Retention

Figure 1. Packages

SO8 (MN)

150 mil width

VFQFPN8 (MP)

(MLP8)

M25P20

2/34

SUMMARY DESCRIP TION

The M25P20 is a 2 Mbit (256K x 8) Serial Flash

Memory, with advanced write protection mecha-

nisms, acces se d by a high speed SPI- compatible

bus.

The memory can be programmed 1 to 256 bytes at

a time, using the Page Program instruction.

The mem ory is organi ze d as 4 sec tors, eac h con-

taining 256 p ages. Each page is 256 bytes wide.

Thus, the whole memory can be viewed as con-

sisting of 1024 pages, or 262,144 by tes .

The whole mem ory can b e erased using t he Bulk

Erase instruction, or a sector at a time, using the

Sector Erase instruction.

Figu re 2. L o gi c D iagram

Figure 3. SO and VFQFPN Connections

Note: 1. See page 30 (onwards) for package dimensions, and how

to identify pin-1.

Table 1. Sign al Names

AI04080

VCC

M25P20

HOLD

VSS

AI04081B

5DVSS C

HOLDQ

M25P20

C Serial Clock

D Serial Data Input

Q Serial Data Outp ut

SChip Select

W Write Protect

HOLD Hold

VCC Supply Voltage

VSS Ground

3/34

M25P20

SIGNAL DESCRIPTION

Serial Data Output (Q). This output signal is

used to transfer data serially out of the device.

Data is shifted out on the falling edge of Serial

Clock (C).

Serial Data Input (D). This input si gnal is used to

transfer data serial ly into the device. It receives in-

structions, addresses, and the data to be pro-

grammed. Values are latched on the rising edge of

Serial Clock (C).

Serial Clock (C). This input signal provides the

timing of the s erial interface. Instructions , address-

es, or data present at Serial Data Input (D) are

latched on the ris ing edge of Serial Clock (C) . Data

on Serial Data Output (Q) changes after the falling

edge of Serial Clock (C).

Chip Select (S). When this input signal is High,

the device is deselected and Serial Data Output

(Q) is at high impedance. Unless an internal Pro-

gram, Erase or Write Status Register cycle is in

progress, the device will b e in the Standby mode

(this is not the Deep Power-down mode). Driving

Chip S e lec t ( S ) Low enabl es the device, placing it

in the active power mode.

After Power-up, a falling edge on Chip Select (S)

is required prior to the start of any instruction.

Hold (HOLD). The Hold (HOLD) signal is used to

pause any serial communi cations with the device

without deselecti ng the device.

During the Hold condition, the Serial Data Output

(Q) is high impedance, and Serial Data Input (D)

and Serial Clock (C) are Don’t Care.

To start the Hol d condit ion, t he devi ce must be se-

lected, wit h C h ip Selec t ( S) driven Low.

Write Protect (W). The main purpose of this in-

put signal is to freeze the size of the area of m em-

ory that is protected against program or erase

instructions (as specified by the values in the BP1

and BP0 bits of the Status Register).

M25P20

4/34

SPI MODES

These dev ices can be drive n by a microcont ro ller

with its SPI peripheral running in either of the two

following modes:

– CP OL= 0, CPHA=0

– CP OL= 1, CPHA=1

For these two modes, input data is latched in on

the ri sing edge of Serial Cl ock (C), and output data

is available from the falling edge of Serial Clock

(C).

The difference between the two modes, as shown

in Fi gure 5, is the clock polarity when the bus mas-

ter is in Stand-by mode and not transferring data:

– C remains at 0 for (CPOL=0, CPHA=0)

– C remains at 1 for (CPOL=1, CPHA=1)

Figure 4. Bus Master and Memo ry Devi ces on the SPI Bus

Note: 1. The W ri te Protec t (W) and Hold (HOLD) signals should be dr i ven, High or Low as appropri at e.

Figu re 5. S PI Modes S up ported

AI03746D

Bus Master

(ST6, ST7, ST9,

ST10, Others) SPI Memory

Device

SDO

SDI

SCK

CQD

SPI Memory

Device

CQD

SPI Memory

Device

CQD

CS3 CS2 CS1

SPI Interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

WHOLD WHOLD WHOLD

AI01438B

MSB

CPHA

CPOL

MSB

5/34

M25P20

OPERATING FEATURE S

Page P rogramm i ng

To program one dat a byte, t wo i ns tructions ar e re-

quired: Write Enable (WREN), which is one byte,

and a Page Program (PP) sequence, which con-

sists of four bytes plus data. This is f ollowed by the

internal Program cycle (of duration tPP).

To spread this ove rhead, the Page P rogram (PP)

instruction allows up to 256 bytes to be pro-

grammed at a time (changing bits from 1 to 0), pro-

vided that they lie in consecutive addresses on the

same page of memory.

Sector Erase and Bul k Erase

The Page Program (PP) instruction allows bits to

be reset from 1 to 0. Before this can be applied, the

bytes of memo ry need to hav e been erased to a ll

1s (FFh). Thi s can be achieved either a s ector at a

time, using the Sector Erase (SE) instruction, or

throughout the entire memory, using the Bulk

Erase (BE) instruction. This starts an internal

Erase cycle (of duration tSE or tBE).

The Erase instruction must be preceeded by a

Write Enabl e (WREN) instruction.

Polling Duri ng a Wri te, Program or Erase Cycle

A further improvement in the time to Write Status

BE) can be achieved by not waiting for the worst

case delay (tW, tPP, tSE, or tBE). The Write In

Progress (WIP) bit is provided in t he Status Regi s-

ter so that the application program can m onitor its

value, polling it to establish when the previous

Write cycle, Pro gram cycle or Erase cycle is com-

plete.

Active Power, St a nd - by Po wer an d De ep

Power-Down Modes

When Chip Select (S) is Low, the device is en-

abled, and in the Active Power mode.

When Chip Select (S) is High, the device is dis-

abled, but could remain in the Active Power mode

until all internal cycles hav e completed (P ro gram,

Erase, Write Status Register). The device then

goes in t o the Stand-by P ower mode. T he dev ice

consumpt i on drops to ICC1.

The Deep Power-down mode is entered when the

specific instruction (the Enter Deep Power-down

Mode (DP) instruction) is executed. The device

consump tio n drops further to ICC2. T he device re-

mains in this mode until another specific instruc-

tion (the Release from Deep Power-down Mode

and Read Electro nic Signature (RE S) instruction)

is executed.

All other instructions are igno red whil e the dev ice

is in the Deep Power-down mode. This can be

used as an ext ra soft ware protection mecha nism,

when the device is not in active use, to protect the

device from inadvertant Write, Program or Erase

instructions.

Status Register

The Status Register contains a number of status

and control bits, as shown in Table 5, that can be

read or set (as appropriate) by specific instruc-

tions.

WIP bit. The Writ e In Progress (WIP) bit indic ates

whether the memory is busy with a Write Status

WEL bit. The Write Enable Latch (WEL) bit indi-

cates the status of the int ernal Write Enable Latch.

BP1, BP0 b its. The Block Protect (BP1, BP0) bits

are non-volatile. They define the size of the area to

be software protected against Program and Erase

instructions.

SRWD bit. The Status Register Write Disable

(SRWD) bit is operated in conjunction with the

Write Protect (W) signal. The Status Register

Write Disable (SRWD) bit and Write Protect (W)

signal allow the device to be put in th e Hardware

Protected mode. In this mode, the non-v olati le bits

of t he Status Register (SRWD, BP1, BP0) become

read-only bits.

M25P20

6/34

P rotec t i on Mode s

The environments where non-vol atile memory de-

vices are used can be very noisy. No SPI device

can operate correct ly i n the presence of excessive

noise. To help combat t his, the M25P20 boasts the

following data protection mechanisms:

■Power-On Reset and an internal timer (tPUW)

can provide protection against inadv ertant

change s while the power supply is o utside the

operating specification.

■Program , Erase and Write Status Register

instructions are checked that they consist of a

number of clock pulses that is a multiple of

eight, before they are accepted for execution.

■All instructions that modify data mus t be

preceded by a Write Enable (WREN) instruction

to set the Write Enable Latch (WEL) bit . This bit

is returned to its reset state by the fo llowing

events:

– Power-up

– Write Disable (WRDI) instruction completion

– Write Status Register (WRSR) instruction

completion

– Page Program (PP) i nstruction completion

– Sector Erase (SE) instruction completion

– Bulk Erase (BE) instruction completio n

■The Bl ock Protect (BP1, BP0) bits allow part of

the memory to be configured as read-only. This

is the Software Protected Mode (SPM).

■The Write Protect (W) signal, in co-operation

with t he Stat us Register Write Di sabl e (SRWD)

bit, allows the Block Protect (BP1, BP0) bits and

Status Register Write Disable (SRWD) bit to be

write-protected. This is the Hardware Protected

Mode (HPM).

■In addi tion to the low power consumption

feature, the Deep Power-down mode offers

extra software protection from inadvertant

Write, Program and Erase instructions, as all

instructions are ignored except one particular

instruction (the Release from Deep Power-

down instruction).

Table 2. Pro tected Area Sizes

Note: 1. The de vi ce is ready to accept a Bu l k E rase in st ruction i f, and on l y if, bo th Block Protect (BP1, BP0) are 0.

Status Regis ter

Content Memory Content

BP1 Bit BP0 Bit Protected Area Unprotected Area

0 0 none All sectors1 (four sectors: 0, 1, 2 and 3)

0 1 Upper quarter (Sector 3) Lower three-quarters (three sectors: 0 to 2)

1 0 Upper half (two sectors: 2 and 3) Lower half (Sectors 0 and 1)

1 1 All sectors (four sectors: 0, 1, 2 and 3) none

7/34

M25P20

Hold Conditio n

The Hold (HOLD ) s ignal is used to pause any se-

rial communications with the device wi thou t reset-

ting the clocking sequence. However, taking this

signal Low does not terminate any Write Status

in progress.

To enter the Hold condition, the device must be

sele c ted, with C hip Select (S) Low.

The Hold condit ion start s on the falling edge of the

Hold (HOLD) signal, provided that this coincides

with Serial Clock (C) bei ng Low (as shown i n F ig-

ure 6).

The Hold condition ends on the rising edge of the

Hold (HOLD) signal, provided that this coincides

with Serial Clock (C) being Low.

If the falling edge does not coincide with Serial

Clock (C) being Low, the Hold condition s tarts a f-

ter Serial Clock (C) next goes Low. Similarly, if the

rising edge does not coincide with Serial Clock (C)

being Low, the Hold condition ends after Serial

Clock (C) next goes Low. (This is shown i n Figure

6).

During the Hold condition, the Serial Data Output

(Q) is high impedance, and Serial Data Input (D)

and Serial Clock (C) are Don’t Care.

Normally, the device is kept selected, with Chip

Select (S) driven Low, f or t he whole dur ation of the

Hold condition. This is to en su re th at the state of

the internal logic remains unchanged from the mo-

ment of entering the Hold condition.

If Chip Select (S) go es High whil e the device is in

the Hold c ondition, this has the effect of reset ting

the internal logic of the device. To restart commu-

nication with the device, it is necessary to drive

Hold (HO LD) High, and then to drive Chip Select

(S) Low. This prevent s t he device from going back

to the Hold condition.

Figure 6 . Hold Condition Activatio n

AI02029D

HOLD

Hold

Condition

(standard use)

Hold

Condition

(non-standard use)

M25P20

8/34

ME M OR Y ORGANIZA TI ON

The memory is organized as :

■262,144 byt es (8 bits each)

■4 sec tors (512 Kbits, 65536 bytes each)

■1024 pages (256 bytes each).

Each page can be individually programmed (bits

are programmed from 1 to 0). The device is Sector

or Bulk Erasable (bits are erased from 0 to 1) but

not Page Erasable.

Table 3. Memory Organization

Figu re 7. Blo ck Dia gram

Sector Address Range

3 30000h 3FFFFh

2 20000h 2FFFFh

1 10000h 1FFFFh

0 00000h 0FFFFh

AI04079

HOLD

WControl Logic High Voltage

Generator

I/O Shift Register

Address Register

and Counter 256 Byte

Data Buffer

256 Bytes (Page Size)

X Decoder

Y Decoder

Status

00000h

10000h

20000h

30000h

3FFFFh

000FFh

Size of the

read-only

memory area

9/34

M25P20

INSTRUCTIONS

All instructions, addresses a nd data are shifted in

and out of the device, most significant bit fi rst.

Serial Data Input (D) is sampled on the first ri sing

edge of Serial Clock (C) after Chip Select (S) is

driven Low. Then, the one-byte instruction code

must be shifted in to the device, most signif icant bit

first, on Serial Data Input (D), each bit being

latched on the rising edges of Seri al Clock (C).

The instruct i on set is listed i n Table 4.

Every instruction sequence st arts with a one-byte

instruction code. Depending on the instruction,

this might be f ollowed by address bytes, or by data

bytes, or by both or none. Chip Select (S) must be

driven High after the last bit of the instruction se-

quence has been shifted in.

In the case of a Read Data Bytes (READ), Read

Data Bytes at Higher Speed (Fast_Read), Read

Status Register (RDSR) or Release from Deep

Power-down, and Read Electronic Signature

(RES) instruction, the shifted-in instruction se-

quence is followed by a data-out sequence. Chip

Select (S) can be driven High after any bit of the

data-out sequen ce is being shifted out.

In the c as e of a Page Program (PP), Sector Erase

(SE), Bulk Erase (BE), Write Status Register

(WRSR), Write Enable (WREN), Write Disable

(WRDI) or Deep Power-down (DP) instruction,

Chip Select (S) must be driven High exactly at a

byte bounda ry, otherwise the instructio n is reject-

ed, and is not executed. That is, Chip Select (S)

must driven High when the number of clock pulses

after Chip Select (S) being driven Low is an ex act

multiple of eight.

All attempts to access the mem ory array during a

Write Status Register cycle, Program cycle or

Erase cycle are ignored, and the internal Write

Status Register cycle, Program cycle or Erase cy-

cle cont i nues unaf fected.

Table 4. Instructi on Set

Instruction Description One-byte Instruction Code Address

Bytes Dummy

Bytes Data

Bytes

WREN Write Enable 0000 0110 0 0 0

WRDI Write Disable 0000 0100 0 0 0

RDSR Read Status Register 0000 0101 0 0 1 to ∞

WRSR Write Status Register 0000 0001 0 0 1

READ Read Data Bytes 0000 0011 3 0 1 to ∞

FAST_READ Read Data Bytes at Higher Speed 0000 1011 3 1 1 to ∞

PP Page Program 0000 0010 3 0 1 to 256

SE Sector Erase 1101 1000 3 0 0

BE Bulk Erase 1100 0111 0 0 0

DP Deep Power-down 1011 1001 0 0 0

RES Release from Deep Power-down,

and Read Electronic Signature 1010 1011 0 3 1 to ∞

Release from Deep Power-down 0 0 0

M25P20

10/34

Figure 8. Write En able (WRE N) Instruction Sequenc e

Write Enable (WREN)

The Write Enable (WREN) instruction (Figure 8)

sets the Write Enable Latch (WEL ) bit.

The Write Enabl e Latch (WEL) bi t must be set pri-

or to every Page Program (PP), Sector Erase

(SE), Bulk Erase (BE) and Write Status Register

(WRSR) instruction.

The Write Enable (WREN) instruction is entered

by driving Chip Select (S) Low, sending the in-

struction code, and then driving Chip Select (S)

High.

Figure 9. Write Disable (WRDI) Instruction Sequence

Write Disabl e (WRDI)

The Write Disable (WRDI) instruction (Figure 9)

resets the Write Enable Latch (WEL) bit.

The Write Disable (WRDI) instruction is entered by

driving Chip Select (S) Low, sending the instruc-

tion code, and then driving Chip Select (S ) High.

The Write Enable Latch (WEL) bit is reset under

the following conditions:

– Power-up

– Write Disabl e (WRDI) instruction compl eti on

– Write Status Register (WRSR) instruction com-

pletion

– P age P rogram (PP) instruction completion

– Sect or Erase (SE) instruction completion

– B ulk Erase (BE) instruction completion

AI02281E

21 34567

High Impedance

Instruction

AI03750D

21 34567

High Impedance

Instruction

11/34

M25P20

Figure 10. Read Status Register (RDSR) Instruct ion Sequence and Data-Out Sequence

Read Status Register (RDSR)

The Read Status Register (RDSR) instruction al-

lows the Status Register to be read. The Status

Program, Erase or Write Status Register cycle is in

progress. When one of these cycl es i s in progress,

it is rec ommended to check the Write In Progress

(WIP) bit before sending a new instruction to the

device. It is also possibl e to read the Status Reg-

ister continuously, as shown in Figure 10.

Table 5. Status Register Format

The status and cont rol bits of the Stat us Register

are as fol l ows:

WIP bit. The Writ e In Progress (WIP) bit indic ates

whether the memory is busy with a Write Status

such a cycle is in progress, when reset to 0 no

suc h cycle is in pr ogress.

WEL bit. The Write Enable Latch (WEL) bit indi-

cates the status of the int ernal Write Enable Latch.

When set to 1 the internal Write Enable Latch is

set, whe n set to 0 the i nternal Write Enabl e Latch

is reset and no Write Status Reg ister, Program or

Erase instruct ion is accepted.

BP1, BP0 b its. The Block Protect (BP1, BP0) bits

are non-volatile. They define the size of the area to

be software protected against Program and Erase

instructions. These b its are written with the Write

Status Register (WRSR) instruction. When one or

both of the Block Protect (BP 1, B P0) bit s i s set to

1, the relevant memory area (as defined in Table

2) becomes protected against Page Program (PP)

and Sector Erase (SE) instructions. The Block

Protect (BP1, BP0) bits can be written provided

that the Hardware Protected mode has not been

set. The Bulk Erase (BE) instruction is ex ecuted if ,

and only if, both Block Protect (BP1, BP0) bits are

SRWD bit. The Status Register Write Disable

(SRWD) bit is operated in conjunction with the

Write Protect (W) signal. The Status Register

Write Disable (SRWD) bit and Write Protect (W)

signal allow the device to be put in th e Hardware

Protected mode (when the Status Register Write

Disable (SRWD) bit is set to 1 , and Write Protect

(W) is driven Low). In this mode, the non-volatile

bits of the Status Register (SRWD, BP1, BP0) be-

come read-only bit s and the Write Status Regis ter

(WRSR) instruction is no longer accepted for exe-

cution.

21 3456789101112131415

Instruction

AI02031E

Q76543210

Status Register Out

High Impedance

MSB

76543210

Status Register Out

MSB

b7 b0

SRWD 0 0 0 BP1 BP0 WEL WIP

Status Register Write Protect

Block Protect Bits

Write Enable Latch Bit

Write In Progress Bit

M25P20

12/34

Figure 11. Write S tatus Register (WRSR) Instruction Sequence

Write Status Regist er (WRSR)

The Write Status Register (WRSR) instruction al-

lows new val ues to be written to the Status Regis-

ter. Before it can be accepted, a Write Enable

(WREN) instruction must previously have been ex-

ecuted. After the Write Enable (WREN) instruction

has been d ecoded and ex ecuted, the de vice se ts

the Write Enable Latch (WEL).

The Write Status Register (WRSR) instruction is

entered by driving Chip Select (S) Low, followed

by the instruction code and the dat a byt e on Serial

Data Input (D).

The instruction sequence is shown in Figure 11.

The Write Status Register (WRSR) instruction has

no effect on b6, b5, b4, b1 and b0 of the Status

Chip Select (S) must be driven High after the

eighth bit of the data byte has been latched in. If

not, the W rite Status Regi ster (WRSR) instruction

is not executed. As soon as Chip Select (S) is driv-

en Hi gh, th e self-ti med Write S tatus Register cycle

(whose du ration is t W) is init iate d. Wh ile the Wr ite

Status Register cycle is in progress, the Status

Write In P rogress (WIP) bit. T he Write In Progress

(WIP) bit is 1 during the self-timed Write Status

some unspecified time before the cycle is complet-

ed, the Write Enab le Latch (WEL) is reset.

The Write Status Register (WRSR) instruction al-

lows the user to change the values of the Block

Protect (BP1, BP0) bits, to define the size of the

area that i s to be treated as rea d-only, as defined

in Table 2. The Write Status Register (WRSR) in-

struction also allows the user to set or reset the

Status Register Write Disable (SRWD) bit in ac-

cordance with the Write Protect (W) signal. The

Status Register Write Disable (SRWD) bit and

Write Protect (W) signal allow the devi ce to be put

in the Hardware Protected Mode (HPM). The Write

Status Register (WRSR) instruction is n ot execut-

ed once the Hardware Protected Mode (HPM) is

entered.

AI02282D

21 3456789101112131415

High Impedance

Instruction Status

765432 0

MSB

13/34

M25P20

Table 6. Pro tection M ode s

Note: 1. As defi ned by th e values in the Block Pr otect (B P1, BP0) bi ts of the Status Reg i st er, as shown in Table 2.

The prot ection f eat ures of the device are summ a-

rized in Tabl e 6.

When the Status Register Write Disable (SRWD)

bit of the Status Register is 0 (its initial delivery

state), it is possible to write to the Status Regi ster

provided that the Write Enable Latch (WEL) bit has

previously been set by a Write Enable (WREN) in-

struction, rega rdless o f the wh ether W rite Protect

(W) is driven High or Low.

When the Status Register Write Disable (SRWD)

bit of the Status Register is set to 1, two cases

need to be considered , depending on t he state of

Write Protect (W):

– I f Write Protect (W) is driven High, it is possible

to write to the Status Regis ter provided tha t the

Write Enable Latch (WEL) bit has previously

been set by a Write Enable (WREN) instruction.

– I f Write Prot ect (W) i s driven Low, it is

not

pos-

sible to write to the Status Register

even

if the

Write Enable Latch (WEL) bit has previously

been set by a Write Enable (WREN) instruction.

(Attempts to write to the Status Register are re-

jected, and are no t accepted for ex ecution). As

a consequence, all the data by tes in the memo-

ry area that are sof tware protected (SPM) by the

Block Protect (BP1, BP 0) bits of the Status Reg-

ister, are also hardware protected against data

modification.

Regardless of the order of the two events, the

Hardware Protected Mode (HPM) can be ent ered:

– by setting the Status Register Write Disable

(SRWD) bit after driving Write Protect (W) Low

– or by dri ving Write Protect (W) Low after setting

the Status Register Write Di sable (SRWD) bit.

The only way to exit the Hardware Protected Mode

(HPM) once entered is to pull Write Protect (W)

High.

If Write Protect (W) is permanently tied High, the

Hardware Protected Mode (HPM) can never be

activated, and only the Software Protected Mode

(SPM), using the Block Protect (B P1, BP 0) bi ts of

the Status Register, can be used.

Signal SRWD

Bit Mode Write Protection of the

Status Register

Memory Content

Protected Area1Unprotected Area1

Software

Protected

(SPM)

Status Register is

Writable (if the WREN

instruction has set the

WEL bit)

The values in the SRWD,

BP1 and BP0 bits can be

changed

Protected again st Page

Program, Sector Erase

and Bulk Erase

Ready to accept Page

Program and Sector

Erase instructions

Hardware

Protected

(HPM)

Status Register is

Hardware write protected

The values in the SRWD,

BP1 and BP0 bits cannot

be changed

Protected again st Page

Program, Sector Erase

and Bulk Erase

Ready to accept Page

Program and Sector

Erase instructions

M25P20

14/34

Figure 12. Read Dat a Bytes (READ) Instruction Sequence and Data-Out Seq u ence

Note: 1. Address bits A23 to A18 are Don’t Ca re.

Read Data Bytes (READ)

The de vice is f irst sel ec ted by driving Chip Sele ct

(S) Low. The instruction code for the Read Data

Bytes (READ) instruction is followed by a 3-byte

address (A23-A0), each bit being latched- in during

the rising edge of Serial Cl ock (C). Then the mem-

ory contents , at that address, is shifted out on Se-

rial Data Output (Q), eac h b it bein g s hift ed o ut, at

a maximum frequency fR, during the falling edge of

Serial Clock (C).

The instruction sequence is shown in Figure 12.

The first byte addressed can be at any location.

The address is automatically incremented to the

next higher address after each byte of data is shift-

ed out. The whole memory can, t herefore, be read

with a si ngl e Read Data Byt es (READ) i nstruc tion.

When the highes t address is reached, the address

counter rolls over to 000000h, allowing the read

sequence to be continued indefinitely.

The Read Data Bytes (READ) instruction is termi-

nated by driving Chi p Select (S) Hi gh. Chip Sel ect

(S) can be driven High at any time during data out-

put. Any Read Data Bytes (READ) instruction,

while an Erase, Program or Write cycle is in

progress, is rej ected without having any ef fects on

th e cycle tha t is i n progress.

AI03748D

21 345678910 2829303132333435

2221 3210

36 37 38

76543 1 7

High Impedance Data Out 1

Instruction 24-Bit Address

MSB

Data Out 2

15/34

M25P20

Figure 13. Read Data Bytes at Higher Sp eed (FAST_RE AD) Instruction Sequence and Data-Out

Sequence

Note: 1. Address bits A23 to A18 are Don’t Ca re.

Read Data Bytes at H igher Speed

(FAST_READ)

The de vice is f irst sel ec ted by driving Chip Sele ct

(S) Low. The instruction code for the Read Data

Bytes at Higher Speed (FAST_READ) instruction

is followed by a 3-byte address (A23-A0) and a

dummy byte, each bit being latched-in during the

rising edge of S erial Clock (C). Then the me mory

contents, at that address, is shifted out on Serial

Data Output (Q), each bit being shifted out, at a

maximum frequency fC, durin g the falling edg e of

Serial Clock (C).

The instruction sequence is shown in Figure 13.

The first byte addressed can be at any location.

The address is automatically incremented to the

next higher address after each byte of data is shift-

ed out. The whole memory can, t herefore, be read

with a single Read Data Bytes at Higher Speed

(FAST_READ) instruction. When the highest ad-

dress is reached, the address counter rolls over to

000000h, allowing the read sequence to be contin-

ued indefinitely.

The Read Data Bytes at Higher Speed

(FAST_READ) instruction is terminated by driving

Chip Select (S) High. Chip Select (S) can be driv-

en High at any time during data outp ut. Any Read

Data Bytes at Higher Speed (FAST_READ) in-

struction, while an Erase, Program or Write cycle

is in progress, is rejected without having any ef-

fects on the cycle that is in progress.

AI04006

21 345678910 28293031

2221 3210

High Impedance

Instruction 24 BIT ADDRESS

32 33 34 36 37 38 39 40 41 42 43 44 45 46

765432 0

DATA OUT 1

Dummy Byte

MSB

76543210

DATA OUT 2

MSB MSB

765432 0

M25P20

16/34

Figure 14. Page Program (PP) Instruction Sequence

Note: 1. Address bits A23 to A18 are Don’t Ca re.

Page Prog ram (PP)

The Page Pr ogram (PP) instruction allows bytes to

be programmed in t he memory (changing bits from

1 to 0). Before i t can be acc ept ed, a Wri te Enable

(WREN) instruction must previously have been ex-

ecuted. After the Write Enable (WREN) instruction

has been decoded, the device sets the Write En-

able Latch (WEL).

The Page Pro gram (PP) instruction is entered by

driving Chip Select (S) Low, followed by the in-

struction code, three address bytes and at least

one data byte on Serial Data Input (D). If the 8

least significant address bits (A7-A0) are not all

zero, all transmitted dat a that goes beyond the end

of the current page are programmed from the star t

address of the same page (from the address

whose 8 l east si gnificant bi ts (A7-A0) are all zero).

Chip Select (S) must be driven Low for the entire

duration of the seq uence.

The instruction sequence is shown in Figure 14.

If more than 256 bytes are sent to the device, pre-

viously latched data are discarded and the last 256

data bytes are guaranteed to be programmed cor-

rectly within the sam e pag e. If less than 256 Data

bytes are sent to device, they are correctly pro-

grammed at the request ed addresses without hav-

ing any effects on the other bytes of the same

page.

Chip Select (S) must be driven High after the

eighth bi t of the l ast data byte has been latched in,

otherwise the Page Program (PP) instruction is not

executed.

As soon as Chip Select (S ) is driv en H i gh , th e s e lf -

timed Pa ge Program cycle (whose dura ti o n is tPP)

is initiated. While the Page Program cycle is in

progress, the Status Register may be read to

check the value of the Write In Progress (WIP) bit .

The Write In Progress ( WIP) bit is 1 during the self-

timed Page Program cycle, and is 0 when it is

completed. At some unspecified time before the

cycle is completed, the Write Enable Latch (WEL)

bi t i s reset.

A Page Program (PP) instruction applied to a page

which is protected by the Block Protect (BP1, BP0)

bits (see Tables 3 and 2) is not executed.

AI04082B

4241 43 44 45 46 47 48 49 50 52 53 54 5540

21 345678910 2829303132333435

2221 3210

36 37 38

Instruction 24-Bit Address

765432 0

Data Byte 1

765432 0

Data Byte 2

765432 0

Data Byte 3 Data Byte 256

2079

2078

2077

2076

2075

2074

2073

765432 0

2072

MSB MSB

MSB MSB MSB

17/34

M25P20

Figure 15. Sector Erase (SE) Instruction Sequence

Note: 1. Address bits A23 to A18 are Don’t Ca re.

Sector Erase (SE)

The Sector E rase (SE) instruction sets t o 1 (FFh)

all bits inside the chosen sector. Before it can be

accepted, a Write Enable (WREN) instruction

must previously have been executed. After the

Write Enable (WREN) instruction has been decod-

ed, the device sets the Write Enable Latch (WE L).

The Sector Erase (SE) instruction is entered by

driving Chip Select (S) Low, followed by the in-

struction code, and three address bytes on Serial

Data Input (D). Any address inside the Sector (see

Table 3) is a valid address for the Sector Erase

(SE) instruction. Chip Select (S) must be driven

Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 15.

Chip Select (S) must be driven High after the

eighth bit of the last address byt e has been latched

in, otherwise the Sector Erase (SE) instruction is

not executed. As soon as Chip Select (S) is driven

High, the self-timed Sector Erase cycle (whose du-

ration is tSE) is initiated. While the Sector Erase cy-

cle is in progress, the Status Register may be read

to check the value of the Wri te In Progres s (WIP)

bit. The Wri t e In Progress (WIP) bit is 1 during the

self-timed Secto r Erase cycle, and is 0 when it is

completed. At some unspecified time before the

cycle is completed, the Write Enable Latch (WEL)

bi t i s reset.

A Sec tor E ras e (SE ) in structi on applie d to a page

which is prot ected by the Block Protect (BP1, BP0)

bits (see Tables 3 and 2) is not executed.

24 Bit Address

AI03751D

21 3456789 293031

Instruction

23 22 2 0

MSB

M25P20

18/34

Figure 16. Bulk Erase (BE) Instru ction Sequence

Bulk Erase ( BE)

The Bulk Erase (BE) instruction sets all bits to 1

(FFh). Before it can be acce pted , a Write Enable

(WREN) instruction must previously have been ex-

ecuted. After the Write Enable (WREN) instruction

has been decoded, the device sets the Write En-

able Latch (WEL).

The Bulk Erase (BE) instr uction is entered by driv-

ing Chip Select (S) Low, followed by the instruction

code on Serial Data Input (D). Chip Select (S)

must be driven Low for the entire duration of the

sequence.

The instruction sequence is shown in Figure 16.

Chip Select (S) must be driven High after the

eighth bi t of the instruction code has been l atched

in, otherwise the Bulk Erase instruction is not exe-

cuted. As soon as Chip Select (S) is driven High,

th e s elf-timed Bulk Era se cycle (whose durat ion is

tBE) is initiated. While the Bulk Erase cycle is in

progress, the Status Register may be read to

check the value of the Write In Progress (WIP) bit .

The Write In Progress ( WIP) bit is 1 during the self-

timed Bulk Erase cycle, and is 0 when it is com-

pleted. At some unspecifie d time before the cycle

is completed, the Write Enable Latch (WEL) bit is

reset.

The Bulk Erase (BE) instruction is executed only if

both Block Pr otect (BP 1, BP0) bi ts are 0. The Bulk

Erase (BE) instruction is ignored if one, or more,

sectors are protected.

AI03752D

21 345670

Instruction

19/34

M25P20

Figure 17. Deep Power-down ( DP) Instruction Sequ ence

Deep Pow er-down (DP)

Executing the Deep Power-down (DP) instruction

is the only way to put the device in t he lowest con-

sumption mode (the Deep Power-down mode). It

can also be used as an extra software protection

mechanism, while the device is not in active use,

since in this mode, the device ignores all Write,

Program and Eras e instructions.

Driving Chip Select (S) High deselects the device,

and puts the dev ice in the Sta ndby m ode (if t here

is no internal cycle currently in progress). But this

mode is not the Deep Power-down mode. The

Deep Power-down mode can only be entered by

executing the Deep Power-down (DP) instru ction,

to reduce the standby current (from ICC1 to I CC2,

as specified in Table 12).

Once the device has entered the Deep Power-

down mode, all instructions are ignored except the

Release from Deep Power-down and Read Elec-

tronic Signature (RES) instruction. This releases

the device from this mode. The Release from

Deep Power-down and Read Electronic Signature

(RES) instruc tion also allows the Electr onic Signa-

ture of the device t o be output on S erial Data Out-

put (Q).

The Deep P ower-down m ode automatically stops

at Power-down, and the device always Powers-up

in the St andby mode.

The Deep Power-down (DP) instructi on is entered

by driving Chip Select (S) Low, followed by the in-

struction code on Serial Data Input (D ). Chip Se-

lect (S) m us t be driven Low f or the entire duration

of the seq uence.

The instruct i on sequence is shown in Figure 17.

Chip Select (S) must be driven High after the

eighth bi t of the instruction code has been l atched

in, otherwise the Deep Power-down (DP ) instruc-

tion is not executed. As soon as Chip Select (S) i s

driven High, it requires a delay of tDP before the

supply current is reduced to ICC2 and the Deep

Power-down mode is entered.

Any Deep Power-down (DP) instruction, while an

Erase, Program or Write cycle is in progress, is re-

jected without having any eff ec ts on the cycle t h at

is in progr ess.

AI03753D

21 345670 t

Deep Power-down Mode

Stand-by Mode

Instruction

M25P20

20/34

Figure 18. Rel ease from Deep Po wer-d ow n and Read Electro nic Sign atur e (RES) Instruction

Sequence and Data -O u t Se qu e nce

Release from Deep Power-do wn and Read

Electronic Sign ature (RES)

Once the device has entered the Deep Power-

down mode, all instructions are ignored except the

Release from Deep Power-down and Read Elec-

tronic Signature (RES) instruction. Executing this

instruction takes the device out of the Deep Pow-

er-down mode. The instruction can also be used to

read, on Serial Dat a Output (Q), the 8-bit Electron-

ic Signature of the device.

Except while an Erase, Program or Write Status

Deep Power-down and Read Electronic Signature

(RES) instruction always provides access to the

Electronic Signatur e of the device, and can be ap-

plied even i f the Deep Po wer-down mode has not

been entered.

Any Release from Deep Power-down and Read

Electronic Signature (RES) instruction while an

Erase, Program or Write Status Register cycle is in

progress, is not decoded, and has no effect on the

cycle that i s in progress.

This instruction serves a s econd purpose. The de-

vice features an 8-bit Electroni c Signature, whose

value for the M25P 20 is 11h. This can be read us-

ing th e Release from Deep Power-down and Read

Electronic Signature (RES) instruction.

The de vice is f irst sel ec ted by driving Chip Sel ect

(S) Low. The instruction code is followed by 3

dummy bytes, each bit being latch ed-in on Seri al

Data Input (D) during the rising edge of Serial

Clock (C). Then, the 8-bit Electronic Signature,

stored in the memory, is shift ed out on Serial Data

Output (Q), each bit being shifted out during the

falling edge of Serial Clock (C).

The instruct i on sequence is shown in Figure 18.

The Release from Deep Power-down and Read

Electronic Si gnature (RES) instruction is terminat-

ed by driving Chip Select (S) High after the Elec-

tronic Signature has been read at least once.

Sending additional clock cycles on Serial Clock

(C), while Chip Select (S) is dr iven Low, cause the

Electronic Signature to be output repeatedly.

When Chip Select (S) i s dr iven High, t he devi ce i s

put in the Stand-by Power mode. If the device was

not previously in the Deep Power-down mode, the

transition to t he S tand-by Pow er mode is imm edi-

ate. If the device was previousl y in the Deep Pow-

er-down mode, though, the transition to the Stand-

by Power mode is delayed by tRES2, and Chip Se-

lect ( S ) must remain High for at least tRES2(max),

as specified in Table 13. Once in the Stand-by

Power mode, the device waits to be selected, so

that it can receive, decode and execute instruc-

tions.

AI04047C

21 345678910 2829303132333435

2221 3210

36 37 38

765432 0

High Impedance Electronic Signature Out

Instruction 3 Dummy Bytes

MSB

Stand-by Mode

Deep Power-down Mode

MSB

tRES2

21/34

M25P20

Figure 19. Rel ease from Deep Po wer-d ow n (RES) Instruction S eq uen ce

Driving Chip Select (S) High af ter the 8-bit inst ruc-

tion byte has been received by the device, but be-

fore the whole of the 8-bit Electronic Signature has

been transmit ted for the first time (as shown in Fig-

ure 19), still insures that the device is put into

Stand-by P ower mode. I f the d evice was not pre-

viously in the Deep Power-down mode, the transi-

tion to the Stand-by Power mode is immediate. If

the device was previously in the Deep Power-

down mode, though, the transition to the Stand-by

Power mode is delayed by t RES1, and Chip S elec t

(S) must remain High for at least tRES1(max), as

specified in Table 13. Once in the Stand-by Power

mode, the device waits to be selected, so that it

can receive, decode and execut e instructions.

AI04078B

21 345670 t

RES1

Stand-by Mode

Deep Power-down Mode

QHigh Impedance

Instruction

M25P20

22/34

POWER-UP AND POWER-DOWN

At Power-up and Power-down, the device must

not be selected (that is Chip Select (S ) must follow

the volt age appl i ed on VCC) until VCC reaches the

correct value:

–V

CC(min) at Power-up, and then for a further de-

lay o f tVSL

–V

SS at Power-down

Usually a simple pull-up resistor on Chip Select (S)

can be used to insure safe and proper Power-up

and Power-down.

To avoid data corruption and inadvertent write

operations during power up, a Power On Reset

(POR) circuit is included. The logic inside the

device is held reset while VCC is less than the POR

threshold value, VWI – a ll operations are disabled,

and the device does not respond to any

instruction.

Moreover, the device ignores all Write Enable

(WREN), Page Program (PP), Sector Erase (SE),

Bulk Erase (BE) and Write Status Register

(WRSR) instructi ons until a time delay of tPUW has

elapsed after the moment that VCC rises above the

VWI threshold. However, the correct operation of

the device is not guaranteed if, by t his time, VCC is

still below VCC(min). No Write Status Register,

Program or Erase inst ructions should be sent unti l

the later of:

–t

PUW af ter VCC passed the VWI threshold

–t

VSL afterVCC pass ed the VCC(min) level

These values are specified in Table 7.

If the delay, tVSL, has elapsed, after VCC has risen

above VCC(min), the device can be selected for

READ instructions even if the tPUW delay is not y et

fully elapsed.

At Power-up, the dev ice is in the following state:

– The device is in the Standby mode (not the

Deep Power-down mode).

– The Write Enable Latch (WEL) bit is reset.

Normal precautions must be taken for supply rail

decoupling, to stabl ise the V CC fe ed. Ea ch dev ice

in a syst em should have t he VCC rail decoupled by

a suitable capacitor close to the package pins.

(Generally, this capacitor is of the order of 0.1µF).

At Power-down, when VCC drops from the

operating voltage, to below the POR threshold

value, VWI, all operations are disabled and the

device does not respond to any instruction. (The

designer needs to be aw are that if a Power-down

occurs while a Writ e, Program or Erase cycle is in

progress, some data corruption can result.)

Figure 20. Power-up Timing

VCC

AI04009C

VCC(min)

VWI

Reset State

of the

Device

Chip Selection Not Allowed

Program, Erase and Write Commands are Rejected by the Device

tVSL

tPUW

time

Read Access allowed Device fully

accessible

VCC(max)

23/34

M25P20

Table 7. Power-Up Timing and VWI Thresh ol d

No te : 1. Thes e param e t e rs are characterize d onl y.

INITIAL DELIVERY STATE

The device is delivered with the memory array

erased: all bits are set to 1 (each byte contains

FFh). The Status Register cont ains 00h (all Status

Symbol Parameter Min. Max. Unit

tVSL1VCC(min) to S low 10 µs

tPUW1Time delay to Write instruction 1 10 ms

VWI1Write Inhibit Voltage 1 2 V

M25P20

24/34

MAX I MUM R A TI N G

Stressing the device ab ove t he rating listed in t he

Absolute Maximum Ratings" table may cause per-

manent damage to the device. These are stress

ratings only and operation of the device at t hese or

any other con ditions ab ove those i ndicated in t he

Operating sections of this specification is not im-

plied. Exposure to Absolute Max imum Rating con-

ditions for extended periods may affect device

reliability. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 8. Absolute Maximum Ratings

Not e: 1. I PC/ JEDEC J- STD-02 0A

2. JED EC Std JESD22-A11 4A (C1=100 pF, R1=1500 Ω, R2=500 Ω)

Symbol Parameter Min. Max. Unit

TSTG Storage Temperature –65 150 °C

TLEAD Lead Temperature during Soldering

(20 secon ds max.)1SO 235 °C

VFQFPN 235 °C

VIO Input and Output Voltage (with respect to Ground) –0.6 4.0 V

VCC Supply Voltage –0.6 4.0 V

VESD Electrostatic Discharge Voltage (Human Body model) 2–2000 2000 V

25/34

M25P20

DC AND AC PARAME TERS

This section summarizes the operating and m ea-

surement conditions, and the DC and AC charac-

teristics of the de vice . The parameters in the DC

and AC Characteristic tables that follow are de-

rived from tests performed under the Measure-

ment Conditions summarized in the relevant

tables. Des igners shoul d c heck that the operating

conditions in t heir circuit mat ch the meas urement

conditions when relying on the quoted parame-

ters.

Table 9. Operating Conditions

Table 10. AC Measurement Conditions

Note: 1. Output Hi-Z i s defined as the point where data out is no l onger dri ven.

Figure 21. AC Measurement I/O Waveform

Table 11. Capacitance

Note: Sampled o nl y, not 100% tested , at TA=25°C an d a frequency of 20 M Hz.

Symbol Parameter Min. Max. Unit

VCC Supply Voltage 2.7 3.6 V

TAAmbient Operati ng Temperatur e –40 85 °C

Symbol Parameter Min. Max. Unit

CLLoad Capacitance 30 pF

Input Rise and Fall Times 5 ns

Input Pulse Voltages 0.2VCC to 0.8VCC V

Input and Output Timing Reference Voltages 0.3VCC to 0.7VCC V

Symbol Parameter Test Condition Min.Max.Unit

COUT Output Capacitance (Q) VOUT = 0V 8 pF

CIN Input Capacitance (other pins) VIN = 0V 6 pF

AI00825B

0.8VCC

0.2VCC

0.7VCC

0.3VCC

Input and Output

Timing Reference Levels

Input Levels

M25P20

26/34

Table 12. DC Characteristics

Table 13. AC Characteristics

Symbol Parameter Test Condition

(in addition to those in Table 9) Min. Max. Unit

ILI Input Leakage Current ± 2 µA

ILO Output Leakage Current ± 2 µA

ICC1 Standby Current S = VCC, VIN = VSS or VCC 50 µA

ICC2 Deep Power-down Current S = VCC, VIN = VSS orVCC 5µA

CC3 Operating Current (READ) C = 0.1VCC / 0.9.VCC at 25 MHz,

Q = open 4mA

CC4 Operating Current (PP) S = VCC 15 mA

ICC5 Operating Current (WRSR) S = VCC 15 mA

ICC6 Operating Current (SE) S = VCC 15 mA

ICC7 Operating Current (BE) S = VCC 15 mA

VIL Input Low Voltage – 0.5 0.3VCC V

VIH Input High Volta ge 0.7VCC VCC+0.4 V

VOL Output Low Voltage IOL = 1.6 mA 0.4 V

VOH Output High Voltage IOH = –100 µAV

CC–0.2 V

Test conditions specified in Table 9 and Table 10

Symbol Alt. Parameter Min. Typ. Max. Unit

fCfCClock Frequency for the following instructions:

FAST_READ, PP, SE, BE, DP, RES,

WREN, WRDI, RDSR, WRSR D.C. 25 MHz

fRClock Fre quen cy for READ instruc tions D.C. 20 MHz

tCH 1tCLH Clock High Time 18 ns

tCL 1tCLL Clock Low Tim e 18 ns

tCLCH 2Clock Rise Time3 (peak to peak) 0.1 V/ns

tCHCL 2Clock Fall Time3 (peak to peak) 0.1 V/ns

tSLCH tCSS S Active Setup Time (relative to C) 10 ns

tCHSL S Not Active Hold Time (relative to C) 10 ns

tDVCH tDSU Data In Setup Time 5 ns

tCHDX tDH Data In Hold Time 5 ns

tCHSH S Active Hold Time (relative to C) 10 ns

tSHCH S Not Active Setup Time (relative to C) 10 ns

tSHSL tCSH S Dese lect Time 100 ns

tSHQ Z 2tDIS O utput Disable Time 15 ns

tCLQV tVClock Low to Output Valid 15 ns

27/34

M25P20

Note: 1. tCH + tCL must be greater than or equal to 1/ fC

2. Value guaranteed by charact erization, not 100% tested in pro duction.

3. Expressed as a slew-rate.

4. Only applicab l e as a constra i nt for a WRSR i nstruction wh en S RWD is set at 1.

tCLQX tHO O utput Hold Time 0 ns

tHLCH HOLD Setup Time (relative to C) 10 ns

tCHHH HOLD Hold Time (relative to C) 10 ns

tHHCH HOLD Setup Time (relative to C) 10 ns

tCHHL HOLD Hold Time (relative to C) 10 ns

tHHQX 2tLZ HOLD to Output Low-Z 15 ns

tHLQZ 2tHZ HOLD to Output High-Z 20 ns

tWHSL 4Write Protect Setup Time 20 ns

tSHWL 4Write Protect Hold Time 100 ns

tDP 2S High to Deep Power-down Mode 3 µs

tRES1 2S High to Standby Mode without Electronic

Signature Read 3µs

tRES2 2S High to Standby Mode with Electronic

Signature Read 1.8 µs

tWWrite Status Register Cycle Time 5 15 ms

tPP Page Program Cycle Time 1.5 5 ms

tSE Sector Erase Cycle Time 2 3 s

tBE Bulk Erase Cycle Time 3 6 s

Test conditions specified in Table 9 and Table 10

Symbol Alt. Parameter Min. Typ. Max. Unit

M25P20

28/34

Figure 22. Serial Input Timing

Figu re 23 . Wri te Pr ot ect Se tu p an d H ol d Tim in g du rin g WR S R wh en S R WD =1

AI01447C

MSB IN

tDVCH

High Impedance

LSB IN

tSLCH

tCHDX

tCHCL

tCLCH

tSHCH

tSHSL

tCHSHtCHSL

High Impedance

tWHSL tSHWL

AI07439

29/34

M25P20

Figure 24. Hold Timing

Figure 25. Output Timing

AI02032

HOLD

tCHHL

tHLCH

tHHCH

tCHHH

tHHQXtHLQZ

AI01449D

LSB OUT

DADDR.LSB IN

tSHQZ

tCH

tCL

tQLQH

tQHQL

tCLQX

tCLQV

tCLQX

tCLQV

M25P20

30/34

PACKAGE MECHANICAL

SO8 narrow – 8 lead Plastic Smal l Outline, 150 mils body wi dth, Pac kage Outline

Not e: Drawing is not to scale.

SO8 narrow – 8 lead Plastic Smal l Outline, 150 mils body wi dth, Pac kage Mecha ni cal Data

SO-a

LA1 α

h x 45˚

Symb. mm inches

Typ. Min. Max. Typ. Min. Max.

A 1.35 1.75 0.053 0.069

A1 0.10 0.25 0.004 0.010

B 0.33 0.51 0.013 0.020

C 0.19 0.25 0.007 0.010

D 4.80 5.00 0.189 0.197

E 3.80 4.00 0.150 0.157

e 1.27 – – 0.050 – –

H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.020

L 0.40 0.90 0.016 0.035

α0° 8° 0° 8°

N8 8

CP 0.10 0.004

31/34

M25P20

VFQFPN 8 – 8-contact Very-thin Fine-pitch QFP No-lead, Pac kage Ou tline

Not e: Drawing is not to scale.

VFQFPN 8 – 8-contact Very-thin Fine-pitch QFP No-lead, Pac kage Mecha ni cal Data

VFQFPN-01

eE2

Symb. mm inches

Typ. Min. Max. Typ. Min. Max.

A 0.85 1.00 0.0335 0.0394

A1 0.00 0.05 0.0000 0.0020

A2 0.65 0.0256

A3 0.20 0.0079

b 0.40 0.35 0.48 0.0157 0.0138 0.0189

D 6.00 0.2362

D1 5.75 0.2264

D2 3.40 3.20 3.60 0.1339 0.1260 0.1417

E 5.00 0.1969

E1 4.75 0.1870

E2 4.00 3.80 4.20 0.1575 0.1496 0.1654

e 1.27 0.0500

L 0.60 0.50 0.75 0.0236 0.0197 0.0295

θ12° 12°

M25P20

32/34

PART NUMBERING

Table 14. Ordering Information Scheme

For a list of available options (speed, package,

etc.) or for further i nf ormation on any aspect of this

device, please con tact your nearest ST Sales O f-

fice.

Example: M25P20 – V MN 6 T

Device Type

M25P

Device Function

20 = 2 Mbit (256K x 8)

Operating Voltage

V = VCC = 2.7 to 3.6V

Package

MN = SO8 (150 mil width)

MP = VFQFPN8 (MLP8)

Temperature Range

6 = –40 to 85 °C

Option

T = Tape & Reel Packing

33/34

M25P20

RE VISION HISTORY

Table 15. Document Revisio n History

Date Rev. Description of Revision

12-Apr-2001 1.0 Document written

25-May-2001 1.1 Serial Paged Flash Memory renamed as Serial Flash Memory

11-Sep-2001 1.2

Changes to text: Signal Description/Chip Select; Hold Condition/1st para; Protection modes;

Release from Power-down and Read Electronic Signature (RES); Power-up

Repositioning of several tables and illustrations without changing their contents

Power-up timing illustration; SO8W package removed

Changes to tables: Abs Max Ratings/VIO; DC Characteristics/VIL

16-Jan-2002 1.3 FAST_READ instruction added. Document revised with new timings, VWI, ICC3 and clock slew

rate. Descriptions of Polling, Hold Condition, Page Programming, Release for Deep Power-

down made more precise. Value of tW(max) modified.

16-May-2002 1.4 Clarification of descriptions of entering Stand-by Power mode from Deep Power-down mode,

and of terminating an instruction sequence or data-out sequence.

12-Sep-2002 1.5 VFQFPN8 package (MLP8) added. Document promoted to full datasheet.

13-Dec-2002 1.6 Typical Page Program time improved. Write Protect setup and hold times specified, for

applications that switch Write Protect to exit the Hardware Protection mode immediately bef ore

a WRSR, and to enter the Hardware Protection mode again immediately after.

M25P20

34/34

Info rm atio n fur ni shed is bel i eved to be ac curate an d rel i able. However, STMicro el ectro ni cs assumes no responsibility for the consequ ences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licen se is granted

by i m pl i cation or oth erwise under any pat ent or paten t righ ts of STMic roelec tr onics. Speci fications mentioned i n this publ ication are subject

to change without notice. This publication supersedes and replaces all informat ion previously supplied. STMicroelectronics products are not

authorized for use as critical comp onents in li fe support devi ces or syst em s without exp ress writ t en approval of STMi croel ectronics.

The ST l ogo is re gi stered tr ademark of STM i croel ectro ni cs

All other names are th e prope rt y of their respect ive owners

STM i croelectron ic s group of companies

Aus tralia - Brazil - Canada - Chi na - Finland - Fr ance - Germany - Hong Kong -

India - Israel - Italy - Japan - M al aysia - M a l t a - M orocco - Singapore - Spai n - S weden - Switzer l and - Un ited Kingdom - United States.