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M25P20
OPERATING FEATURE S
Page P rogramm i ng
To program one dat a byte, t wo i ns tructions ar e re-
quired: Write Enable (WREN), which is one byte,
and a Page Program (PP) sequence, which con-
sists of four bytes plus data. This is f ollowed by the
internal Program cycle (of duration tPP).
To spread this ove rhead, the Page P rogram (PP)
instruction allows up to 256 bytes to be pro-
grammed at a time (changing bits from 1 to 0), pro-
vided that they lie in consecutive addresses on the
same page of memory.
Sector Erase and Bul k Erase
The Page Program (PP) instruction allows bits to
be reset from 1 to 0. Before this can be applied, the
bytes of memo ry need to hav e been erased to a ll
1s (FFh). Thi s can be achieved either a s ector at a
time, using the Sector Erase (SE) instruction, or
throughout the entire memory, using the Bulk
Erase (BE) instruction. This starts an internal
Erase cycle (of duration tSE or tBE).
The Erase instruction must be preceeded by a
Write Enabl e (WREN) instruction.
Polling Duri ng a Wri te, Program or Erase Cycle
A further improvement in the time to Write Status
Register (WRSR), Program (PP) or Erase (SE or
BE) can be achieved by not waiting for the worst
case delay (tW, tPP, tSE, or tBE). The Write In
Progress (WIP) bit is provided in t he Status Regi s-
ter so that the application program can m onitor its
value, polling it to establish when the previous
Write cycle, Pro gram cycle or Erase cycle is com-
plete.
Active Power, St a nd - by Po wer an d De ep
Power-Down Modes
When Chip Select (S) is Low, the device is en-
abled, and in the Active Power mode.
When Chip Select (S) is High, the device is dis-
abled, but could remain in the Active Power mode
until all internal cycles hav e completed (P ro gram,
Erase, Write Status Register). The device then
goes in t o the Stand-by P ower mode. T he dev ice
consumpt i on drops to ICC1.
The Deep Power-down mode is entered when the
specific instruction (the Enter Deep Power-down
Mode (DP) instruction) is executed. The device
consump tio n drops further to ICC2. T he device re-
mains in this mode until another specific instruc-
tion (the Release from Deep Power-down Mode
and Read Electro nic Signature (RE S) instruction)
is executed.
All other instructions are igno red whil e the dev ice
is in the Deep Power-down mode. This can be
used as an ext ra soft ware protection mecha nism,
when the device is not in active use, to protect the
device from inadvertant Write, Program or Erase
instructions.
Status Register
The Status Register contains a number of status
and control bits, as shown in Table 5, that can be
read or set (as appropriate) by specific instruc-
tions.
WIP bit. The Writ e In Progress (WIP) bit indic ates
whether the memory is busy with a Write Status
Register, Program or Era se cycle.
WEL bit. The Write Enable Latch (WEL) bit indi-
cates the status of the int ernal Write Enable Latch.
BP1, BP0 b its. The Block Protect (BP1, BP0) bits
are non-volatile. They define the size of the area to
be software protected against Program and Erase
instructions.
SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in th e Hardware
Protected mode. In this mode, the non-v olati le bits
of t he Status Register (SRWD, BP1, BP0) become
read-only bits.