SY89855U Precision Low Power Differential LVPECL 4:1 MUX with 1:2 Fanout and Internal Termination General Description The SY89855U is a 2.5V/3.3V precision, high-speed, 4:1 differential multiplexer with 100K LVPECL (800mV) compatible outputs, capable of handling clocks up to 2.5GHz and data streams up to 2.5Gbps. In addition, a 1:2 fanout buffer provides two copies of the selected inputs. The differential input includes Micrel's unique, 3-pin input termination architecture that allows customers to interface to any differential signal (AC- or DC-coupled) as small as 100mV without any level shifting or termination resistor networks in the signal path. The result is a clean, stub-free, low-jitter interface solution. The outputs are 800mV LVPECL, (100K temperature compensated) with fast rise/fall times guaranteed to be less than 180ps. The SY89855U operates from a 2.5V 5% supply or a 3.3V 10% supply and is guaranteed over the full industrial temperature range of -40C to +85C. For applications that require higher performance, consider the SY58029U. The SY89855U is part of Micrel's highspeed, Precision Edge(R) product line. All support documentation can be found on Micrel's web site at www.micrel.com. Typical Performance (R) Precision Edge Features * * * * * * * * * * * * Select 1 of 4 differential inputs Provides two copies of the selected input Low power 260mW (VCC = 2.5V) Guaranteed AC performance over temperature and voltage: - DC-to->2.5Gbps data rate throughput - <410ps In-to-Q tpd - <180ps tr / tf times Ultra low-jitter design: - <10psPP total jitter (clock) - <1psRMS random jitter - <10psPP deterministic jitter - <0.7psRMS crosstalk-induced jitter Unique, patent-pending input design minimizes crosstalk Accepts an input signal as low as 100mV Unique patented input termination and VT pin accepts DC- and AC-coupled inputs (CML, LVPECL, LVDS) 800mV 100K LVPECL output swing Power supply 2.5V 5% or 3.3V 10% -40C to +85C temperature range Available in 32-pin (5mm x 5mm) QFN package Applications * * * * * Redundant clock and/or data distribution All SONET/OC-3 to OC-48 clock/data distribution Loopback All Fibre Channel applications All GigE applications Markets * * * * LAN/WAN communication Enterprise servers ATE Test and measurement Precision Edge is a registered trademark of Micrel, Inc. Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com August 2007 M9999-082907-C hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89855U Functional Block Diagram Truth Table SEL1 SEL0 Q 0 0 IN0 Input Select 0 1 IN1 Input Select 1 0 IN2 Input Select 1 1 IN3 Input Select August 2007 2 M9999-082907-C hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89855U Ordering Information(1) Package Type Part Number Operating Range Package Marking Lead Finish SY89855UMG QFN-32 Industrial SY89855U with Pb-Free bar-line indicator NiPdAu Pb-Free SY89855UMGTR(2) QFN-32 Industrial SY89855U with Pb-Free bar-line indicator NiPdAu Pb-Free Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only. 2. Tape and Reel. Pin Configuration 32-Pin QFN Pin Description Pin Number Pin Name Pin Function 1, 4 5, 8 25, 28 29, 32 IN0, /IN0, IN1, /IN1, IN2, /IN2, IN3, /IN3 Differential Input: Each pair accepts AC- or DC-coupled signals as small as 100mV. Each pin of a pair internally terminates to a VT pin through 50. Note that these inputs will default to an indeterminate state if left open. If an input is not used, connect one end of the differential pairs to ground through a 1k resistor, and leave the other end to VCC through an 825 resistor. Unused VT and VREF-AC pins may also be left floating. Please refer to the "Input Interface Applications" section for more details. 2, 6 26, 30 VT0, VT1 VT2, VT3 Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The VT pin provides a center-tap to the termination network for maximum interface flexibility. See "Input Interface Applications" section for more details. 15, 18 SEL0, SEL1 14, 19 NC 10, 13, 16 17, 20, 23 VCC 11, 12 21, 22 /Q0, Q0 /Q1, Q1 9, 24 GND, Exposed Pad Ground: Ground pins and exposed pad must be connected to the most negative potential of the chip. 3 7 27 31 VREF-AC0, VREF-AC1, VREF-AC2, VREF-AC3 Reference Voltage: This reference output is equivalent to VCC-1.2V. It is used for ACcoupled inputs. When interfacing to AC input signals, connect VREF-AC directly to the VT pin and bypass with a 0.01F low ESR capacitor to VCC. See "Input Interface Applications" section. Maximum sink/source current is 1.5mA. August 2007 This Single-Ended TTL/CMOS compatible input selects the inputs to the multiplexer. Note that this input is internally connected to a 25k pull-up resistor and will default to a logic HIGH state if left open. Input logic threshold is VCC/2. See "Truth Table" for select control. Not connected. Positive Power Supply: Bypass with 0.1F||0.01F low ESR capacitors placed as close as possible to each VCC pin. Differential Outputs: These 100K-compatible (internally temperature compensated) LVPECL output pairs are copies of the selected input. Unused output pins may be left floating. See "Output Interface" for terminating guidelines. 3 M9999-082907-C hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89855U Absolute Maximum Ratings(1) Operating Ratings(2) Supply Voltage (VCC) ............................-0.5V to +4.0V Input Voltage (VIN) ....................................-0.5V to VCC LVPECL Output Current (IOUT) Continuous................................................. 50mA Surge ....................................................... 100mA Termination Current Source or Sink Current on VT .................. 100mA Input Current Source or Sink Current on IN, /IN.............. 50mA Current (VREF-AC) Source or Sink Current on VREF-AC ............... 2mA Lead Temperature (soldering, 20sec.) ...............260C Storage Temperature (Ts) ................ -65C to +150C Supply Voltage (VCC) .....................+2.375V to +2.625V .....................................................+3.0V to +3.6V Ambient Temperature (TA)....................-40C to +85C Package Thermal Resistance(3) QFN (JA) Still-Air......................................................35C/W 500lfpm ....................................................28C/W QFN (JB) Junction-to-Board.....................................16C/W DC Electrical Characteristics(4) TA = -40C to +85C, unless otherwise noted. Symbol Parameter Condition Min Typ Max Units VCC Power Supply Voltage VCC = 2.5V VCC = 3.3V 2.375 3.0 2.5 3.3 2.625 3.6 V V ICC Power Supply Current No load, max. VCC. 65 85 mA RIN Input Resistance (IN-to-VT) 45 50 55 RDIFF_IN Differential Input Resistance (IN-to-/IN, /IN-to-VT) 90 100 110 VIH Input High Voltage (IN, /IN) VCC- 1.6 VCC V VIL Input Low Voltage (IN, /IN) 0 VIH- 0.1 V VIN Input Voltage Swing (IN-to-/IN) See Figure 1a. 0.1 1.7 V VDIFF_IN Differential Input Voltage Swing |IN - /IN | See Figure 1b. 0.2 VT_IN Maximum Input Voltage (IN-to-VT) VREF-AC Output Reference Voltage Note 5 VCC- 1.3 V VCC- 1.2 1.28 V VCC- 1.1 V Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. JA and JB values are determined for a 4-layer board in still-air, unless otherwise stated. 4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 5. VIH (min) not lower than 1.2V. August 2007 4 M9999-082907-C hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89855U LVPECL Output DC Electrical Characteristics(5) VCC = 2.5V 5% or 3.3V 10%; RL = 50 to VCC-2V; TA = -40C to +85C, unless otherwise noted. Symbol Parameter Condition Min Typ Max Units VOH Output High Voltage (Q, /Q) VCC-1.145 VCC-0.895 V VOL Output Low Voltage (Q, /Q) VCC-1.945 VCC-1.695 V VOUT Output Voltage Swing (Q, /Q) See Figure 1a. 400 800 mV VDIFF-OUT Differential Output Voltage Swing (Q, /Q) See Figure 1b. 800 1600 mV Min Typ LVTTL/CMOS DC Electrical Characteristics(5) VCC = 2.5V 5% or 3.3V 10%; TA = -40C to +85C, unless otherwise noted. Symbol Parameter VIH Input High Voltage Condition VIL Input Low Voltage IIH Input High Current VIN = VCC IIL Input Low Current VIN = 0.5V Max 2.0 Units V 0.8 V 75 A -300 A Notes: 5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. August 2007 5 M9999-082907-C hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89855U AC Electrical Characteristics(6) VCC = 2.5V 5% or 3.3V 10%; TA = -40C to + 85C, RL = 50 to VCC-2V, unless otherwise stated. Symbol Parameter Condition Min fMAX Maximum Operating Frequency NRZ Data 2.5 Gbps Clock, VOUT > 400mV 2.5 GHz VIN > 100mV 210 300 410 ps 100 300 500 ps tpd Typ Max Units Propagation Delay IN-to-Q SEL-to-Q tpd Tempco Differential Propagation Delay Temperature Coefficient tSKEW Output-to-Output Note 7 Part-to-Part Note 8 tJITTER 234 9 fs/C 20 ps 150 ps Data Random Jitter (RJ) Note 9 1 psRMS Deterministic Jitter (DJ) Note 10 10 psPP Clock tr, tf Cycle-to-Cycle Jitter Note 11 1 psRMS Total Jitter (TJ) Note 12 10 psPP Crosstalk-induced Jitter (Adjacent Channel) Note 13 0.7 psRMS Output Rise/Fall Time (20% to 80%) At full output swing. 180 ps 50 100 Notes: 6. High frequency AC electricals are guaranteed by design and characterization. 7. Output-to-output skew is measured between outputs under identical input conditions. 8. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs. 9. Random jitter is measured with a K28.7 character pattern, measured at <fMAX. 23 10. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2 -1 PRBS pattern. 11. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn - Tn-1 where T is the time between rising edges of the output signal. 12 12. Total jitter definition: with an ideal clock input of frequency <fMAX, no more than one output edge in 10 output edges will deviate by more than the specified peak-to-peak jitter value. 13. Crosstalk is measured at the output while applying two similar differential clock frequencies that are asynchronous with respect to each other at the inputs. August 2007 6 M9999-082907-C hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89855U Typical Operating Characteristics VCC = 2.5V, GND = 0, VIN = 100mV; TA = -40C to + 85C, RL = 50 to VCC-2V, unless otherwise stated. August 2007 7 M9999-082907-C hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89855U Functional Characteristics VCC = 3.3V 10%; TA = -40C to + 85C, RL = 50 to VCC-2V, unless otherwise stated. August 2007 8 M9999-082907-C hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89855U Single-Ended and Differential Swings Figure 1a. Single-Ended Voltage Swing Figure 1b. Differential Voltage Swing Timing Diagram IN-to-Q Timing Diagram SEL-to-Q Timing Diagram August 2007 9 M9999-082907-C hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89855U Input and Output Stages Figure 2b. PECL Output Stage Figure 2a. Simplified Differential Input Stage Input Interface Applications option: may connect VT to VCC Figure 3a. LVPECL Interface (DC-Coupled) Figure 3b. LVPECL Interface (AC-Coupled) Figure 3d. CML Interface (AC-Coupled) Figure 3e. LVDS Interface August 2007 10 Figure 3c. CML Interface (DC-Coupled) M9999-082907-C hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89855U Output Interface Applications LVPECL has high input impedance, very low output (open emitter) impedance, and small signal swing, which result in low EMI. LVPECL is ideal for driving 50 and 100 controlled impedance transmission lines. There are different techniques for terminating LVPECL outputs: parallel termination theveninequivalent, parallel termination (3-resistor), and ACcoupled termination. Unused output pairs may be left floating; however, single-ended outputs must be terminated or balanced. Note: Note: For a 2.5V system, R1 = 250, R2 = 62.5. 1. For a 2.5V system, Rb = 19. Figure 4a. Parallel Thevenin-Equivalent Termination Figure 4b. Parallel Termination (3-Resistor) Note: Note: For a 2.5V system, R = 50. For a 2.5V system, R1 = 250, R2 = 62.5 . Figure 4d. Parallel Thevenin-Equivalent Termination Figure 4c. AC-Coupled Termination Related Product and Support Documentation Part Number Function Data Sheet Link SY58029U Ultra Precision Differential LVPECL 4 :1 MUX with 1 :2 Fanout Internal Termination www.micrel.com/product-info/products/sy58029u.shtml. HBW Solutions New Products and Applications www.micrel.com/product-info/products/solutions.shtml August 2007 11 M9999-082907-C hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89855U Package Information 32-Pin QFN PCB Thermal Consideration for 32-Pin QFN Package (Always solder, or equivalent, the exposed pad to the PCB) Packages Notes: August 2007 1. Package meets Level 2 Moisture Sensitivity Classification. 2. All parts are dry-packed before shipment. 3. Exposed pads must be soldered to a ground for proper thermal management. 12 M9999-082907-C hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89855U MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2005 Micrel, Incorporated. August 2007 13 M9999-082907-C hbwhelp@micrel.com or (408) 955-1690