CPC7584 Line Card Access Switch Description * Small 16-pin SOIC or micro-leadframe package * Micro-leadframe package (MLP) printed circuit board footprint is 70% smaller than 4TH generation EMRs and 60% smaller than SOIC version * Monolithic IC reliability * Low matched RON * Eliminates the need for zero cross switching * Flexible switch timing to transition from ringing mode to talk mode. * Clean, bounce free switching * Tertiary protection consisting of integrated current limiting, voltage clamping, and thermal shutdown for SLIC protection * 5V operation with power consumption < 10 mW * Intelligent battery monitor * Latched logic level inputs, no external drive circuitry required The CPC7584 is a monolithic solid state switch in a 16-pin SOIC or MLP surface mount package. It provides the necessary functions to replace two 2-Form-C electro-mechanical relays on traditional analog and integrated voice and data (IVD) line cards found in Central Office, Access, and PBX equipment. The device contains solid state switches for tip and ring line break, ringing injection/ringing return and channel test access. The CPC7584 requires only a +5V supply and offers "break-before-make" or "make-before-break" switch operation using simple logic-level input control. The CPC7584xC logic differs from the CPC7584xA/B with an enhancement permitting channel monitoring in the test state. See "Functional Description" on page 9 for more information. The CPC7584xC also has a higher trigger and hold current for the protection SCR. Specify CPC7584Bx for SOIC or specify CPC7582Mx for MLP devices shipped in tubes. Append the part number with the suffix TR for tape and reel packaging. im in ar y Features Applications el Central office (CO) Digital Loop Carrier (DLC) PBX Systems Digitally Added Main Line (DAML) Hybrid Fiber Coax (HFC) Fiber in the Loop (FITL) Pair Gain System Channel Banks Ordering Information Part Number CPC7584xA CPC7584xB CPC7584xC Pr * * * * * * * * Description With protection SCR Without protection SCR With protection SCR and "Monitor" test state Figure 1. CPC7584 Block Diagram TTEST (TCHANTEST) +5 Vdc 8 TRINGING 6 VDD 1 CPC7584 Tip TLINE 4 X SW3 X SW5 3 TBAT X SW1 Ring Secondary Protection SLIC SW2 RLINE 13 X SW4 VBAT 12 RRINGING RINGING 14 RBAT X X SW6 16 SCR and Trip Circuit 2 FGND VREF 15 8 DGND 300 (min.) L A T C H Switch Control Logic 9 10 11 INTEST INRINGING LATCH 7 TSD VBAT RTEST (RCHANTEST) DS-CPC7584 - R0B www.clare.com 1 CPC7584 ar y 1. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Absolute Maximum Ratings (at 25 C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Electrical Characteristics, TA = -40 C to +85 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.1 Power Supply Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.2 Break Switches, SW1 and SW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.3 Ringing Return Switch, SW3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.4 Ringing Switch, SW4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.5 Test Switches, SW5 and SW6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Digital Input Characteristics - INTEST,INRINGING and LATCH Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 Power Consumption Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7 Thermal Shutdown Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8 Protection Circuitry Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.9 Truth Table - CPC7584xA/B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.10 Truth Table - CPC7584xC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pr el im in 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Switch Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 Make-Before-Break Operation (Ringing to Talk Transition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Break-Before-Make Operation (Ringing to Talk Transition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3 Alternate Break-Before-Make Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Ring Access Switch Zero-Cross Current Turn Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Battery Voltage Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.1 Diode Bridge/SCR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.2 Current Limiting function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 Temperature Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8 External Protection Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.9 Data Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3. Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Mechanical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2 MLP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Printed-Circuit Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 MLP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Tape and Reel Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 Moisture Reflow Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Washing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 www.clare.com 3 3 3 4 4 4 4 5 6 6 7 7 8 8 9 9 10 10 10 11 11 11 12 12 12 12 12 12 12 13 13 14 14 14 14 15 15 15 15 15 15 15 16 16 R0B CPC7584 1. Specifications 1.1 Package Pinout 1.2 Pinout CPC7584 FGND 2 15 VBAT TBAT 3 14 RBAT TLINE 4 13 RLINE 12 RRINGING VDD 6 11 LATCH TSD 7 10 INRINGING DGND 8 9 INTEST Connect to Tip lead of test bus 2 FGND Fault ground 3 TBAT Connect to tip lead of SLIC 4 TLINE Connect to tip lead of the line (drop) 7 el Pr Rev. B TTEST 6 im TRINGING 5 1 5 Description TRINGING Connect to ringing generator return ar y 16 RTEST Name in TTEST 1 Pin VDD +5 V supply TSD Temperature shutdown indicator pin. Bi-directional I/O with internal pull up to VDD. Output function indicates status of thermal shutdown circuitry, Input function can be used to set the "All-Off" mode using an open-drain type output. 8 DGND Digital ground 9 INTEST Logic-level switch control input 10 INRINGING Logic-level switch control input Data latch control, active high, transparent low 11 LATCH 12 RRINGING Connect to ringing generator current limiting resistor 13 RLINE Connect to ring lead of the line (drop) 14 RBAT Connect to ring lead of the SLIC 15 VBAT Connect to ring lead of SLIC 16 RTEST Battery voltage supply. Must be capable of sourcing the trigger current for proper operation of the protection SCR. www.clare.com 3 CPC7584 1.3 Absolute Maximum Ratings (at 25 C) Parameter Minimum Maximum Absolute maximum ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at conditions beyond those indicated in the operational sections of this data sheet is not implied. Unit Operating temperature -40 +110 C Storage temperature -40 +150 C Operating relative humidity 5 95 % Pin soldering temperature (10 seconds max) - +260 C -0.3 7 V VDD +4.5 +5.0 +5.5 V - -85 V VBAT1 -19 - -72 V -0.3 VDD+0.3 V 1V Logic input to switch output isolation - 330 V Switch isolation (SW1, SW2, SW3, SW5, SW6) - 330 V Switch Isolation (SW4) - 465 V Battery Supply Minimum Typical Maximum Unit BAT is used only for internal protection circuitry. If VBAT rises above -10 V, the device will enter and remain in the all-off state until the battery exceeds -15 V. ESD Rating (Human Body Model) 1000 V in Logic input voltage Supply ar y +5 V power supply 1.4.1 Power Supply Specifications el im 1.4 Electrical Characteristics, TA = -40 C to +85 C Unless otherwise specified: Minimum and maximum values are production testing requirements. Typical values are provided for information purposes only and are not part of the testing requirements. They are characteristic of the device and are the result of engineering evaluations. VDD = +5Vdc and VBAT = -48Vdc Parameter Pr 1.4.2 Break Switches, SW1 and SW2 Conditions Symbol Minimum Typical Maximum Unit 1 A VSW1 = TLINE to TBAT VSW2 = RLINE to RBAT Open Contact Isolation Off-state leakage current VSW = -320V to GND VSW = +260 V to -60 V +25C VSW = -330V to GND VSW = +270 V to -60 V +85C VSW = -310 V to GND VSW = +250 V to -60 V -40C 0.1 ISW ISW = 10 mA, 40 mA, TBAT = -2 V +85C ISW = 10 mA, 40 mA, TBAT = -2 V Switch Resistance Matching DC Current Limit 4 RON -40C Per On Resistance test conditions above. Magnitude RON SW1 - RON SW2 VSW (on) = 10 V +25C VSW (on) = 10 V +85C VSW (on) = 10 V -40C 0.3 0.1 ISW = 10 mA, 40 mA, TBAT = -2 V +25C On Resistance - RON ILIM www.clare.com - 14.5 - - 20.5 28 - 10.5 - - 0.15 0.8 - 300 - 80 160 - - 400 425 mA Rev. B CPC7584 Dynamic Current Limit (t = <0.5 s) Contacts to Input Isolation Conditions Symbol Minimum Typical Maximum Unit Break switches on, all other switches off, apply 1 kV 10/1000 s pulse to Tip/Ring interface with appropriate protection in place. ISW - 2.5 - A 1 A VSW (TLINE, RLINE) = 320 V logic inputs = GND +25C VSW (TLINE, RLINE) = 330 V logic inputs = GND +85C VSW (TLINE, RLINE) = 310 V, logic inputs = GND -40C Applied voltage = 100 V p-p square wave at 100 Hz dv/dt sensitivity Parameter Conditions VSW = -320V to GND VSW = +260 V to -60 V im +85C VSW = -310 V to GND VSW = +250 V to -60 V -40C ISW (on) = 0 mA, 10 mA +25C ISW (on) = 0 mA, 10 mA +85C ISW (on) = 0 mA, 10 mA el DC Current Limit Dynamic current limit (t = <0.5 s) Contacts to Input Isolation dv/dt sensitivity Rev. B - 0.3 - 200 - V/s Minimum Typical Maximum Unit 1 A +25C VSW = -330 V to GND VSW = +270 V to -60 V 0.1 ISW - 0.3 0.1 60 - 85 100 -40C 45 - VSW (on) = 10 V +25C 135 VSW (on) = 10 V +85C VSW (on) = 10 V -40C Pr On Resistance - 0.1 Symbol VSW3 = TLINE to TRINGING Open Contact Isolation Off-state leakage current ISW in 1.4.3 Ringing Return Switch, SW3 0.1 ar y Parameter Ringing switches on, all other switches off, apply 1 kV 10/1000 s pulse to Tip/Ring interface with appropriate protection in place. VSW (TLINE, TRINGING) = 320 V logic inputs = GND +25C VSW (TLINE, TRINGING) = 330 V logic inputs = GND +85C VSW (TLINE, TRINGING) = 310 V logic inputs = GND -40C Applied voltage = 100 V p-p square wave at 100 Hz RON ISW - - 85 - mA - A 1 A - V/s 210 ISW - 2.5 0.1 ISW - 0.3 0.1 - www.clare.com - 200 5 CPC7584 1.4.4 Ringing Switch, SW4 Parameter Conditions Symbol Minimum Typical Maximum Unit 1 A VSW4 = RLINE to RRINGING +25C VSW = -270 V to +210 V VSW = +270 V to -210 V +85C VSW = -245 V to +210 V VSW = +245 V to -210 V -40C On Voltage ISW (on) = 1 mA On Resistance ISW (on) = 70 mA, 80 mA Surge current* Ringing switches on. Release current Remove ringing mode, SW4 on. VSW (RLINE, RRINGING) = 320 V logic inputs = GND +25C VSW (RLINE, RRINGING) = 330 V logic inputs = GND +85C VSW (RLINE, RRINGING) = 310 V logic inputs = GND -40C Pr Contacts to Inout Isolation el im Ringing switches on. dv/dt sensitivity ISW - 0.1 0.05 VSW - 1.5 3 V RON - 8.5 12 IRINGING - 0.1 0.25 mA - - - 2 A - - - 2 A ISW - 300 - A 1 A in Ringing generator current Ringing switches on. to ground On steady-state current* 0.05 ar y Open Contact Isolation Off-state leakage current VSW = -255 V to +210 V VSW = +255 V to -210 V Applied voltage = 100 V p-p square wave at 100 Hz 0.05 ISW - 0.1 0.05 - - 200 - V/s Symbol Minimum Typical Maximum Unit 1 A * Secondary protection and ringing source current limiting must prevent exceeding these parameters. 1.4.5 Test Switches, SW5 and SW6 Parameter Conditions VSW5 = TTEST to TBAT VSW6 = RTEST to RBAT Open Contact Isolation Off-state leakage current 6 VSW = -320 V to GND VSW = +260 V to -60 V +25C VSW = -330 V to GND VSW =+270 V to -60 V +85C VSW = -310 V to GND VSW = +250 V to -60 V -40C 0.1 ISW www.clare.com - 0.3 0.1 Rev. B CPC7584 Parameter Conditions Symbol Minimum Typical Maximum 38 - 46 70 28 - - 175 - 80 110 - - 210 250 TLINE = 10 mA, 40 mA, TBAT = -2 V +25C TLINE = 10 mA, 40 mA, TBAT = -2 V +85C On Resistance RON - TLINE = 10 mA, 40 mA, TBAT = -2 V -40C Dynamic current limit (t = <0.5 s) +25C VSW (on) = 10 V +85C VSW (on) = 10 V -40C Test switches on , ringing access switches off, apply 1 kV at 10/1000 s pulse, with appropriate secondary protection in place. VSW (TTEST, RTEST) = 320 V logic inputs = GND VSW (TTEST, RTEST) = 330 V logic inputs = GND +85C VSW (TTEST, RTEST) = 310 V logic inputs = GND - im 2.5 mA - A 1 A 0.1 ISW - -40C Applied voltage = 100 V p-p square wave at 100 Hz - 0.3 0.1 - 200 - V/s Symbol Minimum Typical Maximum Unit Logic low VIL - - 1.5 Logic high VIH 3.5 - - VDD = 5.5 V, VBAT = -75 V, VIH = 5 V IIH - 0.1 1 VDD = 5.5 V, VBAT = -75 V, VIL = 0 V IIL - 0.1 1 Symbol Minimum Typical Maximum - 1.1 2.0 - 1.3 2.0 IBAT - 0.1 10 5.5 10 P - el dv/dt sensitivity ISW in Contacts to Input Isolation +25C ISW ar y DC Current Limit VSW (on) = 10 V Unit Parameter Input Threshold Pr 1.5 Digital Input Characteristics - INTEST,INRINGING and LATCH Pins Input Leakage Current Conditions V A 1.6 Power Consumption Characteristics Parameter VDD Current Consumption Conditions VDD = 5 V, VBAT = -48V, Talk or All-Off states. VDD = 5 V, VBAT = -48 V, Ringing or Test states. V = 5 V, VBAT = -48 V, VBAT Current Consumption DD Any state Power Consumption Rev. B VDD = 5 V, VBAT = -48 V, Talk or All-Off states. VDD = 5 V, VBAT = -48 V, Ringing or Test states. IDD mA A mW 6.5 www.clare.com Unit 10 7 CPC7584 1.7 Thermal Shutdown Characteristics Parameter Conditions Symbol Minimum Typical Maximum Unit Activation Temperature TSD => Low T 110 125 150 C Hysteresis TSD => High T 10 - 25 C Symbol Minimum Typical Maximum Unit 1.8 Protection Circuitry Electrical Specifications Parameter Conditions Voltage drop at continuous Apply dc current limit of break switches current (50/60 Hz) Voltage drop at surge current Apply dynamic current limit of break switches Parameters Related to the Protection SCR - +25C Trigger current +85C +85C IGATE = ITrigger ** Reverse leakage current VBAT = -48V el Gate trigger voltage On-state voltage im +25C Hold current 0.5 A, t = 0.5 ms 2.0 A, t = 0.5 ms VF - VF - - - in Surge current ar y Parameters Related to the Diodes in the Diode Bridge ITRIG - 2.1 3 V 5 - - * A - mA - mA 60 35 - 100 60 70 VTBAT or VRBAT VBAT -4 - VBAT -2 V IVBAT - - 1.0 A VTBAT or VRBAT - - V IHOLD -3 -5 Pr *Passes GR1089 and ITU-T K.20 with appropriate protection in place. ** VBAT must be capable of sourcing ITRIGGER for the internal SCR to activate. 8 www.clare.com Rev. B CPC7584 1.9 Truth Table - CPC7584xA/B INRINGING INTest Talk 0 0 Ringing 1 0 Test 0 1 State LATCH 0 All Off 1 1 Latched X X 1 All off X X X 1 TSD 1 Break Switches Ringing Switches Test Switches On Off Off Off On Off Off Off On Off Off Off 1 or Floating Unchanged Unchanged Unchanged 0 Off Off Off 1.10 Truth Table - CPC7584xC INTest Talk 0 0 Ringing 1 0 0 1 Latched X All off X 1 0 1 im Test / Monitor All Off LATCH Break Switches Ringing Switches Test Switches On Off Off Off On Off On Off On Off Off Off TSD 1 in INRINGING State ar y If TSD = 5V, thermal shutdown is disabled. If TSD is left floating, the thermal shutdown mechanism is enabled. 1 or Floating 1 X 1 X X Unchanged Unchanged Unchanged 0 Off Off Off Pr el If TSD = 5V, thermal shutdown is disabled. If TSD is left floating, the thermal shutdown mechanism is enabled. Rev. B www.clare.com 9 CPC7584 2. Functional Description im The CPC7584xC replaces the Test state with the Test/Monitor state as defined below. el * Test/Monitor. Line break switches SW1 and SW2 closed, ringing switches SW3 and SW4 open, and test-in switches SW5 and SW6 closed. Pr The CPC7584 offers break-before-make and make-before-break switching with simple logic-level input control. Solid-state switch construction means no impulse noise is generated when switching during ring cadence or ring trip, eliminating the need for external zero-cross switching circuitry. State-control is via logic-level input so no additional driver circuitry is required. The line break switches SW1 and SW2 are linear switches that have exceptionally low RDSON and excellent matching characteristics. The ringing access switch SW4 has a breakdown voltage rating of greater than 480 V. This is sufficiently high, with proper protection, to prevent breakdown in the presence of a transient fault condition (i.e., passing the transient on to the ring generator). Integrated into the CPC7584 is a diode bridge/SCR clamping circuit, current limiting, and a thermal shutdown mechanism to provide protection to the SLIC device during a fault condition. Positive and negative surges are reduced by the current limiting circuitry and steered to ground via diodes and the integrated SCR. Power-cross transients are also reduced by the current limiting and thermal shutdown circuits. Note that only the CPC7584xA and CPC7584xC parts include the integrated protection SCR. 10 The CPC7584 operates from a +5 V supply only. This gives the device extremely low idle and active power dissipation and allows use with virtually any range of battery voltage. A battery voltage is also used by the CPC7584 as a reference for the integrated protection circuit. In the event of a loss of battery voltage, the CPC7584 enters the all-off state. in * Talk. Line break switches SW1 and SW2 closed, ringing switches SW3 and SW4 open, and test switches SW5 and SW6 open. * Ringing. Line break switches SW1 and SW2 open, ringing switches SW3 and SW4 closed, and test-in switches SW5 and SW6 open. * Test. Line break switches SW1 and SW2 open, ringing switches SW3 and SW4 open, and test-in switches SW5 and SW6 closed. * All off. Line break switches SW1 and SW2 open, ringing switches SW3 and SW4 open, and loop test switches SW5 and SW6 open. To protect the CPC7584 from an overvoltage fault condition, use of a secondary protector is required. The secondary protector must limit the voltage seen at the tip and ring terminals to a level below the maximum breakdown voltage of the switches. To minimize the stress on the solid-state contacts, use of a foldback or crowbar type secondary protector is recommended. With proper selection of the secondary protector, a line card using the CPC7582BC will meet all relevant ITU, LSSGR, FCC and UL protection requirements. ar y 2.1 Introduction The CPC7584xA/B has four states: 2.2 Switch Timing The CPC7584 provides, when switching from the ringing state to the idle/talk state, the ability to control the release timing of the ringing access switches SW3 and SW4 relative to the state of the line break switches SW1 and SW2 using simple logic-level input. This is referred to a make-before-break or break-before-make operation. When the line break switch contacts (SW1 and SW2) are closed (or made) before the ringing access switch contacts (SW3 and SW4) are opened (or broken), this is referred to make-before-break operation. Break-before-make operation occurs when the ringing access contacts (SW3 and SW4) are opened (broken) before the line break switch contacts (SW1 and SW2) are closed (made). With the CPC7584, the make-before-break and break-before-make operations can easily be selected by applying logic-level inputs to pins 9 and 10 (INRING and INTEST-IN) of the device. The logic sequences for either mode of operation are given in "Make-Before-Break Operation (Ringing to Talk Transition)" on page 11 and "Break-Before-Make Operation (Ringing to Talk Transition)" on page 11. Logic states and explanations are given in "Truth Table - CPC7584xA/B" on page 9. Break-before-make operation can also be achieved using pin 7 (TSD) as an input. In "Break-Before-Make Operation (Ringing to Talk Transition)" on page 11 lines 2 and 3, it is possible to induce the switches to the all-off state by grounding pin 7 (TSD) instead of www.clare.com Rev. B CPC7584 Setting TSD to +5 V allows switch control using the logic pins 9 and 10. This setting, however, also disables the thermal shutdown circuit and is therefore not recommended. When using logic controls via the input pins 9 and 10, pin 7 (TSD) should be allowed to float. As a result, the two recommended states when using pin 7 (TSD) as a control are 0, which forces the device to the all-off state, or float, which allows logic inputs to pins 9 and 10 to remain active. This may require the use of an open-collector buffer. apply logic input to the pins. This has the effect of overriding the logic inputs and forcing the device to the all-off state. Hold this input state for 25 ms. During this hold period, toggle the inputs from the ringing state (10) to the idle/talk state (00). After the 25 ms, release pin 7 (TSD) to return the switch control to the input pins 9 and 10 and reset the device to the idle/talk state. ar y 2.2.1 Make-Before-Break Operation (Ringing to Talk Transition) Break Switches Ringing Return Switch (SW3) Ringing Switch (SW4) Test Switches Open Closed Closed Open State INRINGING INTEST TSD Timing Ringing 1 0 Floating - Closed Open Closed Open Closed Open Open Open Ringing Return Switch (SW3) Ringing Switch (SW4) Test Switches Closed Open 0 0 Talk 0 0 Floating im in Makebeforebreak SW4 waiting for next zero-current crossing to turn off. Maximum time is one-half of ringing. In this transition state, current that is Floating limited to the dc break switch current limit value will be sourced from the ring node of the SLIC. Zero-cross current has occurred TSD Timing Break Switches 0 Floating - Open Closed 1 Hold this state for at least 25 ms. SW4 Floating waiting for zero current to turn off. SW4 has opened. Open Open Floating Closed INRINGING INTEST Ringing 1 Talk 1 0 Pr State All-off el 2.2.2 Break-Before-Make Operation (Ringing to Talk Transition) 0 Close Break Switches Closed Open Open Open Open Open 2.2.3 Alternate Break-Before-Make Operation Break-before-make operation can also be achieved using TSD as an input. In lines 2 and 3 of "Break-Before-Make Operation (Ringing to Talk Transition)" on page 11, instead of using the logic input pins to force the all-off state, force TSD to ground. This overrides the logic inputs and also forces the all off state. Hold this state for 25 ms. During this 25 ms all-off state, toggle the inputs from the ringing state (Ring = 5 V, Test-In = 0 V) to the idle/talk state (Ring = 0 V, Test-In=0 V). After 25 ms, release TSD to return switch control to the input pins which will set the idle talk state. logic input pins. However, setting TSD to +5 V also disables the thermal shutdown mechanism. This is not recommended. Therefore, to allow switch control via the logic input pins, allow TSD to float. When using TSD as an input, the two recommended states are 0 (overrides logic input pins and forces all off state) and float (allows switch control via logic input pins and the thermal shutdown mechanism is active). This may require use of an open-collector buffer. When using the CPC7584 in this mode, forcing TSD to ground overrides the input pins and force an all off state. Setting TSD to +5 V allows switch control via the Rev. B www.clare.com 11 CPC7584 positive transient condition, the fault current is conducted through the diode bridge to ground. Voltage is clamped to the diode drop above ground. During a negative transient of 2 to 4 V more negative than the battery, the SCR conducts and faults are shunted to ground via the SCR and diode bridge. ar y In order for the SCR to crowbar or foldback, the on voltage (see "Protection Circuitry Electrical Specifications" on page 8) of the SCR must be less negative than the battery reference voltage. If the battery voltage is less negative the SCR on voltage, the SCR will not crowbar, however it will conduct fault currents to ground. For power induction or power-cross fault conditions, the positive cycle of the transient is clamped to the diode drop above ground and the fault current directed to ground. The negative cycle of the transient will cause the SCR to conduct when the voltage exceeds the battery reference voltage by two to four volts, steering the current to ground. in 2.3 Ring Access Switch Zero-Cross Current Turn Off After the application of a logic input to turn SW4 off, the ring access switch is designed to delay the change in state until the next zero-crossing. Once on, the switch requires a zero-current cross to turn off, and therefore should not be used to switch a pure DC signal. The switch will remain in the on state no matter what logic input until the next zero crossing. For proper operation, pin 12 (RRING) should be connected using proper impedance to a ring generator or other AC source. These switching characteristics will reduce and possibly eliminate overall system impulse noise normally associated with ringing access switches. The attributes of ringing access switch SW4 may make it possible to eliminate the need for a zero-cross switching scheme. A minimum impedance of 300 in series with the ring generator is recommended. im 2.4 Power Supplies Both a +5 V supply and battery voltage are connected to the CPC7584. CPC7584 switch state control is powered exclusively by the +5 V supply. As a result, the CPC7584 exhibits extremely low power dissipation during both active and idle states. Pr el The battery voltage is not used for switch control but rather as a reference for the integrated secondary protection circuitry. The integrated SCR is designed to trigger when pin 3 (TBAT) or pin 14 (RBAT) drops 2 to 4 V below the battery. This trigger prevents a fault induced overvoltage event at the TBAT or RBAT nodes. 2.5 Battery Voltage Monitor The CPC7584 also uses the voltage reference to monitor battery voltage. If battery voltage is lost, the CPC7582BC immediately enters the all-off state. It remains in this state until the battery voltage is restored. The device also enters the all-off state if the battery voltage rises above -10 V and remains in the all-off state until the battery voltage drops below -15 V. This battery monitor feature draws a small current from the battery (less than 1 mA typical) and will add slightly to the device's overall power dissipation. 2.6 Protection 2.6.1 Diode Bridge/SCR The CPC7584 uses a combination of current limited break switches, a diode bridge/SCR clamping circuit, and a thermal shutdown mechanism to protect the SLIC device or other associated circuitry from damage during line transient events such as lightning. During a 12 2.6.2 Current Limiting function If a lightning strike transient occurs when the device in the talk/idle state, the current is passed along the line to the integrated protection circuitry and limited by the dynamic current limit response of break switches SW1 and SW2. When a 1000V 10/1000 pulse (LSSGR lightning) is applied to the line though a properly clamped external protector, the current seen at pins 2 (TBAT) and pin 15 (RBAT) will be a pulse with a typical magnitude of 2.5 A and a duration of less than 0.5 ms. If a power-cross fault occurs with the device in the talk/idle state, the current is passed though break switches SW1 and SW2 on to the integrated protection circuit and is limited by the dynamic DC current limit response of the two break switches. The DC current limit, specified over temperature, is between 80 mA and 425 mA, and the circuitry has a negative temperature coefficient. As a result, if the device is subjected to extended heating due to power cross fault, the measured current at pin 2 (TBAT) and pin 15 (RBAT) will decrease as the device temperature increases. If the device temperature rises sufficiently, the temperature shutdown mechanism will activate and the device will default to the all-off state. 2.7 Temperature Shutdown The thermal shutdown mechanism will activate when the device temperature reaches a minimum of 110 C, placing the device in the all-off state regardless of logic input. During thermal shutdown mode, pin 7 (TSD) will read 0 V. Normal output of TSD is +VDD. www.clare.com Rev. B CPC7584 ar y switches will remain in the position they were in when the LATCH changed from logic 0 to logic 1 and will not respond to changes in input as long as the latch is at logic 1. The TSD input is not tied to the data latch. Therefore, TSD is not affected by the LATCH input and the TSD input will override state control via pin 10 (INRING) and pin 9 (INTEST-IN) and the LATCH. im in If presented with a short duration transient such as a lightning event, the thermal shutdown feature will typically not activate. But in an extended power-cross transient, the device temperature will rise and the thermal shutdown will activate forcing the switches to the all-off state. At this point the current measured at pin 3 (TBAT) and pin 14 (RBAT) will drop to zero. Once the device enters thermal shutdown it will remain in the all-off state until the temperature of the device drops below the activation level of the thermal shutdown circuit. This will return the device to the state prior to thermal shutdown. If the transient has not passed, current will flow at the value allowed by the dynamic DC current limiting of the switches and heating will begin again, reactivating the thermal shutdown mechanism. This cycle of entering and exiting the thermal shutdown mode will continue as long as the fault condition persists. If the magnitude of the fault condition is great enough, the external secondary protector could activate and shunt all current to ground. The thermal shutdown mechanism of the CPC7584 can be disable by applying +VDD to pin 7 (TSD). Pr el 2.8 External Protection Elements The CPC7584 requires only one overvoltage secondary protector on the loop side of the device. The integrated protection feature described above negates the need for protection on the line side. The secondary protector limits voltage transients to levels that do not exceed the breakdown voltage or input-output isolation barrier of the CPC7584. A foldback or crowbar type protector is recommended to minimize stresses on the device. Consult Clare's application note, AN-100, "Designing Surge and Power Fault Protection Circuits for Solid State Subscriber Line Interfaces" for equations related to the specifications of external secondary protectors, fused resistors and PTCs. 2.9 Data Latch The CPC7584 has an integrated data latch. The latch operation is controlled by logic-level input pin 11 (LATCH). The data input of the latch is pin 10 (INRING) and pin 9 (INTEST-IN) of the device while the output of the data latch is an internal node used for state control. When LATCH control pin is at logic 0, the data latch is transparent and data control signals flow directly through to state control. A change in input will be reflected in a change is switch state. When LATCH control pin is at logic 1, the data latch is active and a change in input control will not affect switch state. The Rev. B www.clare.com 13 CPC7584 3. Manufacturing Information 3.1 Mechanical Dimensions 3.1.1 SOIC 16 Pin SOIC (JEDEC Package) 10.11 MIN / 10.31 MAX (.398 MIN / .406 MAX) 1.27 (.050) 0.23 MIN / 0.32 MAX (.0091 MIN / .0125 MAX) 2.44 MIN / 2.64 MAX (.096 MIN / .104 MAX) 10.11 MIN / 10.51 MAX (.398 MIN / .414 MAX) ar y 7.40 MIN / 7.60 MAX (.291 MIN / .299 MAX) 0.51 MIN / 1.01 MAX (.020 MIN / .040 MAX) in 0.36 MIN / 0.46 MAX (.014 MIN / .018 MAX) 3.1.2 MLP im 7 el INDEX AREA 6 Pr TOP VIEW 0.2 0.80 (0.10) SEATING PLANE SIDE VIEW 0.23 0.55 0.02 (+0.05, -0) 1 0.33 (+0.07, -0.05) 2 EXPOSED PAD 0.55 4.0 (0.05) 0.55 (0.1) 16 6.0 (0.05) 0.80 Terminal Tip BOTTOM VIEW Dimensions in mm 14 www.clare.com Rev. B CPC7584 3.2 Printed-Circuit Board Layout 3.2.2 MLP 5.75 3.2.1 SOIC 0.75 on center 0.65 PC Board Pattern (Top View) 0.38 1.270 (.050) 5.35 on center 6.1 Detail A 9.728 .051 (.383 .002) ar y 1.193 (.047) 6.13 Detail A .787 (.031) All dimensions in mm Not drawn to scale 0.66 0.47 0.65 in 0.38 im 3.3 Tape and Reel Packaging 3.3.1 SOIC A0 3.00 el 6.50 2.00 B0 6.80 1.30 Pr R = .50 K1 16.00 K0 2.30 2.70 7.50 12.00 4.00 2.00 1.50 A0 = 6.5 mm B0 = 10.3 mm 2.3 mm 2.7 mm K0 = K1 = NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS AND CARRY TOLERANCES OF EIA STANDARD 481-2. 2. THE TAPE COMPLIES WITH ALL "NOTES" FOR CONSTANT DIMENSIONS LISTED ON PAGE 5 OF EIA-481-2. 3.4 Soldering 3.4.1 Moisture Reflow Sensitivity Clare has characterized the moisture reflow sensitivity of LCAS products using IPC/JEDEC standard J-STD-020A. Moisture uptake from atmospheric humidity occurs by diffusion. During the solder reflow Rev. B process, in which the component is attached to the PCB, the whole body of the component is exposed to high process temperatures. The combination of moisture uptake and high reflow soldering www.clare.com 15 temperatures may lead to moisture induced delamination and cracking of the component. To prevent this, this component must be handled in accordance with IPC/JEDEC standard J-STD-020A per the labeled moisture sensitivity level (MSL), level 1 for the SOIC package, and level 2 for the MLP package. Pr el im 3.5 Washing Clare does not recommend ultrasonic cleaning of LCAS parts. in The maximum ramp rates, dwell times, and temperatures of the assembly reflow profile should not exceed those specified in IPC/JEDEC standard J-STD-020A, which were used to determine the moisture sensitivity level of this component. ar y 3.4.2 Reflow Profile For additional information please visit www.clare.com Clare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed or implied. Except as set forth in Clare's Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty relating to its products, including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of Clare's product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice. Specifications: DS-CPC7584 - R0B (c) Copyright 2004, Clare, Inc. All rights reserved. Printed in USA. 1/23/2004