R1243x Series
30 V Input 2 A Buck DC/DC Converter
NO.EA-206-170608
1
OUTLINE
The R1243x is a CMOS-based step-down DC/DC converter with internal Nch high-side Tr. (0.175 Ω), which
can provide the maximum 2 A output current. Internally, the R1243x consists of an oscillator, a PW M control
circuit, a reference voltage unit, an error amplifier, phase compensation circuits, a slope circuit, a soft-start
circuit, protection circuits, internal voltage regulators and a switch for bootstrap circuit. A step-down DC/DC
converter can be confi gured by only adding an inductor, resistors, a diode and capacitors to the R1243x .
The R1243x is a current mode operating type DC/DC converter that does not require external current sense
resistor. It has high-speed response time and is high efficiency and compatible wit h cera m i c capacitors.
The oscillator frequency of the R1243x001A/B/E is fixed to 1000 kHz. The oscillator frequency of the
R1243x001C/D is fixed 330 kHz.
The R1243x has a cycle-by-cycle peak current limit function, a short protection function, a thermal shutdown
function and an UVLO as protection features. The R1243x001A/C/E has a latch protection with 2 ms delay
time, the R1243x001B/D has a fold-back protection that keep operating during short condition with lower
operating frequency and limiting the LX current. The R1243x has a built-in soft-start time (Typ. 0.4 ms). In
addition to this, t he soft-st art time is adjustable by addi ng an external capacit or. The R1243x has the FLG pin,
which mainly monitors the FB pin voltage and gives a flag output by the Nch open drain if the abnormal
condition is detected.
The R1243x is offered in 8-pin HSOP-8E and 10-pin DFN(PLP)2527-10 packages that can achieve high
density mount ing.
FEATURES
• Operating Voltage Range ...................................... 4.5 V to 30 V
• Standby Current .................................................... Max. 10 µA (VIN = 30 V, CE = L)
• Supply Current ....................................................... Typ. 0.7 mA (VIN = 30 V, VFB = 1.0 V)
• Output Voltage Range ........................................... 0.8 V to 18 V, Adjustable with ext ernal resistors
• Feedback Voltage .................................................. 0.5 V with 1.4% accuracy
• Output Current ....................................................... Max. 2 A(1)
• Peak Current Limiting ............................................ Typ. 3.8 A
• Internal Nch MOSFE T Driver ................................. Typ. 175 mΩ
• Maximum Duty Cycle ............................................. Min. 85%
• Oscillator Frequency .............................................. R1243x001A/B/E: 1000 kHz, R1243x001C/D: 330 kHz
• Latch Type Protection ............................................ R1243x001A/C: Typ. 2 ms, R1243x001E: 0.08 ms
• Fold-back Type Protection ..................................... R1243x001B: 250 kHz, R1243x001D: 82.5 kH
• Internal Soft-start Time .......................................... Typ. 0.4 ms, TSS = Open
• External Soft-start Time ......................................... Typ. 12 ms, CSS = 0.1 µF
• Flag Output ............................................................ Typ. 0.25 ms, FLG “OFF” delay tim e
• UVLO Released Voltage ........................................ Typ. 4.0 V
• Thermal Shutdown ................................................ Typ. 160°C, Hysteresis = 35°C
• Package ............................................................... HSOP-8E, DFN(PLP)2527-10
(1) This is an approximate value, because output current depends on conditions and external parts.
R1243x
NO.EA-206-170608
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APPLICATIONS
• Digital Home Appliances
• Hand-held Communication Equipment: Cameras, VCRs, Camcorders
• Battery-powered Equipment
• Battery Charger
SELECTION GUIDE
The package type, the oscillator frequency (Fixed: 1000 kHz, 330 kHz) and the short-circuit protection type
(Latch, Fold-back) are user-selectable options.
Selection Guide
Product Name
Package
Quantity per Reel
Pb Free
Halogen Free
R1243S001
∗
-E2-FE
HSOP-8E
1,000 pcs
Yes
Yes
R1243K001
∗
-TR
DFN(PLP)2527-10 5,000 pcs Yes Yes
∗: Specify the oscillator frequency and the short-circuit protection ty pe.
(A) Fixed Frequency: 1000 kHz, Latch Type (2 ms)
(B) Fixed Frequency: 1000 kHz, F o ld-back Type
(C) Fixed Frequency: 330 kHz, Latch Type (2 ms)
(D) Fixed Frequency: 330 kHz, Fold-back Type
(E) Fixed Frequency: 1000 kHz, Latch Type (2 ms), onl y for HSOP-8E
R1243x
NO.EA-206-170608
3
BLOCK DIAGRA M
FB
CE
-
+
Oscillator
*1
Regulator 5V
R
S D
Current Slope Circuit
Reference
Soft Start
Circuit
-
+
UVLO
0.5V
Regulator
Thermal Shutdown
Peak Current
Limit Circuit
VIN
Limit Latch
Circuit(2msec/0.08msec)
*1
Shutdown
GND
FLG
BST
Over/Under
Voltage
Detection
O/U VD
Shutdown
O/U VD
TSS
OFF Delay
(0.25msec)
-
+
3V SS
Set Pulse
Maxduty Pulse
SS
LX
Reset
Shutdown
SS
("H" during Soft Start)
R1243x Block Diagram
*1
Version
Oscillator Frequency
Short-circuit Protection Type
A 1000 kHz Latch Type (2 ms)
B
1000 kHz
Fold-back Type
C
330 kHz
Latch Type (2 ms)
D
330 kHz
Fold-back Type
E
1000 kHz
Latch Type (0.08 ms)
R1243x
NO.EA-206-170608
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PIN DESCRIPTIONS
Top View
Bottom View
5
8
6
4
2
1
3
8
6
5
7
1
3
4
2
7
∗
Bottom View
Top View
6
10
7
8
9
5
1
4
3
2
10
6
9
8
7
1
5
2
3
4
∗
HSOP-8E Pin Configuration DFN(PLP)2527-10 Pin Configuration
∗ The tab is subst rate level (GND). It must be connected to the GND level.
R1243S001x Pin Description
Pin No
Symbol
Pin Description
1
BST
Bootstrap Pin
2
VIN
Power Supply P i n
3
LX
LX Switching Pin
4
GND
Ground Pin
5
FB
Feedback Pin
6
FLG
Flag Output Pin
7
CE
Chip Enable Pin, Active with “H”
8
TSS
Soft-start Pin
R1243K001x Pin Description
Pin No
Symbol
Pin Description
1
LX
LX Switching Pin
2
LX
LX Switching Pin
3
GND
Ground Pin
4
FB
Feedback Pin
5
FLG
Flag Output Pin(1)
6
CE
Chip Enable Pin, Active with “H”
7
TSS
Soft-start Pin
8
BST
Bootstrap Pin
9
VIN
Power Supply P i n
10
VIN
Power Supply P i n
(1) The FLG pin should be connected to GND or should be left f l oating when it is not used.
R1243x
NO.EA-206-170608
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INTERNAL EQUIVALENT CIRCUIT FOR EACH PIN
BST Pin
LX Pin
FB Pin
FLG Pin
CE Pin
TSS Pin
BST
L
X
Regulator
L
X
V
IN
FB
Regulator
FLG
CE
VIN
TSS
Regulator
R1243x
NO.EA-206-170608
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ABSOLUTE MAXI MUM RA TI NGS
Absolute Maximum Ratings (GND = 0 V)
Symbol
Parameter
Rating
Unit
V
IN
Input Voltage
−0.3 V to 32 V
V
VBST
Boost Pin Voltage
VLX −0.3 V to VLX + 6 V
V
V
LX
LX Pin Voltage
−0.3 V to V
IN
+ 0.3
V
V
CE
CE Pin Input Voltage
−0.3 V to V
IN
+ 0.3
V
V
FB
VFB Pin Voltage
−0.3 V to 6 V
V
V
FLG
FLG Pin Voltage
−0.3 V to 6 V
V
VTSS
TSS Pin Voltage
−0.3 V to 6 V
V
PD Power Dissipation(1)
(HSOP-8E)
Standard
2900
mW
(DFN(PLP)2527-10)
Standard
910
High Wattage
1400
Tj
Junction Tem peratu re Range
−40 to 125
ºC
Tstg
Storage Temperature Ran ge
−55 to 125
ºC
ABSOLUTE MAXIMUM RATINGS
Electronic and mechanical stress momentarily exceeded absolute maximum ratings may cause the permanent
damages and may degrade t he li fe time and safety for both device and sys tem using the device in the fiel d.
The functional operation at or over these a bsolute max imum ratings are not assur ed.
RECOMMENDED OPERATING CONDITIONS
Recommended Op erating Conditions
Symbol
Parameter
Rating
Unit
V
IN
Operating Input V ol tage
4.5 to 30
V
Ta
Operating Temperature Ra nge
−40 to 85
°C
RECOMMENDED OPERATING CONDITI ONS
All of electronic equipment should be designed that the mounted semiconductor devices operate within the
recommended operating conditions. The semiconductor devices cannot operate normally over the recommended
operating conditions, even if when they are used ov er such conditions by momentar y electronic noise or surge. And
the semiconductor devices may receive serious damage when they continue to operate over the recommended
operating conditions.
(1) Refer to POWER DISSIPATION for detailed information.
R1243x
NO.EA-206-170608
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ELECTRICAL CHARACTERISTICS
VIN = 12 V, unless otherwise noted.
Electrical Characteristics (Ta = 25°C)
Symbol
Parameter
Test Conditions/Comments
Min.
Typ.
Max.
Unit
Istandby
Standby Current
VIN = 30 V, VCE = 0 V
0
10
µA
ISS
Supply Current
VIN = 30 V, VFB = 1.0 V
0.7
1.0
mA
VUVLO1
UVLO Detector Threshold
Falling
3.6
3.8
4.0
V
VUVLO2
UVLO Released Voltage
Rising
3.8
4.0
4.2
V
VUVLOHYS
UVLO Hysteresis
VUVLO2 − VUVLO1
0.2
V
VFB
Feedback Voltage
0.493
0.500
0.507
V
∆VFB/∆Ta
Feedback Voltage
Temperature Coefficient
−40ºC ≤ Ta ≤ 85ºC ±100
ppm
/ºC
fosc
Oscillator Frequency
(R1243x001A/B)
900 1000 1100 kHz
Oscillator Frequency
(R1243x001C/D)
290 330 370 kHz
fFLB
Fold-back Frequency
(R1243x001B/D)
VFB < 0.35 V, fosc Ratio 25 %
Maxduty
Oscillator Maximum Duty Cycle
VIN = 6 V
85
90
95
%
ITSS
TSS Pin Current
VTSS = 0 V
4.0
µA
tSS1
Soft-start Time 1
TSS = open
0.2
0.4
0.8
ms
tSS2
Soft-start Time 2
CSS = 0.1 µF
6
12
18
ms
tDLY
Latch Protection Delay Time
(R1243x001A/C)
VIN = 5.0 V 2.0 ms
Latch Protection Delay Time
(R1243x001E)
0.08
ILXHOFF
Highside Switch Leakage Current
VIN = 30 V, VCE = 0 V
0
10
µA
RLXH
Highside Switch ON Resistance
VBST – VLX = 4.5 V
175
mΩ
ILIMLXH
Highside Switch Limited Current
VBST – VLX = 4.5 V
2.8
3.8
A
VCEH
CE “H” Input Voltage
VIN = 30 V
1.4
V
VCEL
CE “L” Input Voltage
VIN = 30 V
0.4
V
ICEH
CE “H” Input Current
VIN = 30 V, VCE = 30 V
−1.0
0
1.0
µA
ICEL
CE “L” Input Current
VIN = 30 V, VCE = 0 V
−1.0
0
1.0
µA
IFBH
FB “H” Input Current
VFB = 2.0 V
−1.0
0
1.0
µA
IFBL
FB “L” Input Current
VFB = 0 V
−1.0
0
1.0
µA
TTSD
Thermal Shutdown Detect
Temperature
Hysteresis 35ºC 160 ºC
VFLGL
FLG “L” Voltage
IFLG = 1 mA
0.4
V
IFLGOFF
FLG “OFF” Current
VFLG = 5.5 V
0.0
1.0
µA
tFLGOFF
FLG “OFF” Delay Time
0.05
0.25
0.60
ms
VOVD
Overvoltage Detection Voltage
VFB
0.55
0.60
0.65
V
VUVD
Undervoltage Detection Voltage
VFB
0.35
0.40
0.45
V
R1243x
NO.EA-206-170608
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OPERATING DESCRIPTIONS
SOFT-START TIM E ADJUST M ENT FUNCTI ON AND FLAG FUNCTION
Soft-Start Time Adjustment Function
The soft-start time (tSS) of the R1243x is adjustable by adding the soft-start time adjusting capacitor (CSS) to
the TSS pin. The soft-start time can be set long er than the internal sof t-start time (Typ. 0.4 ms).
For example, if the soft-start time adjusting capacitor (CSS) is 0.1µF, the externally adjusted soft-start time will
be 12 ms (Typ.). If there is no need of adjusting the soft-start time, leave the TSS pin as open so that the
internal soft-start time (Typ. 0.4 ms) will be applied.
Fig. 1 CSS vs. tSS (Typ.)
Flag Function
The R1243x includes a flag output function using Nch open drain. If an abnormal state is detected, the flag
output function turns the Nch transistor on and switches the FLG pin low. After recovering from the abnormal
state, the flag output function turns the Nch transistor off and switches the FLG pin high after recovering from
the low voltage detection (Typ. 0.4 V) and waiting for the delay time (Typ. 0.25 ms). The flag function detects
the following condit i ons as abnormal states.
CE = ”L” (Shutdown)
UVLO (Shutdown)
Thermal Shutdow n
VFB Overvoltage Detection (Typ. 0.6 V)
VFB Undervoltage Detect ion (Typ. 0.4 V)
Active Latch Function (R1243x001A/C/E)
Overvoltage Protection for TSS Pin after the Completion of Soft-start (Typ. 3 V)
t
SS
12ms
6ms
1.2ms
0.4ms
03300pF
0.01μF
0.047μF 0.1μF
C
SS
R1243x
NO.EA-206-170608
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The flag resistors (RFLG) have to be between 10 kΩ to 100 kΩ. If the flag funct ion is not used, the FLG pin has
to be left open or connect ed to GND.
Fig. 2 Flag Function Sequence
V
CE
1.4V<
0.4V>
time
VFB
VOVD 0.60V(Typ.)
0.500V(Typ.)
VUVD 0.40V(Typ.)
0.45V(Typ.)
time
VFLG tSS
VFLGIN
0.4V>
time
tFLGOFF
0.25ms
R1243x
NO.EA-206-170608
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OPERATION OF STEP-DO WN DC/DC CONVERTE R AN D OUTPUT CURRENT
The step-down DC/DC converter stores energy in the inductor (L) when the LX transistor turns on, and releases
energy from L when the LX transistor turns off. This is why it can control with less energy loss and provide a
lower output voltage (VOUT) than the input voltage (VIN). The operation of the step-down DC/DC converter is
explained in the foll owing figures.
Nch Tr.
L
Diode
VIN
i1
VOUT
COUT
i2
GND
Basic Circuit
Inductor Current flo wing through Inductor
Step 1. The Nch transistor turns on and the inductor current (i1) flows, L is charged with energy. At this moment,
i1 increases from the minimum inductor current (ILmin), which is 0 A, and reaches the maximum
inductor current (I Lm ax) in proportion to the on-time period (ton) of t he Nc h t ransistor.
Step 2. When the Nch transistor turns off, L tries to maintain IL at ILmax, so L turns the diode on and the
inductor current (i2) f l ows into L.
Step 3. i2 decreases gradually and reaches ILmin after t he open-time period (to pen) of the Nch transistor, and
then the diode turns of f. This is called disc ont i nuous current mode.
As the output current (I OUT) increas es, the off-t ime period (toff ) of t he Nch tra nsist or run s out b efore I L
reaches ILmin. The next cycle starts, and the Nch transistor turns on and the diode turns off, which
means IL starts increasing from ILmin. T hi s is called continuo us current mode.
In the case of PWM mode, VOUT is maintained by controlling ton. During PWM mode, the oscillator frequency
(fosc) is being maintained constant.
t = 1 / fosc
toff
topen
ILmin
ILmax
ton
IL
R1243x
NO.EA-206-170608
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APPLICATION INFORMATION
TYPICAL APPLICATION CIRCUIT
VOUT = 0.8 V, tSS = 0.4 ms
R1243x001A/B/E Typical Application
V
OUT
= 0.8 V, t
SS
= 0.4 ms
R1243x001C/D Typical Application
C
BST
0.47µF
CIN
10µF
VIN
5.0V
RCE
47kΩ
“H”active
L
2.2µH
COUT
47µF
VOUT
0.8V
RUP
1.2kΩ
RBOT
2.0kΩ
D
CSPD
1800pF
GND
Lx
VIN
BST
FB
FLG
CE
TSS
R1243x001A/B, R1243S001E
C
BST
0.47µF
C
IN
10µF
V
IN
12V
R
CE
47kΩ
“H”active
L
4.7µH
COUT
47µFx2
V
OUT
0.8V
RUP
1.2kΩ
RBOT
2.0kΩ
D
C
SPD
2700pF
GND
Lx
V
IN
BST
FB
FLG
CE
TSS
R1243x001C/D
BST TSS
VIN CE
LX FLG
GND FB
BST TSS
VIN CE
LX FLG
GND FB
R1243x
NO.EA-206-170608
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VOUT = 1.8 V, tSS = 0.4 ms
R1243x001A/B/E Typical Application
VOUT = 1.8 V, tSS = 0.4 ms
R1243x001C/D Typical Application
C
BST
0.47µF
CIN
10µF
V
IN
12V
R
CE
47kΩ
“H”active
L
4.7µH
COUT
10µF
VOUT
1.8V
RUP
5.2kΩ
RBOT
2.0kΩ
D
CSPD
560pF
GND
Lx
V
IN
BST
FB
FLG
CE
TSS
R1243x001A/B, R1243S001E
CBST
0.47µF
CIN
10µF
V
IN
12V
RCE
47kΩ
“H”active
L
4.7µH
COUT
47µF
V
OUT
1.8V
RUP
5.2kΩ
RBOT
2.0kΩ
D
CSPD
1000pF
GND
Lx
V
IN
BST
FB
FLG
CE
TSS
R1243x001C/D
BST TSS
VIN CE
LX FLG
GND FB
BST TSS
VIN CE
LX FLG
GND FB
R1243x
NO.EA-206-170608
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VOUT = 3.3 V, tSS = 0.4 ms
R1243x001A/B/E Typical Application
V
OUT
= 3.3 V, t
SS
= 0.4 ms
R1243x001C/D Typical Application
C
BST
0.47µF
CIN
10µF
V
IN
12V
R
CE
47kΩ
“H”active
L
4.7µH
COUT
10µF
VOUT
3.3V
RUP
11.2kΩ
RBOT
2.0kΩ
D
CSPD
220pF
GND
Lx
V
IN
BST
FB
FLG
CE
TSS
R1243x001A/B, R1243S001E
CBST
0.47µF
CIN
10µF
V
IN
12V
RCE
47kΩ
“H”active
L
10µH
COUT
22µF
VOUT
3.3V
RUP
11.2kΩ
RBOT
2.0kΩ
D
C
SPD
390pF
GND
Lx
V
IN
BST
FB
FLG
CE
TSS
R1243x001C/D
BST TSS
VIN CE
LX FLG
GND FB
BST TSS
VIN CE
LX FLG
GND FB
R1243x
NO.EA-206-170608
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VOUT = 15 V, tSS = 0.4 ms
R1243x001A/B/E Typical Application
VOUT = 15 V, tSS = 0.4 ms
R1243x001C/D Typical Application
C
BST
0.47µF
CIN
10µF
V
IN
24V
R
CE
47kΩ
“H”active
L
4.7µH
COUT
10µF
VOUT
15V
RUP
58kΩ
RBOT
2.0kΩ
D
CSPD
47pF
GND
Lx
V
IN
BST
FB
FLG
CE
TSS
R1243x001A/B, R1243S001E
CBST
0.47µF
CIN
10µF
V
IN
24V
RCE
47kΩ
“H”active
L
10µH
COUT
10µFx2
VOUT
15V
RUP
58kΩ
RBOT
2.0kΩ
D
CSPD
100pF
GND
Lx
V
IN
BST
FB
FLG
CE
TSS
R1243x001C/D
BST TSS
VIN CE
LX FLG
GND FB
BST TSS
VIN CE
LX FLG
GND FB
R1243x
NO.EA-206-170608
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VOUT = 5.0 V, tSS = 0.4 ms, Flag Function Using
R1243x001A/B/E Typical Application
CBST
0.47µF
C
IN
10µF
V
IN
24V
R
CE
47kΩ
“H”active
L
4.7µH
C
OUT
10µF
V
OUT
5.0V
R
UP
18kΩ
R
BOT
2.0kΩ
D
R
FLG
47kΩ
V
FLG
V
FLGIN
C
SPD
150pF
GND
Lx
VIN
BST
FB
FLG
CE
TSS
R1243x001A/B, R1243S001E
BST TSS
VIN CE
LX FLG
GND FB
R1243x
NO.EA-206-170608
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VOUT = 5.0 V, tSS = 12 ms, Flag Function Using
R1243x001C/D Typical Application
The R1243x includes a flag output function using Nch open drain. If an abnormal state is detected, the flag
output function turn s the Nch transistor on and swit ches the FLG pin low . After recov ering from the abnormal
state, the flag output function turns the Nch transistor off and switches the FLG pin high after recovering
from the low voltage detection (Typ. 0.4 V) and w ai ting for the dela y time (Typ. 0.25 ms).
If VOUT is used as VFLGIN, the FLG pin high voltage (VFLGH) will be same voltage level as VOUT even before
the completion of soft-start. When usi ng the soft-sta rt time adjustment in the sequential startup cir cuits, note
that VFLGH is dependent on VFLGIN (connecting to VOUT directly or us i ng other voltage sour ce).
• CE = “L” (Shutdown)
• UVLO (Shutdown)
• Thermal Shutdow n
• VFB Overvoltage D et ect i on (Typ. 0.6 V)
• VFB Undervolt age Det ection (Typ. 0.4 V)
• Active Latch Function (R1243x001A/C/E)
• Overvoltage Protection for the TSS pin after the completion of soft-start (Typ. 3 V)
CBST
0.47µF
C
IN
10µF
V
IN
24V
C
SS
0.1µF
V
FLGIN
5.0V
R
CE
47kΩ
“H”active
R
FLG
47kΩ
FLAG
L
10µH
C
OUT
22µF
VOUT
5.0V
R
UP
18kΩ
R
BOT
2.0kΩ
GND
Lx
V
IN
BST
FB
FLG
CE
TSS
R1243x001C/D
D
C
SPD
220pF
BST TSS
VIN CE
LX FLG
GND FB
R1243x
NO.EA-206-170608
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SEQUENTIAL START-UP
The figure below shows the example of s equential startup cir cuits using soft-st art t i m e adj ustment and flag
functions. Where: t he i nput voltage is 12 V, the out put voltage of the R124 3x001A/B/E (DCDC1) is 5.0 V, the
output voltage of the R1243x001A/B / E (DCDC2) is 3.3 V, the electrolytic capacit or f or t he 5. 0 V output is 470
µF and the electrolyt ic capacitor for the 3. 3 V out put is 100 µF. The DCDC1 circuit starts up first fol lowed by
the DCDC2 circuit, s o that the output voltage of DCDC1 will not drop below the o utput voltage of the DC DC2.
Soft-start Tim e and Cha rging Current
During the soft-start, the R1243x generates a charging current (ICHRG) for a cap acitor connect ed to VOUT in
addition to the output current (IOUT) for suppl ying the output load. Ther efore, IOUT is given by:
IOUT’ = IOUT + ICHRG = IOUT + VOUT x (COUT + CL) / tSS
IOUT2’ (DCDC1) and IOUT2’ (DCDC2) are given by:
DCDC1: IOUT’ = IOUT + VOUT / (COUT + CL) / tSS = IOUT + 5.0 V x (10 μF + 470 μF) / 26 ms = IOUT + 92 mA
DCDC2: IOUT2’ = IOUT2 + VOUT2 / (COUT2 + CL2) / tSS = IOUT + 3.3 V x (10 μF + 100 μF) / 2.6 ms = IOUT2 + 140 mA
The output current should not exceed 2.0 A even during soft-start.
Using the Output Voltage of DCDC1 as the FLG Pin Voltage of DCDC1
The R1243x includes a flag output function using Nch open drain. If an abnormal condition is detected, the
flag output function turns the Nch transistor on and switches the FLG pin low. If an abnormal condition is not
detected, the flag output function turns the Nch transistor off and switches the FLG pin high after recovering
from the low voltage detection (Min. 0.35 V) and waiting for the delay time (Min. 0.05 ms). If VOUT is used as
VFLGIN, the FLG pin high voltage (VFLGH) will be same v oltage lev el as V OUT even bef ore fini shi ng t he soft-start.
After recovering f rom the low voltage detection, the lowe st VFLGH will be 70% of the set output voltage (VSET).
Using the FLG Pin Voltage of DCDC1 as the CE Pin Input Voltage of DCDC2
The lowest CE pin low voltage (VCEL) is 0.4 V, and the highest CE pin high voltage (V CEH) is 1.4 V. The highest
flag pin low voltage (VFLGL) is 0.4 V and the lowest VFLGH of DCDC1 is approximately 3.5 V, so the flag pin
voltage (VFLG) can be used as the CE pi n input voltage (VCE) of DCDC2.
Auto-discharge using the FLG Pin
The R1243x turns the Nch transistor on and switches the FLG pin low during shutdown. If the FLG pin is
switched low, a FLG pin current (IFLG) flows from VFLGIN to the FLG pin resistor (RFLG) and the Nch transistor.
Therefore, using VOUT as VFLGIN can discharge the electric charges of a capacitor connected to VOUT during
shutdown.
The highest IFLG will be VFLGIN divided by RFLG. When determining the RFLG value, ensure that the highest IFLG
will be 5 mA or less. Do not directly connect VOUT to the FLG pin. IFLG may becom e exces sive and damage the
device.
VFLGL is regulated as IFLG = 1 mA. If RFLG is set higher than IFLG = 1 mA, the highest VFLGL of 0.4 V is not
guaranteed, hence t he flag function itself may be spoi l ed.
R1243x
NO.EA-206-170608
18
Typical Application Circuit with Start-up Sequencing
(DCDC1) R1243x 001A/B/E: 1000 kHz, VIN = 12 V, VOUT = 5.0 V, tSS = 26 ms (CSS = 0.22 μF)
(DCDC2) R1243x 001A/B/E: 1000 kHz, VIN = 12 V, VOUT = 3.3 V, tSS = 2.6 ms (CSS = 0.022 μF)
C
BST
0.47µF
C
IN
10µF
V
IN
12V
C
SS
0.22µF
L
4.7µH
C
OUT
10µF
V
OUT
5.0V
RUP
18kΩ
R
BOT
2.0kΩ
D
C
SPD
150pF
GND
Lx
V
IN
BST
FB
FLG
CE
TSS
R1243x001A/B,
R1243S001E
R
FLG
10kΩ
R
CE
10kΩ
C
BST2
0.47µF
C
IN2
10µF
C
SS2
0.022µF
L
2
4.7µH
C
OUT2
10µF
V
OUT2
3.3V
R
UP2
11.2kΩ
R
BOT2
2.0kΩ
D
2
C
SPD 2
220pF
GND
Lx
V
IN
BST
FB
FLG
CE
TSS
R1243x001A/B,
R1243S001E
R
FLG2
1.0kΩ
C
L
470µF
C
L2
100µF
V
CE
V
FLG
V
FLG2
IFLG2
DCDC1
DCDC2
+
+
I
OUT
I
OUT2
BST TSS
VIN CE
LX FLG
GND FB
BST TSS
VIN CE
LX FLG
GND FB
R1243x
NO.EA-206-170608
19
Fig. 3 Start-up/ Shutdo wn Sequencing
DCDC1
VCE
1.4V<
0.4V>
time
DCDC1
VOUT
VOVD 6.0V(Typ.)
VOUT 5.0V(Typ.)
VUVD 4.0V(Typ.)
4.5V(Typ.)
time
DCDC1
V
FLG
tSS 26ms(Typ.)
VOUT 5.0V(Typ.)
0.4V>
time
DCDC2
VOUT2 tFLGOFF 0.25ms(Typ.)
VOVD 3.96V(Typ.)
VOUT2 3.3V(Typ.)
VUVD 2.64.V(Typ.)
2.97V(Typ.)
time
DCDC2
VFLG2
tSS 2.6ms(Typ.)
VOUT2 3.3V(Typ.)
time
DCDC2
IFLG2 tFLGOFF 0.25ms(Typ.)
IFLG2 3.3mA(Typ.)
time
R1243x
NO.EA-206-170608
20
THE MINIMUM ON-TIME
The minimum On-Time of the R1243 Series is set at 150 ns (Typ.). The minimum On-Time (150 ns) is
determined by consi dering the tolerable delay time and t he necessary stability of the current sense circuits.
The R1243 Series has adopted the current control mode system, which does not require any sense resistor.
By substituting t he RON (Nch driver's on-resistance) val ue into t he following equation, the ILX (Inductor cur rent)
value can be obtaine d: VIN - VLX = ILX x RON. ILX can be sense d only while the Nch driver is tur ned on (LX = High
period). If the ILX is sensed during the switching surge immediately after the Nch driver is turned on, the
switching surge may cause the malfunction. To avoid the malfunction caused by the switching surge, disable
the current sensing function of Nch driver for a while immediately after the Nch driver is turned on. While the
current sensing function of the Nch driver is disabled, both the current control mode system and the limited
current circuit cannot function norm al ly.
Fig. 4 is a graph with the on time on the horizontal axi s, and the limit current on the vertic al . The graph shows
that the delay time is occurred in the limited current circuit within 150 ns because the current sensing is not
functioning normally. As a result, the detecting current is increased dramatically. The delay time occurred in
the limited circuit current includes the circuit delay time occurred between the current sense circuit and the
driver.
This could happen in the current control mode system as well. The current control mode system does not
function normally under 150 ns but the operation becomes similar operation to the voltage control mode system
that is low stable.
For the above reasons, the stability and the over-current limit accuracy of the R1243 Series degrades
dramatically under 150 ns. In t he c ase o f set ting t he minimum on time equal o r les s than 150 ns, an ade quat e
stability has t o be ensured by the ext ernal parts a nd also the ov er current p rotection ci rcuit has to be design ed
without depending on the current limit circuit of the IC.
Fig. 4 On-time and Peak Current of LX pin (ILXLIMIT) at Current Limit Detection of LX pin
3.8
4.0
4.2
4.4
4.6
4.8
5.0
5.2
5.4
5.6
5.8
100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400
Ont i m e [ns]
I
LXLIMIT
[A]
VIN=5.0V
VIN=12V
VIN=24V
R1243x
NO.EA-206-170608
21
OUTPUT CURRENT AND SELECTION O F EXTERNAL COMPONENTS
The following equati ons explain the rel ationship between output current and p eripheral components.
IRP is the ripple current P-P value, RONH is the ON resistance of Highside T r ., RL is the DC resistance of inductor .
First, when Highside Tr. is “ON”, the following equation is satisfied.
VIN = VOUT + (RONH + RL) × IOUT + L × IRP / ton ................................................................................ Equation 1
Second, when Highside Tr . is "OFF" (Diode is "ON"), the following equation is satisfied.
L × IRP / toff = VF + VOUT + RL × IOUT ............................................................................................... Equation 2
Put Equation 2 to Equation 1 to solve ON duty of Highside Tr. (DON = ton / (toff + ton):
DON = (VOUT + VF + RL × IOUT) / (VIN + VF - RONH × IOUT) .................................................................. Equation 3
Ripple Current is giv en by:
IRP = (VIN - VOUT - RONH × IOUT - RL × IOUT) × DON / fosc / L .............................................................. Equation 4
Peak current (ILmax) that flows throu gh L, and LX Tr. is given by:
ILmax = IOUT + IRP / 2 ...................................................................................................................... Equation 5
The valley current (ILmin) is given by:
ILmin = IOUT - IRP / 2 ....................................................................................................................... Equation 6
If ILmin is smaller than 0 (ILmin < 0), the step-down DC/ DC conv ert er operate in discontinuous mode.
The step--down DC/DC converter operates in discontinuous mode when:
IOUT < IRP / 2 .................................................................................................................................... Equation 7
It is important to consider ILmax and ILmin when making the input/output conditions or selecting the external
components. The above explanation is base d on the ideal operation of continuous mode.
R1243x
NO.EA-206-170608
22
Ripple Current and LX Current Limiting
The fluctuatio n in ripple current of indu ctor can be caused by vari ous reasons. The R1243x has a LX current
limiting that sets the upper limitation of the inductor current (LX peak current limit). Note that the LX peak
current limit is not the ave rage inductor current (sam e as out p ut c urrent value). The larger t he rip ple cu rrent
is, the larger the LX peak current will be. The R1243x001B/D is using this characteristic in the fold-back
current limiting. The fold-back current limiting maintains the LX peak current limiting and reduces the
switching frequency to lower the average inductor current. To release the fold-back current limiting, the LX
peak current of the R1243x001B (250 kHz) or the R1243x001D (82.5 kHz) should not go beyond the LX
peak current limit. Fig. 5 shows the LX current limit se quencing.
Fig. 5 LX Current Limit Sequencing
t
t
VOUT
VOUT
short
2ms or 0.08ms
shutdown restart
(CE="H"→"L"→"H")
short
open
open
VFB<0.35V
VOUT
IOUT
VOUT
IOUT
VFB<0.35V
Limit Latch
(R1243x001A/C/E)
Fold Back
(R1243x001B/D)
shutdown
2msec or 0.08ms
R1243x
NO.EA-206-170608
23
Latch Protection for the R1243x001A/C/E
After current limit detection, if a voltage drop continues more than a specified time, the R1243x001A/C/E
enables a latch prote ction to turn of f output. Note t hat if a power voltage rising is sl ow and the output volt age
after soft-start is less than a set output voltage for more than a latch timer period. Refer to TECHNICAL
NOTES for details.
Fold-back Protection for the R1243x001B/D
The R1243x00B/D enables a fold-back protection after soft-start. The fold-back protection reduces the
oscillator frequency to 1/4 if the output voltage drops to 70% (Typ.) or less of a set output voltage, which
means the FB pin voltage is typically 0.35 V or less. If an oscillator frequency decreases, a ripple current
increases. As shown in Equation 8, with LX current limiting, the average current decreases as the ripple
current increase s.
IOUT = ILmax − IRP / 2………………………………………………………………………………………Equation 8
Once the fold-back p rotection is enabled during heavy load, the R1243x may not be able to return to normal
operation due to the increased ripple current. Note that if a power voltage rising is slow and the output
voltage drops 70% (typ.) or less of a set output voltage after soft-start. Refer to TECHNICAL NOTES for
details.
R1243x
NO.EA-206-170608
24
POWER LOSS AND EFFICI ENCY
Nch High-side Tr. Turn-on Loss: PON = RONH x IOUT2 x Onduty
Nch High-sid e Tr. Switching Loss: PF = (tR + tF) / 2 × VIN x IOUT x fOSC
Diode Loss: POFF = VF × IOUT x Offduty
Inductor Conduction Loss: PL = RL x IOUT2
IC’s Consumption Current Loss: PD = VIN x ISS
Inductor’s Ripple Current Loss: PPP = 1 / 4 x RC x IRP2
Efficiency η = (VOUT x IOUT) / ((VOUT x IOUT) + PON + PF + PCL + PD + PPP) x 100%
PON, PF and PD are power losses in the ICs. Thes e power losses are converted into heat inside the IC. Usin g
the following equation, ensure that the junction temperature does not rise above 125°C:
Tj = θja x (PON + PF + PD) + Ta < 125°C
L
O
A
D
R
ONH
LX L
V
F
C
OUT
R
L
V
OUT
I
OUT
R
C
V
IN
V
IN
GND
t
R
t
F
LX
R1243x
NO.EA-206-170608
25
TECHNICAL NOTES ON SHUTDOWN USING INPUT VOLTAGE CONTROL
If the CE pin is enabled without switchi ng the CE pin status, whi ch means connecting t he CE pin to the VIN
pin, while a set output voltage (VSET) is higher than the UVLO detection threshold (typ. 3.8 V), the input/
output ratio may exceed the maximum duty ratio at sh utdown. If the input/ output ratio exceeds the maximum
duty ratio, the output voltage drops and if t he input/output ratio falls below the max i m um duty ratio, the output
voltage rises. These vol tage fluctuations generates oscillating waveforms at s hutdown.
As shown in Fig. 6, if the input voltage drops before the output v ol tage drops, a large rev erse current may
flow. To avoid this, ensure the input volt age i s high enough befor e switching the CE pin status low, or
otherwise add a dis charge circuit.
Fig. 6 Shutdown Using Input Voltage Control
Load
VOUT
GND
LX
VOUT
VIN
Reverse Current (V
IN
+ 0.3 V < V
OUT
)
VUVLO1
VIN
Reverse Current
Potential Area
VIN + 0.3 V < VOUT
R1243x
NO.EA-206-170608
26
TECHNICAL NOTES
• External components have to be connected as close as possible to the IC and have to be wired as shor t
as possible. Especially, the capacitor connected between VIN and GND pin must be wired the shortest. If
the impedances of the power supply line and the GND line are high, the operation can be unstable due to
the switching curre nt, which fluctuate s the power line of the inside the IC. The impedances of power suppl y
line and GND line must be as low as possible. It is necessary to give careful consideration to the large
current flowing int o the power supply, GND, LX, VOUT and inductor whe n designing their wirings. The wiri ng
of output voltage s et ting resistance (RUP) and the wi ring of inductor m ust be separated from load wiring.
• The capacitors to be use d in the R1243x must be low ESR ceram ic capacito rs. The CIN capacitor betwee n
VIN and GND should be equal or more than 10 µF. Please pay attention to the bias-dependent properties
and the temperature variability characteristics of the ceramic capacitors.
• The internal phase compensation of this IC is designed within the recommended values of inductor and
COUT ceramic capacitor. If the inductor value is small, the peak values of the switching current increase
along with the load current. When the peak value of the switching current reaches to the current limit, the
over current protecti on circuit may start to function.
• If the parasitic capacitor of the schottky diode is large , the operation m ay result in unstable be cause of t he
large switching current when the switch is turned on. Please use the schottky diode with 100 pF or less
when the reverse v oltage is 10 V.
• The output voltage (VOUT) can be calcula t ed by t his equat ion: VOUT = VFB × (RUP + RBOT) / RBOT. By changing
RUP and RBOT, the output voltage (VOUT) is adjustable. If resistance values of RUP and RBOT are high, the
impedance of the FB pins become high, and the IC becomes vulnerable to an influence of noise. RBOT is
recommended to be between 1.0 kΩ to 4.7 kΩ. If the operation become unstable due to the high impedance,
it is important to consi der lowering the impedance.
• In the IC, ESD protection diode is connected between CE pin and VIN pin. If there is a possibility that the
CE pin voltage become s higher than the VIN pin voltage, it is recommende d to insert a 10 kΩ resistance or
more in order to prev ent the large current f l owing from CE pin into VIN pin.
• Connect the reverse side of the IC pad to GND. To improve the radiation of heat of the multiple-layered
board, it is effective to mak e the via on the connection part of the reverse side of the IC pad to release t he
heat to multiple layers.
• The flag resistor (RFLG) is recommended to be between 10 kΩ to 100 kΩ. If the flag function is not used,
FLG pin has to be left open or connected to GND.
• If the soft-start time adjustment function is not used, TSS pin must be lef t open. In this case, soft -start time
is set as 0.4 ms (Typ.).
• After the completion of the soft-start, latch function (R1243x001A/C/E) starts to function. The internal
counter starts counting when the overcurrent protection circuits runs the current limit detection. When the
internal counter count s up to 2 ms typically (R1243x001A/C) or up to 0.08 ms (R1243x001E), lat ch function
turns off the output. The turned off output can be reset when CE pin is changed to “L”, and also VIN pin
voltage became less than 3.8 V typically, which is UVLO detecting voltage. If the output voltage becomes
more than the setting voltage (FB pin voltage is 0.50 V typically within the latch timer period, the counter
restores the default. Therefore, the careful attention is required when the power-supply voltage’s start-up
is slow and the output voltage is not reached to the setting voltage within the latch timer period after the
completion of t he soft-start.
R1243x
NO.EA-206-170608
27
• After the completion of the soft-start, fold-back fu nction ( R1243x001B/D) starts to function. The fold-back
function limits the oscillation frequencies into 1/4 when FB pin voltage becomes less than 0.35 V (Typ.).
Therefore, the caref ul attention is required whe n the power-supply voltage’s st art-up is slow and t he output
voltage is not reached to the 70% (Typ.) of the setting voltage even for a short period of time after the
completion of t he soft-start.
• The quality of the power supply circuit using the R1243x largely depends on the external compone nts. The
careful attention is re quired for the ext ernal component parameters.
• The careful attention is required for the maximum ratings (voltage, current, and wattage) of the external
components, board layout pattern and the IC.
• The table on the nex t page shows the recommended values for setting output voltage.
R1243x
NO.EA-206-170608
28
Table 1. R1243x Recommended Value for Each Output Voltage
R1243x001A/B/E: 1000 kHz
VIN VOUT L [µH] COUT [µF]
CSPD CBST [µF] RBOT [kΩ]
4.5 ≤ VIN ≤ Max 0.8 ≤ VOUT ≤ 1.2 2.2 47 ∗1 0.47 2.0
4.5 ≤ VIN ≤ Max 1.2 ≤ VOUT ≤ 1.8 2.2 22 ∗1 0.47 2.0
4.5 ≤ V
IN
≤ Max
1.8 ≤ V
OUT
≤ 2.5
4.7
10
∗1
0.47
2.0
4.5 ≤ VIN ≤ 6 2.5 ≤ VOUT ≤ Maxduty 4.7 22 open 0.47 2.0
6 ≤ VIN ≤ Max 2.5 ≤ VOUT ≤ 5 4.7 10 ∗1 0.47 2.0
Min ≤ V
IN
≤ Max
5 ≤ V
OUT
≤ Maxduty
4.7
10
∗
1
0.47
2.0
R1243x001C/D: 330 kHz
VIN VOUT L [µH] COUT [µF] CSPD CBST [µF] RBOT [kΩ]
4.5 ≤ VIN ≤ 7.5 0.8 ≤ VOUT ≤ 1.2 4.7 47×2 open 0.47 2.0
4.5 ≤ V
IN
≤ 7.5
1.2 ≤ V
OUT
≤ Maxduty
10
47
×
2
open
0.47
2.0
7.5 ≤ VIN ≤ Max 0.8 ≤ VOUT ≤ 1.2 4.7 47×2 ∗2 0.47 2.0
7.5 ≤ VIN ≤ 12 1.2 ≤ VOUT ≤ 2.5 10 47 ∗2 0.47 2.0
7.5 ≤ V
IN
≤ Max
1.2 ≤ V
OUT
≤ 2.5
4.7
47
∗
2
0.47
2.0
7.5 ≤ V
IN
≤ Max
2.5 ≤ V
OUT
≤ 5
10
22
∗2
0.47
2.0
7.5 ≤ VIN ≤ Max 5 ≤ VOUT ≤ 18 10 10×2 ∗2 0.47 2.0
∗1 R1243x001A/B/E: 1000 kHz
∗2 R1243x001C/D: 330 kHz
V
OUT
[V]
C
SPD
[pF]
R
UP
[kΩ]
R
BOT
[kΩ]
V
OUT
[V]
C
SPD
[pF]
R
UP
[kΩ]
R
BOT
[kΩ]
0.8
1800
1.2
2.0
0.8
2700
1.2
2.0
1
1200
2.0
2.0
1
2200
2.0
2.0
1.2
1000
2.8
2.0
1.2
1500
2.8
2.0
1.5
820
4.0
2.0
1.5
1200
4.0
2.0
1.8
560
5.2
2.0
1.8
1000
5.2
2.0
2.5
390
8.0
2.0
2.5
560
8.0
2.0
3.3
220
11.2
2.0
3.3
390
11.2
2.0
5
150
18.0
2.0
5
220
18.0
2.0
6
120
22.0
2.0
6
180
22.0
2.0
9
82
34.0
2.0
9
150
34.0
2.0
12
56
46.0
2.0
12
100
46.0
2.0
15
47
58.0
2.0
15
100
58.0
2.0
18
47
70.0
2.0
18
100
70.0
2.0
R1243x
NO.EA-206-170608
29
Table 2. R1243x Recommended External Components
CIN
V
IN
Cap.
Spec.
Part Name
Manufacturer
≤ 12.5 V
10 µF
25 V
GRM31CR71E106K
Murata
≤ 12.5 V
10 µF
25 V
CM316X5R106K25ABH
Kyocera
All
10 µF
50 V
UMK325BJ106MM-P
Taiyo Y uden
All 10 µF 50 V CGA6P3X7S1H106K TDK
COUT
V
OUT
Cap.
Spec.
Part Name
Manufacturer
≤ 8 V
47 µF
16 V
GRM32EB31C476KE15
Murata
≤ 5 V
22 µF
10 V
GRM31CR71A226M
Murata
≤ 12.5 V
10 µF
25 V
GRM31CR71E106K
Murata
≤ 8 V
22 µF
16 V
CM316X5R226K16AB
Kyocera
≤ 12.5 V 22 µF 25 V CM32X5R226M25AB Kyocera
≤ 12.5 V
10 µF
25 V
CM316X5R106K25ABH
Kyocera
All
10 µF
50 V
UMK325BJ106MM-P
Taiyo Y uden
All
10 µF
50 V
CGA6P3X7S1H106K
TDK
CBST
V
OUT
Cap.
Spec.
Part Name
Manufacturer
all
0.47 µF
16 V
EMK212BJ474KD-T
Taiyo Y uden
all
0.47 µF
16 V
C1608JB1C474K
TDK
D
V
IN
Spec.
Part Name
Manufacturer
≤ 15 V
15 V, 2A
SBS010M
SANYO
≤ 15 V
15 V, 2A
SS20015M
SANYO
all
40 V, 3A
CMS16
TOSHIBA
L
Ind.
Spec.
Part Name
Manufacturer
2.2 µH
5.4 A
RLF7030T-2R2M5R4
TDK
4.7 µH 3.4 A RLF7030T-4R7M3R4 TDK
10 µH
2.5 A
SLF10145T-100M2R5
TDK
2.2 µH
2.7 A
NR6020T2R2N
Taiyo Y uden
4.7 µH
2.6 A
NR6028T4R7M
Taiyo Y uden
10 µH 2.5 A NR6045T100M Taiyo Y uden
R1243x
NO.EA-206-170608
30
TECHNICAL NOTES ON PCB LAYOUT PATTERN
1. The exposed pad on the bottom of the package enhances the thermal performance and is electrically
connected to GND insi de the package. It is recomm ended that the expos ed pad be connected to t he ground
plane on the board with t hermal vias if pos sible.
2. Connect shortest pos sible: “a wiring between the VIN pin of input capacitor (CIN) and the VIN pin of IC” and “a
wiring between the GND pin of input capacitor (CIN) and the GND pin of IC”.
Connect as short as possible: “a wiring among the Lx pin of IC, the Lx pin of diode, the GND pin of diode,
and the GND pin of input capacitor (CIN)”.
These are recomm ended to wire without intermediary of a t hrough hole.
3. Wire the Lx pin short so that the parasitic capacitance would not be provided. It is recommended to
implement without i ntermediary of a through hole.
4. Connect between the GND pin of COUT and the GND pin of diode as shor t as possi ble. It is recomme nded
to wire without intermediary of a through hole.
5. T he FB pin side of RUP, RBOT, CSPD, and RSPD should be design ed to keep a distan ce from inductor, BST pin,
and Lx pin in order to avoid the high imp edance and noise effect. These can be wired via through hole.
6. For VOUT wiring to RUP, the feed-back must be made as close as possible from the output capacitor (COUT).
This can be wired via through hole.
7. For the GND wiring to the soft-start time adjusting capacitor (CSS), avoid the current path of parts including
input capacitors (CIN) and diodes. This can be wired via through hol e.
R1243x
NO.EA-206-170608
31
PCB LAYOUT
R1243S001x Ev al uation Board TOP VIEW
(The broad land of Lx section enable s a connection with large inductors and diodes).
R1243S001x Ev al uat i on Board TOP VIEW
R1243x
NO.EA-206-170608
32
R1243K001x Ev al uation Board TOP VIEW
R1243K001x Ev al uation Board TOP VIEW
R1243x
NO.EA-206-170608
33
TYPICAL PERFORMANCE CHARACTERISTICS
Note: Typical Characteristics are intended to be used as r eference data; t h ey are not guaranteed.
1) FB Voltage vs Temperature 2) Driver On Resistance vs Temperature
R1243x001x R1243x001x
3) Oscillator Frequency vs Temperature 4) Oscillator Frequency vs Temperature
R1243x001A/R1243x001B, R1243S001E R1243x001C/R1243x001D
5) Maxduty vs Temperature 6) Maxduty vs Temperature
R1243x001A/R1243x001B, R1243S001E R1243x001C/R1243x001D
(V
IN
=12V) (V
IN
=12V)
0.492
0.494
0.496
0.498
0.500
0.502
0.504
0.506
0.508
-50 -25 0 25 50 75 100
Ta (ºC)
FB Voltage (V)
100
150
200
250
300
-50 -25 0 25 50 75 100
Ta (ºC)
Driver On Resistance (mΩ)
(V
IN
=12V) (V
IN
=12V)
800
850
900
950
1000
1050
1100
1150
1200
-50 -25 0 25 50 75 100
Ta (ºC)
Frequency (kHz)
270
290
310
330
350
370
390
-50 -25 0 25 50 75 100
Ta (ºC)
Frequency (kHz)
(VIN=12V) (VIN=12V)
75
80
85
90
95
-50 -25 0 25 50 75 100
Ta (º C)
Maxduty (%)
75
80
85
90
95
-50 -25 0 25 50 75 100
Ta (º C)
Maxduty (%)
R1243x
NO.EA-206-170608
34
7) Fold-back Frequency vs Temperature 8) Fold-back Frequency vs Temperature
R1243x001A/R1243x001B R1243x001C/R1243x001D
9) FLG Voltage “L” vs. Input Voltage 10) FLG Voltage “L” vs. Temperature
R1243x001x R1243x001x
(V
CE
=0V, Ta=25ºC) (V
CE
=0V)
0.00
0.10
0.20
0.30
0.40
0 5 10 15 20 25 30
VIN (V)
FLG “L” Voltage (V)
0.00
0.10
0.20
0.30
0.40
-50 -25 0 25 50 75 100
Ta (ºC)
FLG “L” Voltage (V)
VIN=2V VIN=4.5V
VIN=12V VIN=30V
(VIN=12V) (VIN=12V)
15
20
25
30
35
-50 -25 025 50 75 100
Ta (ºC)
Foldback frequency ratio (%)
15
20
25
30
35
-50 -25 025 50 75 100
Ta (ºC)
Foldback frequency ratio (%)
R1243x
NO.EA-206-170608
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11) Soft-Start W aveform
R1243x001x R1243x001x
tSS = 0.4 ms tSS = 12 ms
(R1243S001A, VIN = 12 V, VOUT = 3.3 V, tSS = open, (R1243S001A, VIN = 12 V, VOUT = 3.3 V, CSS = 0.1 μ F,
VFLGIN = 5.0 V, ROUT = 3.3 Ω (IOUT = 1.0 A), Ta = 25ºC) VFLGIN = 5.0 V, ROUT = 3.3 Ω (IOUT = 1.0 A), Ta = 25ºC)
12) Output Voltage Wav eform (AC)
R1243x001A/R1243x001B, R1243S001E R1243x001C/R1243x001D
(R1243K001A, VIN = 12 V, VOUT = 3.3 V, L = 4.7 μH, (R1243K001D, VIN = 12 V, VOUT = 3.3 V, L = 10 μH,
COUT = 10 μF, ROUT = 3.3 Ω (IOUT = 1.0 A), Ta = 25ºC) COUT = 22 μF, ROUT = 3.3 Ω (IOUT =1.0 A), Ta = 25ºC)
13) Output Voltage Wav eform (AC), Load Transient Response
R1243x001A/R1243x001B, R1243S001E R1243x001C/R1243x001D
(R1243K001A, VIN = 12 V, VOUT = 3.3 V, L = 4.7 μH, (R1243K001A, VIN = 12 V, VOUT = 3.3 V, L = 4.7 μH,
COUT = 10 μF, IOUT = 1.0 A→2.0 A, Ta = 25ºC) COUT = 10 μF, IOUT = 2.0 A→1.0 A, Ta = 25ºC)
V
OUT
(AC) V
OUT
(AC)
(10mV/DIV) (10mV/DIV)
(400ns/DIV)
(1μs/DIV)
IOUT IOUT
(1A/DIV) (1A/DIV)
VOUT (AC) VOUT (AC)
(50mV/DIV) (50mV/DIV)
(10μs/DIV)
(10μs/DIV)
VCE VCE
(5V/DIV) (5V/DIV)
VOUT VOUT
(1V/DIV) (1V/DIV)
VFLG VFLG
(5V/DIV) (5V/DIV)
(100μs/DIV)
(4ms/DIV)
R1243x
NO.EA-206-170608
36
R1243x001C/R1243x001D R1243x001C/R1243x001D
(R1243K001D, VIN = 12 V, VOUT = 3.3 V, L = 10 μH, (R1243K001D, VIN = 12 V, VOUT = 3.3 V, L = 10 μH,
COUT = 22 μF, IOUT = 1.0 A→2.0 A, Ta = 25ºC) COUT = 10 μF, IOUT = 2.0 A→1.0 A, Ta = 25ºC)
14) Switching Operation Waveform
R1243x001A/R1243x001B, R1243S001E R1243x001A/R1243x001B, R1243S001E
(R1243K001A, VIN = 24 V, VOUT = 5.0 V, L = 4.7 μH, (R1243K001A, VIN = 24 V, VOUT = 5.0 V, L = 4.7 μH,
COUT = 10 μF, IOUT = 0 mA, Ta = 25ºC) COUT = 10 μF, R OUT = 5.0 Ω (IOUT = 1.0 A), Ta = 25ºC)
R1243x001C/R1243x001D R1243x001C/R1243x001D
(R1243K001D, VIN = 24 V, VOUT = 3.3 V, L = 10 μH, (R1243K001D, VIN = 24 V, VOUT = 3.3 V, L = 10 μH,
COUT = 22 μF, IOUT = 0 mA, Ta = 25ºC) COUT = 22 μF, ROUT = 3.3 Ω (IOUT = 1.0 A), Ta = 25ºC)
IOUT IOUT
(1A/DIV) (1A/DIV)
VOUT (AC) VOUT (AC)
(50mV/DIV) (50mV/DIV)
(10μs/DIV)
(10μs/DIV)
V
VIN
V
VIN
(5V/DIV) (5V/DIV)
VBST VBST
(5V/DIV) (5V/DIV)
V
LX
V
LX
(5V/DIV) (5V/DIV)
(1μs/DIV)
(200ns/DIV)
V
VIN
V
VIN
(5V/DIV) (5V/DIV)
VBST VBST
(5V/DIV) (5V/DIV)
V
LX
V
LX
(5V/DIV) (5V/DIV)
(1μs/DIV)
(1μs/DIV)
R1243x
NO.EA-206-170608
37
15) Limit-latch Operation Waveform 16) Latch-type Limit Detection Release Waveform
R1243x001A/R1243x001C R1243x001A/R1243x001C
(R1243K001A, VIN = 12 V, VOUT = 3.3 V, L = 4.7 μH, (R1243K001A, VIN = 12 V, VOUT = 3.3 V, L = 4.7 μH,
COUT = 10 μF, ROUT = 3.3 Ω→0.5 Ω, Ta = 25ºC) COUT = 10 μF, ROUT = 3.3 Ω→0.5 Ω→3.3 Ω, Ta = 25ºC)
17) Fold-back Operation Waveform 18) Fold-back Release Waveform
R1243x001B/R1243x001D R1243x001B/R1243x001D
(R1243S001D, VIN = 12 V, VOUT = 5.0 V, L = 10 μH, (R1243S001D, VIN = 12 V, VOUT = 5.0 V, L = 10 μH,
COUT = 22 μF, ROUT = 5.0 Ω→0.5 Ω, Ta = 25ºC) COUT = 22 μF, ROUT = 0.5 Ω→5.0 Ω, Ta = 25ºC)
VFLG VFLG
(5V/DIV) (5V/DIV)
VOUT VOUT
(1V/DIV) (1V/DIV)
IOUT IOUT
(1A/DIV) (1A/DIV)
(400μs/DIV)
(400μs/DIV)
VFLG VFLG
(5V/DIV) (5V/DIV)
VOUT VOUT
(1V/DIV) (1V/DIV)
ILIL
(1A/DIV) (1A/DIV)
IOUT IOUT
(1A/DIV) (1A/DIV)
(10μs/DIV)
(20μs/DIV)
R1243x
NO.EA-206-170608
38
19) Output Current vs. E fficiency
R1243x001A/R1243x001B, R1243S001E R1243x001A/R1243x001B, R1243S001E
VOUT = 0.8 V VOUT = 3.3 V
R1243x001A/R1243x001B, R1243S001E R1243x001A/R1243x001B, R1243S001E
VOUT = 5.0 V VOUT = 18 V
R1243x001C/R1243x001D R1243x001C/R1243x001D
VOUT = 0.8 V VOUT = 3.3 V
(Ta=25ºC) (Ta=25ºC)
0
10
20
30
40
50
60
70
80
90
100
110 100 1000 10000
I
OUT
(mA)
Efficiency (%)
VIN=5.0V
0
10
20
30
40
50
60
70
80
90
100
110 100 1000 10000
I
OUT
(mA)
Efficiency (%)
VIN=5.0V
VIN=12V
(Ta=25ºC) (Ta=25ºC)
0
10
20
30
40
50
60
70
80
90
100
110 100 1000 10000
IOUT (mA)
Efficiency (%)
VIN=12V
VIN=24V
0
10
20
30
40
50
60
70
80
90
100
110 100 1000 10000
IOUT (mA)
Efficiency (%)
VIN=24V
(Ta=25ºC) (Ta=25ºC)
0
10
20
30
40
50
60
70
80
90
100
110 100 1000 10000
I
OUT
(mA)
Efficiency (%)
VIN=5.0V
VIN=12V
0
10
20
30
40
50
60
70
80
90
100
110 100 1000 10000
I
OUT
(mA)
Efficiency (%)
VIN=5.0V
VIN=12V
VIN=24V
R1243x
NO.EA-206-170608
39
R1243x001C/R1243x001D R1243x001C/R1243x001D
VOUT = 5.0 V VOUT = 18 V
20)
出力電流対出力電圧特性例
R1243x001A/R1243x001B, R1243S001E R1243x001A/R1243x001B, R1243S001E
VOUT = 0.8 V VOUT = 3.3 V
R1243x001A/R1243x001B, R1243S001E R1243x001A/R1243x001B, R1243S001E
VOUT = 5.0 V VOUT = 18 V
(Ta=25ºC) (Ta=25ºC)
0
10
20
30
40
50
60
70
80
90
100
110 100 1000 10000
IOUT (mA)
Efficiency (%)
VIN=24V
0
10
20
30
40
50
60
70
80
90
100
110 100 1000 10000
IOUT (mA)
Efficiency (%)
VIN=12V
VIN=24V
(Ta=25ºC) (Ta=25ºC)
0.784
0.788
0.792
0.796
0.800
0.804
0.808
0.812
0.816
0500 1000 1500 2000
I
OUT
(mA)
Output Vol t age (V)
VIN=5.0V
3.24
3.26
3.28
3.30
3.32
3.34
3.36
0500 1000 1500 2000
I
OUT
(mA)
Output Vol t age (V)
VIN=5.0V
VIN=12V
(Ta=25ºC) (Ta=25ºC)
4.88
4.92
4.96
5.00
5.04
5.08
5.12
0500 1000 1500 2000
IOUT (mA)
Output Vol t age (V)
VIN=12V
VIN=24V
17.6
17.7
17.8
17.9
18.0
18.1
18.2
18.3
18.4
0500 1000 1500 2000
IOUT (mA)
Output Vol t age (V)
VIN=24V
R1243x
NO.EA-206-170608
40
R1243x001C/R1243x001D R1243x001C/R1243x001D
VOUT = 0.8 V VOUT = 3.3 V
R1243x001C/R1243x001D R1243x001C/R1243x001D
VOUT = 5.0 V VOUT = 18 V
21)
入力電圧対出力電圧特性例
R1243x001A/R1243x001B, R1243S001E R1243x001A/R1243x001B, R1243S001E
VOUT = 0.8 V VOUT = 3.3 V
(Ta=25ºC) (Ta=25ºC)
0.784
0.788
0.792
0.796
0.800
0.804
0.808
0.812
0.816
0500 1000 1500 2000
IOUT (mA)
Output Vol tage (V)
VIN=5.0V
VIN=12V
3.24
3.26
3.28
3.30
3.32
3.34
3.36
0500 1000 1500 2000
IOUT (mA)
Output Vol tage (V)
VIN=5.0V
VIN=12V
VIN=24V
(Ta=25ºC) (Ta=25ºC)
17.6
17.7
17.8
17.9
18.0
18.1
18.2
18.3
18.4
0500 1000 1500 2000
I
OUT
(mA)
Output Vol tage (V)
VIN=24V
4.88
4.92
4.96
5.00
5.04
5.08
5.12
0500 1000 1500 2000
I
OUT
(mA)
Output Vol tage (V)
VIN=12V
VIN=24V
(Ta=25ºC) (Ta=25ºC)
0.784
0.788
0.792
0.796
0.800
0.804
0.808
0.812
0.816
3.5 4.0 4.5 5.0 5.5 6.0
V
IN
(V)
Output Vol t age (V)
IOUT=0mA IOUT=10mA
IOUT=100mA IOUT=2000mA
3.24
3.26
3.28
3.30
3.32
3.34
3.36
3 6 9 12 15 18 21 24
V
IN
(V)
Output Vol t age (V)
IOUT=0mA IOUT=10mA
IOUT=100mA IOUT=2000mA
R1243x
NO.EA-206-170608
41
R1243x001A/R1243x001B, R1243S001E R1243x001A/R1243x001B, R1243S001E
VOUT = 5.0 V VOUT = 18 V
R1243x001C/R1243x001D R1243x001C/R1243x001D
VOUT = 0.8 V VOUT = 3.3 V
R1243x001C/R1243x001D R1243x001C/R1243x001D
VOUT = 5.0 V VOUT = 18 V
(Ta=25ºC) (Ta=25ºC)
0.784
0.788
0.792
0.796
0.800
0.804
0.808
0.812
0.816
3.5 4.0 4.5 5.0 5.5 6.0
V
IN
(V)
Output Vol tage (V)
IOUT=0mA IOUT=10mA
IOUT=100mA IOUT=2000mA
3.24
3.26
3.28
3.30
3.32
3.34
3.36
3 6 9 12 15 18 21 24 27 30
V
IN
(V)
Output Vol tage (V)
IOUT=0mA IOUT=10mA
IOUT=100mA IOUT=2000mA
(Ta=25ºC) (Ta=25ºC)
4.88
4.92
4.96
5.00
5.04
5.08
5.12
3 6 9 12 15 18 21 24 27 30
V
IN
(V)
Output Vol tage (V)
IOUT=0mA IOUT=10mA
IOUT=100mA IOUT=2000mA
17.6
17.7
17.8
17.9
18.0
18.1
18.2
18.3
18.4
16 18 20 22 24 26 28 30
V
IN
(V)
Output Vol tage (V)
IOUT=0mA IOUT=10mA
IOUT=100mA IOUT=2000mA
(Ta=25ºC) (Ta=25ºC)
4.88
4.92
4.96
5.00
5.04
5.08
5.12
36912 15 18 21 24 27 30
V
IN
(V)
Output Vol tage (V)
IOUT=0mA IOUT=10mA
IOUT=100mA IOUT=2000mA
17.6
17.7
17.8
17.9
18.0
18.1
18.2
18.3
18.4
16 18 20 22 24 26 28 30
V
IN
(V)
Output Vol tage (V)
IOUT=0mA IOUT=10mA
IOUT=100mA IOUT=2000mA
POWER DISSIPAT I ON HSOP-8E
Ver. A
i
The power dissipation of the package is dependent on PCB material, layout, and environmental conditions.
The following conditions are used in this measurement.
Measurement Conditions
Ultra-High Wattage Land Pattern
Environment Mounting on Board (Wind Velocity = 0 m/s)
Board Material Glass Cloth Epoxy Plastic (Four-Layer Board)
Board Dimensions 76.2 mm × 114.3 mm × 0.8 mm
Copper Ratio Outer Layers (First and Fourth Layers): Approx. 95% of 50 mm Square
Inner Layers (Second and Third Layers): Approx. 100% of 50 mm Square
Through-holes φ 0.4 mm × 21 pcs
Measurement Result (Ta = 25°C, Tjmax = 125°C)
Ultra-High Wattage Land Pattern
Power Dissip ati on 2.9 W
Thermal Resistance
θja = (125 − 25°C) / 2.9 W = 35°C/W
θjc = 10°C/W
IC Mount Area (mm)
Power Dissipation vs. Ambient Temperature
Measurement Board Pattern
Power Dissip ati on (W)
0
25 50 75 100 125 150
Ambient Temperature (°C)
4.0
3.0
2.0
1.0
0 85
Ultra-
High Wattage Land Pattern
2.9
40
50
76.2
114.3
50
POWER DISSIPAT I ON DFN(PLP)2527-10
Ver. A
i
The power dissipation of t he package is dependent on PCB material, layout, and environmental conditions. The following conditions are
used in this measurement.
Measurement Conditi ons
High Wattage Land Pattern Standard Land Pattern
Environment Mounting on Board (Wi nd Velocity = 0 m/s) Mounting on B oard (Wi nd Velocity = 0 m/s)
Board Material Glass Cloth Epoxy Pla s tic (Four-Layer Board) Glass Cloth Epoxy Plast ic (Double-Sided Board)
Board Dimensions 35 mm × 90 mm × 0.8 mm 40 mm × 40 mm × 1.6 mm
Copper Ratio Outer Layers (First and Fourth Layers): Approx.15%
Inner Layers (Second and Third Layers): Approx.15% Top Side: Approx. 50%
Bottom Si de: Approx. 50%
Copper Foil Thickness Outer Layers (First and Fourth Layers): Approx. 35 µm
Inner Layers (Second and Third Layers): Approx. 18 µm
Top Side: Approx. 35 µm
Bottom Si de: Approx. 35 µm
Through-holes
φ 0.3 mm × 9 holes
(connecting outer and inner layers to a package tab)
φ 0.5 mm × 10 holes
(connecting pins)
φ 0.54 mm × 30 holes
Measurement Result (Ta = 25°C, T j max = 125°C)
High Wattage Land Pattern Standard Land Pattern
Power Dissipation 1400 mW (Tjmax = 125°C) 910 mW (Tjmax = 125°C)
Thermal Resistanc e θja = (125 − 25°C) / 1.4 W = 71°C/W θj c = (125 − 25°C) / 0.91 W = 110°C/W
High Wattage
Standard
IC Mount Area (mm)
Power Dissipation vs. Ambient Temperature
Measurement Board Pattern
40
40
Power Dissip ati on
(mW)
2000
1500
1000
500
0
0
25 50 75 100 125 150
Ambient Temperature (°C)
85
1400
High Wattage Land Pattern
Standard Lan d Patt er n
910
PACKAGE DIMENSIONS
DFN(PLP)2527-10
Ver. A
i
DFN(PLP)2527-10 Package Dimensions
∗ The tab on the bottom of the package is substrate level (GND). It is recommended that the tab be connected to the
ground plane on the board, or otherwise be left floating.
2.50
2.70
A B
0.05
X4
INDEX
0.6max.
0.05min.
S0.05 S
6 10
5 1
0.25±0.1
0.25±0.1
0.10nom.
0.30±0.1
1.5±0.1
0.50
0.20±0.1 0.05
M
AB
2.3±0.1
φ 0.5±0.05
∗
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transportationequipment,combustionequipment,safetydevices,lifesupportsystemetc.)shouldfirstcontactus.
6.Wearemakingourcontinuousefforttoimprovethequalityandreliabilityofourproducts,butsemiconductorproducts
arelikelytofailwithcertainprobability.Inordertopreventanyinjurytopersonsordamagestopropertyresultingfrom
suchfailure,customersshouldbecarefulenoughtoincorporatesafetymeasuresintheirdesign,suchasredundancy
feature,firecontainmentfeatureandfail-safefeature.Wedonotassumeanyliability
orresponsibilityforanylossor
damagearisingfrommisuseorinappropriateuseoftheproducts.
7.Anti-radiationdesignisnotimplementedintheproductsdescribedinthisdocument.
8.The X-ray exposure can influence functions and characteristics of the products. Confirm the product functions and
characteristicsintheevaluationstage.
9.WLCSP products should be used in light shielded environments. The light exposure can influence functions and
characteristicsoftheproductsunderoperationorstorage.
10.There can be variation in the marking when different AOI (Automated Optical Inspection) equipment is used. In the
caseofrecognizingthemarkingcharacteristicwithAOI,pleasecontactRicohsalesorourdistributorbeforeattempting
touseAOI.
11.
PleasecontactRicohsalesrepresentativesshouldyouhaveanyquestionsorcommentsconcerningtheproductsor
thetechnicalinformation.
