ECL input and outputs Delays stable and precise 32-pin DIP package (.250 high) Available in delays from 11 to 1000ns 10% tapseach isolated and with 70 ECL DC fan-out capacity Fast rise time on all outputs design notes The DIP Series Logic Delay Modules developed by Engin- eered Components Company have been designed to provide precise tapped delays with required driving and pick-off circuitry contained in a single 32-pin DIP package compatible with ECL 10,000 series circuits, These logic delay modules are of hybrid construction utilizing the proven technologies of active inte- grated circuitry and of passive networks utilizing capacitive, inductive and resistive elements. The ICs utilized in these modules are burned-in to Level B of MIL-STD-883 to ensure a high MTBF. The MTBF on these modules, when calculated per MIL-HOBK-2176 for a 50C ground fixed environment, is in excess of 1.5 million hours. Module design includes compensation for propagation delays and incorporates internal termination at the output; no additional external components are needed to obtain the desired delay. The DECLDM is offered in 23 delays from 11ns to 1000ns with each module incorporating taps at 10% increments of total 2 L engineered components company low profile ECL COMPATIBLE DOUBLE LOGIC DELAY MODULE delay. Delay tolerances and rise times are maintained as shown in the accompanying part number table, when tested under the Test Conditions" shown. Delay time is measured at the -1.3V level on the leading edge; rise times are measured from 20% to 80% pulse amplitude, Temperature coefficient of delay is apprax- imately +300 ppm/"C over the operating temperature range of -30 to +85C. These modules accept either logic 1" or logic O" inputs and reproduce the logic at the selected output tap without inversion, The delay modules are intended primarily for use with positive going pulses and are calibrated to the tolerances shown in the table on rising edge delay; where best accuracy is desirecl in appli- cations using falling edge timing, it is recommended that a special unit be calibrated for the specific application, Each module has the capability of driving up to 70 ECL DC loads on any one tap. These DIP Series modules are packaged in a 32-pin DIP housing, molded of flame-proof Diallyl Phthalate per MIL-M-14, Type SDG-F, and are fully encapsulated in epoxy resin, Flat metal leads meet the solderability requirements of MIL-STD-202, Method 208. Leads provide positive standoff fram the printed circuit board to permit solder-fillet formation and flush clean- ing of solder-flux residues for improved reliability. Marking consists of manufacturer's mare, logo {EC2}, part number, terminal identificatian and date code of manufacture, All marking is applied by silk screen process using white epoxy paint in accordance with MIL-STD-130, to meet the permanency of identification required by MIL-STB-202, Method 215, 3580 Sacramento Drive, P.O. Box 8121, San Luis Obispo, CA 93403-8121 Phone: (805) 544-3800BLOCK DIAGRAM IS SHOWN BELOW MECHANICAL DETAIL IS SHOWN BELOW Vee 10% 30% 50% Vee 60% 80% OUT 1.600 oe 327 31 30 29 24 23 22 21 | mets d banter i f [vias lv 6 8 OUT * x ] 480]@ DECLDM- ___ l | { VY 24 IN VelV 79 Ve | 1 o ia s 19 i Swe 025 | DELAY LINE WITH enh ig [, ECLORIVER > cer iooovrickorr | | Me MAT le ' | | | WY VU TT jae | | 012 TYP. 18 TYP. Es -100 i P. 1 3-5 8 9 1112 16 TYP. Br a pene 150 TYP. Vee 20% 40% IN Vee Vee 70% 90% Vee 7" 5 Ooo olo oa a .300 OPERATING SPECIFICATIONS + t t Bag 8d & Bo oO *Supply valtage: se ee eee 5. 2V 25% to Vee (can be . | operated on +5 to Vcc) = L-.100 TYP. > ~ 100 TYP. Supply current: + eee ee ee ) 110ma typical bi .7 50 ere es Logic 1 input at 25C: TYP. Woltage see te ee ees - 98 min. Currant sss ee ee ee ee 265ua max. TEST CONDITIONS Logic 0 input at 25 C: 1. All measurements are made at 25C. Voltage sccrrteerrre += 1.65 man, 2. Vee supply voltage is maintained at 5.2V DC. pee ee eee Guraah, 3. All unit tested using a positive input pulse provided by a Logic 1 Voltage out at 96C: +. = 96 min. : ae ose Shadi = Logic 0 Voltage out at 95C: +> -1.65 max. standard open emitter ECL 10,000 gate. The input and out- Operating temperature range: -+ + -30 to +85 C. put utilize a 100 ohm pulldown resistor to - 2V; the output Storage temperature: +++ es ~55 to +125 'C, is also loaded with one ECL 10,000 gate. *Delays increase or decrease less than .5% for a respective @4. Input pulse width used is 5 to 10ns longer than full delay of increase or decrease of 5% in supply voltage. module under test; spacing between pulses (falling edge to PART NUMBER TABLE rising edge) is three times the pulse width used, # DELAYS AND TOLERANCES (in ns} Rise Part Number Lag Tap 1| Tap2 | Tap3 | Tap4 | Tap5S | Tap6 | Tap? | Tap8 | Tap9 | Output ax. DECLDM- 11 4 22.5 34.5 445 544 6+1 7+ B41 9+1 10 +1 1121 DECLDM- 20 4 2+.5 445 6+1 B41 1021 1221 1441 1621 18 1 2041 DECLDM- 30 A 34.5 6+1 g+t 1241 1521 18 +1 2141 2441.5] 2741.5] 3041.5 DECLDM-40 | 44.5 8+1 1221 | 1641 2041 2441.5] 2821.5} 3221.5] 3641.5) 4022 DECLDOM-50 4 5+1 1041 1521 | 20+1 25+1.5| 3021.5} 3541.5] 4042 | 45+2 50 +2 DECLDM-60 4 641 121 1B+1 | 2441.5] 3041.5] 3621.5| 4242 | 4822 | 5442 60 22.5 DECLDM-70 4 721 1441 2141 | 2841.5] 3541.5| 4242 | 4942 | 5622 | 6342 70 +2.5 DECLDM-80 4 +1 16+1 2441.5| 3241.5] 40+2 48+2 | 5642 | 6442.5) 7222.5] 8043 DECLDM-90 5 9+1 1841 2741.5| 3641.5| 4542 5442 | 6342 7222.5| 8123 90 +3 DECLOM- 100 5 | 10+1 20 +1 30+1.5| 40+2 50 +2 60+2.5| 70+2.5} 8023 | 9023 | 10043 DECLDM- 150 8 | 15 +1 30+1.5} 4542 | 6O+2.5| 7542.5] 9043 | 105%4 | 12024 | 13644 | 15045 DECLDM- 200 10 20+) 40 +2 6042.5] 80+3 100 +3 170+4 |140+5 | 160+5 | 180 +6 200 +6 DECLDM- 250 15 26+15] 50+2 7542.5) 100 3 125 +4 15045 | 17545 | 20046 | 22547 250 +8 DECLDOM- 300 15 3041.5) GO425) 9043 |120+4 150 +5 1BO+6 | 21047 | 24047 | 27048 300 +9 DECLDM-350 | 20 3541.5) 70425) 105+4 | 14025 175+5 | 210+7 | 245+8 | 28029 | 315210) 350+11 BECLDM-400 | 20 40 +2 8043 | 12044 | 16045 20046 | 24047 | 280+9 | 3204210 | 360211 | 400412 DECLDOM-450 | 25 45 +2 90+3 | 13544 |180+6 | 225+7 | 270+8 | 315+10 | 360411 | 405212 | 450414 DECLOM-500 | 25 50 +2 100+3 | 15045 |200=6 | 25048 | 300+9 | 350411 | 400 12 | 450414 | 500415 DECLOM-600 | 30 6O+2.5 |) 120+4 | 180=6 | 24027 300+9 | 360 +11 | 420213 | 48015 | 540416 | G00 +18 BECLDM-700 | 35 70+9.5| 14045 | 210+7 | 28049 | 350+11 | 42013| 490215 | 560217 | 630419 | 700 +20 DECLDM-800 |} 40 | 8043 160+5 | 240+7 |320410 | 400412 | 480215 | 560+17 | 640419 | 720420 | 800220 DECLOM-900 | 45 9043 180+6 | 27048 [360411 | 450414 | 540416 | 630419 | 720420 | 810420 | 900222 BECLDM- 1000); 50 |100+43 200+6 | 30049 |400+12 | 500415 | 600418 | 700420 | 800420 | 900 +22 |1000 222 @ All modules can be operated with a minimum input pulse width of 20% of full delay and pulse period approaching square wave; since delay accuracies may be somewhat degraded, it is suggested that the module be evaluated under the intended specific operating conditions. Special modules can be readily manufactured to improve accuracies and/or provide customer specified randam delay times far specific applications. Catalog No. C/O10480R