SN74VMEH22501A www.ti.com SCES3620A - DECEMBER 2004 - REVISED FEBRUARY 2010 8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS Check for Samples: SN74VMEH22501A FEATURES 1 * * * * * * * * * * * * * * Member of the Texas Instruments WidebusTM Family UBTTM Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Modes OECTM Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference (EMI) Compliant With VME64, 2eVME, and 2eSST Protocols Bus Transceiver Split LVTTL Port Provides a Feedback Path for Control and Diagnostics Monitoring I/O Interfaces Are 5-V Tolerant B-Port Outputs (-48 mA/64 mA) Y and A-Port Outputs (-12 mA/12 mA) Ioff, Power-Up 3-State, and BIAS VCC Support Live Insertion Bus Hold on 3A-Port Data Inputs 26- Equivalent Series Resistor on 3A Ports and Y Outputs Flow-Through Architecture Facilitates Printed Circuit Board Layout Distributed VCC and GND Pins Minimize High-Speed Switching Noise Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II * ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101) DGG OR DGV PACKAGE (TOP VIEW) DESCRIPTION/ORDERING INFORMATION The SN74VMEH22501A 8-bit universal bus transceiver has two integral 1-bit three-wire bus transceivers and is designed for 3.3-V VCC operation with 5-V tolerant inputs. The UBTTM transceiver allows transparent, latched, and flip-flop modes of data transfer, and the separate LVTTL input and outputs on the bus transceivers provide a feedback path for control and diagnostics monitoring. This device provides a high-speed interface between cards operating at LVTTL logic levels and VME64, VME64x, or VME320 (1) backplane topologies. The SN74VMEH22501A is pin-for-pin capatible to the SN74VMEH22501 (TI literature number SCES357), but operates at a wider operating temperature (-40C to 85C) range. (1) VME320 is a patented backplane construction by Arizona Digital, Inc. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2004-2010, Texas Instruments Incorporated SN74VMEH22501A SCES3620A - DECEMBER 2004 - REVISED FEBRUARY 2010 www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) High-speed backplane operation is a direct result of the improved OECTM circuitry and high drive that has been designed and tested into the VME64x backplane model. The B-port I/Os are optimized for driving large capacitive loads and include pseudo-ETL input thresholds (1/2 VCC 50 mV) for increased noise immunity. These specifications support the 2eVME protocols in VME64x (ANSI/VITA 1.1) and 2eSST protocols in VITA 1.5. With proper design of a 21-slot VME system, a designer can achieve 320-Mbyte transfer rates on linear backplanes and, possibly, 1-Gbyte transfer rates on the VME320 backplane. All inputs and outputs are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. Active bus-hold circuitry holds unused or undriven 3A-port inputs at a valid logic state. Bus-hold circuitry is not provided on 1A or 2A inputs, any B-port input, or any control input. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff circuitry prevents damaging current to backflow through the device when it is powered off/on. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability. When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, output-enable (OE and OEBY) inputs should be tied to VCC through a pullup resistor and output-enable (OEAB) inputs should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the drive capability of the device connected to this input. ORDERING INFORMATION TA -40C to 85C (1) 2 PACKAGE (1) ORDERABLE PART NUMBER TOP-SIDE MARKING BGA MicroStarTM Junior - ZQL Tape and reel SN74VMEH22501AZQLR VK501A TSSOP - DGG Tape and reel SN74VMEH22501ADGGR VMEH22501A TVSOP - DGV Tape and reel SN74VMEH22501ADGVR VK501A VFBGA - GQL Tape and reel SN74VMEH22501AGQLR VK501A Package drawings, thermal data, and symbolization are available at www.ti.com/sc/packaging. Submit Documentation Feedback Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): SN74VMEH22501A SN74VMEH22501A www.ti.com SCES3620A - DECEMBER 2004 - REVISED FEBRUARY 2010 GQL OR ZQL PACKAGE (TOP VIEW) TERMINAL ASSIGNMENTS (1) (1) 1 2 3 4 5 6 A 1OEBY NC NC NC NC 1OEAB B 1Y 1A GND GND VCC 1B C 2Y 2A VCC VCC BIAS VCC 2B D 3A1 2OEBY GND GND 2OEAB 3B1 E 3A2 LE VCC 3B2 F 3A3 OE VCC 3B3 G 3A4 CLKBA GND GND CLKAB 3B4 H 3A5 3A6 VCC VCC 3B6 3B5 J 3A7 3A8 GND GND 3B8 3B7 K DIR NC NC NC NC VCC NC - No internal connection Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): SN74VMEH22501A Submit Documentation Feedback 3 SN74VMEH22501A SCES3620A - DECEMBER 2004 - REVISED FEBRUARY 2010 www.ti.com FUNCTIONAL DESCRIPTION The SN74VMEH22501A is a high-drive (-48/64 mA), 8-bit UBT transceiver containing D-type latches and D-type flip-flops for data-path operation in transparent, latched, or flip-flop modes. Data transmission is true logic. The device is uniquely partitioned as 8-bit UBT transceivers with two integrated 1-bit three-wire bus transceivers. Functional Description for Two 1-Bit Bus Transceivers The OEAB inputs control the activity of the 1B or 2B port. When OEAB is high, the B-port outputs are active. When OEAB is low, the B-port outputs are disabled. Separate 1A and 2A inputs and 1Y and 2Y outputs provide a feedback path for control and diagnostics monitoring. The OEBY inputs control the 1Y or 2Y outputs. When OEBY is low, the Y outputs are active. When OEBY is high, the Y outputs are disabled. The OEBY and OEAB inputs can be tied together to form a simple direction control where an input high yields A data to B bus and an input low yields B data to Y bus. 1-BIT BUS TRANSCEIVER FUNCTION TABLE INPUTS OEAB OEBY OUTPUT MODE Isolation L H Z H H A data to B bus L L B data to Y bus H L A data to B bus, B data to Y bus True driver True driver with feedback path Functional Description for 8-Bit UBT Transceiver The 3A and 3B data flow in each direction is controlled by the OE and direction-control (DIR) inputs. When OE is low, all 3A- or 3B-port outputs are active. When OE is high, all 3A- or 3B-port outputs are in the high-impedance state. FUNCTION TABLE INPUTS OUTPUT OE DIR H X Z L H 3A data to 3B bus L L 3B data to 3A bus The UBT transceiver functions are controlled by latch-enable (LE) and clock (CLKAB and CLKBA) inputs. For 3A-to-3B data flow, the UBT operates in the transparent mode when LE is high. When LE is low, the 3A data is latched if CLKAB is held at a high or low logic level. If LE is low, the 3A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. The UBT transceiver data flow for 3B to 3A is similar to that of 3A to 3B, but uses CLKBA. 4 Submit Documentation Feedback Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): SN74VMEH22501A SN74VMEH22501A www.ti.com SCES3620A - DECEMBER 2004 - REVISED FEBRUARY 2010 Table 1. UBT TRANSCEIVER FUNCTION TABLE (1) INPUTS (1) (2) (3) OE LE H L OUTPUT 3B MODE Z Isolation CLKAB 3A X X X L H X B0 (2) L L L X B0 (3) L H X L L L H X H H L L L L L L H H Latched storage of 3A data True transparent Clocked storage of 3A data 3A-to-3B data flow is shown; 3B-to-3A data flow is similar, but uses CLKBA. Output level before the indicated steady-state input conditions were established, provided that CLKAB was high before LE went low Output level before the indicated steady-state input conditions were established The UBT transceiver can replace any of the functions shown in Table 2. Table 2. SN74VMEH22501A UBT Transceiver Replacement Functions FUNCTION 8 BIT Transceiver '245, '623, '645 Buffer/driver '241, '244, '541 Latched transceiver '543 Latch '373, '573 Registered transceiver '646, '652 Flip-flop '374, '574 SN74VMEH22501A UBT transceiver replaces all above functions Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): SN74VMEH22501A Submit Documentation Feedback 5 SN74VMEH22501A SCES3620A - DECEMBER 2004 - REVISED FEBRUARY 2010 www.ti.com LOGIC DIAGRAM (POSITIVE LOGIC) 48 1OEAB 1 1OEBY 2 46 1A 1B 3 1Y 2OEAB 2OEBY 41 8 43 5 2A 2Y OE DIR CLKAB LE 2B 6 14 24 32 11 17 CLKBA 9 3A1 1D C1 CLK 40 3B1 1D C1 CLK To Seven Other Channels Pin numbers shown are for the DGG and DGV packages. 6 Submit Documentation Feedback Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): SN74VMEH22501A SN74VMEH22501A www.ti.com SCES3620A - DECEMBER 2004 - REVISED FEBRUARY 2010 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC, BIAS VCC Supply voltage range VI Input voltage range (2) VO Voltage range applied to any output in the high-impedance or power-off state VO Voltage range applied to any output in the high or low state (2) IO Output current in the low state IO Output current in the high state IIK IOK Tstg (1) (2) (3) 4.6 V -0.5 7 V V -0.5 7 3A port or Y output -0.5 VCC + 0.5 B port -0.5 4.6 50 100 3A port or Y output -50 UNIT V mA mA B port -100 Input clamp current VI < 0 -50 mA Output clamp current VO < 0 or VO > VCC, B port -50 mA DGG package 70 DGV package 58 GQL/ZQL package 42 Storage temperature range -65 150 C/W C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. VCC, BIAS VCC Supply voltage VI Input voltage VIH High-level input voltage VIL Low-level input voltage IIK Input clamp current IOH High-level output current IOL Low-level output current t/v Input transition rise or fall rate t/VCC Power-up ramp rate TA Operating free-air temperature (2) -0.5 B port Recommended Operating Conditions (1) (1) MAX 3A port or Y output Package thermal impedance (3) qJA (2) MIN (2) MIN NOM MAX UNIT 3.15 3.3 3.45 V Control inputs or A port VCC 5.5 B port VCC 5.5 Control inputs or A port B port 2 V 0.5 VCC + 50 mV Control inputs or A port 0.8 B port 0.5 VCC - 50 mV -18 3A port and Y output -12 B port -48 3A port and Y output 12 B port 64 Outputs enabled 10 20 -40 V V mA mA mA ns/V ms/V 85 C All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS VCC = 3.3 V first, I/O second, and VCC = 3.3 V last, because the BIAS VCC precharge circuitry is disabled when any VCC pin is connected. The control inputs can be connected at any time, but normally are connected during the I/O stage. If B-port precharge is not required, any connection sequence is acceptable, but generally, GND is connected first. Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): SN74VMEH22501A Submit Documentation Feedback 7 SN74VMEH22501A SCES3620A - DECEMBER 2004 - REVISED FEBRUARY 2010 www.ti.com Electrical Characteristics over recommended operating free-air temperature range for A and B ports (unless otherwise noted) PARAMETER VIK VOH VCC = 3.15 V, II = -18 mA 3A port, any B ports, and Y outputs VCC = 3.15 V to 3.45 V, IOH = -100 mA 3A port and Y outputs VCC = 3.15 V Any B port VCC = 3.15 V 3A port, any B ports, and Y outputs VCC = 3.15 V to 3.45 V, 3A port and Y outputs VCC = 3.15 V VOL II IOZH (2) IOZL (2) MIN TYP (1) MAX TEST CONDITIONS -1.2 IOH = -6 mA 2.4 IOH = -12 mA 2 IOH = -24 mA 2.4 IOH = -48 mA 2 IOL = 100 mA 0.2 IOL = 6 mA 0.55 IOL = 12 mA 0.8 IOL = 24 mA 0.4 IOL = 48 mA 0.55 IOL = 64 mA 0.6 Control inputs, 1A and 2A VCC = 3.45 V, VI = VCC or GND 1 VCC = 0 or 3.45 V, VI = 5.5 V 5 VCC = 3.45 V, VO = VCC or 5.5 V 5 VCC = 3.45 V, VO = GND Any B port Ioff -5 -20 VCC = 0, BIAS VCC = 0, VI or VO = 0 to 5.5 V IBHL (3) 3A port VCC = 3.15 V, VI = 0.8 V IBHH (4) 3A port VCC = 3.15 V, VI = 2 V IBHLO (5) 3A port VCC = 3.45 V, IBHHO (6) 3A port VCC = 3.45 V, IOZ(PU/PD) ICC (4) (5) (6) (7) (8) 8 (8) 10 V mA mA mA mA 75 mA -75 mA VI = 0 to VCC 500 mA VI = 0 to VCC -500 mA VCC 1.5 V, VO = 0.5 V to VCC, VI = GND or VCC, OE = don't care VCC = 3.45 V, IO = 0, VI = VCC or GND, One data input switching at one-half clock frequency, 50% duty cycle ICCD (1) (2) (3) (7) VCC = 3.45 V, IO = 0, VI = VCC or GND ICC V VCC = 3.15 V 3A port and Y outputs V VCC - 0.2 Any B port 3A port, any B port, and Y outputs UNIT 10 Outputs high 30 Outputs low 30 Outputs disabled 30 Outputs enabled 76 Outputs disabled 19 VCC = 3.15 V to 3.45 V, One input at VCC - 0.6 V, Other inputs at VCC or GND mA mA mA/ clock MHz/ input 750 mA All typical values are at VCC = 3.3 V, TA = 25C. For I/O ports, the parameters IOZH and IOZL include the input leakage current. The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND, then raising it to VIL max. The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC, then lowering it to VIH min. An external driver must source at least IBHLO to switch this node from low to high. An external driver must sink at least IBHHO to switch this node from high to low. High-impedance state during power up or power down This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. Submit Documentation Feedback Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): SN74VMEH22501A SN74VMEH22501A www.ti.com SCES3620A - DECEMBER 2004 - REVISED FEBRUARY 2010 Electrical Characteristics (continued) over recommended operating free-air temperature range for A and B ports (unless otherwise noted) PARAMETER 1A and 2A inputs Ci Control inputs Co 1Y or 2Y outputs 3A port Cio Any B port MIN TYP (1) MAX TEST CONDITIONS 2.8 VI = 3.15 V or 0 VCC = 3.3 V, pF 2.6 VO = 3.15 V or 0 5.6 pF 7.9 VO = 3.3 V or 0 11 UNIT 12.5 pF Live-Insertion Specifications over recommended operating free-air temperature range for B port PARAMETER MAX UNIT VCC = 0 to 3.15 V, BIAS VCC = 3.15 V to 3.45 V, IO(DC) = 0 5 mA VCC = 3.15 V to 3.45 V (2), BIAS VCC = 3.15 V to 3.45 V, IO(DC) = 0 10 mA VO VCC = 0, BIAS VCC = 3.15 V to 3.45 V 1.7 V IO VCC = 0 ICC (BIAS VCC) (1) (2) MIN TYP (1) TEST CONDITIONS 1.3 1.5 VO = 0, BIAS VCC = 3.15 V -20 -100 VO = 3 V, BIAS VCC = 3.15 V 20 100 mA All typical values are at VCC = 3.3 V, TA = 25C. VCC - 0.5 V < BIAS VCC Timing Requirements for UBT Transceiver over recommended operating conditions (unless otherwise noted) (see Figure 1 and Figure 2) MIN fclock Clock frequency tw Pulse duration LE high 3A before LE tsu Setup time 3B before CLK 3B before LE 3A after CLK 3A after LE th Hold time 3B after CLK 3B after LE Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): SN74VMEH22501A UNIT 120 MHz 2.5 CLK high or low 3A before CLK MAX 3 Data high 2.1 Data low 2.2 CLK high 2 CLK low 2 Data high 2.5 Data low 2.7 CLK high 2 CLK low 2 Data high 0 Data low 0 CLK high 1 CLK low 1 Data high 0 Data low 0 CLK high 1 CLK low 1 Submit Documentation Feedback ns ns ns 9 SN74VMEH22501A SCES3620A - DECEMBER 2004 - REVISED FEBRUARY 2010 www.ti.com Switching Characteristics for Bus Transceiver Function over recommended operating conditions (unless otherwise noted) (see Figure 1 and Figure 2) PARAMETER tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ TO (OUTPUT) 1A or 2A 1B or 2B 1A or 2A 1Y or 2Y OEAB 1B or 2B OEAB 1B or 2B tr Transition time, B port (10%-90%) tf Transition time, B port (90%-10%) tPLH tPHL tPZH tPZL tPHZ tPLZ 10 FROM (INPUT) Submit Documentation Feedback MIN TYP MAX 5.1 8.9 4.5 7.8 7.2 14.5 6.1 13 4.6 8.1 3.7 7.4 3.3 9.7 1.8 4.8 4.3 1Y or 2Y OEBY 1Y or 2Y OEBY 1Y or 2Y ns ns ns ns ns 4.3 1B or 2B UNIT ns 1.6 5.6 1.6 5.6 1.2 5.6 1.8 4.9 1.4 5.4 1.7 4.5 ns ns ns Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): SN74VMEH22501A SN74VMEH22501A www.ti.com SCES3620A - DECEMBER 2004 - REVISED FEBRUARY 2010 Switching Characteristics for UBT Transceiver over recommended operating conditions (unless otherwise noted) (see Figure 1 and Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) MIN TYP MAX fmax 120 tPLH 5.5 9.3 4.7 8.3 3A 3B LE 3B CLKAB 3B OE 3B OE 3B tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tr Transition time, B port (10%-90%) tf Transition time, B port (90%-10%) tPLH 3B 3A LE 3A CLKBA 3A OE 3A OE 3A tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): SN74VMEH22501A UNIT MHz 6 10.6 4.9 8.7 5.8 10.1 4.6 8.4 4.6 9.3 3.5 8.5 4.8 9.3 2.4 5.7 4.3 ns ns ns ns ns ns 4.3 ns 1.7 5.9 1.7 5.9 1.7 5.9 1.7 5.9 1.4 5.5 1.4 5.5 1.5 6.2 2.1 5.5 1.8 6.2 2.3 5.6 Submit Documentation Feedback ns ns ns ns ns 11 SN74VMEH22501A SCES3620A - DECEMBER 2004 - REVISED FEBRUARY 2010 www.ti.com Skew Characteristics for Bus Transceiver for specific worst-case VCC and temperature within the recommended ranges of supply voltage and operating free-air temperature (see Figure 1 and Figure 2) PARAMETER tsk(LH) tsk(HL) tsk(LH) tsk(HL) tsk(t) (1) tsk(pp) (1) FROM (INPUT) TO (OUTPUT) 1A or 2A 1B or 2B 1B or 2B 1Y or 2Y 1A or 2A 1B or 2B 1.7 1B or 2B 1Y or 2Y 1.2 1A or 2A 1B or 2B 2.8 1B or 2B 1Y or 2Y 1.4 MIN MAX 0.8 0.7 0.7 0.6 UNIT ns ns ns ns tsk(t) - Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs of the same packaged device. The specifications are given for specific worst-case VCC and temperature and apply to any outputs switching in opposite directions, both low to high (LH) and high to low (HL) [tsk(t)]. Skew Characteristics for UBT for specific worst-case VCC and temperature within the recommended ranges of supply voltage and operating free-air temperature (see Figure 1 and Figure 2) PARAMETER tsk(LH) tsk(HL) tsk(LH) tsk(HL) tsk(LH) tsk(HL) tsk(LH) tsk(HL) tsk(t) (1) tsk(pp) (1) 12 FROM (INPUT) TO (OUTPUT) 3A 3B CLKAB 3B 3B 3A CLKBA 3A MIN MAX 1.3 1.1 0.8 0.8 0.7 0.6 0.7 0.6 3A 3B 1.9 CLKAB 3B 2.1 3B 3A 1.2 CLKBA 3A 1 3A 3B 2.8 CLKAB 3B 2.7 3B 3A 1.3 CLKBA 3A 1.2 UNIT ns ns ns ns ns ns tsk(t) - Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs of the same packaged device. The specifications are given for specific worst-case VCC and temperature and apply to any outputs switching in opposite directions, both low to high (LH) and high to low (HL) [tsk(t)]. Submit Documentation Feedback Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): SN74VMEH22501A SN74VMEH22501A www.ti.com SCES3620A - DECEMBER 2004 - REVISED FEBRUARY 2010 PARAMETER MEASUREMENT INFORMATION A PORT 6V S1 500 From Output Under Test Open TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH B-to-A Skew GND CL = 50 pF (see Note A) 500 S1 Open 6V GND Open LOAD CIRCUIT tw 3V 3V Timing Input 1.5 V 1.5 V Input 0V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 3V Data Input VCC/2 3V VCC/2 0V VCC/2 1.5 V 0V tPLZ tPZL 3V Input 1.5 V Output Control VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 0V tPLH Output Waveform 1 S1 at 6 V (see Note B) 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 3V 1.5 V VOL + 0.3 V VOL tPHZ tPZH tPHL VOH Output 1.5 V Output Waveform 2 S1 at GND (see Note B) VOH 1.5 V VOH - 0.3 V 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time, with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): SN74VMEH22501A Submit Documentation Feedback 13 SN74VMEH22501A SCES3620A - DECEMBER 2004 - REVISED FEBRUARY 2010 www.ti.com PARAMETER MEASUREMENT INFORMATION B PORT 6V 500 From Output Under Test S1 Open TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH A-to-B Skew GND CL = 50 pF (see Note A) 500 S1 Open 6V GND Open LOAD CIRCUIT tw 3V 3V Timing Input Input 1.5 V 0V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 3V Data Input 1.5 V 3V 1.5 V 0V 1.5 V 0V Output Waveform 1 S1 at 6 V (see Note B) VOH VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 3V VCC/2 Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ tPZH tPHL VCC/2 tPLZ tPZL 1.5 V tPLH 1.5 V 0V 3V Input 1.5 V Output Control VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output 1.5 V 1.5 V VOH VCC/2 VOH - 0.3 V 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time, with one transition per measurement. Figure 2. Load Circuit and Voltage Waveforms 14 Submit Documentation Feedback Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): SN74VMEH22501A SN74VMEH22501A www.ti.com SCES3620A - DECEMBER 2004 - REVISED FEBRUARY 2010 Distributed-Load Backplane Switching Characteristics The preceding switching characteristics tables show the switching characteristics of the device into the lumped load shown in the parameter measurement information (PMI) (see Figure 1 and Figure 2). All logic devices currently are tested into this type of load. However, the designer's backplane application probably is a distributed load. For this reason, this device has been designed for optimum performance in the VME64x backplane as shown in Figure 3. 5V 5V 330 0.42" 330 0.42" 0.84" 0.84" 0.42" 0.42" ZO Conn. 1.5" 470 Conn. ZO 1.5" Conn. 1.5" Conn. 1.5" Conn. 470 Conn. 1.5" 1.5" Rcvr Rcvr Rcvr Rcvr Rcvr Slot 2 Slot 3 Slot 19 Slot 20 Slot 21 Drvr Slot 1 Unloaded backplane trace natural impedence (ZO) is 45 . 45 to 60 is allowed, with 50 being ideal. Card stub natural impedence (Z ) is 60 . O Figure 3. VME64x Backplane The following switching characteristics tables derived from TI-SPICE models show the switching characteristics of the device into the backplane under full and minimum loading conditions, to help the designer better understand the performance of the VME device in this typical backplane. See www.ti.com/sc/etl for more information. Driver in Slot 11, With Receiver Cards in All Other Slots (Full Load) Switching Characteristics for Bus Transceiver Function over recommended operating conditions (unless otherwise noted) (see Figure 3) PARAMETER tPLH tPHL (1) (2) FROM (INPUT) TO (OUTPUT) 1A or 2A 1B or 2B MIN TYP (1) MAX 5.9 8.5 5.5 8.7 UNIT ns tr (2) Transition time, B port (10%-90%) 9 8.6 11.4 ns tf (2) Transition time, B port (90%-10%) 8.9 9 10.8 ns All typical values are at VCC = 3.3 V, TA = 25C. All values are derived from TI-SPICE models. All tr and tf times are taken at the first receiver. Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): SN74VMEH22501A Submit Documentation Feedback 15 SN74VMEH22501A SCES3620A - DECEMBER 2004 - REVISED FEBRUARY 2010 www.ti.com Switching Characteristics for UBT over recommended operating conditions (unless otherwise noted) (see Figure 3) PARAMETER tPLH tPHL tPLH tPHL tPLH tPHL (1) (2) FROM (INPUT) TO (OUTPUT) 3A 3B LE 3B CLKAB 3B MIN TYP (1) MAX 6.2 8.9 5.6 9 6.1 9.1 5.6 9 6.2 9.1 5.7 9 UNIT ns ns ns tr (2) Transition time, B port (10%-90%) 9 8.6 11.4 ns tf (2) Transition time, B port (90%-10%) 8.9 9 10.8 ns All typical values are at VCC = 3.3 V, TA = 25C. All values are derived from TI-SPICE models. All tr and tf times are taken at the first receiver. Skew Characteristics for Bus Transceiver for specific worst-case VCC and temperature within the recommended ranges of supply voltage and operating free-air temperature (see Figure 3) PARAMETER tsk(LH) tsk(HL) tsk(t) (2) tsk(pp) (1) (2) FROM (INPUT) TO (OUTPUT) 1A or 2A 1B or 2B 1A or 2A 1B or 2B 1A or 2A 1B or 2B MIN TYP (1) MAX 2.5 3 0.5 UNIT ns 1 ns 3.4 ns All typical values are at VCC = 3.3 V, TA = 25C. All values are derived from TI-SPICE models. tsk(t) - Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs of the same packaged device. The specifications are given for specific worst-case VCC and temperature and apply to any outputs switching in opposite directions, both low to high (LH) and high to low (HL) [tsk(t)]. Skew Characteristics for UBT for specific worst-case VCC and temperature within the recommended ranges of supply voltage and operating free-air temperature (see Figure 3) PARAMETER tsk(LH) tsk(HL) tsk(LH) tsk(HL) tsk(t) (2) tsk(pp) (1) (2) FROM (INPUT) TO (OUTPUT) 3A 3B CLKAB 3B MIN TYP (1) MAX 2.4 3.4 2.7 3.4 3A 3B 1 CLKAB 3B 1 3A 3B 0.5 3.4 CLKAB 3B 0.6 3.5 UNIT ns ns ns ns All typical values are at VCC = 3.3 V, TA = 25C. All values are derived from TI-SPICE models. tsk(t) - Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs of the same packaged device. The specifications are given for specific worst-case VCC and temperature and apply to any outputs switching in opposite directions, both low to high (LH) and high to low (HL) [tsk(t)]. Driver in Slot 1, With One Receiver in Slot 21 (Minimum Load) Switching Characteristics for Bus Transceiver Function over recommended operating conditions (unless otherwise noted) (see Figure 3) 16 Submit Documentation Feedback Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): SN74VMEH22501A SN74VMEH22501A www.ti.com SCES3620A - DECEMBER 2004 - REVISED FEBRUARY 2010 Switching Characteristics for Bus Transceiver Function (continued) over recommended operating conditions (unless otherwise noted) (see Figure 3) PARAMETER tPLH tPHL (1) (2) FROM (INPUT) TO (OUTPUT) 1A or 2A 1B or 2B MIN TYP (1) MAX 5.5 7.4 5.3 7.4 UNIT ns tr (2) Transition time, B port (10%-90%) 3.9 3.4 4.4 ns tf (2) Transition time, B port (90%-10%) 3.7 3.4 4.8 ns MIN TYP (1) MAX All typical values are at VCC = 3.3 V, TA = 25C. All values are derived from TI-SPICE models. All tr and tf times are taken at the first receiver. Switching Characteristics for UBT over recommended operating conditions (unless otherwise noted) (see Figure 3) PARAMETER FROM (INPUT) TO (OUTPUT) 3A 3B LE 3B CLKAB 3B tPLH tPHL tPLH tPHL tPLH tPHL (1) (2) 5.8 7.9 5.5 7.7 5.9 8 5.5 7.8 5.9 8.1 5.5 7.7 UNIT ns ns ns tr (2) Transition time, B port (10%-90%) 3.9 3.4 4.4 ns tf (2) Transition time, B port (90%-10%) 3.7 3.4 4.8 ns All typical values are at VCC = 3.3 V, TA = 25C. All values are derived from TI-SPICE models. All tr and tf times are taken at the first receiver. Skew Characteristics for Bus Transceiver for specific worst-case VCC and temperature within the recommended ranges of supply voltage and operating free-air temperature (see Figure 3) PARAMETER tsk(LH) tsk(HL) tsk(t) (2) tsk(pp) (1) (2) FROM (INPUT) TO (OUTPUT) 1A or 2A 1B or 2B 1A or 2A 1B or 2B 1A or 2A 1B or 2B MIN TYP (1) MAX 1.7 2.1 0.2 UNIT ns 1 ns 2.1 ns All typical values are at VCC = 3.3 V, TA = 25C. All values are derived from TI-SPICE models. tsk(t) - Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs of the same packaged device. The specifications are given for specific worst-case VCC and temperature and apply to any outputs switching in opposite directions, both low to high (LH) and high to low (HL) [tsk(t)]. Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): SN74VMEH22501A Submit Documentation Feedback 17 SN74VMEH22501A SCES3620A - DECEMBER 2004 - REVISED FEBRUARY 2010 www.ti.com Skew Characteristics for UBT for specific worst-case VCC and temperature within the recommended ranges of supply voltage and operating free-air temperature (see Figure 3) PARAMETER tsk(LH) tsk(HL) tsk(LH) tsk(HL) tsk(t) (2) tsk(pp) (1) (2) FROM (INPUT) TO (OUTPUT) 3A 3B CLKAB 3B MIN TYP (1) MAX 2 2.3 2.1 2.4 3A 3B 1 CLKAB 3B 1 3A 3B 0.2 2.5 CLKAB 3B 0.2 2.9 UNIT ns ns ns ns All typical values are at VCC = 3.3 V, TA = 25C. All values are derived from TI-SPICE models. tsk(t) - Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs of the same packaged device. The specifications are given for specific worst-case VCC and temperature and apply to any outputs switching in opposite directions, both low to high (LH) and high to low (HL) [tsk(t)]. By simulating the performance of the device using the VME64x backplane (see Figure 3), the maximum peak current in or out of the B-port output, as the devices switch from one logic state to another, was found to be equivalent to driving the lumped load shown in Figure 4. 5V 165 From Output Under Test 235 390 pF LOAD CIRCUIT Figure 4. Equivalent AC Peak Output-Current Lumped Load In general, the rise- and fall-time distribution is shown in Figure 5. Since VME devices were designed for use into distributed loads like the VME64x backplane (B/P), there are significant differences between low-to-high (LH) and high-to-low (HL) values in the lumped load shown in the PMI (see Figure 1 and Figure 2). 18 Submit Documentation Feedback Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): SN74VMEH22501A SN74VMEH22501A www.ti.com SCES3620A - DECEMBER 2004 - REVISED FEBRUARY 2010 6.4 6.2 Time - ns 6.0 5.8 LH 5.6 HL 5.4 5.2 5.0 Full B/P Load Minimum B/P Load PMI Lumped Load Figure 5. Characterization-laboratory data in Figure 6 and Figure 7 show the absolute ac peak output current, with different supply voltages, as the devices change output logic state. A typical nominal process is shown to demonstrate the devices' peak ac output drive capability. 137 162 136 160 135 Peak I O(HL) - mA Peak I O(LH) - mA 158 134 133 132 131 156 154 152 150 130 148 129 146 128 3.15 3.30 3.45 VCC - V 144 3.15 3.30 3.45 VCC - V Figure 6. Figure 7. Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): SN74VMEH22501A Submit Documentation Feedback 19 SN74VMEH22501A SCES3620A - DECEMBER 2004 - REVISED FEBRUARY 2010 www.ti.com TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREQUENCY A TO B SUPPLY CURRENT vs FREQUENCY B TO A 35 30 VCC = 3.15 V 30 25 CC(Enabled) - mA 25 VCC = 3.45 V 20 15 VCC = 3.3 V 20 VCC = 3.15 V 15 I I CC(Enabled) - mA VCC = 3.45 V VCC = 3.3 V 10 10 5 20 40 60 80 100 120 5 20 40 f - Switching Frequency - MHz Submit Documentation Feedback 80 100 120 f - Switching Frequency - MHz Figure 8. 20 60 Figure 9. Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): SN74VMEH22501A SN74VMEH22501A www.ti.com SCES3620A - DECEMBER 2004 - REVISED FEBRUARY 2010 TYPICAL CHARACTERISTICS HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 300 VCC = 3.15 V VOH - High-Level Output Voltage - V 250 VCC = 3.3 V 200 VCC = 3.45 V 150 100 50 0 0 10 20 30 40 50 60 70 80 90 100 IOH - High-Level Output Current - mA Figure 10. VOL vs IOL <br/> LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 4.0 VCC = 3.45 V VOL - Low-Level Output Voltage - V 3.5 VCC = 3.3 V 3.0 2.5 VCC = 3.15 V 2.0 1.5 1.0 0.5 0.0 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 IOL - Low-Level Output Current - mA Figure 11. VOH vs IOH Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): SN74VMEH22501A Submit Documentation Feedback 21 SN74VMEH22501A SCES3620A - DECEMBER 2004 - REVISED FEBRUARY 2010 www.ti.com VMEbus Summary In 1981, the VMEbus was introduced as a backplane bus architecture for industrial and commercial applications. The data-transfer protocols used to define the VMEbus came from the MotorolaTM VERSA bus architecture that owed its heritage to the then recently introduced Motorola 68000 microprocessor. The VMEbus, when introduced, defined two basic data-transfer operations: single-cycle transfers consisting of an address and a data transfer, and a block transfer (BLT) consisting of an address and a sequence of data transfers. These transfers were asynchronous, using a master-slave handshake. The master puts address and data on the bus and waits for an acknowledgment. The selected slave either reads or writes data to or from the bus, then provides a data-acknowledge (DTACK*) signal. The VMEbus system data throughput was 40 Mbyte/s. Previous to the VMEbus, it was not uncommon for the backplane buses to require elaborate calculations to determine loading and drive current for interface design. This approach made designs difficult and caused compatibility problems among manufacturers. To make interface design easier and to ensure compatibility, the developers of the VMEbus architecture defined specific delays based on a 21-slot terminated backplane and mandated the use of certain high-current TTL drivers, receivers, and transceivers. In 1989, multiplexing block transfer (MBLT) effectively increased the number of bits from 32 to 64, thereby doubling the transfer rate. In 1995, the number of handshake edges was reduced from four to two in the double-edge transfer (2eVME) protocol, doubling the data rate again. In 1997, the VMEbus International Trade Association (VITA) established a task group to specify a synchronous protocol to increase data-transfer rates to 320 Mbyte/s, or more. The unreleased specification, VITA 1.5 [double-edge source synchronous transfer (2eSST)], is based on the asynchronous 2eVME protocol. It does not wait for acknowledgement of the data by the receiver and requires incident-wave switching. Sustained data rates of 1 Gbyte/s, more than ten times faster than traditional VME64 backplanes, are possible by taking advantage of 2eSST and the 21-slot VME320 star-configuration backplane. The VME320 backplane approximates a lumped load, allowing substantially higher-frequency operation over the VME64x distributed-load backplane. Traditional VME64 backplanes with no changes theoretically can sustain 320 Mbyte/s. From BLT to 2eSST - A Look at the Evolution of VMEbus Protocols by John Rynearson, Technical Director, VITA, provides additional information on VMEbus and can be obtained at www.vita.com. Maximum Data Transfer Rates FREQUENCY (MHz) DATE TOPOLOGY PROTOCOL DATA BITS PER CYCLE DATA TRANSFERS PER CLOCK CYCLE PER SYSTEM (Mbyte/s) BACKPLANE CLOCK 1981 VMEbus IEEE-1014 BLT 32 1 40 10 10 10 1989 VME64 MBLT 64 1 80 10 1995 VME64x 2eVME 64 2 160 10 20 1997 VME64x 2eSST 64 2-No Ack 160-320 10-20 20-40 1999 VME320 2eSST 64 2-No Ack 320-1000 20-62.5 40-125 Applicability Target applications for VME backplanes include industrial controls, telecommunications, simulation, high-energy physics, office automation, and instrumentation systems. 22 Submit Documentation Feedback Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): SN74VMEH22501A PACKAGE OPTION ADDENDUM www.ti.com 4-May-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) 74VMEH22501ADGGRE4 ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74VMEH22501ADGGRG4 ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74VMEH22501ADGVRE4 ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74VMEH22501ADGVRG4 ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74VMEH22501ADGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74VMEH22501ADGVR ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74VMEH22501AGQLR LIFEBUY BGA MICROSTAR JUNIOR GQL 56 1000 TBD SNPB Level-1-240C-UNLIM SN74VMEH22501AZQLR ACTIVE BGA MICROSTAR JUNIOR ZQL 56 1000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com (3) 4-May-2012 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74VMEH22501A : * Enhanced Product: SN74VMEH22501A-EP NOTE: Qualified Version Definitions: * Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 23-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1.8 12.0 24.0 Q1 SN74VMEH22501ADGGR TSSOP DGG 48 2000 330.0 24.4 8.6 15.8 SN74VMEH22501ADGVR TVSOP DGV 48 2000 330.0 16.4 7.1 10.2 1.6 12.0 16.0 Q1 SN74VMEH22501AGQLR BGA MI CROSTA R JUNI OR GQL 56 1000 330.0 16.4 4.8 7.3 1.45 8.0 16.0 Q1 SN74VMEH22501AZQLR BGA MI CROSTA R JUNI OR ZQL 56 1000 330.0 16.4 4.8 7.3 1.5 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74VMEH22501ADGGR TSSOP DGG 48 2000 367.0 367.0 45.0 SN74VMEH22501ADGVR TVSOP DGV 48 2000 367.0 367.0 38.0 SN74VMEH22501AGQLR BGA MICROSTAR JUNIOR GQL 56 1000 333.2 345.9 28.6 SN74VMEH22501AZQLR BGA MICROSTAR JUNIOR ZQL 56 1000 333.2 345.9 28.6 Pack Materials-Page 2 MECHANICAL DATA MPDS006C - FEBRUARY 1996 - REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0-8 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins - MO-153 14/16/20/56 Pins - MO-194 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MECHANICAL DATA MTSS003D - JANUARY 1995 - REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0- 8 A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as "components") are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI's terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers' products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers' products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI's goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or "enhanced plastic" are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such components to meet such requirements. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP(R) Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2012, Texas Instruments Incorporated