3-36
TM
FN3179.2
ICL7660S
Super Voltage Converter
The ICL7660S Super Voltage Converter is a monolithic
CMOS voltage conversion IC that guarantees significant
performance advantages over other similar devices. It is a
direct replacement for the industry standard ICL7660 offering
an extended operating supply voltage range up to 12V, with
lower supply current. No external diode is needed for the
ICL7660S. In addition, a Frequency Boost pin has been
incorporated to enable the user to achieve lower output
impedance despite using smaller capacitors. All
improvements are highlighted in the Electrical Specifications
section. Critical parameters are guaranteed over the entire
commercial, industrial and military temperature ranges.
The ICL7660S performs supply voltage conversion from
positive to negative for an input range of 1.5V to 12V,
resulting in complem entary output voltages of -1.5V t o -12V.
Only 2 non-critical external capacitors are n eeded for the
charge pump and charge reservoir fu nction s. The ICL76 60S
can be connected to function as a voltage doubler and will
genera te up to 22. 8V wit h a 12V i nput. I t can als o be used as
a voltage multi plier or voltage divider.
The chip contains a seri es DC power supply regulat or, RC
oscillator, voltage level translator, and f our output power
MOS switches. The oscillator , when unlo aded, osc ill ates at a
nominal frequency of 10kHz for an input sup ply voltage of
5.0V. This frequency can be lowered by the addition of an
external capacitor t o the “OSC” terminal, or the oscillator
may be over-dr iven by an external clock.
The “LV” ter minal may be tied to GND to byp ass the intern al
seri es regulator and imp rove low voltage (LV) operation. At
medium to hi gh voltages (3.5V to 12V), t he LV pin is left
float ing to prevent device latc hup.
Features
• Guaranteed Lower Max Supply Curren t for All
Temperature Ranges
• Wide Operating Voltage Range 1.5V to 12V
• 100% Tested at 3V
• No External Diode Over Full Temperat ure and Voltage
Range
• Boost Pin ( Pin 1) for Higher Swit ching Frequency
• Guaranteed Minim um Power Efficiency of 96%
• Improved Mini mu m Open Circuit Voltage Conversion
Efficiency of 99%
• Improved SCR Latchup Protection
• Simple Conversion of +5V Logic Supply to ±5V Supplies
• Simple Voltage Multipl ication VOUT = (-)nVIN
• Easy to Use - Requi res Only 2 External Non-Criti cal
Passive Components
• Improved Direct Replacement for In dustry Stan dard
ICL7660 and Other Second Source Devic es
Applications
• Simple Conversion of +5V to ±5V Suppl ies
• Volt age M ultiplicati on VOUT = ±nVIN
• Negative Supplies for Data Acquisition Systems and
Instrumentation
• RS232 Power Supplies
• Supply Splitte r, V OUT = ±VS/2
Pinouts
I CL 7 66 0S ( PD IP, S O IC)
TOP VIEW
ICL7660S (CAN)
TOP VIEW
Ordering Information
PART
NUMBER
TEMP.
RANGE
(oC) PACKAGE PKG. NO.
ICL7660SCBA 0 to 70 8 Ld P SOIC (N) M8.15
ICL7660SCPA 0 to 70 8 Ld PD IP E8.3
ICL7660SIBA -40 to 85 8 Ld P SOIC (N) M8.15
ICL7660SIPA -40 to 85 8 Ld PD IP E8.3
ICL7660SMTV
(Note) -55 to 125 8 Pin Metal Can T8.C
NOTE: Add /883B to part numbe r if 883 B pr ocessing is r equir ed.
BOOST
CAP+
GND
CAP-
1
2
3
4
8
7
6
5
V+
OSC
LV
VOUT
V+ (AND CASE)
LV
CAP+
CAP-
BOOST
GND
OSC
VOUT
2
4
6
1
3
7
5
8
Data S heet April 1999
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-8 88-INTERSIL or 321-724-7143 |Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
3-37
Absolute Maximum Ratings Thermal Information
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13.0V
LV and OSC Input Voltage (Note 1)
V+ < 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V+ + 0.3V
V+ > 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . .V+ -5.5V to V+ +0.3V
Current into LV (Note 1)
V+ > 3.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20µA
Output Short Duration
VSUPPLY ≤ 5.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Continuous
Storage Temperature Range . . . . . . . . . . . . . . . . . . -65oC to 150oC
Ope rat i ng Condi t io ns
Temperature Range
ICL7660SM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
ICL7660SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
ICL7660SC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Thermal R esistance (Typical, Note 2) θJA (oC/W) θJC (oC/W)
PDIP. . . . . . . . . . . . . . . . . . . . . . . . . . . 1 50 N/A
Plastic SOIC. . . . . . . . . . . . . . . . . . . . . 170 N/A
Metal Can. . . . . . . . . . . . . . . . . . . . . . . 155 70
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
CAUTIO N: Stresses abo ve those l ist ed in “A bsolut e Ma ximum R atings” may c ause per ma nent damag e to the dev ice. Thi s is a stres s only rating and oper ation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Connecting any terminal to voltages greater than V+ or less than GND may cause destructive latchup. It is recommended that no inputs from
sources operating from external supplies be applied prior to “power up” of ICL7660S.
2. θJA is me asured with the component mounted on an eval uation PC boa rd in free air.
Electrical Specifications V+ = 5V, TA = 25oC , O SC = Fr ee runnin g, Test Circuit Figure 12 , Un less Otherwise S pecified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Supply Current (Note 5) I+ RL = ∞, 25oC-80160µA
0oC < TA < +70oC--180µA
-40oC < TA < 85oC--180µA
-55oC < TA < 125oC--200µA
Supply Vo ltage Range - High
(N ote 6) V+HRL = 10K, L V O pen, TMIN < TA < TMAX 3.0 - 12 V
Supply Vo ltage Range - Lo w V+LRL = 10K, LV to GND, TMIN < T A < TMAX 1.5 - 3.5 V
Output Source Resistance ROUT IOUT = 2 0m A - 60 100 Ω
IOUT = 20mA, 0oC < TA < 70oC--120Ω
IOUT = 20mA, -25oC < TA < 8 5oC--120Ω
IOUT = 20mA, -55oC < TA < 1 25oC--150Ω
IOUT = 3mA, V+ = 2V, LV = GND,
0oC < TA < 70oC--250Ω
IOUT = 3mA, V+ = 2V, LV = GND,
-40oC < TA < 85oC--300Ω
IOUT = 3mA, V+ = 2V, LV = GND,
-55oC < TA < 125oC--400Ω
Oscillator Frequency (Note 5) fOSC COSC = 0, Pi n 1 Open or GND 5 10 - kHz
COSC = 0, Pin 1 = V+ - 35 - kHz
Power Efficiency PEFF RL = 5k Ω96 98 - %
TMIN < T A < TMAX RL = 5k Ω95 97 - -
Voltage Conversion Ef ficiency VOUTEFF RL = ∞99 99.9 - %
ICL7660S
3-38
Oscilla tor Impedance ZOSC V+ = 2V - 1 - MΩ
V+ = 5V - 100 - kΩ
NOTES:
3. Der ate linearly above 50oC by 5.5mW/oC
4. In the test circuit, there is no ext ernal capacito r app lied t o pin 7. However, w hen the device is plugge d into a test socket, there is usually a very
s mall but finite stray cap acitance presen t, of the or der of 5pF.
5. The Intersil ICL7660 S can o perat e without an external diode over the fu ll temperature and volta ge ran ge. This device will function in existing
designs w hich incorporate an external diode with no d egrada tion in ov erall circuit performance.
6. All signi ficant improvements over the industry standard ICL7660 are highlighted.
Electrical Specifications V+ = 5V, TA = 25oC , O SC = Fr ee runnin g, Test Circuit Figure 12 , Un less Otherwise S pecified (Continued)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Typical Performance Curves (Test Circuit Figure 12)
FIGURE 1. OPERA TING VOL T AGE AS A
FUNCTION OF TEMPERATURE FIGURE 2. OUTPUT SOURCE RESISTANCE AS A
FUNCTION OF SUPPLY VOLTAGE
FIGURE 3. OUTPUT SOURCE RESISTANCE AS A
FUNCTION OF TEMPERATURE FIGURE 4. POWER CONVERSION EFFICIENCY AS A
FUNCTION OF OSCILLATOR FREQUENCY
-55 -25 0 25 50 100 125
12
10
8
6
4
2
0
SUPPLY VOLTAGE (V)
TEMPERATURE (oC)
SUPPLY VOLTAGE RANGE
(NO DIODE REQUIRED)
250
200
150
100
50
0024681012
SUP PLY VO LTAG E (V)
OUTPUT SOURCE RESISTANCE (Ω)
TA = 125oC
TA = 25oC
TA = -55oC
350
300
250
200
150
100
50
0
OUTPUT SOURCE RESISTANCE (Ω)
-50 -25 0 25 50 75 100 125
TEMPERATURE (oC)
IOUT = 20mA,
V+ = 12V
IOUT = 20mA,
V+ = 5V
IOUT = 20mA,
V+ = 5V
IOUT = 3mA,
V+ = 2V
98
96
94
92
90
88
86
84
82
80
POWER CONVERSION EFFICIENCY (%)
100 1k 10k 50k
OSC FREQUENCY FOSC (H z )
V+ = 5V
TA = 25oC
IOUT = 1mA
ICL7660S
3-39
FIGURE 5. FREQUENCY OF OSCILLATION AS A FUNCTION
OF EXTERNAL OSCILLATOR CAPACITANCE FIGURE 6. UNLOADED OSCILLATOR FREQUENCY AS A
FUNCTION OF TEMPERATURE
FIGURE 7. OUTPUT VOLTAGE AS A FUNCTION
OF OUTPUT CURRENT FIGURE 8. SUPPLY CURRENT AND POWER CONVERSION
EFFICIENCY AS A FUNCTION OF LOAD
CURRENT
FIGURE 9. OUTPUT VOL TAGE AS A FUNCTION OF OUTPUT
CURRENT FIGURE 10. SUPPL Y CURRENT AND POWER CONVERSION
E FFI CIEN CY AS A FU NC TI ON OF LO AD CU RR EN T
Typical Performance Curves (Test Circuit Figure 12) (Continued)
1101001k
OSCILLATOR FREQUENCY fOSC (kHz)
10
9
8
7
6
5
4
3
2
1
0
COSC (pF)
V+ = 5V
TA = 25oC
OSCILLATOR FREQUENCY fOSC (kHz)
20
18
16
14
12
10
8
-55 -25 0 25 50 75 100 125
TEMPERATURE (oC)
V+ = 10V
V+ = 5V
OUTPUT VOLTAGE (V)
1
0
-1
-2
-3
-4
-5
010203040
LOAD CURRENT ( mA)
V+ = 5V
TA = 25oC
POWER CONVERSION EFFICIENCY (%)
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
LOAD CURRENT (mA)
010203040 5060
V+ = 5V
TA = 25oC
SUPPLY CURRENT (mA)
OUTPUT VOLTAG E (V)
2
1
0
-1
-2 012 34 5 6 789
LOAD CURRENT (mA)
TA = 25oC
V+ = 2V 100
90
80
70
60
50
40
30
20
10
0
16
14
12
10
8
6
4
2
0
0 1.5 3 4.5 6 7.5 9
LOAD CURRENT (mA)
V+ = 2V
TA = 25oC
POWER CONVERSION
EFFICIENCY (%)
SUPPLY CURRENT (mA) (NOTE 8)
ICL7660S
3-40
Detailed Description
The ICL7660S contains all the necessary circui try to
com plete a ne gative voltage converter, with t he exception of
2 external capacitors which may be ine xpensive 10µF
polarized electrolytic types. The mode of operation of the
device may be best underst ood by considering Figure 13,
which shows an idealized negative voltage converter.
Capaci tor C1 is char ged to a voltage, V+, for the half cycle
when switches S1 and S3 are cl osed. (Note: Swi tches S2
and S4 are open during this half cycle.) During the second
half cycle of operation, switches S2 and S4 are closed, with
S1 and S3 open, thereby shifti ng capacitor C1 to C2 suc h
that the volt age on C2 is exac tly V+, assuming ideal switches
and no load on C2. The ICL7660S approache s thi s ideal
situation more cl osely th an existing non-mechanical circuits.
In the ICL7660 S, th e 4 swit ches of Figu re 13 are MOS
power switches; S1 is a P-Channel d evices and S2, S3 and
S4 are N-Channel devices. T he main di fficulty with this
approa ch i s that in i ntegra ting t he swit ch es, th e substr ates of
S3 and S4 must always remain reverse biased with respect
to thei r sources, but not so much as to degr ade thei r “ON”
resistances. In additio n, at circuit sta rt up, and under output
short circu it condi t ions (VOUT = V+), th e o utput vo ltag e must
be sensed and the substrate bias adjusted accordingly.
Failure to accomplish this would result in high power losses
and probable device latchup.
This problem is eliminated in the ICL7660S by a logic network
w hich senses the outp ut voltag e (VOUT) together with the
level translators, and switches the substrates of S3 and S4 to
the correct level to maintain necessary reverse bias.
The voltage regula tor portion of the ICL7660S is an integral
part of the anti-latchup circuitry, however its inherent voltage
drop can degrade operati on at l ow voltages. Ther efore, to
improve low voltage operation “LV” pin should be connected
to GND, dis ablin g the re gulato r. For supply vo lt ages greater
than 3. 5V the LV terminal must be lef t open to insure latchup
proof operation, and prevent device damage.
Theoretical Power Efficiency
Considerations
In theory a voltage converter can approach 100% efficienc y
if certain conditi ons are met:
1. The dri ve circuitry consumes minimal power.
2. The out put swi tches hav e ext remely l ow ON res ist ance
and virtually no offset .
3. The imped ance of the pump and reservo ir cap acitors are
negli gible at the pump fr equency.
FIGURE 11. OUTPUT SOURCE RESISTANCE AS A FUNCTION OF OSCILLATOR FREQUENCY
NOTE:
7. These curves include in the supply current that current fed directly into the load RL from the V+ (See Figure 12). Thus, approximately half the
supply current goes directly to the positive side of the load, and the other half, through the ICL7660S, to the negative side of the load. Ideally,
VOUT ∼ 2VIN, IS ∼ 2IL, so VIN x IS ∼ VOUT x IL.
Typical Performance Curves (Test Circuit Figure 12) (Continued)
OUTPUT RESISTANCE (Ω)
400
300
200
100
0
100 1k 10k 100k
OSCILLATOR FREQUENCY (Hz)
V+ = 5V
TA = 25oC
I = 10mA
C1 = C2 =
10µF
C1 = C2 =
1µF
C1 = C2 =
100µF
1
2
3
4
8
7
6
5
+
-
C1
10µF
ISV+(+5V)
IL
RL
-VOU
T
C2
10µF
ICL7660S
V+
+
-
N
OTE: For large values of COSC (> 1000pF ) the valu es of C1 and C
2
s
hould be increased to 10 0µF.
FIGURE 12. ICL7660S TEST CIRCUIT
ICL7660S
3-41
The ICL7660S appr oaches these conditions for negat ive
volt age convers ion if large values of C1 and C2 are used.
ENERGY IS LOST ONLY IN THE TRANSFER OF CHARGE
BETWEEN CAPACITORS IF A CHANGE IN VOLTAGE
OCCURS. The energy lost is def ined by:
E = 1/2C1 (V12 - V22)
where V1 and V2 are the voltages on C1 during the pump
and transfer cycles. If the impedances of C1 and C2 are
relatively high at the pump frequency (refer t o Figure 13)
com pared to the value of RL, the re will be substantial
difference i n the voltages V1 and V2. Therefore it is not only
desi rable to make C2 as lar ge as po ssibl e to e limin ate out put
voltage rippl e, but also to employ a correspondi ngly large
value fo r C 1 in order to achieve maximum efficiency of
operation.
Do’s and D on’ts
1. Do not exceed maximum suppl y voltages.
2. Do not connect LV termi nal to GND for supply voltage
greater than 3.5V.
3. Do not shor t circui t the outpu t to V+ sup ply for sup ply
volt ages above 5.5V fo r extended periods, however, tran-
sient conditi ons including st art-up are okay.
4. Whe n using pol arize d capaci to rs, the + ter mina l of C1
must be connected to pin 2 of the ICL7660S and the +
terminal of C2 must be connected to GND.
5. If the vol tag e suppl y driving the ICL7 660S has a large
source impedance (25Ω - 30Ω), t hen a 2.2µF capacito r
from pin 8 to ground m ay be required to l imit rate of rise
of input voltage to less than 2V/µs.
6. User should insu re that t he o utput (pin 5) does not go
more p ositive than GND (pi n 3). Dev ice l atch up will oc cur
under these conditi ons.
A 1N914 or simi lar diode pl aced in par allel with C2 will
prevent the d evice from lat ching up under these condi-
tions. (Anode pin 5, Cathode pin 3).
Typical Applicatio ns
Simple Negative Vo ltage Con verter
The majority of applications will undoubted ly utilize the
ICL7660 S for generat ion of negat ive suppl y volt ages. Fi gure
14 shows typical connections to provide a negative supply
where a positive suppl y of +1. 5V to +12V i s available. Keep
in mind t hat pin 6 (LV) is tied to the sup ply negat iv e (GND)
for supply voltage below 3.5V.
The output characteristi cs of the circuit in Figure 14 can be
approximated by an ideal voltage source i n seri es with a
resistance as shown in Figu re 14B. The voltage sou rce has
a value of -(V+). The output impedance (RO) is a funct ion of
the ON resi stance of the int ernal MOS switches (shown in
Figure 13), the switching frequency, the value of C1 and C2,
and the ESR (equivalent series res istance) of C1 and C2. A
good first or der approximation for RO is :
Combining the four RSWX te r m s as RSW, we see that:
RSW, the total switch resistance, is a function of supply
voltage and temperature (See the Output Source Resistance
graphs), typically 23Ω at 2 5oC and 5V. Careful selection of C1
and C2 will reduce the remaining terms, minimizing the output
impedance. High value capacitors will reduce the 1/(fPUMP x
C1) component, and low ESR capacitors will lower the ESR
term. Increasing the oscillator frequency will reduce the
1/(fPUMP x C1) term, but may have the side effect of a net
in cr eas e in ou tpu t im pe da nce wh en C1 > 10µF and i s not lo ng
VOUT = -VI
N
C2
VIN
C1
S3S4
S1S2
82
4
33
5
7
FIGURE 13. IDEALIZED NEGATIVE VOLTAGE CONVERTER
RO ≅ 2(R SW1 + RSW3 + ESRC1) + 2(RSW2 + RSW4 + ESRC1)
+
1+ ESRC2fPUMP x
C1
(fPUMP = fOSC ,R
SWX = MOSFET sw itch resistance)
2
RO ≅ 2 x RSW + 1+ 4 x ESRC1 + ESRC2Ω
fPUMP x
C1
1
2
3
4
8
7
6
5
+
-
10µF
10µF
ICL7660S
VOUT = -V+ V++
-
ROVOU
T
V+
+
-
14A. 14B.
FIGURE 14 . SIMPLE NEGATIVE CONVERTER AND ITS
OUTPUT EQUIVALENT
ICL7660S
3-42
enough to fully char ge th e capacitors every cycle. In a typical
application where fOSC = 10kHz and C = C1 = C2 = 10µF:
Since the ESRs of the capacitors are reflected in the output
impedance multiplied by a factor of 5, a high value could
potentially swamp out a low 1/fPUMP x C1) te rm, r endering
an increase in switching frequency or filter capacitance
ineffecti ve. Typ ical elect rolyt ic cap acit ors m ay have ESRs as
high as 10Ω.
Output Ripple
ESR also affects the ripple voltage seen at the outp ut. The
tot al r ipple is det ermined by 2 volt ag es, A and B, as shown i n
Figure 15. Segment A is the voltage drop across the ESR of
C2 at the i nstant it goes f rom being charged by C1 (curr ent
flow i ng in to C2) to being discharged through the load
(current flowing out of C2). The magni tude of th is current
change is 2 x IOUT, hence the total drop is 2 x IOUT x
ESRC2V. Segment B i s the vol tage chang e across C2 d uri ng
tim e t 2, the half of the cycle when C2 supplies current the
load. T he drop at B i s IOUT x t2/C2V . The peak- to-peak rippl e
voltage is the sum of th ese voltage drops:
Ag ai n , a low ESR capa c it or wi ll re s u lt in a high e r
performance output.
Paralleling Devices
Any num ber of ICL7660S voltage converters may be
paralleled t o reduce outp ut resistance. The reservoir
capacitor, C2, serves all devices whil e each device requires
its own pump capacitor , C1. The resul tant output r esistance
would be approximately:
Cascading Devices
The I CL7660 S may be c ascaded a s sh own to p rod uce larger
negat ive multi plic ation of the initi al supply volt age. However,
due t o t he fi nite eff ici ency of eac h dev ice, the pr act ical limi t i s
10 de vices fo r light loa ds. The output voltage is defin ed by:
VOUT = -n(VIN),
where n is an integer representing the number of devices
cascaded. The resulting out put r esistance woul d be
approximately th e weighted sum of the individual ICL7660S
ROUT values.
Changing the ICL7660S Oscillator Frequency
It m ay be de si ra b le i n s o me ap pli ca t ion s , du e to no is e o r ot he r
considerations, to alter the oscillator frequency. This can be
achieved simply by one of several methods described below.
By connecting the Boost Pin (Pin 1) to V+, the osc il lato r
charge and di scharge current is increased and, hence, the
oscillator frequency is increased by approximately 31/2
times. Th e result is a decrease in the output impedance and
ripple. This is of major importance for surface mount
applica ti ons where capaci tor size and cost ar e cri ti cal.
Smaller cap acitors, e.g. 0.1µF, can be used in conjunction
with the Boost Pin in orde r t o achieve similar out put currents
comp ared to the device free runn ing with C1 = C2 = 10µF or
100µF. (Refer to graph of Output Source Resistance as a
Function of Os cillator Frequency).
Increasing the osci lla tor frequency can also be achieved by
overdriving the oscillator from an external clock, as shown in
Figure 18. In order to prevent device latchup, a 1kΩ resistor
must be used in series with the cl ock output. In a situation
where the designer has generated the external cl ock
frequency using TTL logic, the addi tion of a 10kΩ pullup
resistor to V+ supply is required. Note that the pump
frequency with exte rnal clocking, as with internal clocking,
will be 1/2 of the c lock fr equency. Output transi tio ns occ ur on
the positive goin g edge of t he clock.
It i s also pos sible to incr ease the conv ers ion ef fic iency of the
ICL7660S at low load l evels by lo weri ng the osci llator
frequency. This reduces t he sw it ching losses, and is shown
in Fig ure 19. However, lowering the oscillator fr equency will
cause an undesirable incre ase in the imp edance of the
pump (C1) and reservoir (C2) capacitors; this is overcome by
increasing the val ues of C1 and C2 by th e s a me factor that
the frequency has been reduced. For example, the addition
of a 100pF capacitor between pin 7 (OSC and V+ will lower
the oscillator frequency to 1k Hz from its nom inal frequency
of 10kHz (a multi ple of 10), and thereby necessitate
corresponding increa se in t he value of C1 and C2 (from
10µF to 100µF).
RO ≅ 2 x 23 + 1+ 4 x ESRC1 +
ESRC2
(5 x 103 x 10 x 10-6)
RO ≅ 46 + 20 + 5 x ESRCΩ
ROUT = ROUT (of ICL7660S)
n (number of devices)
V
RIPPLE 1
2f
PUMP C2
×
×
--------------------------------------------2 ESRC2IOUT
×+
≅
1
2
3
4
8
7
6
5
+
-
10µF
ICL7660S
VOUT
V+
+
-10µF
V+
CMOS
GATE
1kΩ
FIGURE 15. EXTERNAL CLOCKING
ICL7660S
3-43
Positive Vo ltage Doublin g
The ICL7660S may be employ ed to achieve positive voltage
doublin g using the circuit shown in Figure 20. In this
appli cation, the pump inve rter switches of the ICL7660S are
used to charge C1 to a voltage level of V+ -VF (where V+ is
the supply voltage and VF is the forwar d voltage on C1 plus
the supply vo lt age (V+) is appli ed through diode D2 to
capacitor C2. The voltage thus created on C2 becomes
(2V + ) - (2 V F) or twice the supply voltage minus the
combined forward voltage drops of diodes D1 and D2.
The source impedance of the output (VOUT) will depend on
the output current, but for V+ = 5V and an output curr ent of
10mA it wi ll be approximately 60Ω.
Combined Neg ative Vo ltage Con version and
Positive Supply Doubling
Figure 21 combines the func tions s hown in Fi gure 14 and
Figure 20 to provide negative vol tage conver sion and
positive voltage doubling si multaneously. This approach
would be, for exampl e, suitable for generating +9V and -5V
from an existing +5V suppl y. In this instance capacitors C1
and C3 perfor m the pump and reservoir funct ions
respectively for the generation of the negativ e voltage, while
capacitors C2 and C4 are pump and reservoir respect ively
for the doubled positive voltage. There is a penalty in this
configuration which combines both functions, however, in
that the so urce impedance s of the ge nera ted supp lies will be
som ewhat hig her due t o the fi nite im pedance of t he common
charge pump driver at pin 2 of the device.
Voltage Splitting
The bidirecti onal characteristi cs can also be us ed to split a
high supply in half, as shown in Figure 22. The combined
load wi ll be evenly sh are d between t he two sid es, and a hi gh
value resistor to the LV pin ensures start-up. Because the
switches share the load in parallel, the output impedance is
much lower th an in the sta ndar d circu its , and h igher cu rrent s
can be drawn f rom the device. By using this circuit, and then
the circuit of Figure 17, +15V can be converted (via +7.5 ,
and -7.5 to a nominal -15V, although with rather high series
output res istance (∼250Ω).
Regula t ed N egativ e Voltage Su ppl y
In Some cases, the output impe dance of the IC L7660S can
be a problem, parti cularly if the load current varies
substantiall y. The circuit of Figure 23 can be used to
overcome thi s by controlling the input voltage, via an
ICL7611 low-power CMOS op amp, in such a way as to
maint ain a near l y const ant output volt age . Direct fe edbac k is
inadvis able, since the ICL7 660S’s output does not respond
instantaneously to change in input, but only after the
switching delay. The circuit shown supplies enough delay to
accom m odate the ICL7660S, while maintaining adequate
feedback. An increase in pump and storage capacitors is
desirable, and the values shown pr ovides an output
impedance of less than 5Ω to a l oad of 10mA.
1
2
3
4
8
7
6
5
+
-
ICL7660S
VOUT
V+
+
-C2
C1
COSC
FIGURE 16. LOWERING OSCILLATOR FREQUENCY
1
2
3
4
8
7
6
5
ICL7660S
V+
D1
D2
C1
C2
VOUT =
(2V+) - (2VF)
+
-
+
-
N
OTE: D1 and D2 can be any suitable diode.
FIGURE 17. POSITIVE VOLTAGE DOUBLER
1
2
3
4
8
7
6
5
ICL7660S
V+
D1
D2
C4
VOUT = (2V+)
-
(VFD1) - (VFD2
)
+
-
C2
+
-
C3
+
-
VOUT = -VIN
C1+
-
FIGURE 1 8. COMBINED NEGATIVE VOLTAGE CONVERTER
AND POSITIVE DOUBLER
1
2
3
4
8
7
6
5
+
-
+
-
50µF
50µF
+
-
50µF
RL1
VOUT =V+ - V-
2ICL7660S
V+
V-
RL2
FIGURE 19. SPLITTING A SUPPLY IN HALF
ICL7660S
3-44
Other Applications
Further informat ion on the operatio n and use of the
ICL7660S may be found in AN051 “Principles and
Appli cations of the ICL7660 CM OS Volt age Converter”.
1
2
3
4
8
7
6
5
+
-
100µFICL7660S
100µF
VOUT
+
-10µF
ICL7611
+
-100Ω
50k
+8V
100k
50k
ICL8069
56k
+8V
800k 250k
VOLTAGE
ADJUST +
-
FIGURE 20. REGULAT ING THE OUTPUT VOLTAGE
1
2
3
4
8
7
6
5
+
-
ICL7660S
+
-
10µF
16
TTL DATA
INPUT
15
4
10µF
13 14
12 11
+5V LOGIC SUPPLY
RS232
DATA
OUTPUT
IH5142
1
3+5V
-5V
FIGURE 21. RS232 LEVELS FROM A SINGLE 5V SUPPLY
ICL7660S
