Integrated Circuit Solution Inc. 1
LPSR011-0B 06/06/2001
IC62LV12816L
IC62LV12816LL
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
DESCRIPTION
The 1+51 IC62LV12816L and IC62LV12816LL are high-speed,
2.097,152-bit static RAMs organized as 131,072 words by 16
bits. They are fabricated using 1+51's high-performance CMOS
technology. This highly reliable process coupled with innova-
tive circuit design techniques, yields high-performance and
low power consumption devices.
When CE is HIGH (deselected) or when CE is low and both LB
and UB are HIGH, the device assumes a standby mode at
which the power dissipation can be reduced by using CMOS
input levels.
Easy memory expansion is provided by using Chip Enable
Output and Enable inputs, CE and OE. The active LOW Write
Enable (WE) controls both writing and reading of the memory.
A data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
The IC62LV12816L and IC62LV12816LL are packaged in the
JEDEC standare 44-pin 400mil TSOP-2 and 48-pin 6*8mm
TF-BGA.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
CE
OE
WE
128K x 16
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VCC
I/O
DATA
CIRCUIT
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
UB
LB
IC62LV12816L
IC62LV12816LL
128K x 16 LOW VOLTAGE, ULTRA
LOW POWER CMOS STATIC RAM
FEATURES
High-speed access times: 55, 70, 100 ns
CMOS low power operation
-- 60 mW (typical) operating
-- 3 µW (typical) CMOS standby
TTL compatible interface levels
Single 2.7V-3.6V Vcc power supply
Fully static operation: no clock or refresh re-
quired
Three state outputs
Data control for upper and lower bytes
Industrial temperature available
Available in the 44-pin TSOP-2 and 48-pin
6*8mm TF-BGA
2Integrated Circuit Solution Inc.
LPSR011-0B 06/06/2001
IC62LV12816L
IC62LV12816LL
TRUTH TABLE
I/O PIN
Mode WEWE
WEWE
WE CECE
CECE
CE OEOE
OEOE
OE LBLB
LBLB
LB UBUB
UBUB
UB I/O0/-I/O7 I/O8-I/O15 Vcc Current
Not Selected X H X X X High-Z High-Z ISB, ISB
X L X H H High-Z High-Z ISB, ISB
Output Disabled H L H X X High-Z High-Z ICC
X L X H H High-Z High-Z ISB
Read H L L L H DOUT High-Z ICC
H L L H L High-Z DOUT
HLLLL DOUT DOUT
Write L L X L H DIN High-Z ICC
L L X H L High-Z DIN
LLXLL DIN DIN
PIN DESCRIPTIONS
A0-A16 Address Inputs
I/O0-I/O15 Data Input/Output
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
LB Lower-byte Control (l/O0-I/O7)
UB Upper-byte Control (l/O8-I/O15)
NC No Connection
Vcc Power
GND Ground
48-Pin TF-BGA
1 2 3 4 5 6
A
B
C
D
E
F
G
H
LB OE A0 A1 A2 N/C
I/O
8
UB A3 A4 CE I/O
0
I/O
9
I/O
10
A5 A6 I/O
1
I/O
2
GND I/O
11
NC A7 I/O
3
Vcc
Vcc I/O
12
NC A16 I/O
4
GND
I/O
14
I/O
13
A14 A15 I/O
5
I/O
6
I/O
15
NC A12 A13 WE I/O
7
NC A8 A9 A10 A11 NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
PIN CONFIGURATIONS
44-Pin TSOP-2
Integrated Circuit Solution Inc. 3
LPSR011-0B 06/06/2001
IC62LV12816L
IC62LV12816LL
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND 0.5 to Vcc + 0.5 V
TBIAS Temperature Under Bias 40 to +85 °C
VCC Vcc related to GND 0.3 to +4.0 V
TSTG Storage Temperature 65 to +150 °C
PTPower Dissipation 1.0 W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CAPACITANCE(1)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Output Capacitance VOUT = 0V 8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = 1 mA 2.0 V
VOL Output LOW Voltage VCC = Min., IOL = 2.1 mA 0.4 V
VIH Input HIGH Voltage 2.2 VCC + 0.2 V
VIL Input LOW Voltage 0.2 0.4 V
ILI Input Leakage GND £ VIN £ VCC 1 1 µA
ILO Output Leakage GND £ VOUT £ VCC, OUTPUTS DISABLED 1 1 µA
Notes:
1. VIL(min.) = 2.0V for pulse width less than 10 ns.
OPERATING RANGE
Range Ambient Temperature VCC
Commercial 0°C to +70°C 2.7V - 3.6V
Industrial 40°C to +85°C 2.7V - 3.6V
4Integrated Circuit Solution Inc.
LPSR011-0B 06/06/2001
IC62LV12816L
IC62LV12816LL
IC62LV12816L POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-55 -70 -100
Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit
ICC Vcc Dynamic Operating VCC = Max., Com. 40 30 20 mA
Supply Current IOUT = 0 mA, f = fMAX Ind. 45 35 25
ISBTTL Standby Current VCC = Max., Com. 0.5 0.5 0.5 mA
(TTL Inputs) VIN = VIH or VIL, Ind. 1.0 1.0 1.0
CE
£
VIH, f = 0
OR
ULB Control VCC = Max., VIN = VIH or VIL
CE
=
VIL, f = 0, UB
=
VIH, LB
=
VIH
ISB CMOS Standby VCC = Max., Com. 35 35 35 µA
Current (CMOS Inputs) CE
³
VCC  0.2V, Ind. 50 50 50
VIN
³
VCC  0.2V, or
VIN
£
0.2V, f = 0
OR
ULB Control VCC = Max., CE
=
VIL
VIN
£
0.2V, f = 0, UB / LB
=
VCC  0.2V
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0.4V to 2.2V
Input Rise and Fall Times 5 ns
Input and Output Timing 1.3V
and Reference Level
Output Load See Figures 1 and 2
AC TEST LOADS
Figure 1 Figure 2
5 pF
Including
jig and
scope
OUTPUT
1 TTL
100 pF
Including
jig and
scope
OUTPUT
1 TTL
Integrated Circuit Solution Inc. 5
LPSR011-0B 06/06/2001
IC62LV12816L
IC62LV12816LL
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-55 -70 -100
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tRC Read Cycle Time 55 70 100 ns
tAA Address Access Time 55 70 100 ns
tOHA Output Hold Time 10 10 15 ns
tACE CE Access Time 55 70 100 ns
tDOE OE Access Time 30 35 50 ns
tHZOE
 
OE to High-Z Output 20 25 30 ns
tLZOE
 
OE to Low-Z Output 5 5 5 ns
tHZCE
 
CE to High-Z Output 0 20 0 25 0 30 ns
tLZCE
 
CE to Low-Z Output 10 10 10 ns
tBA LB, UB Access Time 55 70 100 ns
tHZB LB, UB o High-Z Output 0 25 0 25 0 35 ns
tLZB LB. UB to Low-Z Output 0 0 0 ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.3V, input pulse levels
of 0.4V to 2.2V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
IC62LV12816LL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-55 -70 -100
Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit
ICC Vcc Dynamic Operating VCC = Max., Com. 40 30 20 mA
Supply Current IOUT = 0 mA, f = fMAX Ind. 45 35 25
ISBTTL Standby Current VCC = Max., Com. 0.5 0.5 0.5 mA
(TTL Inputs) VIN = VIH or VIL, Ind. 1.0 1.0 1.0
CE
³
VIH, f = 0
OR
ULB Control VCC = Max., VIN = VIH or VIL
CE
=
VIL, f = 0, UB
=
VIH, LB
=
VIH
ISB CMOS Standby VCC = Max., f = 0 Com. 10 10 10 µA
Current (CMOS Inputs) CE
³
VCC  0.2V, Ind. 15 15 15
VIN
³
VCC  0.2V, or
VIN
£
0.2V, f = 0
OR
ULB Control VCC = Max., CE
=
VIL
VIN
£
0.2V, f = 0, UB / LB
=
VCC  0.2V
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
6Integrated Circuit Solution Inc.
LPSR011-0B 06/06/2001
IC62LV12816L
IC62LV12816LL
tRC
tOHA
tAA
tDOE
tLZOE
tACE
tLZCE
tHZOE
HIGH-Z DATA VALID
tHZB
ADDRESS
OE
CE
LB, UB
DOUT
tHZCE
tBA
tLZB
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
AC WAVEFORMS
READ CYCLE NO. 2(1,3) (CS, OE, AND UB/LB Controlled)
AC TEST LOADS
READ CYCLE NO.1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)
DATA VALID
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
DOUT
ADDRESS
Integrated Circuit Solution Inc. 7
LPSR011-0B 06/06/2001
IC62LV12816L
IC62LV12816LL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
-55 -70 -100
Symbol Parameter Min. Max. Min. Max. Min. Max Unit
tWC Write Cycle Time 55 70 100 ns
tSCE CE to Write End 50 65 80 ns
tAW Address Setup Time to Write End 50 65 80 ns
tHA Address Hold from Write End 0 0 0 ns
tSA Address Setup Time 0 0 0 ns
tPWB LB, UB Valid to End of Write 45 60 80 ns
tPWE
"
WE Pulse Width 40 40 80 ns
tSD Data Setup to Write End 25 30 40 ns
tHD Data Hold from Write End 0 0 0 ns
tHZWE
!
WE LOW to High-Z Output 30 30 40 ns
tLZWE
!
WE HIGH to Low-Z Output 5 5 5 ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.3V, input pulse levels of 0.4V to 2.2V
and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CE LOW, and UB or LB, and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
4. Tested with OE HIGH
DATA UNDEFINED
t
WC
VALID ADDRESS
t
SCS
t
PWE1
t
PWE2
t
AW
t
HA
HIGH-Z
t
PWB
t
HD
t
SA
t
HZWE
ADDRESS
CS
UB, LB
WE
D
OUT
D
IN DATA
IN
VALID
t
LZWE
t
SD
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CS, Controlled, OE = HIGH or LOW)
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS and WE inputs and at least
one of the LB and UB inputs being in the LOW state.
2. WRITE = (CS) [ (LB) = (UB) ] (WE).
8Integrated Circuit Solution Inc.
LPSR011-0B 06/06/2001
IC62LV12816L
IC62LV12816LL
WRITE CYCLE NO. 2 (WE Controlled; OE is HIGH During Write Cycle)
DATA UNDEFINED
LOW
t WC
VALID ADDRESS
t PWE1
t AW
t HA
HIGH-Z
t PWB
t HD
t SA
t HZWE
ADDRESS
CS
UB, LB
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t LZWE
t SD
WRITE CYCLE NO. 3 (WE Controlled; OE is LOW During Write Cycle)
DATA UNDEFINED
t
WC
VALID ADDRESS
LOW
LOW
t
PWE2
t
AW
t
HA
HIGH-Z
t
PWB
t
HD
t
SA
t
HZWE
ADDRESS
CE
UB, LB
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
Integrated Circuit Solution Inc. 9
LPSR011-0B 06/06/2001
IC62LV12816L
IC62LV12816LL
DATA RETENTION SWITCHING CHARACTERISTICS (L/LL)
Symbol Parameter Test Condition Min. Max. Unit
VDR Vcc for Data Retention See Data Retention Waveform 1.5 3.6 V
IDR Data Retention Current Vcc = 2.0V, CE
³
Vcc  0.2V Com. (-L) 20 µA
Com. (-LL) 5 µA
Ind. (-L) 25 µA
Ind. (-LL) 7 µA
tSDR Data Retention Setup Time See Data Retention Waveform 0 ns
tRDR Recovery Time See Data Retention Waveform tRC ns
WRITE CYCLE NO. 4 (UB / LB Controlled)
DATA UNDEFINED
t
WC
ADDRESS 1 ADDRESS 2
t
WC
HIGH-Z
t
PWB
WORD 1
LOW
WORD 2
t
HD
t
SA
t
HZWE
ADDRESS
CS
UB, LB
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
t
PWB
DATA
IN
VALID
t
SD
t
HD
t
SA
t
HA
t
HA
DATA RETENTION WAVEFORM (CE Controlled)
V
CC
CE ≥ V
CC
- 0.2V
t
SDR
t
RDR
V
DR
CE
GND
2.7V
2.2V
Data Retention Mode
10 Integrated Circuit Solution Inc.
LPSR011-0B 06/06/2001
IC62LV12816L
IC62LV12816LL
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No. Package
55 IC62LV12816L-55T 400mil TSOP-2
IC62LV12816L-55B 6*8mm TF-BGA
70 IC62LV12816L-70T 400mil TSOP-2
IC62LV12816L-70B 6*8mm TF-BGA
100 IC62LV12816L-100T 400mil TSOP-2
IC62LV12816L-100B 6*8mm TF-BGA
Industrial Range: -40°C to +85°C
Speed (ns) Order Part No. Package
55 IC62LV12816L-55TI 400mil TSOP-2
IC62LV12816L-55BI 6*8mm TF-BGA
70 IC62LV12816L-70TI 400mil TSOP-2
IC62LV12816L-70BI 6*8mm TF-BGA
100 IC62LV12816L-100TI 400mil TSOP-2
IC62LV12816L-100BI 6*8mm TF-BGA
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No. Package
55 IC62LV12816LL-55T 400mil TSOP-2
IC62LV12816LL-55B 6*8mm TF-BGA
70 IC62LV12816LL-70T 400mil TSOP-2
IC62LV12816LL-70B 6*8mm TF-BGA
100 IC62LV12816LL-100T 400mil TSOP-2
IC62LV12816LL-100B 6*8mm TF-BGA
Industrial Range: -40°C to +85°C
Speed (ns) Order Part No. Package
55 IC62LV12816LL-55TI 400mil TSOP-2
IC62LV12816LL-55BI 6*8mm TF-BGA
70 IC62LV12816LL-70TI 400mil TSOP-2
IC62LV12816LL-70BI 6*8mm TF-BGA
100 IC62LV12816LL-100TI 400mil TSOP-2
IC62LV12816LL-100BI 6*8mm TF-BGA
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
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