www.irf.com 1
05/18/04
IRL7833PbF
IRL7833SPbF
IRL7833LPbF
HEXFET® Power MOSFET
Notes through are on page 12
Applications
Benefits
lVery Low RDS(on) at 4.5V VGS
lUltra-Low Gate Impedance
lFully Characterized Avalanche Voltage
and Current
lHigh Frequency Synchronous Buck
Converters for Computer Processor Power
lHigh Frequency Isolated DC-DC
Converters with Synchronous Rectification
for Telecom and Consumer Use
lLead-Free
D2Pak
IRL7833S
TO-220AB
IRL7833 TO-262
IRL7833L
VDSS RDS(on) max Qg
30V 3.8m
:
32nC
Absolute Maximum Ratings
Parameter Units
V
DS Dr ain-to-Source Vo lt age V
VGS Gat e- to-Sou r ce Voltage
ID @ TC = 25 °C
Co ntinuo us Dr ain C urr e nt, V
GS
@ 10V
ID @ TC = 10 0°C Co ntinuo us Dr ain C urr e nt, VGS @ 10V A
IDM
Pulsed Drain Curr ent
c
PD @TC = 25°C
Maximum Power Dissipation
g
W
PD @TC = 100°C
Maximum Power Dissipation
g
Linear Derating Factor W/°C
TJ Operat ing Junction and °C
TSTG Storage Te m peratur e Ra ng e
Mo unting Tor q ue, 6- 3 2 or M 3 s crew
Thermal Resistance
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 1.04
RθCS
Ca s e- to-Sink , Fl at, Gr ea sed Sur fac e
h
0.50 ––– °C/W
RθJA Junction-to-Ambient
h
––– 62
RθJA
g
––– 40
Max.
150
f
110
f
600
± 20
30
10 lbf
y
in (1.1N
y
m)
-55 to + 175
140
0.96
72
PD - 95270
IRL7833/S/LPbF
2www.irf.com
S
D
G
Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units
BV
DSS Dr ai n- to- Sou r c e B reak down Volt a ge 30 ––– ––– V
∆Β
V
DSS
/
∆
T
J Breakdown Voltage Te m p. Coefficie nt ––– 18 –– – mV/°C
R
DS(on) Static D r ai n- to- S our c e O n-R es istan c e ––– 3. 1 3.8
m
Ω
––– 3.7 4.5
V
GS(th) Gate Threshold Voltage 1.4 ––– 2.3 V
∆
V
GS(th)
/
∆
T
JGate Th r es h old V o ltage Coeffi c ien t ––– -11 – –– mV/°C
I
DSS Dr ai n- to- Sou r c e Leak a ge Cu rr ent ––– ––– 1. 0 µA
––– ––– 150
I
GSS Gate- to- Sou r c e Fo r w ard Lea k age ––– ––– 100 nA
Gate- t o- Source Reve r s e Leak a ge ––– ––– -10 0
gfs For wa rd Transco nductance 150 ––– ––– S
Q
gTotal Gate Charge ––– 32 47
Q
gs1 Pre-Vth Gate-to-Source Charge ––– 8.7 –––
Q
gs2 Post - Vt h G ate-to-S ource Cha r ge ––– 5.1 ––– nC
Q
gd Gate- to-Drain Charge ––– 13 –––
Q
godr G ate C ha r ge Ov e r dr i ve ––– 5. 3 ––– Se e Fig. 16
Q
sw
Switch Charge (Q
gs2
+ Q
gd
)
––– 18 –––
Q
oss Output Charge ––– 22 ––– nC
t
d(on) Turn-On Delay Time ––– 18 –––
t
rRise Tim e ––– 50 ––– ns
t
d(off) Turn-Off Delay Tim e ––– 21 –––
t
fFall Ti m e –– – 6.9 –– –
C
iss Input Capacitance ––– 4170 –––
C
oss Output Capaci tance ––– 950 ––– pF
C
rss Reverse Transfer Capacitance ––– 470 –––
Avalanche Charac t eristics
Parameter Units
E
AS
Sing le Pul s e Avala nch e En erg y
dh
mJ
I
AR
Avalanche Current
c
A
E
AR
Repe ti ti ve Avalanche En er gy
c
mJ
Diode Charac teristics
Para me t e r Min. T y p . Max . Units
I
SContinuo us Source Cur ren t ––– ––– 150
f
(Body Diode) A
I
SM Pulsed Source Current ––– ––– 600
(Body Diode)
ch
V
SD Diod e Forward Voltage –– – ––– 1.2 V
t
rr Reverse Recovery Time ––– 42 63 ns
Q
rr Reverse Recovery Charge ––– 34 51 nC
VGS = 20V
VGS = -20 V
Conditions
14
Max.
560
30
ƒ = 1. 0M H z
Conditions
VGS = 0V, ID = 250µA
Reference to 2 5 °C, ID = 1mA
VGS = 10V, ID = 38A
f
VDS = VGS, ID = 250µ A
VDS = 24V , V GS = 0V
VDS = 24V , V GS = 0V, TJ = 12 5°C
Cla m ped Indu ctiv e Load
VDS = 15V , I D = 30A
VDS = 16V , V GS = 0V
VDD = 15V, V GS = 4.5V
f
ID = 26A
VDS = 16V
TJ = 25°C, IF = 30 A, VDD = 15V
di/d t = 100A /µ s
f
TJ = 25°C, IS = 30A, VGS = 0V
f
showing the
integra l revers e
p-n junction diode.
MOSFET symbol
VGS = 4.5V, ID = 30A
f
–––
VGS = 4.5V
Typ.
–––
–––
ID = 30A
VGS = 0V
VDS = 15V
IRL7833/S/LPbF
www.irf.com 3
Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
0.1 110 100 1000
VDS, Dr ain-to-Source Voltage (V)
1
10
100
1000
ID, Drain-to-Source Current (A)
2.7V
20µs PU LSE WIDT H
Tj = 25°C
VGS
TOP 10V
7.0V
4.5V
3.7V
3.5V
3.3V
3.0V
BOTTOM 2.7V
0.1 110 100 1000
VDS, Dr ain-to-Source Voltage (V)
1
10
100
1000
ID, Drain-to-Source Current (A)
2.7V
20µs PU LSE WIDT H
Tj = 175°C
VGS
TOP 10V
7.0V
4.5V
3.7V
3.5V
3.3V
3.0V
BOTTOM 2.7V
-60 -40 -20 020 40 60 80 100 120 140 160 180
TJ , Juncti on Temperature (°C)
0.5
1.0
1.5
2.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID = 75A
VGS = 10V
2.0 3.0 4.0 5.0 6.0 7.0 8.0
VGS, G ate-to-Source Voltage (V)
10
100
1000
ID, Drain-to-Source Current (Α)
TJ = 25°C
TJ = 175°C
VDS = 15V
20µs PULSE WIDTH
IRL7833/S/LPbF
4www.irf.com
Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
110 100
VDS, Dr ain-to-Source Voltage (V)
100
1000
10000
100000
C, Capacitance(pF)
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
0.0 0.5 1.0 1.5 2.0 2.5 3.0
VSD, Sour ce-to- Drain Voltage (V)
0.10
1.00
10.00
100.00
1000.00
ISD, Reverse Drain Current (A)
TJ = 25°C
TJ = 175°C
VGS = 0V
1 10 100
VDS, Dr ain-to-Source Voltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
Tc = 25°C
Tj = 175°C
Singl e Pul se
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY RDS(on)
100µsec
0 5 10 15 20 25 30 35 40
QG Total Gate Char ge (nC)
0.0
2.0
4.0
6.0
8.0
10.0
12.0
VGS, Gate-to-Source Voltage (V)
VDS= 24V
VDS= 15V
ID= 30A
IRL7833/S/LPbF
www.irf.com 5
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current Vs.
Case Temperature Fig 10. Threshold Voltage Vs. Temperature
25 50 75 100 125 150 175
0
40
80
120
160
I , D rain C urrent (A)
D
LIMITED BY PACKAGE
TC, Case Temperature (°C) -75 -50 -25 025 50 75 100 125 150 175
TJ , Temperature ( °C )
0.0
0.5
1.0
1.5
2.0
2.5
VGS(th) Gate threshold Voltage (V)
ID = 250µA
0.01
0.1
1
10
0.00001 0.0001 0.001 0.01 0.1 1
Notes:
1. Duty factor D = t / t
2. Peak T = P x Z + T
1 2
JDM thJC C
P
t
t
DM
1
2
t , Rectangular Pulse Duration (sec)
Therm al Response (Z )
1
thJC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(THERMAL RESPONSE)
IRL7833/S/LPbF
6www.irf.com
D.U.T. V
D
S
I
D
I
G
3mA
V
GS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
Fig 13. Gate Charge Test Circuit
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
VGS
25 50 75 100 125 150 175
0
400
800
1200
1600
2000
E , Single Puls e Av alanc he Energy (m J )
AS
ID
TOP
BOTTOM
12A
21A
30A
Fig 14a. Switching Time Test Circuit
Fig 14b. Switching Time Waveforms
VGS
VDS
9
0%
10%
td(on) td(off)
trtf
VGS
Pu l se Wi dth < 1µs
Duty Factor < 0.1%
VDD
VDS
LD
D.U.T
+
-
IRL7833/S/LPbF
www.irf.com 7
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
R
e-Applied
V
oltage
Reverse
Recovery
Current Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P.W.
Period
* VGS = 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
RGVDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
Fig 16. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2 Qgd Qgodr
IRL7833/S/LPbF
8www.irf.com
Control FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
Power losses in the control switch Q1 are given
by;
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
This can be expanded and approximated by;
P
loss =Irms 2×Rds(on )
()
+I×Qgd
ig
×Vin ×f
⎛
⎝
⎜ ⎞
⎠
⎟ +I×Qgs2
ig
×Vin ×
f
⎛
⎝
⎜ ⎞
⎠
⎟
+Qg×Vg×f
()
+Qoss
2×Vin ×f
⎛
⎝ ⎞
⎠
This simplified loss equation includes the terms Qgs2
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain cur-
rent rises to Idmax at which time the drain voltage be-
gins to change. Minimizing Qgs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the out-
put capacitance of the MOSFET during every switch-
ing cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (non-
linear) capacitances Cds and Cdg when multiplied by
the power supply input buss voltage.
Synchronous FET
The power loss equation for Q2 is approximated
by;
P
loss =P
conduction +P
drive +P
output
*
P
loss =Irms
2×Rds(on)()
+Qg×Vg×f
()
+Qoss
2×Vin ×f
⎛
⎝
⎜ ⎞
⎠ +Qrr ×Vin ×
f
(
)
*dissipated primarily in Q1.
For the synchronous MOSFET Q2, Rds(on) is an im-
portant characteristic; however, once again the im-
portance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the con-
trol IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and re-
verse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions be-
tween ground and Vin. As Q1 turns on and of f there is
a rate of change of drain voltage dV/dt which is ca-
pacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
Power MOSFET Selection for Non-Isolated DC/DC Converters
Figure A: Qoss Characteristic
IRL7833/S/LPbF
www.irf.com 9
L EAD ASS IGNMENTS
1 - GATE
2 - DRAI N
3 - SOURCE
4 - DRAI N
- B -
1.32 (.052)
1.22 (.048)
3X 0.55 (.022)
0.46 (.018)
2.92 (.115)
2.64 (.104)
4.6 9 (.185)
4.2 0 (.165)
3X 0.93 (.037)
0.69 (.027)
4.06 (.160)
3.55 (.140)
1.15 (.045)
MIN
6.47 (.255)
6.10 (.240)
3.78 (.149)
3.54 (.139)
- A -
10.54 (.415)
10.29 (.405)
2.87 (.113)
2.62 (.103)
15.2 4 (.600)
14.8 4 (.584)
14.09 (.555)
13.47 (.530)
3X 1.40 (.055)
1.15 (.045)
2.54 (.100)
2X
0.36 (.014) M B A M
4
1 2 3
N
OTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 3 OUTLINE CONFORM S TO JEDEC OUTLINE TO-220AB.
2 CONTROLLING DIMENSION : INCH 4 HEATSI NK & LEAD MEASUREMENTS DO NOT I NC LUDE BURRS
.
TO-220AB Part Marking Information
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
EXAMPLE:
IN THE ASSEMB LY LINE "C"
THIS IS AN IRF101 0
LOT CODE 1789
ASS EMBLED ON WW 19, 1997 PART NUMB E
R
AS SE MBLY
LOT CODE
DATE CODE
YEAR 7 = 1997
LINE C
WEEK 19
LOGO
RECTIFIER
INTERNATIONAL
Note: "P" in assembly line
position indicates "Lead-Free"
IRL7833/S/LPbF
10 www.irf.com
D2Pak Part Marking Information
D2Pak Package Outline
Note: "P" in assembly line
position indicates "Lead-F ree"
F530S
THIS IS AN IRF530S WITH
LOT CODE 8024
ASSEMBLED O N WW 02, 2000
IN THE ASSEMBLY LINE "L"
ASSEMBLY
LOT CODE
INTERNATIONAL
RECTIFIER
LOGO
PART NUMBE
R
DATE CODE
YEA R 0 = 2000
WEEK 02
LINE L
OR
F530S
A = ASSEMBLY SIT E CODE
WE E K 02
P = DESIGNATES LEAD-FREE
PRODUCT (OPTIO NAL)
RECTIFIER
INTERNATIONAL
LOGO
LOT CODE
ASSEMBLY Y EAR 0 = 2000
DATE C O DE
PART NUMBER
IRL7833/S/LPbF
www.irf.com 11
TO-262 Part Marking Information
TO-262 Package Outline
ASSEMBLY
LOT CODE
RECTIFIER
INTERNATIONAL
ASSEMBLED ON WW 19, 1997
Note: "P" in assemb ly line
pos ition indicates "L ead-F ree"
IN THE ASSEMBLY LINE "C" LOGO
THIS IS A N IRL3103 L
LOT CODE 1789
EXAMPLE:
LINE C
DATE C ODE
WEEK 19
YEAR 7 = 1997
PART NUMBER
PART NUMBE R
LOGO
LOT CODE
ASSEMBLY
INTERNATIONAL
RECTIFIER
PRODUCT (OPTIONAL)
P = DESIGN ATES LEAD -FREE
A = AS S E MBL Y S IT E CODE
WEEK 19
YEAR 7 = 1997
DATE CODE
OR
IRL7833/S/LPbF
12 www.irf.com
Notes:
Repetitive rating; pulse width limited by max. junction temperature.
Starting TJ = 25°C, L = 1.3mH, RG = 25Ω, I AS = 30A.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 75A.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to
application note #AN-994.
This is only applied to TO-220AB package.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.05/04
Dimensions are shown in millimeters (inches)
D2Pak Tape & Reel Information
3
4
4
TRR
F
EED DIRECTION
1.85 (.073)
1.65 (.065)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
TRL
F
EED DIRECTION
10.90 (.429)
10.70 (.421) 16. 10 (. 634)
15. 90 (. 626)
1.75 (.069)
1.25 (.049)
11.60 (.45 7)
11.40 (.44 9) 15.42 (.609)
15.22 (.601)
4.72 (.136)
4.52 (.178)
24.30 (.957
)
23.90 (.941
)
0.368 (.0145)
0.342 (.0135)
1.60 (.063)
1.50 (.059)
13.50 (.532)
12.80 (.504)
330.00
(14.173)
MAX.
27.40 (1.079)
23.90 (.941)
60.00 (2.362
)
MIN.
30.40 (1.197)
MAX.
26.40 (1.039)
24.40 (.961)
NOT ES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
TO-220AB package isnot recommended for Surface Mount Application.
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/