the energy consumption and the workload of the CPU, and enables the system to stay in low energy modes when moving for instance

data from the USART to RAM or from the External Bus Interface to a PWM-generating timer. The DMA controller uses the PL230

µDMA controller licensed from ARM.

3.1.5 Reset Management Unit (RMU)

The RMU is responsible for handling the reset functionality of the EFM32WG.

3.1.6 Energy Management Unit (EMU)

The Energy Management Unit (EMU) manage all the low energy modes (EM) in EFM32WG microcontrollers. Each energy mode man-

ages if the CPU and the various peripherals are available. The EMU can also be used to turn off the power to unused SRAM blocks.

3.1.7 Clock Management Unit (CMU)

The Clock Management Unit (CMU) is responsible for controlling the oscillators and clocks on-board the EFM32WG. The CMU pro-

3.1.9 Peripheral Reflex System (PRS)

The Peripheral Reflex System (PRS) system is a network which lets the different peripheral module communicate directly with each

other without involving the CPU. Peripheral modules which send out Reflex signals are called producers. The PRS routes these reflex

signals to consumer peripherals which apply actions depending on the data received. The format for the Reflex signals is not given, but

edge triggers and other functionality can be applied by the PRS.

3.1.10 External Bus Interface (EBI)

The External Bus Interface provides access to external parallel interface devices such as SRAM, FLASH, ADCs and LCDs. The inter-

face is memory mapped into the address bus of the Cortex-M4. This enables seamless access from software without manually manipu-

lating the IO settings each time a read or write is performed. The data and address lines are multiplexed in order to reduce the number

of pins required to interface the external devices. The timing is adjustable to meet specifications of the external devices. The interface is

3.1.12 Universal Serial Bus Controller (USB)

The USB is a full-speed USB 2.0 compliant OTG host/device controller. The USB can be used in Device, On-the-go (OTG) Dual Role

Device or Host-only configuration. In OTG mode the USB supports both Host Negotiation Protocol (HNP) and Session Request Proto-

col (SRP). The device supports both fullspeed (12MBit/s) and low speed (1.5MBit/s) operation. The USB device includes an internal

dedicated Descriptor-Based Scatter/Gather DMA and supports up to 6 OUT endpoints and 6 IN endpoints, in addition to endpoint 0.

The on-chip PHY includes all OTG features, except for the voltage booster for supplying 5V to VBUS when operating as host.

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