I C S8745B-21 1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR Description Features The ICS8745B-21 is a highly versatile 1:1 LVDS Clock Generator and a member of the HiPerClockSTM HiPerClockSTM f family of High Performance Clock Solutions from IDT. The ICS8745B-21 has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider, and has an output frequency range of 31.25MHz to 700MHz. The Reference Divider, Feedback Divider and Output Divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve "zero delay" between the input clock and the output clock. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers. * One differential LVDS output designed to meet or exceed the requirements of ANSI TIA/EIA-644 One differential feedback output pair * * Differential CLK, CLK input pair * * * * Output frequency range: 31.25MHz to 700MHz * Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 * * * * * * Cycle-to-cycle jitter: 30ps (maximum) ICS Input frequency range: 31.25MHz to 700MHz VCO range: 250MHz to 700MHz External feedback for "zero delay" clock regeneration with configurable frequencies Output skew: 35ps (maximum) Static phase offset: 25ps 125ps Full 3.3V supply voltage 0C to 70C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Pin Assignment Block Diagram PLL_SEL Pullup /1, /2, /4, /8, /16, /32, /64 CLK Pulldown CLK Pullup 0 1 Q Q QFB QFB PLL FB_IN Pulldown FB_IN Pullup CLKx, CLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 CLK CLK MR FB_IN FB_IN SEL2 VDDO QFB QFB GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 SEL1 SEL0 VDD PLL_SEL VDDA SEL3 GND Q Q VDDO ICS8745B-21 20-Lead SOIC 7.5mm x 12.8mm x 2.3mm package body M Package Top View SEL0 Pulldown SEL1 Pulldown SEL2 Pulldown SEL3 Pulldown MR Pulldown IDTTM / ICSTM LVDS ZERO DELAY CLOCK GENERATOR 1 ICS8745BM-21REV. C APRIL 17, 2007 ICS8745B-21 1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR Table 1. Pin Descriptions Number Name Type 1 CLK Input Pulldown 2 CLK Input Pullup Description Non-inverting differential clock input. Inverting differential clock input. 3 MR Input Pulldown Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true output Q to go low and the inverted output Q to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. 4 FBIN Input Pullup Inverting differential feedback input to phase detector for regenerating clocks with "Zero Delay." 5 FBIN Input Pulldown Non-inverted differential feedback input to phase detector for regenerating clocks with "Zero Delay." 6, 15, 19, 20 SEL2, SEL3, SEL0 SEL1 Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. 7, 11 VDDO Power Output supply pins. 8, 9 QFB/QFB Output Differential feedback output pair. LVDS interface levels. 10, 14 GND Power Power supply ground. 12, 13 Q/Q Output Differential output pair. LVDS interface levels. 16 VDDA Power Analog supply pin. 17 PLL_SEL Input 18 VDD Power Pullup PLL select. Selects between the PLL and reference clock as the input to the dividers. When LOW, selects reference clock. LVCMOS/LVTTL interface levels. Core supply pin. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k IDTTM / ICSTM LVDS ZERO DELAY CLOCK GENERATOR Test Conditions 2 Minimum Typical Maximum Units ICS8745BM-21REV. C APRIL 17, 2007 ICS8745B-21 1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR Function Tables Table 3A. Control Input Function Table Inputs Outputs PLL_SEL = 1 PLL Enable Mode SEL3 SEL2 SEL1 SEL0 Reference Frequency Range (MHz)* Q/Q 0z 0 0 0 250 - 700 /1 0 0 0 1 125 - 350 /1 0 0 1 0 62.5 - 175 /1 0 0 1 1 31.25 - 87.5 /1 0 1 0 0 250 - 700 /2 0 1 0 1 125 - 350 /2 0 1 1 0 62.5 - 175 /2 0 1 1 1 250 - 700 /4 1 0 0 0 125 - 350 /4 1 0 0 1 250 - 700 /8 1 0 1 0 125 - 350 x2 1 0 1 1 62.5 - 175 x2 1 1 0 0 31.25 - 87.5 x2 1 1 0 1 62.5 - 175 x4 1 1 1 0 31.25 - 87.5 x4 1 1 1 1 31.25 - 87.5 x8 *NOTE: VCO frequency range for all configurations above is 250MHz to 700MHz. IDTTM / ICSTM LVDS ZERO DELAY CLOCK GENERATOR 3 ICS8745BM-21REV. C APRIL 17, 2007 ICS8745B-21 1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR Table 3B. PLL Bypass Function Table Inputs Outputs PLL_SEL = 0 PLL Bypass Mode SEL3 SEL2 SEL1 SEL0 Q/Q 0z 0 0 0 /4 0 0 0 1 /4 0 0 1 0 /4 0 0 1 1 /8 0 1 0 0 /8 0 1 0 1 /8 0 1 1 0 /16 0 1 1 1 /16 1 0 0 0 /32 1 0 0 1 /64 1 0 1 0 /2 1 0 1 1 /2 1 1 0 0 /4 1 1 0 1 /1 1 1 1 0 /2 1 1 1 1 /1 IDTTM / ICSTM LVDS ZERO DELAY CLOCK GENERATOR 4 ICS8745BM-21REV. C APRIL 17, 2007 ICS8745B-21 1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuos Current Surge Current 10mA 15mA Package Thermal Impedance, JA 46.2C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. LVDS Power Supply DC Characteristics, VDD = VDDA = VDDO = 3.3V 5%, TA = 0C to 70C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 125 mA IDDA Analog Supply Current 17 mA IDDO Output Supply Current 59 mA Maximum Units Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDA = VDDO = 3.3V 5%, TA = 0C to 70C Symbol Parameter Test Conditions Minimum Typical VIH Input High Voltage 2 VDD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current IIL Input Low Current SEL[0:3], MR VDD = VIN = 3.465V 150 A PLL_SEL VDD = VIN = 3.465V 5 A SEL[0:3], MR VDD = 3.465V, VIN = 0V -5 A PLL_SEL VDD = 3.465V, VIN = 0V -150 A IDTTM / ICSTM LVDS ZERO DELAY CLOCK GENERATOR 5 ICS8745BM-21REV. C APRIL 17, 2007 ICS8745B-21 1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR Table 4C. Differential DC Characteristics, VDD = VDDA = VDDO = 3.3V 5%, TA = 0C to 70C Symbol Parameter IIH Input High Current IIL Test Conditions Minimum Typical Maximum Units CLK, FB_IN VDD = VIN = 3.465V 150 A CLK, FB_IN VDD = VIN = 3.465V 5 A CLK, FB_IN VDD = 3.465V, VIN = 0V -5 A CLK, FB_IN VDD = 3.465V, VIN = 0V -150 A Input Low Current VPP Peak-to-Peak Voltage VCMR Common Mode Input Voltage; NOTE 1, 2 0.15 1.3 V GND + 0.5 VDD - 0.85 V NOTE 1: Common mode input voltage is defined as VIH. NOTE 2: For single-ended applications, the maximum input voltage for CLK, CLK is VDD + 0.3V. Table 4D. LVDS DC Characteristics, VDD = VDDA = VDDO = 3.3V 5%, TA = 0C to 70C Symbol Parameter Test Conditions VOD Differential Output Voltage VOD VOD Magnitude Change VOS Offset Voltage VOS VOS Magnitude Change Minimum Typical Maximum Units 320 440 550 mV 0 50 mV 1.2 1.35 V 25 mV 1.05 Table 5. Input Frequency Characteristics, VDD = VDDA = VDDO = 3.3V 5%, TA = 0C to 70C Symbol Parameter FIN Input Frequency Test Conditions Minimum PLL_SEL = 1 31.25 Typical Maximum Units 700 A 700 V CLK, CLK IDTTM / ICSTM LVDS ZERO DELAY CLOCK GENERATOR PLL_SEL = 0 6 ICS8745BM-21REV. C APRIL 17, 2007 ICS8745B-21 1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR AC Electrical Characteristics Table 6. AC Characteristics, VDD = VDDA = VDDO = 3.3V 5%, TA = 0C to 70C Parameter Symbol fMAX Output Frequency tPD Propagation Delay; NOTE 1 tsk(O) Static Phase Offset; NOTE 2, 5 tsk(o) Output Skew; NOTE 3, 5 tjit(cc) Test Conditions Minimum Typical Maximum Units 700 MHz PLL_SEL = 0V, f 700MHz 3.1 3.4 4.0 ns PLL_SEL = 3.3V -100 25 150 ps 35 ps Cycle-to-Cycle Jitter; NOTE 5, 6 30 ps tjit() Phase Jitter; NOTE 4, 5, 6 52 ps tL PLL Lock Time tR / tF Output Rise/Fall Time; NOTE 7 odc Output Duty Cycle 20% to 80% 200 46 50 1 ms 700 ps 54 % NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal across all conditions, when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Characterized at VCO frequency of 622MHz. NOTE 7: Measured from the 20% to 80% points. Guaranteed by characterization. Not production tested. IDTTM / ICSTM LVDS ZERO DELAY CLOCK GENERATOR 7 ICS8745BM-21REV. C APRIL 17, 2007 ICS8745B-21 1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR Parameter Measurement Information VDD SCOPE VDD, 3.3V5% POWER SUPPLY + Float GND - CLK Qx V VDDA, VDDO V Cross Points PP LVDS CMR CLK nQx GND Differential Input Level 3.3V LVDS Output Load AC Test Circuit CLK VOH CLK VOL FB_IN VOH FB_IN VOL Qx Qy t(O) Qx tjit(O) = t(O) - t(O) mean = Phase Jitter t(O) mean = Static Phase Offset Qy tsk(o) (where t(O) is any random sample, and t(O) mean is the average of the sampled cycles measured on controlled edges) Output Skew Phase Jitter and Static Phase Offset Q 80% Q 80% VOD tcycle n tcycle n+1 Clock Outputs tjit(cc) = tcycle n - tcycle n+1 1000 Cycles Cycle-to-Cycle Jitter IDTTM / ICSTM LVDS ZERO DELAY CLOCK GENERATOR 20% 20% tR tF Output Rise/Fall Time 8 ICS8745BM-21REV. C APRIL 17, 2007 ICS8745B-21 1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR Parameter Measurement Information, continued Q CLK Q CLK t PW t PW Q Q x 100% tPD t PERIOD Output Duty Cycle Propagation Delay VDD VDD out LVDS DC Input out DC Input LVDS 100 VOD/ VOD out out VOS/ VOS odc = PERIOD t Offset Voltage Setup IDTTM / ICSTM LVDS ZERO DELAY CLOCK GENERATOR Differential Output Voltage Setup 9 ICS8745BM-21REV. C APRIL 17, 2007 ICS8745B-21 1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR Application Information Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8745B-21 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA pin. The 10 resistor can also be replaced by a ferrite bead. 3.3V VDD .01F 10 VDDA .01F 10F Figure 1. Power Supply Filtering Wiring the Differential Input to Accept Single Ended Levels Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K Figure 2. Single-Ended Signal Driving Differential Input IDTTM / ICSTM LVDS ZERO DELAY CLOCK GENERATOR 10 ICS8745BM-21REV. C APRIL 17, 2007 ICS8745B-21 1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR Differential Clock Input Interface The CLK /CLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both signals must meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the HiPerClockS CLK/CLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 3A, the input termination applies for IDT HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Zo = 50 CLK CLK Zo = 50 Zo = 50 nCLK nCLK HiPerClockS Input LVHSTL R1 50 IDT HiPerClockS LVHSTL Driver R2 50 HiPerClockS Input LVPECL R1 50 R2 50 R2 50 Figure 3B. HiPerClockS CLK/CLK Input Driven by a 3.3V LVPECL Driver Figure 3A. HiPerClockS CLK/CLK Input Driven by an IDT HiPerClockS LVHSTLDriver 3.3V 3.3V 3.3V R3 125 3.3V R4 125 3.3V Zo = 50 Zo = 50 CLK CLK R1 100 Zo = 50 nCLK LVPECL R1 84 R2 84 HiPerClockS Input Zo = 50 LVDS Figure 3C. HiPerClockS CLK/CLK Input Driven by a 3.3V LVPECL Driver IDTTM / ICSTM LVDS ZERO DELAY CLOCK GENERATOR nCLK Receiver Figure 3D. HiPerClockS CLK/CLK Input Driven by a 3.3V LVDS Driver 11 ICS8745BM-21REV. C APRIL 17, 2007 ICS8745B-21 1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR Recommendations for Unused Input and Output Pins Inputs: Outputs: LVCMOS Control Pins: LVDS Output All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, we recommend that there is no trace attached. CLK/CLK INPUT: For applications not requiring the use of the differential input, both CLK and CLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground. 3.3V LVDS Driver Termination A general LVDS interface is shown in Figure 4. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. 3.3V 50 3.3V LVDS Driver + R1 100 - 50 100 Differential Transmission Line Figure 4. Typical LVDS Driver Termination IDTTM / ICSTM LVDS ZERO DELAY CLOCK GENERATOR 12 ICS8745BM-21REV. C APRIL 17, 2007 ICS8745B-21 1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR Schematic Example The schematic of the ICS8745B-21 layout example is shown in Figure 5A. The ICS8745B-21 recommended PCB board layout for this example is shown in Figure 5B. This layout example is used as 3.3V (155.52 MHz) U1 Zo = 50 Ohm Zo = 50 Ohm SEL2 VDDO 3.3V PECL Driver R8 50 R9 50 R2 100 SP = Space (i.e. not intstalled) RU4 1K RU5 SP RU6 1K RU7 SP PLL_SEL SEL0 SEL1 SEL2 SEL3 RD3 SP RD4 SP 1 2 3 4 5 6 7 8 9 10 CLK nCLK MR nFB_IN FB_IN SEL2 VDDO nQFB QFB GND SEL1 SEL0 VDDI PLL_SEL VDDA SEL3 GND Q nQ VDDO 20 19 18 17 16 15 14 13 12 11 SEL1 SEL0 VDD PLL_SEL VDDA SEL3 VDDO RD5 1K RD6 SP C1 0.1uF R7 C11 0.01u VDD 10 C16 10u ICS8745B-21 (77.76 MHz) R10 50 VDD RU3 1K a general guideline. The layout in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P.C. board. + Bypass capacitors located near the power pins (U1-7) RD7 1K VDDO C4 0.1uF R4 100 VDD=3.3V (U1-11) - LVDS_input VDDO=3.3V C2 0.1uF Zo = 100 Ohm Differential SEL[3:0] = 0101, Divide by 2 Figure 5A. ICS8745B-21 LVDS Zero Delay Buffer Schematic Example IDTTM / ICSTM LVDS ZERO DELAY CLOCK GENERATOR 13 ICS8745BM-21REV. C APRIL 17, 2007 ICS8745B-21 1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR The following component footprints are used in this layout example. and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. All the resistors and capacitors are size 0603. * The differential 50 output traces should have the same length. Power and Grounding Place the decoupling capacitors as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. * Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. * Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. * To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. The RC filter consisting of R7, C11, and C16 should be placed as close to the VDDA pin as possible. Clock Traces and Termination Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board * Make sure no other signal traces are routed between the clock trace pair. * The matching termination resistors should be located as close to the receiver input pins as possible. U1 ICS8745B-21 GND VDDO C1 VDD C16 VDDA C11 VIA C4 R7 100 O hm Differential Traces C2 Figure 5B. PCB Board Layout for ICS8745B-21 IDTTM / ICSTM LVDS ZERO DELAY CLOCK GENERATOR 14 ICS8745BM-21REV. C APRIL 17, 2007 ICS8745B-21 1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR Power Considerations This section provides information on power dissipation and junction temperature for the ICS8745B-21. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8745B-21 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (125mA + 17mA) = 492mW * Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 59mA = 204mW Total Power_MAX = 492mW + 204mW = 696mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 39.7C/W per Table 7below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.696W * 39.7C/W = 97.6C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer). Table 7. Thermal Resitance JA for 20 Lead TSSOP, Forced Convection JA vs. Air Flow Linear Feet per Minute 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 83.2C/W 65.7C/W 57.5C/W Multi-Layer PCB, JEDEC Standard Test Boards 46.2C/W 39.7C/W 36.8C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. IDTTM / ICSTM LVDS ZERO DELAY CLOCK GENERATOR 15 ICS8745BM-21REV. C APRIL 17, 2007 ICS8745B-21 1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR Reliability Information Table 8. JA vs. Air Flow Table for a 20 Lead TSSOP JA vs. Air Flow Linear Feet per Minute 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 83.2C/W 65.7C/W 57.5C/W Multi-Layer PCB, JEDEC Standard Test Boards 46.2C/W 39.7C/W 36.8C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. Transistor Count The transistor count for ICS8745B-21 is: 2772 Package Outline and Package Dimension Package Outline - M Suffix for 20 Lead SOIC Table 9. Package Dimensions for 20 Lead SOIC 300 Millimeters All Dimensions in Millimeters Symbol Minimum Maximum N 20 A 2.65 A1 0.10 A2 2.05 2.55 B 0.33 0.51 C 0.18 0.32 D 12.60 13.00 E 7.40 7.60 e 1.27 Basic H 10.00 10.65 h 0.25 0.75 L 0.40 1.27 0 7 Reference Document: JEDEC Publication 95, MS-013, MS-119 IDTTM / ICSTM LVDS ZERO DELAY CLOCK GENERATOR 16 ICS8745BM-21REV. C APRIL 17, 2007 ICS8745B-21 1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR Ordering Information Table 10. Ordering Information Part/Order Number ICS8745BM-21 ICS8745BM-21T ICS8745BM-21LF ICS8745BM-21LFT Marking ICS8745BM-21 ICS8745BM-21 TBD TBD Package 20 Lead SOIC 20 Lead SOIC "Lead-Free" 20 Lead SOIC "Lead-Free" 20 Lead SOIC Shipping Packaging Tube 1000 Tape & Reel Tube 1000 Tape & Reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDTTM / ICSTM LVDS ZERO DELAY CLOCK GENERATOR 17 ICS8745BM-21REV. C APRIL 17, 2007 ICS8745B-21 1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR Revision History Sheet Rev B B Table Page T4D 5 LVDS DC Characteristics Table - modified VOS 0.90V min. to 1.05V min, 1.15V typical to 1.2V typical, and 1.4V max. to 1.35V max. 3/17/04 T9 1 14 Added Lead-Free bullet. Ordering Information Table - added Lead-Free part and note. 12/2/04 7 12 15 AC Characteristics Table - changed tPD max limit from 3.7ns to 4.0ns. Added Recommendations for Unused Input & Output Pins. Added Power Considerations section. Updated format throughout the datasheet. 4/17/07 T6 C Description of Change IDTTM / ICSTM LVDS ZERO DELAY CLOCK GENERATOR 18 Date ICS8745BM-21REV. C APRIL 17, 2007 ICS8745B-21 1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR Innovate with IDT and accelerate your future networks. Contact: www. IDT.com www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 netcom@idt.com 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 (c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. 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