1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY
CLOCK GENERATOR I CS8745B- 21
IDT™ / ICS™
LVDS ZERO DELAY CLOCK GENERATOR 1
ICS8745BM-21REV. C APRIL 17, 2007
Description
The ICS8745B-21 is a highly versatile 1:1 LVDS
Clock Generator and a member of the HiPerClockS™
f family of High Performance Clock Solutions from
IDT. The ICS8745B-21 has a fully integrated PLL
and can be configured as zero delay buffer,
multiplier or divider, and has an output frequency range of
31.25MHz to 700MHz. The Reference Divider, Feedback Divider
and Output Divider are each programmable, thereby allowing for
the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8. The external feedback allows the device to achieve
“zero delay” between the input clock and the output clock. The
PLL_SEL pin can be used to bypass the PLL for system test and
debug purposes. In bypass mode, the reference clock is routed
around the PLL and into the internal output dividers.
Features
•One differential LVDS output designed to meet
or exceed the requirements of ANSI TIA/EIA-644
One differential feedback output pair
•Differential CLK, CLK input pair
•CLKx, CLKx pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
•Output frequency range: 31.25MHz to 700MHz
•Input frequency range: 31.25MHz to 700MHz
•VCO range: 250MHz to 700MHz
•External feedback for “zero delay” clock regeneration
with configurable frequencies
•Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
•Cycle-to-cycle jitter: 30ps (maximum)
•Output skew: 35ps (maximum)
•Static phase offset: 25ps ± 125ps
•Full 3.3V supply voltage
•0°C to 70°C ambient operating temperature
•Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
HiPerClockS™
ICS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
QFB
QFB
VDDO
SEL2
FB_IN
FB_IN
MR
CLK
CLK
GND
SEL1
SEL0
VDD
PLL_SEL
VDDA
SEL3
GND
Q
Q
VDDO
ICS8745B-21
20-Lead SOIC
7.5mm x 12.8mm x 2.3mm package body
M Package
Top View
Block Diagram
PLL_SEL
CLK
CLK
FB_IN
FB_IN
SEL0
SEL1
SEL2
SEL3
MR
Q
Q
QFB
QFB
PLL
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
0
1
÷1, ÷2, ÷4, ÷8,
÷16, ÷32
,
÷64
Pullup
Pullup
Pulldown
Pullup
Pulldown
Pullup
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pin Assignment
ICS8745B-21
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
IDT™ / ICS™
LVDS ZERO DELAY CLOCK GENERATOR 2
ICS8745BM-21REV. C APRIL 17, 2007
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1 CLK Input Pulldown Non-inverting differential clock input.
2CLK
Input Pullup Inverting differential clock input.
3 MR Input Pulldown
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true output Q to go low and the inverted output Q to go high. When
logic LOW, the internal dividers and the outputs are enabled.
LVCMOS / LVTTL interface levels.
4FBINInput Pullup Inverting differential feedback input to phase detector for regenerating clocks
with “Zero Delay.”
5 FBIN Input Pulldown Non-inverted differential feedback input to phase detector for regenerating
clocks with “Zero Delay.”
6, 15,
19, 20
SEL2, SEL3,
SEL0 SEL1 Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
7, 11 VDDO Power Output supply pins.
8, 9 QFB/QFB Output Differential feedback output pair. LVDS interface levels.
10, 14 GND Power Power supply ground.
12, 13 Q/Q Output Differential output pair. LVDS interface levels.
16 VDDA Power Analog supply pin.
17 PLL_SEL Input Pullup
PLL select. Selects between the PLL and reference clock as the input to the
dividers. When LOW, selects reference clock.
LVCMOS/LVTTL interface levels.
18 VDD Power Core supply pin.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
CIN Input Capacitance 4 pF
RPULLUP Input Pullup Resistor 51 kΩ
RPULLDOWN Input Pulldown Resistor 51 kΩ
ICS8745B-21
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
IDT™ / ICS™
LVDS ZERO DELAY CLOCK GENERATOR 3
ICS8745BM-21REV. C APRIL 17, 2007
Function Tables
Table 3A. Control Input Function Table
*NOTE: VCO frequency range for all configurations above is 250MHz to 700MHz.
Inputs Outputs
PLL_SEL = 1
PLL Enable Mode
SEL3 SEL2 SEL1 SEL0 Reference Frequency Range (MHz)* Q/Q
0z 0 0 0 250 - 700 ÷1
0001 125 - 350 ÷1
0010 62.5 - 175 ÷1
0011 31.25 - 87.5 ÷1
0100 250 - 700 ÷2
0101 125 - 350 ÷2
0110 62.5 - 175 ÷2
0111 250 - 700 ÷4
1000 125 - 350 ÷4
1001 250 - 700 ÷8
1010 125 - 350 x2
1011 62.5 - 175 x2
1100 31.25 - 87.5 x2
1101 62.5 - 175 x4
1110 31.25 - 87.5 x4
1111 31.25 - 87.5 x8
ICS8745B-21
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
IDT™ / ICS™
LVDS ZERO DELAY CLOCK GENERATOR 4
ICS8745BM-21REV. C APRIL 17, 2007
Table 3B. PLL Bypass Function Table
Inputs Outputs
PLL_SEL = 0
PLL Bypass Mode
SEL3 SEL2 SEL1 SEL0 Q/Q
0z000 ÷4
0001 ÷4
0010 ÷4
0011 ÷8
0100 ÷8
0101 ÷8
0110 ÷16
0111 ÷16
1000 ÷32
1001 ÷64
1010 ÷2
1011 ÷2
1100 ÷4
1101 ÷1
1110 ÷2
1111 ÷1
ICS8745B-21
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
IDT™ / ICS™
LVDS ZERO DELAY CLOCK GENERATOR 5
ICS8745BM-21REV. C APRIL 17, 2007
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics, VDD = VDDA = VDDO = 3.3V ± 5%, TA = 0°C to 70°C
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDA = VDDO = 3.3V ± 5%, TA = 0°C to 70°C
Item Rating
Supply Voltage, VDD 4.6V
Inputs, VI-0.5V to VDD + 0.5V
Outputs, IO
Continuos Current
Surge Current
10mA
15mA
Package Thermal Impedance, θJA 46.2°C/W (0 lfpm)
Storage Temperature, TSTG -65°C to 150°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD Core Supply Voltage 3.135 3.3 3.465 V
VDDA Analog Supply Voltage 3.135 3.3 3.465 V
VDDO Output Supply Voltage 3.135 3.3 3.465 V
IDD Power Supply Current 125 mA
IDDA Analog Supply Current 17 mA
IDDO Output Supply Current 59 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH Input High Voltage 2 VDD + 0.3 V
VIL Input Low Voltage -0.3 0.8 V
IIH Input High Current SEL[0:3], MR VDD = VIN = 3.465V 150 µA
PLL_SEL VDD = VIN = 3.465V 5 µA
IIL Input Low Current SEL[0:3], MR VDD = 3.465V, VIN = 0V -5 µA
PLL_SEL VDD = 3.465V, VIN = 0V -150 µA
ICS8745B-21
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
IDT™ / ICS™
LVDS ZERO DELAY CLOCK GENERATOR 6
ICS8745BM-21REV. C APRIL 17, 2007
Table 4C. Differential DC Characteristics, VDD = VDDA = VDDO = 3.3V ± 5%, TA = 0°C to 70°C
NOTE 1: Common mode input voltage is defined as VIH.
NOTE 2: For single-ended applications, the maximum input voltage for CLK, CLK is VDD + 0.3V.
Table 4D. LVDS DC Characteristics, VDD = VDDA = VDDO = 3.3V ± 5%, TA = 0°C to 70°C
Table 5. Input Frequency Characteristics, VDD = VDDA = VDDO = 3.3V ± 5%, TA = 0°C to 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
IIH Input High Current CLK, FB_IN VDD = VIN = 3.465V 150 µA
CLK, FB_IN VDD = VIN = 3.465V 5 µA
IIL Input Low Current
CLK, FB_IN VDD = 3.465V,
VIN = 0V -5 µA
CLK, FB_IN VDD = 3.465V,
VIN = 0V -150 µA
VPP Peak-to-Peak Voltage 0.15 1.3 V
VCMR Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 VDD – 0.85 V
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOD Differential Output Voltage 320 440 550 mV
ΔVOD VOD Magnitude Change 0 50 mV
VOS Offset Voltage 1.05 1.2 1.35 V
ΔVOS VOS Magnitude Change 25 mV
Symbol Parameter Test Conditions Minimum Typical Maximum Units
FIN Input Frequency CLK, CLK PLL_SEL = 1 31.25 700 µA
PLL_SEL = 0 700 V
ICS8745B-21
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
IDT™ / ICS™
LVDS ZERO DELAY CLOCK GENERATOR 7
ICS8745BM-21REV. C APRIL 17, 2007
AC Electrical Characteristics
Table 6. AC Characteristics, VDD = VDDA = VDDO = 3.3V ± 5%, TA = 0°C to 70°C
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal across all conditions,
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Characterized at VCO frequency of 622MHz.
NOTE 7: Measured from the 20% to 80% points. Guaranteed by characterization. Not production tested.
Parameter Symbol Test Conditions Minimum Typical Maximum Units
fMAX Output Frequency 700 MHz
tPD Propagation Delay; NOTE 1 PLL_SEL = 0V, f ≤ 700MHz 3.1 3.4 4.0 ns
tsk(Ø) Static Phase Offset; NOTE 2, 5 PLL_SEL = 3.3V -100 25 150 ps
tsk(o) Output Skew; NOTE 3, 5 35 ps
tjit(cc) Cycle-to-Cycle Jitter; NOTE 5, 6 30 ps
tjit(θ) Phase Jitter; NOTE 4, 5, 6 ±52 ps
tLPLL Lock Time 1ms
tR / tFOutput Rise/Fall Time; NOTE 7 20% to 80% 200 700 ps
odc Output Duty Cycle 46 50 54 %
ICS8745B-21
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
IDT™ / ICS™
LVDS ZERO DELAY CLOCK GENERATOR 8
ICS8745BM-21REV. C APRIL 17, 2007
Parameter Measurement Information
3.3V LVDS Output Load AC Test Circuit
Phase Jitter and Static Phase Offset
Cycle-to-Cycle Jitter
Differential Input Level
Output Skew
Output Rise/Fall Time
SCOPE
Qx
nQx
LVDS
3.3V±5%
POWER SUPPLY
+–
Float GND
VDDA,
VDDO
VDD,
➤
➤
t(Ø)
VOH
VOL
VOH
VOL
t
jit(Ø) = ⏐ t(Ø) – t(Ø) mean⏐ = Phase Jitter
t
(Ø) mean = Static Phase Offset
(where t(Ø) is any random sample, and t(Ø) mean is the
average of the sampled cycles measured on controlled edges)
CLK
CLK
FB_IN
FB_IN
➤
➤
➤
➤
tcycle n tcycle n+1
tjit(cc) = tcycle n – tcycle n+1
1000 Cycles
Q
Q
VCMR
Cross Points
VPP
CLK
CLK
VDD
GND
t
sk(o)
Qx
Qx
Qy
Qy
Clock
Outputs 20%
80% 80%
20%
tRtF
VOD
ICS8745B-21
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
IDT™ / ICS™
LVDS ZERO DELAY CLOCK GENERATOR 9
ICS8745BM-21REV. C APRIL 17, 2007
Parameter Measurement Information, continued
Output Duty Cycle
Offset Voltage Setup
Propagation Delay
Differential Output Voltage Setup
tPW
tPERIOD
tPW
tPERIOD
odc = x 100%
Q
Q
out
out
LVDS
DC Input
➤
➤
➤
VOS/Δ VOS
VDD
tPD
Q
Q
CLK
CLK
➤
➤
➤
100
out
out
LVDS
DC Input VOD/Δ VOD
VDD
ICS8745B-21
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
IDT™ / ICS™
LVDS ZERO DELAY CLOCK GENERATOR 10
ICS8745BM-21REV. C APRIL 17, 2007
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. The ICS8745B-21 provides separate
power supplies to isolate any high switching noise from the outputs
to the internal PLL. VDD, VDDA and VDDO should be individually
connected to the power supply plane through vias, and bypass
capacitors should be used for each pin. To achieve optimum jitter
performance, power supply isolation is required. Figure 1
illustrates how a 10Ω resistor along with a 10μF and a .01μF
bypass capacitor should be connected to each VDDA pin. The 10Ω
resistor can also be replaced by a ferrite bead.
Figure 1. Power Supply Filtering
Wiring the Differential Input to Accept Single Ended Levels
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and
R2/R1 = 0.609.
Figure 2. Single-Ended Signal Driving Differential Input
VDD
VDDA
3.3V
10Ω
10µF.01µF
.01µF
V_REF
Single Ended Clock Input
VDD
CLK
nCLK
R1
1K
C1
0.1u R2
1K
ICS8745B-21
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
IDT™ / ICS™
LVDS ZERO DELAY CLOCK GENERATOR 11
ICS8745BM-21REV. C APRIL 17, 2007
Differential Clock Input Interface
The CLK /CLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and
other differential signals. Both signals must meet the VPP and
VCMR input requirements. Figures 3A to 3D show interface
examples for the HiPerClockS CLK/CLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example, in Figure 3A, the input termination applies for IDT
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
Figure 3A. HiPerClockS CLK/CLK Input Driven by an
IDT HiPerClockS LVHSTLDriver
Figure 3C. HiPerClockS CLK/CLK Input
Driven by a 3.3V LVPECL Driver
Figure 3B. HiPerClockS CLK/CLK Input
Driven by a 3.3V LVPECL Driver
Figure 3D. HiPerClockS CLK/CLK Input Driven by
a 3.3V LVDS Driver
R1
50
R2
50
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
nCLK
3.3V
LVHSTL
IDT
HiPerClockS
LVHSTL Driver
HiPerClockS
Input
R3
125
R4
125
R1
84
R2
84
3.3V
Zo = 50Ω
Zo = 50Ω
CLK
nCLK
3.3V
3.3V
LVPECL HiPerClockS
Input
CLK
nCLK
HiPerClockS
Input
LVPECL
3.3V
Zo = 50Ω
Zo = 50Ω
3.3V
R1
50
R2
50
R2
50
3.3V
R1
100
LVDS
CLK
nCLK
3.3V
Receiver
Zo = 50Ω
Zo = 50Ω
ICS8745B-21
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
IDT™ / ICS™
LVDS ZERO DELAY CLOCK GENERATOR 12
ICS8745BM-21REV. C APRIL 17, 2007
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
CLK/CLK INPUT:
For applications not requiring the use of the differential input, both
CLK and CLK can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from CLK to
ground.
Outputs:
LVDS Output
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, we
recommend that there is no trace attached.
3.3V LVDS Driver Termination
A general LVDS interface is shown in Figure 4. In a 100Ω
differential transmission line environment, LVDS drivers require a
matched load termination of 100Ω across near the receiver input.
For a multiple LVDS outputs buffer, if only partial outputs are used,
it is recommended to terminate the unused outputs.
Figure 4. Typical LVDS Driver Termination
3.3V
LVDS Driver
R1
100Ω
–
+
3.3V 50Ω
50Ω
100Ω Differential Transmission Line
ICS8745B-21
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
IDT™ / ICS™
LVDS ZERO DELAY CLOCK GENERATOR 13
ICS8745BM-21REV. C APRIL 17, 2007
Schematic Example
The schematic of the ICS8745B-21 layout example is shown in
Figure 5A. The ICS8745B-21 recommended PCB board layout for
this example is shown in Figure 5B. This layout example is used as
a general guideline. The layout in the actual system will depend on
the selected component types, the density of the components, the
density of the traces, and the stack up of the P.C. board.
Figure 5A. ICS8745B-21 LVDS Zero Delay Buffer Schematic Example
SEL2
PLL_SEL
RD6
SP
RD4
SP
R4
100
VDD
RU3
1K
SP = Space (i.e. not intstalled)
SEL0
SEL3
RU4
1K
SEL[3:0] = 0101,
Divide by 2
R8
50
RD7
1K
(77.76 MHz)
VDDO
VDD
C1
0.1uF
Bypass capacitors located
near the power pins
RU5
SP
C16
10u
SEL3
VDDO
(U1-7)
Zo = 50 Ohm
VDDA
3.3V PECL Driver
SEL1
R9
50
VDD=3.3V
VDDO
R10
50
SEL0
Zo = 50 Ohm
RD5
1K
C11
0.01u
(U1-11)
C4
0.1uF
SEL2
(155.52 MHz)
LVDS_input
+
-
Zo = 100 Ohm Differential
R2
100
SEL1
RU7
SP
C2
0.1uF
R7
10
PLL_SEL
U1
ICS8745B-21
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
20
19
18
17
CLK
nCLK
MR
nFB_IN
FB_IN
SEL2
VDDO
nQFB
QFB
GND VDDO
nQ
Q
GND
SEL3
VDDA
SEL1
SEL0
VDDI
PLL_SEL
RD3
SP
VDD
VDDO=3.3V
RU6
1K
3.3V
ICS8745B-21
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
IDT™ / ICS™
LVDS ZERO DELAY CLOCK GENERATOR 14
ICS8745BM-21REV. C APRIL 17, 2007
The following component footprints are used in this layout
example.
All the resistors and capacitors are size 0603.
Power and Grounding
Place the decoupling capacitors as close as possible to the power
pins. If space allows, placement of the decoupling capacitor on the
component side is preferred. This can reduce unwanted
inductance between the decoupling capacitor and the power pin
caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power and
ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed as
close to the VDDA pin as possible.
Clock Traces and Termination
Poor signal integrity can degrade the system performance or cause
system failure. In synchronous high-speed digital systems, the
clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
• The differential 50Ω output traces should have the same
length.
• Avoid sharp angles on the clock trace. Sharp angle turns
cause the characteristic impedance to change on the
transmission lines.
• Keep the clock traces on the same layer. Whenever
possible, avoid placing vias on the clock traces.
Placement of vias on the traces can affect the trace
characteristic impedance and hence degrade signal
integrity.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
• Make sure no other signal traces are routed between the
clock trace pair.
• The matching termination resistors should be located as
close to the receiver input pins as possible.
Figure 5B. PCB Board Layout for ICS8745B-21
100 Ohm
Differential
Traces
VDDA
VDD
C2
U1
R7
C16
VDDO
GND
C4
C1
IC S8745B-21
VIA
C11
ICS8745B-21
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
IDT™ / ICS™
LVDS ZERO DELAY CLOCK GENERATOR 15
ICS8745BM-21REV. C APRIL 17, 2007
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8745B-21.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8745B-21 is the sum of the core power plus the analog power plus the power dissipated in the
load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (125mA + 17mA) = 492mW
• Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 59mA = 204mW
Total Power_MAX = 492mW + 204mW = 696mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate
air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 39.7°C/W per Table 7below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.696W * 39.7°C/W = 97.6°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 7. Thermal Resitance θJA for 20 Lead TSSOP, Forced Convection
θJA vs. Air Flow
Linear Feet per Minute 0200500
Single-Layer PCB, JEDEC Standard Test Boards 83.2°C/W 65.7°C/W 57.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 46.2°C/W 39.7°C/W 36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
ICS8745B-21
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
IDT™ / ICS™
LVDS ZERO DELAY CLOCK GENERATOR 16
ICS8745BM-21REV. C APRIL 17, 2007
Reliability Information
Table 8. θJA vs. Air Flow Table for a 20 Lead TSSOP
Transistor Count
The transistor count for ICS8745B-21 is: 2772
Package Outline and Package Dimension
Package Outline - M Suffix for 20 Lead SOIC Table 9. Package Dimensions for 20 Lead SOIC
Reference Document: JEDEC Publication 95, MS-013, MS-119
θJA vs. Air Flow
Linear Feet per Minute 0200500
Single-Layer PCB, JEDEC Standard Test Boards 83.2°C/W 65.7°C/W 57.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 46.2°C/W 39.7°C/W 36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
300 Millimeters
All Dimensions in Millimeters
Symbol Minimum Maximum
N20
A2.65
A1 0.10
A2 2.05 2.55
B0.33 0.51
C0.18 0.32
D12.60 13.00
E7.40 7.60
e1.27 Basic
H10.00 10.65
h0.25 0.75
L0.40 1.27
α0° 7°
ICS8745B-21
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
IDT™ / ICS™
LVDS ZERO DELAY CLOCK GENERATOR 17
ICS8745BM-21REV. C APRIL 17, 2007
Ordering Information
Table 10. Ordering Information
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
Part/Order Number Marking Package Shipping Packaging Temperature
ICS8745BM-21 ICS8745BM-21 20 Lead SOIC Tube 0°C to 70°C
ICS8745BM-21T ICS8745BM-21 20 Lead SOIC 1000 Tape & Reel 0°C to 70°C
ICS8745BM-21LF TBD “Lead-Free” 20 Lead SOIC Tube 0°C to 70°C
ICS8745BM-21LFT TBD “Lead-Free” 20 Lead SOIC 1000 Tape & Reel 0°C to 70°C
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements
are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any
IDT product for use in life support devices or critical medical instruments.
ICS8745B-21
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
IDT™ / ICS™
LVDS ZERO DELAY CLOCK GENERATOR 18
ICS8745BM-21REV. C APRIL 17, 2007
Revision History Sheet
Rev Table Page Description of Change Date
BT4D 5 LVDS DC Characteristics Table - modified VOS 0.90V min. to 1.05V min,
1.15V typical to 1.2V typical, and 1.4V max. to 1.35V max. 3/17/04
BT9
1
14
Added Lead-Free bullet.
Ordering Information Table - added Lead-Free part and note. 12/2/04
C
T6 7
12
15
AC Characteristics Table - changed tPD max limit from 3.7ns to 4.0ns.
Added Recommendations for Unused Input & Output Pins.
Added Power Considerations section.
Updated format throughout the datasheet.
4/17/07
www.IDT.com
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
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ICS8745B-21
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
