Order this document by MTP12P10/D SEMICONDUCTOR TECHNICAL DATA P-Channel Enhancement-Mode Silicon Gate This TMOS Power FET is designed for medium voltage, high speed power switching applications such as switching regulators, converters, solenoid and relay drivers. * Silicon Gate for Fast Switching Speeds -- Switching Times Specified at 100C * Designer's Data -- IDSS, VDS(on), VGS(th) and SOA Specified at Elevated Temperature * Rugged -- SOA is Power Dissipation Limited * Source-to-Drain Diode Characterized for Use With Inductive Loads TMOS POWER FET 12 AMPERES 100 VOLTS RDS(on) = 0.3 OHM D G S CASE 221A-06, Style 5 TO-220AB MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit Drain-Source Voltage VDSS 100 Vdc Drain-Gate Voltage (RGS = 1.0 M) VDGR 100 Vdc Gate-Source Voltage -- Continuous Gate-Source Voltage -- Non-repetitive (tp 50 s) VGS VGSM 20 40 Vdc Vpk Drain Current -- Continuous Drain Current -- Pulsed ID IDM 12 28 Adc Total Power Dissipation Derate above 25C PD 75 0.6 Watts W/C TJ, Tstg - 65 to 150 C RJC RJA 1.67 62.5 C/W TL 260 C Rating Operating and Storage Temperature Range THERMAL CHARACTERISTICS Thermal Resistance -- Junction to Case Thermal Resistance -- Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Designer's Data for "Worst Case" Conditions -- The Designer's Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves -- representing boundaries on device characteristics -- are given to facilitate "worst case" design. Designer's is a trademark of Motorola, Inc. REV 1 TMOS Motorola Motorola, Inc. 1996 Power MOSFET Transistor Device Data 1 MTP12P10 ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Max Unit V(BR)DSS 100 -- Vdc -- -- 10 100 OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0, ID = 0.25 mA) Zero Gate Voltage Drain Current (VDS = Rated VDSS, VGS = 0) (VDS = Rated VDSS, VGS = 0, TJ = 125C) Adc IDSS Gate-Body Leakage Current, Forward (VGSF = 20 Vdc, VDS = 0) IGSSF -- 100 nAdc Gate-Body Leakage Current, Reverse (VGSR = 20 Vdc, VDS = 0) IGSSR -- 100 nAdc Gate Threshold Voltage (VDS = VGS, ID = 1.0 mA) TJ = 100C VGS(th) 2.0 1.5 4.5 4.0 Vdc Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 6.0 Adc) RDS(on) -- 0.3 Ohm Drain-Source On-Voltage (VGS = 10 V) (ID = 12 Adc) (ID = 6.0 Adc, TJ = 100C) VDS(on) -- -- 4.2 3.8 gFS 2.0 -- mhos Ciss -- 920 pF Coss -- 575 Crss -- 200 td(on) -- 50 tr -- 150 td(off) -- 150 tf -- 150 Qg 33 (Typ) 50 ON CHARACTERISTICS* Forward Transconductance (VDS = 15 V, ID = 6.0 A) Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 V, VGS = 0, f = 1.0 MHz) See Figure 10 Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS* (TJ = 100C) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 25 V, ID = 0.5 Rated ID, RG = 50 ) See Figures 12 and 13 Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge (VDS = 0.8 Rated VDSS, ID = Rated ID, VGS = 10 V) See Figure 11 Qgs 16 (Typ) -- Qgd 17 (Typ) -- VSD 4.0 (Typ) 5.5 ns nC SOURCE-DRAIN DIODE CHARACTERISTICS* Forward On-Voltage Forward Turn-On Time (IS = Rated ID, VGS = 0) Reverse Recovery Time ton Vdc Limited by stray inductance trr 300 (Typ) -- ns Internal Drain Inductance (Measured from the contact screw on the header closer to the source pin and the center of the die) Ld 5.0 (Typ) -- nH Internal Source Inductance (Measured from the source pin, 0.25 from the package to the source bond pad) Ls 12.5 (Typ) -- 3.5 (Typ) 4.5 (Typ) -- -- 7.5 (Typ) -- INTERNAL PACKAGE INDUCTANCE (TO-204) INTERNAL PACKAGE INDUCTANCE (TO-220) Internal Drain Inductance (Measured from the contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Ld Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) Ls nH * Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2 Motorola TMOS Power MOSFET Transistor Device Data MTP12P10 20 VGS = -20 V -I D, DRAIN CURRENT (AMPS) 18 16 10 V TJ = 25C 8V 14 12 7V 10 8 6V 6 4 5V 2 0 0 1 2 3 4 5 6 7 8 9 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 10 VGS(th), GATE THRESHOLD VOLTAGE (NORMALIZED) TYPICAL ELECTRICAL CHARACTERISTICS 1.2 1 0.9 0.8 -50 I D, DRAIN CURRENT (AMPS) 25C 16 TJ = -55C 100C 12 8 VDS = 20 V 4 0 0 4 8 12 16 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 20 RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.4 25C -55C 0.1 0 0 4 8 12 16 20 24 28 32 150 1.6 VGS = 0 ID = 0.25 mA 1.2 0.8 0.4 0 -50 -75 0 25 50 75 100 125 150 Figure 4. Normalized Breakdown Voltage versus Temperature TJ = 100C 0.2 125 TJ, JUNCTION TEMPERATURE (C) 0.5 0.3 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 2 Figure 3. Transfer Characteristics VGS = 15 V -25 Figure 2. Gate-Threshold Voltage Variation With Temperature VBR(DSS), DRAIN-TO-SOURCE BREAKDOWN VOLTAGE (NORMALIZED) Figure 1. On-Region Characteristics 20 VDS = VGS ID = 1 mA 1.1 36 40 1.8 VGS = 10 V ID = 6 A 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150 ID, DRAIN CURRENT (AMPS) TJ, JUNCTION TEMPERATURE (C) Figure 5. On-Resistance versus Drain Current Figure 6. On-Resistance Variation With Temperature Motorola TMOS Power MOSFET Transistor Device Data 3 MTP12P10 SAFE OPERATING AREA INFORMATION 50 1 ms 10 I D, DRAIN CURRENT (AMPS) I D, DRAIN CURRENT (AMPS) 10 s 0.1 ms 10 ms VGS = 20 V SINGLE PULSE TC = 25C dc MTM/MTP12P06 RDS(on) LIMIT PACKAGE LIMIT THERMAL LIMIT MTM/MTP12P10 1 40 30 20 MTM/MTP12P06 10 MTM/MTP12P10 0 10 1 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 0 Figure 7. Maximum Rated Forward Biased Safe Operating Area 10 30 50 70 20 40 60 80 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 90 100 Figure 8. Maximum Rated Switching Safe Operating Area FORWARD BIASED SAFE OPERATING AREA SWITCHING SAFE OPERATING AREA The FBSOA curves define the maximum drain-to-source voltage and drain current that a device can safely handle when it is forward biased, or when it is on, or being turned on. Because these curves include the limitations of simultaneous high voltage and high current, up to the rating of the device, they are especially useful to designers of linear systems. The curves are based on a case temperature of 25C and a maximum junction temperature of 150C. Limitations for repetitive pulses at various case temperatures can be determined by using the thermal response curves. Motorola Application Note, AN569, "Transient Thermal Resistance-General Data and Its Use" provides detailed instructions. The switching safe operating area (SOA) of Figure 8 is the boundary that the load line may traverse without incurring damage to the MOSFET. The fundamental limits are the peak current, IDM and the breakdown voltage, V(BR)DSS. The switching SOA shown in Figure 8 is applicable for both turn- on and turn-off of the devices for switching times less than one microsecond. The power averaged over a complete switching cycle must be less than: TJ(max) - TC RJC r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1 D = 0.5 0.5 0.3 0.2 0.2 0.1 0.1 P(pk) 0.05 0.05 0.02 0.03 t1 0.02 t2 DUTY CYCLE, D = t1/t2 0.01 SINGLE PULSE 0.01 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 t, TIME (ms) 10 20 RJC(t) = r(t) RJC RJC = 1.67C/W MAX D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 50 100 200 500 1000 Figure 9. Thermal Response 4 Motorola TMOS Power MOSFET Transistor Device Data MTP12P10 0 VGS, GATE SOURCE VOLTAGE (VOLTS) C, CAPACITANCE (pF) 1600 TC = 25C VGS = 0 f = 1 MHz 1200 Ciss 800 Coss 400 Crss 0 0 10 30 20 VDS, SOURCE-TO-DRAIN VOLTAGE (VOLTS) 40 TJ = 25C ID = 12 A -2 -4 -6 -8 -10 VDS = 30 V -12 50 V -14 -16 80 V 0 5 10 15 20 25 30 35 40 45 50 Qg, TOTAL GATE CHARGE (nC) Figure 10. Capacitance Variation Figure 11. Gate Charge versus Gate-To-Source Voltage RESISTIVE SWITCHING VDD ton td(on) RL tr 90% Vout Vin PULSE GENERATOR Rgen 50 DUT z = 50 OUTPUT, Vout toff td(off) 10% 90% 50 INPUT, Vin Motorola TMOS Power MOSFET Transistor Device Data 50% 50% 10% INVERTED Figure 12. Switching Test Circuit tf 90% PULSE WIDTH Figure 13. Switching Waveforms 5 MTP12P10 PACKAGE DIMENSIONS -T- B NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. SEATING PLANE C F T S 4 A Q 1 2 3 STYLE 5: PIN 1. 2. 3. 4. U H K Z L R V J G D N GATE DRAIN SOURCE DRAIN DIM A B C D F G H J K L N Q R S T U V Z INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.147 0.095 0.105 0.110 0.155 0.018 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 --- --- 0.080 MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 3.73 2.42 2.66 2.80 3.93 0.46 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 --- --- 2.04 CASE 221A-06 ISSUE Y Motorola reserves the right to make changes without further notice to any products herein. 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Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE (602) 244-6609 INTERNET: http://Design-NET.com HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 6 *MTP12P10/D* Motorola TMOS Power MOSFET TransistorMTP12P10/D Device Data