1
Motorola TMOS Power MOSFET Transistor Device Data
P–Channel Enhancement–Mode Silicon Gate
This TMOS Power FET is designed for medium voltage, high
speed power switching applications such as switching regulators,
converters, solenoid and relay drivers.
•Silicon Gate for Fast Switching Speeds — Switching Times
Specified at 100°C
•Designer’s Data — IDSS, VDS(on), VGS(th) and SOA Specified
at Elevated Temperature
•Rugged — SOA is Power Dissipation Limited
•Source–to–Drain Diode Characterized for Use With Inductive Loads
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating Symbol Value Unit
Drain–Source Voltage VDSS 100 Vdc
Drain–Gate Voltage (RGS = 1.0 MΩ) VDGR 100 Vdc
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–repetitive (tp ≤ 50 µs) VGS
VGSM ±20
±40 Vdc
Vpk
Drain Current — Continuous
Drain Current — Pulsed ID
IDM 12
28 Adc
Total Power Dissipation
Derate above 25°CPD75
0.6 Watts
W/°C
Operating and Storage Temperature Range TJ, Tstg –65 to 150 °C
THERMAL CHARACTERISTICS
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient°RθJC
RθJA 1.67
62.5 °C/W
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds TL260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics —are given to facilitate “worst case” design.
Designer’s is a trademark of Motorola, Inc.
REV 1
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SEMICONDUCTOR TECHNICAL DATA
TMOS POWER FET
12 AMPERES
100 VOLTS
RDS(on) = 0.3 OHM
D
S
G
CASE 221A–06, Style 5
TO–220AB
Motorola, Inc. 1996
MTP12P10
2Motorola TMOS Power MOSFET Transistor Device Data
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic Symbol Min Max Unit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
(VGS = 0, ID = 0.25 mA) V(BR)DSS 100 — Vdc
Zero Gate Voltage Drain Current
(VDS = Rated VDSS, VGS = 0)
(VDS = Rated VDSS, VGS = 0, TJ = 125°C)
IDSS —
—10
100
µAdc
Gate–Body Leakage Current, Forward (VGSF = 20 Vdc, VDS = 0) IGSSF — 100 nAdc
Gate–Body Leakage Current, Reverse (VGSR = 20 Vdc, VDS = 0) IGSSR — 100 nAdc
ON CHARACTERISTICS*
Gate Threshold Voltage (VDS = VGS, ID = 1.0 mA)
TJ = 100°CVGS(th) 2.0
1.5 4.5
4.0 Vdc
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 6.0 Adc) RDS(on) — 0.3 Ohm
Drain–Source On–Voltage (VGS = 10 V)
(ID = 12 Adc)
(ID = 6.0 Adc, TJ = 100°C)
VDS(on) —
—4.2
3.8
Vdc
Forward Transconductance (VDS = 15 V, ID = 6.0 A) gFS 2.0 — mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 V, VGS = 0,
f = 1.0 MHz)
See Figure 10
Ciss — 920 pF
Output Capacitance
(VDS = 25 V, VGS = 0,
f = 1.0 MHz)
See Figure 10
Coss — 575
Reverse Transfer Capacitance
See Figure 10
Crss — 200
SWITCHING CHARACTERISTICS* (TJ = 100°C)
Turn–On Delay Time
(VDD = 25 V, ID = 0.5 Rated ID,
RG = 50 Ω)
See Figures 12 and 13
td(on) — 50 ns
Rise Time
(VDD = 25 V, ID = 0.5 Rated ID,
RG = 50 Ω)
See Figures 12 and 13
tr— 150
Turn–Off Delay Time
RG = 50 Ω)
See Figures 12 and 13
td(off) — 150
Fall Time tf— 150
Total Gate Charge
(VDS = 0.8 Rated VDSS,
ID = Rated ID, VGS = 10 V)
See Figure 11
Qg33 (Typ) 50 nC
Gate–Source Charge
(VDS = 0.8 Rated VDSS,
ID = Rated ID, VGS = 10 V)
See Figure 11
Qgs 16 (Typ) —
Gate–Drain Charge
See Figure 11
Qgd 17 (Typ) —
SOURCE–DRAIN DIODE CHARACTERISTICS*
Forward On–Voltage
(IS = Rated ID,
VGS = 0)
VSD 4.0 (Typ) 5.5 Vdc
Forward Turn–On Time
(IS = Rated ID,
VGS = 0)
ton Limited by stray inductance
Reverse Recovery Time
VGS = 0)
trr 300 (Typ) — ns
INTERNAL PACKAGE INDUCTANCE (TO–204)
Internal Drain Inductance
(Measured from the contact screw on the header closer
to the source pin and the center of the die)
Ld5.0 (Typ) —
nH
Internal Source Inductance
(Measured from the source pin, 0.25″ from the package
to the source bond pad)
Ls12.5 (Typ) —
INTERNAL PACKAGE INDUCTANCE (TO–220)
Internal Drain Inductance
(Measured from the contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)
Ld3.5 (Typ)
4.5 (Typ) —
—
nH
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad) Ls7.5 (Typ) —
*Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
MTP12P10
3
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
–VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. On–Region Characteristics
TJ, JUNCTION TEMPERATURE (
°
C)
Figure 2. Gate–Threshold Voltage Variation
With Temperature
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 3. Transfer Characteristics
TJ, JUNCTION TEMPERATURE (
°
C)
Figure 4. Normalized Breakdown Voltage
versus Temperature
ID, DRAIN CURRENT (AMPS)
Figure 5. On–Resistance versus Drain Current
TJ, JUNCTION TEMPERATURE (
°
C)
Figure 6. On–Resistance Variation
With Temperature
–ID, DRAIN CURRENT (AMPS)RDS(on), DRAIN–TO–SOURCE RESISTANCE (OHMS)
RDS(on), DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
ID, DRAIN CURRENT (AMPS)
VGS(th), GATE THRESHOLD VOLTAGE (NORMALIZED)
VBR(DSS), DRAIN–TO–SOURCE BREAKDOWN VOLTAGE
(NORMALIZED)
20
18
16
14
12
10
8
6
4
2
0109876543210
1.2
1.1
1
0.9
0.8
–50 –25 0 25 50 75 100 125 150
20
16
12
8
4
0201612840
2
1.6
1.2
0.8
0.4
0
–50 –75 0 25 50 75 100 125 150
0.5
0.4
0.3
0.2
0.1
04036322824201612840
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
–50 –25 0 25 50 75 100 125 150
TJ = 25
°
C
VGS = –20 V
8 V
10 V
7 V
6 V
5 V
VDS = VGS
ID = 1 mA
VDS = 20 V
TJ = –55
°
C
25
°
C
100
°
CVGS = 0
ID = 0.25 mA
TJ = 100
°
C
25
°
C
–55
°
C
VGS = 15 V VGS = 10 V
ID = 6 A
MTP12P10
4Motorola TMOS Power MOSFET Transistor Device Data
SAFE OPERATING AREA INFORMATION
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. Maximum Rated Forward Biased
Safe Operating Area
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 8. Maximum Rated Switching
Safe Operating Area
0 20 40 60 80
0
40
50
100
RDS(on) LIMIT
PACKAGE LIMIT
THERMAL LIMIT
10
VGS = 20 V
SINGLE PULSE
TC = 25
°
C
1
1
10
10
µ
s
1 ms
10 ms 30
10
100
0.1 ms
MTM/MTP12P06
MTM/MTP12P10
20
10 30 50 70 90
MTM/MTP12P06
MTM/MTP12P10
dc
FORWARD BIASED SAFE OPERATING AREA
The FBSOA curves define the maximum drain–to–source
voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned on.
Because these curves include the limitations of simultaneous
high voltage and high current, up to the rating of the device,
they are especially useful to designers of linear systems. The
curves are based on a case temperature of 25°C and a maxi-
mum junction temperature of 150°C. Limitations for repetitive
pulses at various case temperatures can be determined by
using the thermal response curves. Motorola Application
Note, AN569, “Transient Thermal Resistance–General Data
and Its Use” provides detailed instructions.
SWITCHING SAFE OPERATING AREA
The switching safe operating area (SOA) of Figure 8 is the
boundary that the load line may traverse without incurring
damage to the MOSFET. The fundamental limits are the
peak current, IDM and the breakdown voltage, V(BR)DSS. The
switching SOA shown in Figure 8 is applicable for both turn–
on and turn–off of the devices for switching times less than
one microsecond.
The power averaged over a complete switching cycle must
be less than:
TJ(max) – TC
RθJC
Figure 9. Thermal Response
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
R
θ
JC(t) = r(t) R
θ
JC
R
θ
JC = 1.67
°
C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) – TC = P(pk) R
θ
JC(t)
P(pk)
t1t2
DUTY CYCLE, D = t1/t2
t, TIME (ms)
1
0.01
D = 0.5
0.05
0.01
SINGLE PULSE
0.01
0.02
0.03
0.02
0.05
0.1
0.2
0.3
0.5
0.02 0.05 0.1 0.2 0.5 1 2 5 10 20 50 100 200 500 1000
0.1
0.2
MTP12P10
5
Motorola TMOS Power MOSFET Transistor Device Data
VDS, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
C, CAPACITANCE (pF)
Figure 10. Capacitance Variation
1600
4030
1200
800
400
020
100
TC = 25
°
C
VGS = 0
f = 1 MHz
Coss
Ciss
Crss
0 5 10 15 20 25 30 35 40 45 50
Qg, TOTAL GATE CHARGE (nC)
Figure 11. Gate Charge versus
Gate–To–Source Voltage
TJ = 25
°
C
ID = 12 A
VDS = 30 V
80 V
50 V
VGS, GATE SOURCE VOLTAGE (VOLTS)
0
–2
–4
–6
–8
–10
–12
–14
–16
RESISTIVE SWITCHING
PULSE GENERATOR
VDD
Vout
Vin
Rgen 50
Ω
z = 50
Ω
50
Ω
DUT
RL
Figure 12. Switching Test Circuit
toff
OUTPUT, Vout
ton
trtd(off) tf
td(on) 90%90%
10%
INPUT, Vin 10% 50%
90%
50%
PULSE WIDTH
Figure 13. Switching Waveforms
INVERTED
MTP12P10
6Motorola TMOS Power MOSFET Transistor Device Data
PACKAGE DIMENSIONS
CASE 221A–06
ISSUE Y
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.570 0.620 14.48 15.75
B0.380 0.405 9.66 10.28
C0.160 0.190 4.07 4.82
D0.025 0.035 0.64 0.88
F0.142 0.147 3.61 3.73
G0.095 0.105 2.42 2.66
H0.110 0.155 2.80 3.93
J0.018 0.025 0.46 0.64
K0.500 0.562 12.70 14.27
L0.045 0.060 1.15 1.52
N0.190 0.210 4.83 5.33
Q0.100 0.120 2.54 3.04
R0.080 0.110 2.04 2.79
S0.045 0.055 1.15 1.39
T0.235 0.255 5.97 6.47
U0.000 0.050 0.00 1.27
V0.045 ––– 1.15 –––
Z––– 0.080 ––– 2.04
B
Q
H
Z
L
V
G
N
A
K
F
1 2 3
4
D
SEATING
PLANE
–T–
C
S
T
U
R
J
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MTP12P10/D
*MTP12P10/D*
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