General Description
The MAX191 is a monolithic, CMOS, 12-bit analog-to-
digital converter (ADC) featuring differential inputs,
track/hold (T/H), internal voltage reference, internal or
external clock, and parallel or serial µP interface. The
MAX191 has a 7.5µs conversion time, a 2µs acquisition
time, and a guaranteed 100ksps sample rate.
The MAX191 operates from a single +5V supply or from
dual ±5V supplies, allowing ground-referenced bipolar
input signals. The device features a logic power-down
input, which reduces the 3mA VDD supply current to
50µA max, including the internal-reference current.
Decoupling capacitors are the only external compo-
nents needed for the power supply and reference. This
ADC operates with either an external reference, or an
internal reference that features an adjustment input for
trimming system gain errors.
The MAX191 provides three interface modes: two 8-bit
parallel modes, and a serial interface mode that is com-
patible with SPITM, QSPITM, and MICROWIRETM serial-
interface standards.
________________________Applications
Battery-Powered Data Logging
PC Pen Digitizers
High-Accuracy Process Control
Electromechanical Systems
Data-Acquisition Boards for PCs
Automatic Testing Systems
Telecommunications
Digital Signal Processing (DSP)
____________________________Features
♦12-Bit Resolution, 1/2LSB Linearity
♦+5V or ±5V Operation
♦Built-In Track/Hold
♦Internal Reference with Adjustment Capability
♦Low Power: 3mA Operating Mode
20µA Power-Down Mode
♦100ksps Tested Sampling Rate
♦Serial and 8-Bit Parallel µP Interface
♦24-Pin Narrow DIP and Wide SO Packages
MAX191
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
________________________________________________________________
Maxim Integrated Products
1
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
VDD
CLK/SCLK
PAR
HBEN
AIN-
AIN+
VSS
PD
TOP VIEW
CS
RD
D7/DOUT
D6/SCLKOUT
BIP
AGND
REFADJ
VREF
16
15
14
13
9
10
11
12
D5/SSTRB
D4
D3/D11
D2/D10
DGND
D1/D9
D0/D8
BUSY
DIP/SO
MAX191
Pin Configuration
2.46V
REF
IN REF OUT
12-BIT
SAR ADC
OSC
CONTROL
LOGIC
3-STATE
OUTPUT
8-BIT
BUS
AND
SERIAL
I/O
18
17
16
15
14
13
11
10
20
19
9
21
D7/DOUT
D6/SCLKOUT
D5/SSTRB
D4
D3/D11
D2/D10
D1/D9
D0/D8
CS
RD
BUSY
HBEN
REFADJ
VREF
AIN +
AIN -
5
6
3
4
24 23
VDD CLK/SCLK
712 PD
122 8
AGND DGND
2
PARBIP
MAX191
12
VSS
Functional Diagram
19-4506; Rev 4; 2/97
PART TEMP. RANGE PIN-PACKAGE
MAX191ACNG 0°C to +70°C 24 Narrow Plastic DIP
24 Wide SO
±1/2
±1
±1/2
ERROR
(LSB)
24 Narrow Plastic DIP
MAX191BCNG
MAX191ACWG 0°C to +70°C
0°C to +70°C
MAX191BCWG 0°C to +70°C 24 Wide SO ±1
MAX191BC/D Dice* ±10°C to +70°C
MAX191AENG -40°C to +85°C 24 Narrow Plastic DIP ±1/2
MAX191BENG -40°C to +85°C 24 Narrow Plastic DIP ±1
MAX191AEWG -40°C to +85°C 24 Wide SO ±1/2
MAX191AMRG 24 Narrow CERDIP** ±1/2
MAX191BMRG 24 Narrow CERDIP** ±1
-55°C to +125°C
-55°C to +125°C
MAX191BEWG -40°C to +85°C 24 Wide SO ±1
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
EVALUATION KIT MANUAL
FOLLOWS DATA SHEET
* Dice are specified at T
A
= +25°C, DC parameters only.
** Contact factory for availability and processing to MIL-STD-883.
Ordering Information
MAX191
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = 5V ±5%, VSS = 0V or -5V ±5%, fCLK = 1.6MHz, 50% duty cycle, AIN- = AGND, BIP = 0V, slow-memory mode, internal-reference
mode, reference compensation mode—external, synchronous operation, Figure 6, TA= TMIN to TMAX, unless otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to DGND............................................................-0.3V to +7V
VSS to AGND ............................................................-7V to +0.3V
VDD to VSS ..............................................................................12V
AGND, VREF, REFADJ to DGND................-0.3V to (VDD + 0.3V)
AIN+, AIN-, PD to VSS.................................-0.3V to (VDD + 0.3V)
CS, RD, CLK, BIP, HBEN, PAR, to DGND....-0.3V to (VDD + 0.3V)
BUSY, D0–D7 to DGND..............................-0.3V to (VDD + 0.3V)
Continuous Power Dissipation (TA= +70°C)
Narrow Plastic DIP (derate 13.33mW/ °C above +70°C)....1067mW
Wide SO (derate 11.76mW/°C above +70 °C) ......................941mW
Narrow CERDIP (derate 12.50mW/°C above +70 °C) ........1000mW
Operating Temperature Ranges
MAX191_C_ _................................................................0°C to +70°C
MAX191_E_ _ .............................................................-40 °C to +85°C
MAX191_M_ _ ..........................................................-55° C to +125°C
Storage Temperature Range.....................................-65°C to +160°C
Lead Temperature (soldering, 10sec).....................................+300°C
PARAMETER CONDITIONS MIN TYP MAX UNITS
Offset Error MAX191B ±2 LSB
MAX191A ±1
Differential Nonlinearity No missing codes over temperature ±1 LSB
Integral Nonlinearity MAX191B ±1 LSB
MAX191A ±2
Gain Error (Note 3) MAX191B ±3 LSB
Resolution 12 Bits
MAX191A ±1/2
Gain-Error Tempco (Note 4) Excludes internal-reference drift ±0.2 ppm/°C
1kHz input signal, TA= +25°C 70 dB
1kHz input signal, TA= +25°C -80 dB
Spurious-Free Dynamic Range 1kHz input signal, TA= +25°C 80 dB
Synchronous CLK (12 to 13 CLKs)
Conversion Time (Note 5) Internal CLK, CL= 120pF 6 12 18 µs
Track/Hold Acquisition Time 2 µs
Aperture Delay 25 ns
Aperture Jitter 50 ps
0.1 1.6 MHz
Signal-to-Noise plus Distortion
Ratio
Total Harmonic Distortion
(up to the 5th Harmonic)
External Clock Frequency
Range (Note 6)
SYMBOL
DNL
INL
SINAD
SFDR
THD
tCONV
fCLK
7.50 8.125
DC ACCURACY (Note 2)
DYNAMIC ACCURACY (sample rate = 100kHz, VIN = 4Vp-p)
CONVERSION RATE
mA
MAX191
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V ±5%, VSS = 0V or -5V ±5%, fCLK = 1.6MHz, 50% duty cycle, AIN- = AGND, BIP = 0V, slow-memory mode, internal-reference
mode, reference compensation mode—external, synchronous operation, Figure 6, TA= TMIN to TMAX, unless otherwise noted.) (Note 1)
PD External Leakage for Float
State (Note 12)
VFLT V2.8Reference compensation mode—external
PD Floating-State Voltage
nA±100Maximum current allowed for “floating state”
IIN µA±20
PD = 0V to VDD (Note 11)
PD Input Current
±200
PD = high/float
IIN µA
±0.1
PD = low
Input Current CLK
CIN pF10Input Capacitance (Note 6) VIL V0.5
PD Input Low Voltage VIH V4.5
PD Input High Voltage
IIN µA±10
VIN = 0V to VDD
Input Current
VIH V2.4
CS, RD, CLK, HBEN, PAR, BIP
Input High Voltage
VIL V0.8
CS, RD, CLK, HBEN, PAR, BIP
Input Low Voltage
kΩ510External-reference modeInput Resistance mA1External-reference = 5VInput Current
REFADJ Input Adjustment Range
(Note 10)
V2.5 5.0External-reference modeInput Voltage Range
µA60REFADJ = 5VREFADJ Input Current V2.4REFADJ Output Voltage V4.5REFADJ Disable Threshold
mV-60 30
µV±300
VDD = ±5%, VSS = ±5%
Power-Supply Rejection µF4.7Reference compensation mode—externalCapacitive Load Required mA18Output Short-Circuit Current mV4
TA= +25°C, IOUT = 0mA to 2mA
Load Regulation
SYMBOL UNITSMIN TYP MAXCONDITIONSPARAMETER
Input Voltage Range (Note 7) V
VSS VDD
Input Capacitance (Note 6) pF45 80
Input Leakage Current µA±10
VIN = VSS to VDD
50MAX191_C
VREF Output Voltage V4.076 4.096 4.116
TA= +25°C
Small-Signal Bandwidth MHz2
60MAX191_E
Output Current Capability (Note 9) mA2
TA= +25°C
VREF Output Tempco (Note 8) ppm/°C
80MAX191_M
ANALOG INPUT
INTERNAL REFERENCE
REFERENCE INPUT
LOGIC INPUTS
MAX191
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V ±5%, VSS = 0V or -5V ±5%, fCLK = 1.6MHz, 50% duty cycle, AIN- = AGND, BIP = 0V, slow-memory mode, internal-reference
mode, reference compensation mode—external, synchronous operation, Figure 6, TA= TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER
RD Pulse Width
CONDITIONS
150
UNITS
MAX191C/E
MIN TYP MAX
150 ns
140
0140
MAX191M
MIN TYP MAX
150 160
0160
CL= 100pF 120 ns
80 100 ns120t8
110 120100 nst7
100 12080 nst6
0 0
CS to RD Hold Time 0 nst5
SYMBOL
RD to BUSY Delay
CS to RD Setup Time 0 ns
CL= 50pF 120 ns
t4
t3
t2
t1
TIMING CHARACTERISTICS (Figures 6–10)
(VDD =5V ±5%, VSS = 0V or -5V ±5%, TA= TMIN to TMAX, unless otherwise noted.) (Note 14)
Aperture Delay Jitter < 50ps 25 nst12
2 22
200 200200 nst10
HBEN to RD Hold Time 0 0 ns0t9
Data Access Time (Note 15)
Data Setup Time After
BUSY (Note 15)
Bus-Relinquish Time (Note 16)
HBEN to RD Setup Time
Delay Between Read
Operations (Note 6)
200 230 ns260t13
CLK to BUSY Delay (Note 6)
100 130 ns150t14
SCLKOUT to SSTRB
Rise Delay
SCLKOUT to SSTRB
Fall Delay 100 130 ns150t15
TA= +25°C
MIN TYP MAX
µst11
Delay Between Conversions
VSS V-5.25 0Negative Supply Voltage
IDD
VDD
VOL
VOH
COUT
IL
µA20 50
V0.4IOUT = 1.6mA
mA3 5
V4.75 5.25Positive Supply Voltage
Output Low Voltage
SYMBOL
PD = low
PD = high/float
PD = low
LSB±1/2FS change, VSS = -5V ±5%Negative Supply Rejection (Note 13) LSB±1/2FS change, VDD = 5V ±5%Positive Supply Rejection (Note 13)
ISS µA
V
pF
4.0IOUT = -200µAOutput High Voltage
120
CS = RD = VDD,
AIN = 5V, D0/D8–D7/
DOUT = 0V or VDD,
HBEN = PAR = BIP
= 0V or VDD
Positive Supply Current
15
PD = high/float
Three-State Output
Capacitance (Note 6)
20 100
µA
Negative Supply Current
UNITS
±10D0/D8-D7/DOUT
MIN TYP MAXCONDITIONS
Three-State Leakage Current
PARAMETER
LOGIC OUTPUTS
POWER REQUIREMENTS
MAX191
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
_______________________________________________________________________________________ 5
PARAMETER
SCLK to SCLKOUT Delay
CONDITIONS
160
UNITS
ns
CS to DOUT Three-State 100 ns
SYMBOL
CS or RD Setup Time
CS or RD Hold Time ns
150 ns
t20
t19
t17
t16
TIMING CHARACTERISTICS (Figures 6–10) (continued)
(VDD =5V ±5%, VSS = 0V or -5V ±5%, TA= TMIN to TMAX, unless otherwise noted.) (Note 14)
10
MAX191C/E
MIN TYP MAX
180
110
10
150
MAX191M
MIN TYP MAX
200
120
10
150
310 350SCLK to SSTRB Delay 260 nst23
260 280SCLK to DOUT Delay 240 nst22
130SCLKOUT to DOUT Delay 100 nst21 150
Note 1: Performance at power-supply tolerance limits guaranteed by power-supply rejection test.
Note 2: VDD = 5V, VSS = 0V, FS = VREF.
Note 3: FS = VREF, offset nulled, ideal last-code transition = FS - 3/2 LSB.
Note 4: Gain-Error Tempco = ∆GE is the gain-error change from TA= +25°C to TMIN or TMAX.
Note 5: Conversion time defined as the number of clock cycles times the clock period; clock has a 50% duty cycle.
Note 6: Guaranteed by design, not production tested.
Note 7: AIN+, AIN- must not exceed supplies for specified accuracy.
Note 8: VREF TC = ∆T, where ∆VREF is reference-voltage change from TA= +25°C to TMIN or TMAX.
Note 9: Output current should not change during conversion. This current is in addition to the current required by the internal DAC.
Note 10: REFADJ adjustment range is defined as the allowed voltage excursion on REFADJ relative to its unadjusted value of 2.4V.
This will typically result in a 1.7 times larger change in the REF output (Figure 19a).
Note 11: This current is included in the PD supply current specification.
Note 12: Floating the PD pin guarantees external compensation mode.
Note 13: VREF = 4.096V, external reference.
Note 14: All input control signals are specified with tr= tf= 5ns (10% to 90% of 5V) and timed from a voltage level of 1.6V.
Note 15: t3and t6are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V.
Note 16: t7is defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 2.
TA= +25°C
MIN TYP MAX
MAX191
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
6 _______________________________________________________________________________________
__________________________________________Typical Operating Characteristics
10
0.01 0.1 10
CLOCK FREQUENCY
vs. TIMING CAPACITOR
0.1
1
TIMING CAPACITOR (nF)
CLOCK FREQUENCY (MHz)
1
SEE FIGURE 5
TA = +25˚C
GR191-A
0-60 150
5
25
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
120
15
10
0 60
20
-30 30 90
VDD = +5V
VSS = -5V
PD = 0V
ISS
IDD
POWER-DOWN SUPPLY CURRENT
vs. TEMPERATURE
GR191-B
0-60 150
5
25
TEMPERATURE (°C)
ISS (µA)
120
15
10
0 60
20
-30 30 90
NEGATIVE SUPPLY CURRENT
vs. TEMPERATURE
GR191-C
3.5
0.5
-60 -30 30 60
1.0
2.0
TEMPERATURE (°C)
IDD (mA)
0
1.5
90 120 150
2.5
3.0
0
POSITIVE SUPPLY CURRENT
vs. TEMPERATURE
GR191-D
0
-140 0 2 6
1kHz FFT PLOT
-100
-40
GR191-E
FREQUENCY (kHz)
SIGNAL AMPLITUDE (dB)
4
-80
1 3 5
-120
-60
-20 fIN = 1kHz
fS = 100kHz
SNR = 72dB
TA = +25˚C
-94.3dB-96.1dB-98.0dB-93.8dB
0
-140 0 10 30 40
10kHz FFT PLOT
-100
-60
GR191-F
FREQUENCY (kHz)
SIGNAL AMPLITUDE (dB)
15
-80
-120
-40
-20 fIN = 10kHz
fS = 100kHz
SNR = 71.2dB
TA = +25˚C
5 20 25 35
-86.0dB -90.8dB
MAX191
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
_______________________________________________________________________________________ 7
Pin Description
Clock Input/Serial Clock Input in serial mode. An external TTL-/CMOS-compatible clock may be applied to
this pin, or a capacitor (120pF nominal) may be connected between CLK and DGND to operate the internal
oscillator.
High-Byte Enable Input. In parallel mode, HBEN = high multiplexes the 4 MSBs of the conversion result
into the lower bit outputs. HBEN = high also disables conversion starts. HBEN = low places the 8 LSBs
onto the data bus. In serial mode, HBEN = low enables SCLKOUT to operate during the conversion only,
HBEN = high enables SCLKOUT to operate continuously, provided CS is low.
Chip-Select Input must be low for the ADC to recognize RD and HBEN inputs in parallel mode. The falling
edge of CS starts a conversion in serial mode. CS = high in serial mode forces SCLKOUT, SSTRB, and
DOUT into a high-impedance state.
Read Input. In parallel mode, a low signal starts a conversion when CS and HBEN are low (memory
mode). RD also enables the outputs when CS is low. In serial mode, RD = low enables SCLKOUT and
SSTRB when CS is low. RD = high forces SCLKOUT and SSTRB into a high-impedance state.
D6/SCLKOUT
7 Analog GroundAGND
24 Positive Supply, +5V ±5%VDD
23 CLK/SCLK
22 Sets the output mode. PAR = high selects parallel output mode. PAR = low selects serial output mode.PAR
21 HBEN
20 CS
19 RD
18 Three-State Data Output/Data Output in serial modeD7/DOUT
13 Three-State Data OutputsD2/D10
14 Three-State Data Outputs: MSB = D11D3/D11
15 Three-State Data OutputD4
16 Three-State Data Output/Serial Strobe Output in serial modeD5/SSTRB
17 Three-State Data Output/Serial Clock Output in serial mode
10 Three-State Data Outputs: LSB = D0D0/D8
11 Three-State Data OutputsD1/D9
12 Digital GroundDGND
Power-Down Input. A logic low at PD deactivates the ADC—only the bandgap reference is active. A logic
high selects normal operation, internal-reference compensation mode. An open-circuit condition selects
normal operation, external-reference compensation mode.
PIN
9
8
6
BUSY Output is low during a conversion.BUSY
BIP = low selects unipolar mode
BIP = high selects bipolar mode (see
Gain and Offset Adjustment
section)
BIP
5
4
3
Reference Adjust. Connect to VDD to use an extended reference at VREF.REFADJ
Reference-Buffer Output for Internal Reference. Input for external reference when REFADJ is connected to
VDD.
VREF
Analog Input Return. Pseudo-differential (see
Gain and Offset Adjustment
section).AIN-
2
1
Sampled Analog InputAIN+
Negative Supply, 0V to -5.25VVSS
PD
FUNCTION
NAME
_______________Detailed Description
The MAX191 uses successive approximation and input
track/hold (T/H) circuitry to convert an analog input sig-
nal to a 12-bit digital output. Flexible control logic pro-
vides easy interface to microprocessors (µPs), so most
applications require only the addition of passive com-
ponents. No external hold capacitor is required for the
T/H. Figure 3 shows the MAX191 in its simplest opera-
tional configuration.
Pseudo-Differential Input
The sampling architecture of the ADC’s analog com-
parator is illustrated in the Equivalent Input Circuit
(Figure 4). A capacitor switching between the AIN+
and AIN- inputs acquires the signal at the ADC’s ana-
log input. At the end of the conversion, the capacitor
reconnects to AIN+ and charges to the input signal.
An external input buffer is usually not needed for low-
bandwidth input signals (<100Hz) because the ADC
disconnects from the input during the conversion. In
unbuffered applications, an input filter capacitor
reduces conversion noise, but also may limit input
bandwidth.
When converting a single-ended input signal, AIN-
should be connected to AGND. If a differential signal is
connected, consider that the configuration is pseudo
differential—only the signal side to the input channel is
held by the T/H. The return side (AIN-) must remain sta-
ble within ±0.5LSB (±0.1LSB for best results) with
respect to AGND during a conversion. Accomplish this
by connecting a 0.1µF capacitor from AIN- to AGND.
Analog Input—Track/Hold
The T/H enters its tracking mode when the ADC is des-
elected (CS pin is held high and BUSY pin is high).
Hold mode starts approximately 25ns after a conver-
sion is initiated. The variation in this delay from one
conversion to the next (aperture jitter) is about 50ps.
Figures 6–10 detail the T/H and interface timing for the
MAX191
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
8 _______________________________________________________________________________________
DN
3k CL
DGND
+5V
3k
DN
CL
DGND
a. High-Z to VOH and VOL to VOH b. High-Z to VOL and VOH to VOL
Figure 1. Load Circuits for Access Time
DN
3k 10pF
DGND
+5V
3k
DN
10pF
DGND
a. VOH to High-Z b. VOL to High-Z
Figure 2. Load Circuits for Bus-Relinquish Time
1
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
PD
AIN+
AIN-
VREF
REFADJ
AGND
BIP
BUSY
DO/DB
D1/D9
DGNDVSS
2
VDD
CLK/SCLK
PAR
HBEN
CS
RD
D7/DOUT
D6/SCLKOUT
D5/SSTRB
D4
D3/D11
D2/D10
OPEN
OUTPUT
STATUS
4.7µF0.1µF
0.1µF
0V TO -5V
+5V
SERIAL/PARALLEL
INTERFACE MODE
µP CONTROL
INPUTS
MAX191
C1
NOTE: C1 120pF GENERATES 1MHz NOMINAL CLOCK.
µP DATA BUS
Figure 3. Operational Diagram
various interface modes.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. Acquisition time is cal-
culated by: tACQ = 10(RS+ RIN)CHOLD (but never less
than 2µs), where RIN = 2kΩ, RS = source impedance of
the input signal, and CHOLD = 32pF (see Figure 4).
Input Bandwidth
The ADC’s input tracking circuitry has a 1MHz typical
large-signal bandwidth characteristic, and a 30V/µs
slew rate. It is possible to digitize high-speed transients
and measure periodic signals with bandwidths exceed-
ing the ADC’s sample rate of 100ksps by using under-
sampling techniques. Note that if undersampling is
used to measure high-frequency signals, special care
must be taken to avoid aliasing errors. Without ade-
quate input bandpass filtering, out-of-band signals and
noise may be aliased into the measurement band.
Input Protection
Internal protection diodes, which clamp the analog input
to VDD and VSS , allow AIN+ to swing from (VSS - 0.3V) to
(VDD + 0.3V) with no risk of damage to the ADC.
However, for accurate conversions near full scale, AIN+
should not exceed the power supplies by more than
50mV because ADC accuracy is affected when the pro-
tection diodes are even slightly forward biased.
Digital Interface
Starting a Conversion
In parallel mode, the ADC is controlled by the CS, RD,
and HBEN inputs, as shown in Figure 6. The T/H
enters hold mode and a conversion starts at the falling
edge of CS and RD while HBEN (not shown) is low.
BUSY goes low as soon as the conversion starts. On
the falling edge of the 13th input clock pulse after the
conversion starts, BUSY goes high and the conversion
result is latched into three-state output buffers. In seri-
al mode, the falling edge of CS initiates a conversion,
and the T/H enters hold mode. Data is shifted out seri-
ally as the conversion proceeds (Figure 10). See the
Parallel Digital-Interface Mode
and
Serial-Interface
Mode
sections for details.
Internal/External Clock
Figure 5 shows the MAX191 clock circuitry. The ADC
includes internal circuitry to generate a clock with an
external capacitor. As indicated in the
Typical
Operating Characteristics
, a 120pF capacitor con-
nected between the CLK and DGND pins generates
a 1MHz nominal clock frequency (Figure 5).
Alternatively, an external clock (between 100kHz and
1.6MHz) can be applied to CLK. When using an exter-
nal clock source, acceptable clock duty cycles are
MAX191
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
_______________________________________________________________________________________ 9
12-BIT DAC
TRACK CHOLD COMPARATOR
HOLD 32pF
HOLD
CSWITCH
10pF
CPACKAGE
5pF
AIN +
AIN -
RIN
Figure 4. Equivalent Input Circuit
CEXT
DGND
CLK
+1.6V
CLOCK
MAX191
NOTE: CEXT = 120pF GENERATES 1MHz NOMINAL CLOCK
Figure 5. Internal Clock Circuit
MAX191
between 45% and 55%.
Clock and Control Synchronization
For best analog performance on the MAX191, the clock
should be synchronized to the conversion start signals
(CS and RD) as shown in Figure 6. A conversion should
not be started in the 50ns before a clock edge nor in
the 100ns after it. This ensures that CLK transitions are
not coupled to the analog input and sampled by the
T/H. The magnitude of this feedthrough can be a few
millivolts. When the clock and conversion start signals
are synchronized, small end-point errors (offset and
full-scale) are the most that can be generated by clock
feedthrough. Even these errors (which can be trimmed
out) can be avoided by ensuring that the start of a con-
version (RD or CS falling edge) does not occur close to
a clock transition (Figure 6), as described above.
Parallel Digital-Interface Mode
Output-Data Format
The data output from the MAX191 is straight binary in
the unipolar mode. In the bipolar mode, the MSB is
inverted (see Figure 22). The 12 data bits can be out-
put either in two 8-bit bytes or as a serial output. Table
1 shows the data-bus output format.
A 2-byte read uses outputs D7–D0. Byte selection is
controlled by HBEN. When HBEN is low, the lower 8
bits appear at the data outputs. When HBEN is high,
the upper 4 bits appear at D0-D3 with the leading 4 bits
low in locations D4–D7.
Timing and Control
Conversion-start and data-read operations are con-
trolled by the HBEN, CS, and RD digital inputs. A logic
low is required on all three inputs to start a conversion,
and once the conversion is in progress it cannot be
restarted. BUSY remains low during the entire conver-
sion cycle.
The timing diagrams of Figures 7–10 outline two paral-
lel-interface modes and one serial mode.
Slow-Memory Mode
In slow-memory mode, the device appears to the µP as
a slow peripheral or memory. Conversion is initiated
with a read instruction (see Figure 7 and Table 2). Set
the PAR pin high for parallel interface mode. Beginning
with HBEN low, taking CS and RD low starts the con-
version. The analog input is sampled on the falling
edge of RD. BUSY remains low while the conversion is
in progress. The previous conversion result appears at
the digital outputs until the end of conversion, when
BUSY returns high. The output latches are then updat-
ed with the newest results of the 8 LSBs on D7–D0. A
second read operation with HBEN high places the 4
MSBs, with 4 leading 0s, on data outputs D7–D0. The
second read operation does not start a new conversion
because HBEN is high.
ROM Mode
As in slow-memory mode, D7–D0 are used for 2-byte
reads. A conversion starts with a read instruction with
HBEN and CS low. The T/H samples the input on the
falling edge of RD (see Figure 8 and Table 3). PAR is set
high. At this point the data outputs contain the 8 LSBs
from the previous conversion. Two more read operations
are needed to access the conversion result. The first
occurs with HBEN high, where the 4 MSBs with 4 leading
0s are accessed. The second read, with HBEN low, out-
puts the 8 LSBs and also starts a new conversion.
Figure 9 and Table 4 show how to read output data
within one conversion cycle without starting another
conversion. Trigger the falling edge of a read on the ris-
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
10 ______________________________________________________________________________________
tCONV
CS + RD
BUSY
t16
CLK
t17
t2
t13
t2
tCONV
Figure 6. CS, RD, and CLK Synchronous Operation
MAX191
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
______________________________________________________________________________________ 11
DATA
HOLD*
TRACK
NEW DATA
D11–D8
*INTERNAL SIGNAL. TRACKING INPUT SIGNAL WHEN HOLD = Low, HOLDING WHEN HOLD = High.
t8
tCONV
BUSY
RD
CS
HBEN
t1
t2
t3
t12
NEW DATA
D7–D0
OLD DATA
D7–D0
t6t7t3t7
t10
t11
t10
t12
t4
t1t5
t5
t9t8t9
Figure 7. Slow-Memory Mode Timing
HBEN
CS
RD
BUSY
DATA
HOLD*
TRACK
t12
t3t7
t12
t3t7t3t7
t11
t10 t2
t2tCONV
t5
t4
t1
t5
t4
t1
t5
t4
t1
t8t9t8t9t8t9
OLD DATA
D7–D0 NEW DATA
D11–D8 NEW DATA
D7–D0
*INTERNAL SIGNAL. TRACKING INPUT SIGNAL WHEN HOLD = Low, HOLDING WHEN HOLD = High.
Figure 8. ROM Mode Timing
MAX191
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
12 ______________________________________________________________________________________
HBEN
CLK
CS
RD
BUSY
DATA
HOLD*
TRACK
t8
t1t4t5
t2tCONV
t12
t3t7t3t7
t10
t9t8
*INTERNAL SIGNAL. TRACKING INPUT SIGNAL WHEN HOLD = Low, HOLDING WHEN HOLD = High
NEW DATA
D7–D0 NEW DATA
D11–D8
t7
t3OLD DATA
D7–D0
Figure 9. ROM Mode Timing, Reading Data without Starting a Conversion
SCLKOUT
SCLK
CS
SSTRB
DOUT
t20
t20 t22
t16
t23
t14 t15
t22
t21
t19
THREE STATE
THREE STATE
t23
t17
t12
12 SCLK CYCLES
HOLD
TRACK
THREE STATE
THREE STATE
Figure 10. Serial-Interface Mode Timing Diagram (RD = low)
MAX191
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
______________________________________________________________________________________ 13
Table 1. Data-Bus Output, CS = RD = Low
PIN NAME D7/DOUT D4 D3/D11 D2/D10 D1/D9 D0/D8
D7 D6 D5 D4 D3 D2 D1 D0
HBEN = 1, PAR = 1,
PARALLEL MODE Low Low Low Low D11 D10 D9 D8
DOUT SCLKOUT SSTRB Low Low Low Low Low
HBEN = X, PAR = 0,
SERIAL MODE, RD = 1 DOUT Three-
Stated Low Low Low Low Low
D6/SCLKOUT D5/SSTRB
Three-
Stated
HBEN = X, PAR = 0,
SERIAL MODE, RD = 0
Note: D7/DOUT–D0/D8 are the ADC data output pins.
D11–D0 are the 12-bit conversion results. D11 is the MSB.
DOUT = Three-state data output. Data output in serial mode.
SCLKOUT = Three-state data output. Clock output in serial mode.
SSTRB = Three-state data output. Strobe output in serial mode.
Table 2. Slow-Memory Mode, 2-Byte Read Data-Bus Status
HBEN = 0, PAR = 1,
PARALLEL MODE
PIN NAME D7/DOUT D6/SCLKOUT D5/SSTRB D4 D3/D11 D2/D10 D1/D9 D0/D8
FIRST READ (New Data) D7 D6 D5 D4 D3 D2 D1 D0
Low Low Low Low D11 D10 D9 D8SECOND READ (New Data)
Table 3. ROM Mode, 2-Byte Read Data-Bus Status
PIN NAME D7/DOUT D6/SCLKOUT D5/SSTRB D4 D3/D11 D2/D10 D1/D9 D0/D8
D7 D6 D5 D4 D3 D2 D1 D0
SECOND READ (New Data) Low Low Low Low D11 D10 D9 D8
THIRD READ (New Data) D7 D6 D5 D4 D3 D2 D1 D0
Table 4. ROM Mode, 2-Byte Read Data-Bus Status without Starting a Conversion Cycle
PIN NAME D7/DOUT D6/SCLKOUT D5/SSTRB D4 D3/D11 D2/D10 D1/D9 D0/D8
FIRST READ (Old Data) D7 D6 D5 D4 D3 D2 D1 D0
SECOND READ (New Data) D7 D6 D5 D4 D3 D2 D1 D0
THIRD READ (New Data) Low Low Low Low D11 D10 D9 D8
FIRST READ (Old Data)
MAX191
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
14 ______________________________________________________________________________________
3
4
5
6
10
11
12
13
1
2
8
9
18
17
21
23
20
19
16
1
2
8
9
3
4
5
6
10
11
12
13
SCLK
CS
RD DOUT
SCLKOUT
HBEN
SSTRB
+5V
LOGIC INPUT
A
B
CLOCK
CLEAR
QA
QB
QC
QD
QE
QF
QG
QH
A
B
CLOCK
CLEAR
QA
QB
QC
QD
QE
QF
QG
QH
+5V
NOTE: USE SSTRB TO GATE PARALLEL DATA TRANSFER FROM SHIFT REGISTER, OR TO CLEAR SHIFT REGISTERS IF DESIRED.
MAX191
74HC164
74HC164
+5V
t19
DO
D11
CS
SSTRB
SCLKOUT
SCLK
DOUT
Figure 11. Simple Serial-to-Parallel Interface
MAX191
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
______________________________________________________________________________________ 15
ing edge of the first clock cycle after conversion end
(when BUSY goes high). As mentioned previously, two
more read operations (after BUSY goes high) are
needed to access the conversion results. The only dif-
ference is that now the low byte can be read first. This
happens by allowing the first read operation to occur
with HBEN low, where the 8 LSBs are accessed. The
second read, with HBEN high, accesses the 4 MSBs
with 4 leading 0s.
Serial-Interface Mode
The serial mode is compatible with Microwire, SPI and
QSPI serial interfaces. In addition, a framing signal
(SSTRB) is provided that allows the devices to interface
with the TMS320 family of DSPs. Set PAR low for serial
mode. A falling edge on CS causes the T/H to sample
the input (Figure 10). Conversion always begins on the
next falling edge of SCLK, regardless of where CS
occurs. The DOUT line remains high-impedance until a
conversion begins. During the MSB decision, DOUT
remains low (leading 0), while SSTRB goes high to indi-
cate that a data frame is beginning. The data is avail-
able at DOUT on the rising edge of SCLK (SCLKOUT
when using an internal clock) and transitions on the
falling edge. DOUT remains low after all data bits have
been shifted out, inserting trailing 0s in the data stream
until CS returns high. The SCLKOUT signal is synchro-
nous with the internal or external clock.
For interface flexibility, DOUT, SCLKOUT and SSTRB
signals enter a high-impedance state when CS is high.
When CS is low, RD controls the status of SCLKOUT and
SSTRB outputs. A logic low RD enables SCLKOUT and
SSTRB, while a logic high forces both outputs into a
high-impedance state. Also, with CS low and HBEN
high, SCLKOUT drives continuously, regardless of con-
version status. This is useful with µPs that require a
continuous serial clock. If CS and HBEN are low,
SCLKOUT is output only during the conversion cycle,
while the converter internal clock runs continuously.
This is useful for creating a simple serial-to-parallel
interface without shift-register overflow (Figure 11).
Maximum Clock Rate in Serial Mode
The maximum SCLK rate depends on the minimum
setup time required at the serial data input to the µP
and the ADC’s DOUT to SCLK delay (t22) (see Figure
12). The maximum fSCLK is as follows:
DOUT
SCLK
tSETUP (MIN)
t22
1 1
fSCLK (MAX) = –– –––––––––
2 tSU(M) + t22
()
tSU(M) IS THE SETUP TIME REQUIRED AT THE SERIAL DATA INPUT TO THE µP.
t22 IS THE MAXIMUM SCLK TO DOUT DELAY.
Figure 12. fSCLK(MAX) is limited by the setup time required by
the serial data input to the µP.
I/O CS
SCK
MISO
SS
SCLK
DOUT
+5V
CS
SCK
MISO
CS
SCLK
DOUT
+5V
CS
SCLK
DOUT
CS
SCLK
SSTRB
I/O
SK
SI
I/O
CLKX
CLKR
DR
FSR
MAX191
MAX191
MAX191
MAX191
a. SPI
b. QSPI
c. MICROWIRE
d. TMS320 SERIAL INTERFACE
DOUT
SS
Figure 13. Common Serial-Interface Connections to the MAX191
MAX191
fSCLK(MAX) = (1/2) x 1/ (tsu(M) + t22)
where tsu(M) is the minimum data-setup time re-
quired at the serial data input to the µP. For example,
Motorola’s MC68HC11A8 data book specifies a 100ns
minimum data-setup time. Using the worst case for a
military grade part of t22 = 280ns (see
Timing
Characteristics
) and substituting in the above equation
indicates a maximum SCLK frequency of 1.3MHz.
Using the MAX191 with SPI, QSPI and
MICROWIRE Serial Interfaces
Figure 13 shows interface connections to the MAX191
for common serial-interface standards.
SPI and MICROWIRE (CPOL=0, CPHA=0)
The MAX191 is compatible with SPI, QSPI and
MICROWIRE serial-interface standards. When using SPI
or QSPI, two modes are available to interface with the
MAX191. You can set CPOL = 0 and CPHA = 0 (Figure
14a), or set CPOL = 1 and CPHA = 1 (Figure 14b). When
using CPOL = 0 and CPHA = 0, the conversion begins
on the first falling edge of SCLK following CS going low.
Data is available from DOUT on the rising edge of SCLK,
and transitions on the falling edge. Two consecutive
1-byte reads are required to get the full 12 bits from the
ADC. The first byte contains the following, in this order: a
leading unknown bit (DOUT will still be high-impedance
on the first bit), a 0, and the six MSBs. The second byte
contains the remaining six LSBs and two trailing 0s.
SPI (CPOL=1, CPHA=1)
Setting CPOL = 1 and CPHA = 1 starts the clock high
during a read instruction. The MAX191 will shift out a
leading 0 followed by the 12 data bits and three trailing
0s (Figure 14b).
QSPI
Unlike SPI, which requires two 1-byte reads to acquire
the 12 bits of data from the ADC, QSPI allows the mini-
mum number of clock cycles required to clock in the
data (Figure 15).
TMS320 Serial Interface
Figure 13d shows the pin connections to interface the
MAX191 to the TMS320. Since the MAX191 makes data
available on the rising edge of SCLK and the TMS320
shifts data in on the falling edge of CLKR, use CLKX of the
DSP to drive SCLK, and CLKX to drive the DSP’s CLKR
input. The inverter’s propagation delay also provides more
data-setup time at the DSP. For example, with no inverter
delay, and using t22 = 280ns and fSCLK = 1.6MHz, the
available setup time before the SCLK transition is:
setup time = 1/ (2 x fSCLK) - t22 = 1/ (2 x 1.6E6) - 280ns = 32ns
This still exceeds the 13ns minimum DR setup time before
the CLKR goes low (tsu(DR)), however, a generic 74HC04
provides an additional 20ns setup time (see Figure 13d).
Figure 16 shows the DSP interface timing characteris-
tics. The DSP begins clocking data in on the falling
edge of CLKR after the falling edge of SSTRB.
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
16 ______________________________________________________________________________________
DOUT
LEADING
ZERO
MSB D9D10 D7D8 D5D6 D3D4 D1D2 LSB
CS
SCLK
HIGH-Z
1ST BYTE READ 2ND BYTE READ
HIGH-Z
a. CPOL = 0, CPHA = 0
DOUT
LEADING
ZERO
MSB D9D10 D7D8 D5D6 D3D4 D1D2 LSB
CS
SCLK
HIGH-Z HIGH-Z
b. CPOL = 1, CPHA = 1
Figure 14. SPI/MICROWIRE Serial-Interface Timing
MAX191
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
______________________________________________________________________________________ 17
DOUT MSB D9D10 D7D8 D5D6 D3D4 D1D2 LSB
CS
SCLK
HIGH-Z HIGH-Z
a. CPOL = 0, CPHA = 0
DOUT MSB D9D10 D7D8 D5D6 D3D4 D1D2 LSB
CS
SCLK
HIGH-Z HIGH-Z
b. CPOL = 1, CPHA = 1
Figure 15. QSPI Serial-Interface Timing
DOUT MSB D9D10 D7D8 D5D6 D3D4 D1D2 LSB
CS
HIGH-Z HIGH-Z
CLKR
SSTRB
SCLK
HIGH-Z HIGH-Z
Figure 16. TMS320 Interface Timing
MAX191
Following the data transfer, the DSP receive shift regis-
ter (RSR) contains a 16-bit word consisting of the 12
data bits, MSB first, followed by four trailing 0s.
Applications Information
Power-On Initialization
When the +5V power supply is first applied to the
MAX191, perform a single conversion to initialize the
ADC (the BUSY signal status is undefined at power-on).
Disregard the data outputs.
Power-Down Mode
In some battery-powered systems, it is desirable to
power down or remove power from the ADC during
inactive periods. To power down the MAX191, drive PD
low. In this mode, all internal ADC circuitry is off except
the reference, and the ADC consumes less than 50µA
max (assuming all signals CS, RD, CLK, and HBEN are
static and within 200mV of the supplies). Figure 17
shows a practical way to drive the PD pin. If using inter-
nal reference compensation, drive PD between VDD
and DGND with a µP I/O pin or other logic device
(Figure 17a). For external-reference compensation
mode, use the circuit in Figure 17b to drive PD between
DGND and the floating voltage of PD. An alternative is
to drive PD with three-state logic or a switch, provided
the off leakage does not exceed 100nA.
Internal Reference
The internal 4.096V reference is available at VREF and
must be bypassed to AGND with a 4.7µF low-ESR
capacitor (less than 1/2Ω) in parallel with a 0.1µF capaci-
tor, unless internal-reference compensation mode is
used (see the
Internal Reference Compensation
section).
This minimizes noise and maintains a low reference
impedance at high frequencies. The reference output
can be disabled by connecting REFADJ to VDD when
using an external reference.
Reference-Compensation Modes
Power-down performance can be optimized for a given
conversion rate by selecting either internal or external
reference compensation.
Internal Compensation
The connection for internal compensation is shown in
Figure 18a. In this mode, the reference stabilizes quick-
ly enough so that a conversion typically starts within
35µs after the ADC is reactivated (PD pulled high). In
this compensation mode, the reference buffer requires
longer recovery time from SAR transients, therefore
requiring a slower clock (and conversion time). With
internal reference compensation, the typical conversion
time rises to 25µs (Figure 18b). Figure 18c illustrates
the typical average supply current vs. conversion rate,
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
18 ______________________________________________________________________________________
MAX191
MAX191
a. INTERNAL-REFERENCE COMPENSATION MODE
b. EXTERNAL-REFERENCE COMPENSATION MODE
PD
1
1PD
OPEN-DRAIN
BUFFER
Figure 17. Drive Circuits for PD Pin
MAX191
+5V
PD
VREF
REFADJ
0.1µF
1
5
6
Figure 18a. Internal-Compensation Mode Circuit
which can be achieved using power-down between
conversions.
External Compensation
Figure 19a shows the connection for external compensa-
tion with reference adjustment. In this mode, an external
4.7µF capacitor compensates the reference output
amplifier, allowing for maximum conversion speed and
lowest conversion noise. However, when reactivating the
ADC after power-down, the reference takes typically 2ms
to fully charge the 4.7µF capacitor, so more time is
required before a conversion can start (Figure 19b).
Thus, the average current consumed in power-up/power-
down operations is higher in external compensation
mode than in internal compensation mode.
Gain and Offset Adjustment
Figure 20 depicts the nominal, unipolar input/output (I/O)
transfer function, and Figure 22 shows the bipolar I/O
transfer function. Code transitions occur halfway between
successive integer LSB values. Note that 1LSB = 1.00mV
(4.096V/4096) for unipolar operation and 1LSB = 1.00mV
((4.096V/2 - -4.096V/2)/4096) for bipolar operation.
Figures 19a and 21a show how to adjust the ADC gain
in applications that require full-scale range adjustment.
The connection shown in Figure 21a provides ±0.5%
for ±20LSBs of adjustment range and is recommended
for applications that use an external reference. On the
other hand, Figure 19a is recommended for applica-
tions that use the internal reference, because it uses
fewer external components.
If both offset and full scale need adjustment, the circuit
in Figure 21b is recommended. For single-supply
ADCs, it is virtually impossible to null system negative
offset errors. However, the MAX191 input configuration
is pseudo-differential—only the difference in voltage
between AIN+ and AIN- will be converted into its digital
representation. By applying a small positive voltage to
AIN-, the 0 input voltage at AIN+ can be adjusted to
above or below AIN- voltage, thus nulling positive or
negative system offset errors. R9 and R10 can be
removed for applications that require only positive sys-
tem errors to be nulled. To trim the offset error of the
MAX191, apply 1/2LSB to the analog input and adjust
R6 so the digital output code changes between 000
(hex) and 001 (hex). To adjust full scale, apply FS - 1
1/2LSBs and adjust R2 until the output code changes
MAX191
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
______________________________________________________________________________________ 19
25µs
RD
0
1
PD
20µs15µs
VREF
Figure 18b. Low Average-Power Mode Operation (Internal
Compensation)
10,000
10 10
100
1000
fg18c
CONVERSIONS PER SECOND
SUPPLY CURRENT (µA)
50 200 1k 5k 20k 100k
Figure 18c. Average Supply Current vs. Conversion Rate,
Powering Down Between Conversions
MAX191
VREF
REFADJ
PD
1
5
6
0.1µF4.7µF5k
11k
15k
100k
0.01µF
Figure 19a. External-Compensation Mode with Internal
Reference Adjustment Circuit
MAX191
between FFE (hex) and FFF (hex). Because interaction
occurs between adjustments, offset should be adjusted
before gain. For an input gain of two, remove R7 and R8.
The MAX191 accepts input voltages from AGND to VDD
while operating from a single supply, and VSS to VDD
when operating from dual supplies. Figure 22 shows
the bipolar input transfer function with AIN- connected
to midscale for single-supply operation and connected
to GND operating from dual supplies. When operating
from a single supply, the MAX191 can be configured
for bipolar operation on its pseudo-differential input.
Instead of using AIN- as an analog input return, AIN-
can be set to a different positive potential voltage
above ground (BIP pin is set high). The sampled ana-
log input (AIN+) can swing to any positive voltage
above and below AIN-, and the ADC performs bipolar
conversions with respect to AIN-. When operating from
dual supplies, the MAX191 full-scale range is from
-VREF/2 to +VREF/2.
Digital Bus Noise
If the data bus connected to the ADC is active during a
conversion, crosstalk from the data pins to the ADC
comparator may generate errors. Slow-memory mode
avoids this problem by placing the µP in a wait state
during the conversion. In ROM mode, if the data bus is
active during the conversion, it should be isolated from
the ADC using three-state drivers.
The ADC generates considerable digital noise in ROM
mode when RD or CS go high and the output data dri-
vers are disabled after a conversion has started. This
noise can cause large errors if it occurs when the SAR
latches a comparator decision. To avoid this problem,
RD and CS should be active for less than one clock
cycle. If this is not possible, RD or CS should go high at
the rising edge of CLK, since the comparator output is
always latched on falling edges of CLK.
Layout, Grounding, Bypassing
Use printed circuit boards for best system performance.
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
20 ______________________________________________________________________________________
RD
0
OPEN CIRCUIT (FLOAT)
PD
12.5µs
2ms
VREF 200ms
Figure 19b. Low Average-Power Mode Operation (External
Compensation)
11 . . . 111
11 . . . 110
11 . . . 101
00 . . . 011
00 . . . 010
00 . . . 001
00 . . . 000 0 1 2 3 FS
FS–1LSB
OUTPUT
CODE FULL-SCALE
TRANSITION
FS = VREF
1LSB =
4096
FS
AIN INPUT VOLTAGE (LSB)
Figure 20. Unipolar Transfer Function
VIN
R3
10k
R1
100Ω
R2
49.9Ω
R4
10k
TO AIN+
MAX480
Figure 21a. Trim Circuit for Gain (±0.5%)
Wire-wrap boards are not recommended. Board layout
should ensure that digital- and analog-signal lines are
separated from each other. Do not run analog and digi-
tal (especially clock) lines parallel to one another, or
digital lines underneath the ADC package.
Figure 23 shows the recommended system ground
connections. Establish a single-point ground (“star”
ground point) at AGND, separate from the logic
ground. Connect all other analog grounds and DGND
to it. No other digital-system ground should be con-
nected to this single-point analog ground. The ground
return to the power supply for this star ground should
be low impedance and as short as possible for noise-
free operation.
High-frequency noise in the VDD power supply may
affect the high-speed comparator in the ADC. Bypass
these supplies to the single-point analog ground with
MAX191
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
______________________________________________________________________________________ 21
MAX191
AIN +
AIN -
D0–D11
VIN
R7
10k
R8
10k
VREF
R6
10k
R5
10k
R1
10k
R2
100Ω
R3
10k
R4
49.9Ω
VREF
R9*
20k
0.1µF* R10*
49.9Ω
* CONNECT AIN- TO AGND WHEN USING DUAL SUPPLIES
MAX480
Figure 21b. Offset (±10mV) and Gain (±1%) Trim Circuit
01 . . . 111
01 . . . 110
00 . . . 010
00 . . . 001
11 . . . 111
11 . . . 110
00 . . . 000
10 . . . 001
10 . . . 000
11 . . . 101
0V VREF - 1LSB
VREF
––––
2
0V
SINGLE SUPPLY
VREF
AIN- = ––––
2
()
DUAL SUPPLY
AIN- = 0V VREF
–––– - 1LSB
2
-VREF
––––
2
Figure 22. Bipolar Transfer Function
SUPPLIES
+5V -5V GND
VDD AGND VSS DGND +5V DGND
R* = 10Ω
DIGITAL
CIRCUITRY
*OPTIONAL
MAX191
Figure 23. Power-Supply Grounding Connection
MAX191
0.01µF and 10µF bypass capacitors. Minimize capaci-
tor lead lengths for best supply-noise rejection. If the
+5V power supply is very noisy, a 10Ωresistor can be
connected as a lowpass filter to filter out supply noise
(Figure 23).
_____________Dynamic Performance
High-speed sampling capability and throughput make
the MAX191 ideal for wideband signal processing. To
support these and other related applications, Fast
Fourier Transform (FFT) test techniques guarantee the
ADC's dynamic frequency response, distortion, and
noise at the rated throughput. Specifically, this involves
applying a low-distortion sine wave to the ADC input
and recording the digital conversion results for a speci-
fied time. The data is then analyzed using an FFT algo-
rithm, which determines its spectral content.
Conversion errors are then seen as spectral elements
outside the fundamental input frequency. FFT plots are
shown in the
Typical Operating Characteristics
.
ADCs have traditionally been evaluated by specifica-
tions such as zero and full-scale error, integral nonlin-
earity (INL), and differential nonlinearity (DNL). Such
parameters are widely accepted for specifying perfor-
mance with DC and slowly varying signals, but are less
useful in signal-processing applications where the
ADC’s impact on the system transfer function is the
main concern. The significance of various DC errors
does not translate well to the dynamic case, so different
tests are required.
Signal-to-Noise Ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency to
the RMS amplitude of all other A/D output signals,
except signal harmonics. Signal-to-Noise + Distortion
ratio (SINAD) is the same as the SNR, but includes sig-
nal harmonics.
The theoretical minimum A/D noise is caused by quan-
tization error and is a direct result of the ADC’s resolu-
tion: SNR = (6.02n + 1.76) dB, where n is the number of
bits of resolution. 74dB is the SNR of a perfect 12-bit
ADC.
By transposing the equation that converts resolution to
SNR we can compute the effective resolution or the
“effective number of bits” the ADC provides from the
measured SNR:
n = (SNR – 1.76)/6.02
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal (in the frequen-
cy band above DC and below one-half the sample rate)
to the fundamental itself. This expressed as:
THD = 20log [√(V22+ V32+ V42+ V52+ . . . + Vn2) /V1]
where V1is the fundamental RMS amplitude and V2to
Vnare the amplitudes of the 2nd through nth harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range is the ratio of the funda-
mental RMS amplitude to the amplitude of the next
largest spectral component (in the frequency band
above DC and below one-half the sample rate). Usually
this peak occurs at some harmonic of the input fre-
quency. But if the ADC is exceptionally linear, it can
occur at a random peak in the ADC’s noise floor.
Opto-Isolated A/D Interface
Many industrial applications require isolation to prevent
excessive current flow where ground disparities exist
between the ADC and the rest of the system. In Figure
24, a MAX250 and four 6N136 opto-couplers create an
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
22 ______________________________________________________________________________________
MAX191
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
______________________________________________________________________________________ 23
EN GND
9
12
4
1
5
TTL/CMOS
OUTPUTS
TTL/CMOS
INPUTS
11
3
6
10
D1
VCC
D2
2
14
13
5V
1k
1k
1k
1k
1
2
4
3
T1
602117970
(SCHOTT)
8
7
6
5
IC3
ISOLATION
BARRIER
5
8 7
IC2
1
2
4
3
8
7
6
1k
1k
1k
1k
1k
1k
Q1
2N3906
Q2
2N3906
IN
OUT
GND
100µF
16V 5V
100µF
6V
24
AIN+
AIN-
HBEN
RD
PAR
BIP
AGND
VIN
18
16
20
23
5
6
4.7µF
0.1µF
0.1µF
212
REFADJ
VSS DGND
VREF
CS
SSTRB
DOUT VDD
3
4
21
19
22
8
7
0.1µF
IC4
74L05
IC5
MAX191
IC1
MAX250
SHDN
CLK
IC2-3
HCPL2630 (QUALITY TECHNOLOGIES)
Figure 24. Isolated Data-Acquisition Circuit
MAX191
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
24 ______________________________________________________________________________________
___________________Chip Topography
________________________________________________________Package Information
SUBSTRATE CONNECTED TO VDD
PDIPN.EPS