19-4506; Rev 4; 2/97 ANUAL N KIT M EET IO T A U EVAL TA SH WS DA FOLLO Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down The MAX191 operates from a single +5V supply or from dual 5V supplies, allowing ground-referenced bipolar input signals. The device features a logic power-down input, which reduces the 3mA VDD supply current to 50A max, including the internal-reference current. Decoupling capacitors are the only external components needed for the power supply and reference. This ADC operates with either an external reference, or an internal reference that features an adjustment input for trimming system gain errors. The MAX191 provides three interface modes: two 8-bit parallel modes, and a serial interface mode that is compatible with SPITM, QSPITM, and MICROWIRETM serialinterface standards. ________________________Applications Battery-Powered Data Logging PC Pen Digitizers High-Accuracy Process Control Electromechanical Systems Data-Acquisition Boards for PCs Automatic Testing Systems Telecommunications Digital Signal Processing (DSP) OSC 3-STATE OUTPUT 2.46V REF 12 AIN + AIN - 8-BIT BUS AND SERIAL I/O 18 17 16 15 14 13 11 10 3 4 IN REF OUT 12-BIT SAR ADC MAX191 7 12 AGND DGND 2 VSS CONTROL LOGIC 1 22 8 BIP PD PAR Ordering Information PART TEMP. RANGE MAX191ACNG MAX191BCNG MAX191ACWG MAX191BCWG MAX191BC/D MAX191AENG MAX191BENG MAX191AEWG MAX191BEWG MAX191AMRG MAX191BMRG 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -55C to +125C PIN-PACKAGE 24 Narrow Plastic DIP 24 Narrow Plastic DIP 24 Wide SO 24 Wide SO Dice* 24 Narrow Plastic DIP 24 Narrow Plastic DIP 24 Wide SO 24 Wide SO 24 Narrow CERDIP** 24 Narrow CERDIP** ERROR (LSB) 1/2 1 1/2 1 1 1/2 1 1/2 1 1/2 1 Pin Configuration CLK/SCLK 23 5 VREF 6 REFADJ 12-Bit Resolution, 1/2LSB Linearity +5V or 5V Operation Built-In Track/Hold Internal Reference with Adjustment Capability Low Power: 3mA Operating Mode 20A Power-Down Mode 100ksps Tested Sampling Rate Serial and 8-Bit Parallel P Interface 24-Pin Narrow DIP and Wide SO Packages * Dice are specified at TA = +25C, DC parameters only. ** Contact factory for availability and processing to MIL-STD-883. Functional Diagram VDD 24 ____________________________Features 20 19 9 21 TOP VIEW PD 1 24 VDD VSS 2 23 CLK/SCLK D7/DOUT AIN+ 3 22 PAR D6/SCLKOUT D5/SSTRB D4 D3/D11 D2/D10 D1/D9 D0/D8 AIN- 4 21 HBEN CS RD BUSY HBEN VREF 5 MAX191 REFADJ 6 20 CS 19 RD AGND 7 18 D7/DOUT BIP 8 17 D6/SCLKOUT BUSY 9 16 D5/SSTRB D0/D8 10 15 D4 D1/D9 11 14 D3/D11 DGND 12 13 D2/D10 DIP/SO SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 408-737-7600 ext. 3468. MAX191 General Description The MAX191 is a monolithic, CMOS, 12-bit analog-todigital converter (ADC) featuring differential inputs, track/hold (T/H), internal voltage reference, internal or external clock, and parallel or serial P interface. The MAX191 has a 7.5s conversion time, a 2s acquisition time, and a guaranteed 100ksps sample rate. MAX191 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down ABSOLUTE MAXIMUM RATINGS VDD to DGND............................................................-0.3V to +7V VSS to AGND ............................................................-7V to +0.3V VDD to VSS ..............................................................................12V AGND, VREF, REFADJ to DGND................-0.3V to (VDD + 0.3V) AIN+, AIN-, PD to VSS .................................-0.3V to (VDD + 0.3V) CS, RD, CLK, BIP, HBEN, PAR, to DGND....-0.3V to (VDD + 0.3V) BUSY, D0-D7 to DGND..............................-0.3V to (VDD + 0.3V) Continuous Power Dissipation (TA = +70C) Narrow Plastic DIP (derate 13.33mW/C above +70C)....1067mW Wide SO (derate 11.76mW/C above +70C) ......................941mW Narrow CERDIP (derate 12.50mW/C above +70C) ........1000mW Operating Temperature Ranges MAX191_C_ _ ................................................................0C to +70C MAX191_E_ _ .............................................................-40C to +85C MAX191_M_ _ ..........................................................-55C to +125C Storage Temperature Range.....................................-65C to +160C Lead Temperature (soldering, 10sec).....................................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = 5V 5%, VSS = 0V or -5V 5%, fCLK = 1.6MHz, 50% duty cycle, AIN- = AGND, BIP = 0V, slow-memory mode, internal-reference mode, reference compensation mode--external, synchronous operation, Figure 6, T A = TMIN to TMAX, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY (Note 2) Resolution Integral Nonlinearity Differential Nonlinearity 12 INL DNL Offset Error Gain Error (Note 3) Gain-Error Tempco (Note 4) Bits MAX191A 1/2 MAX191B 1 No missing codes over temperature 1 MAX191A 1 MAX191B 2 MAX191A 2 MAX191B 3 Excludes internal-reference drift 0.2 LSB LSB LSB LSB ppm/C DYNAMIC ACCURACY (sample rate = 100kHz, VIN = 4Vp-p) Signal-to-Noise plus Distortion Ratio SINAD 1kHz input signal, TA = +25C Total Harmonic Distortion (up to the 5th Harmonic) THD 1kHz input signal, TA = +25C Spurious-Free Dynamic Range SFDR 1kHz input signal, TA = +25C 70 dB -80 80 dB dB CONVERSION RATE Conversion Time (Note 5) tCONV Synchronous CLK (12 to 13 CLKs) Internal CLK, CL = 120pF 7.50 6 8.125 12 Track/Hold Acquisition Time 2 s s Aperture Delay 25 ns Aperture Jitter 50 ps External Clock Frequency Range (Note 6) 2 18 fCLK 0.1 _______________________________________________________________________________________ 1.6 MHz Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down (VDD = 5V 5%, VSS = 0V or -5V 5%, fCLK = 1.6MHz, 50% duty cycle, AIN- = AGND, BIP = 0V, slow-memory mode, internal-reference mode, reference compensation mode--external, synchronous operation, Figure 6, T A = TMIN to TMAX, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VDD V 10 A ANALOG INPUT VSS Input Voltage Range (Note 7) VIN = VSS to VDD Input Leakage Current Input Capacitance (Note 6) 45 Small-Signal Bandwidth 2 80 pF MHz INTERNAL REFERENCE TA = +25C VREF Output Voltage 4.076 4.096 4.116 V MAX191_C 50 VREF Output Tempco (Note 8) MAX191_E 60 MAX191_M TA = +25C 80 Output Current Capability (Note 9) 2 mA Load Regulation TA = +25C, IOUT = 0mA to 2mA 4 mV Output Short-Circuit Current 18 Capacitive Load Required Reference compensation mode--external VDD = 5%, VSS = 5% Power-Supply Rejection mA 4.7 F 300 REFADJ Input Adjustment Range (Note 10) -60 REFADJ Disable Threshold 4.5 REFADJ Output Voltage V 30 mV V 2.4 REFADJ Input Current mA ppm/C REFADJ = 5V V 60 A 5.0 V 1 mA REFERENCE INPUT Input Voltage Range External-reference mode Input Current External-reference = 5V Input Resistance External-reference mode 2.5 5 10 k LOGIC INPUTS Input Low Voltage VIL CS, RD, CLK, HBEN, PAR, BIP Input High Voltage VIH CS, RD, CLK, HBEN, PAR, BIP Input Current IIN VIN = 0V to VDD 10 PD = high/float 200 0.8 2.4 V V A Input Current CLK IIN Input Capacitance (Note 6) CIN 10 pF PD Input Low Voltage VIL 0.5 V PD Input High Voltage VIH PD Input Current IIN PD = 0V to VDD (Note 11) 20 A Maximum current allowed for "floating state" 100 nA PD External Leakage for Float State (Note 12) PD Floating-State Voltage VFLT PD = low 0.1 4.5 Reference compensation mode--external A V 2.8 V _______________________________________________________________________________________ 3 MAX191 ELECTRICAL CHARACTERISTICS (continued) MAX191 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down ELECTRICAL CHARACTERISTICS (continued) (VDD = 5V 5%, VSS = 0V or -5V 5%, fCLK = 1.6MHz, 50% duty cycle, AIN- = AGND, BIP = 0V, slow-memory mode, internal-reference mode, reference compensation mode--external, synchronous operation, Figure 6, T A = TMIN to TMAX, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 0.4 V LOGIC OUTPUTS Output Low Voltage VOL IOUT = 1.6mA Output High Voltage VOH IOUT = -200A Three-State Leakage Current IL Three-State Output Capacitance (Note 6) 4.0 V D0/D8-D7/DOUT COUT 10 A 15 pF 5.25 V POWER REQUIREMENTS Positive Supply Voltage VDD Negative Supply Voltage VSS Positive Supply Current IDD Negative Supply Current ISS 4.75 -5.25 CS = RD = VDD, AIN = 5V, D0/D8-D7/ DOUT = 0V or VDD, HBEN = PAR = BIP = 0V or VDD 0 V PD = high/float 3 5 mA PD = low 20 50 A PD = high/float 20 100 PD = low 1 20 A Positive Supply Rejection (Note 13) FS change, VDD = 5V 5% 1/2 LSB Negative Supply Rejection (Note 13) FS change, VSS = -5V 5% 1/2 LSB TIMING CHARACTERISTICS (Figures 6-10) (VDD =5V 5%, VSS = 0V or -5V 5%, TA = TMIN to TMAX, unless otherwise noted.) (Note 14) PARAMETER SYMBOL CONDITIONS TA = +25C MIN TYP MAX MAX191C/E MIN TYP MAX MAX191M MIN TYP MAX UNITS CS to RD Setup Time t1 RD to BUSY Delay t2 CL = 50pF 120 140 160 ns Data Access Time (Note 15) t3 CL = 100pF 120 140 160 ns RD Pulse Width t4 150 150 150 ns CS to RD Hold Time t5 0 0 0 ns Data Setup Time After BUSY (Note 15) t6 Bus-Relinquish Time (Note 16) t7 HBEN to RD Setup Time t8 80 100 120 ns HBEN to RD Hold Time t9 0 0 0 ns Delay Between Read Operations (Note 6) t10 200 200 200 ns 2 2 s 0 0 80 100 100 110 ns 120 ns 120 ns Delay Between Conversions t11 Aperture Delay t12 CLK to BUSY Delay (Note 6) t13 200 230 260 ns SCLKOUT to SSTRB Rise Delay t14 100 130 150 ns SCLKOUT to SSTRB Fall Delay t15 100 130 150 ns 4 2 0 Jitter < 50ps 25 ns _______________________________________________________________________________________ Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down (VDD =5V 5%, VSS = 0V or -5V 5%, TA = TMIN to TMAX, unless otherwise noted.) (Note 14) PARAMETER SYMBOL CONDITIONS TA = +25C MIN TYP MAX MAX191C/E MIN TYP MAX MAX191M MIN TYP MAX UNITS CS or RD Hold Time t16 10 10 10 CS or RD Setup Time t17 150 150 150 CS to DOUT Three-State t19 100 110 120 ns SCLK to SCLKOUT Delay t20 160 180 200 ns SCLKOUT to DOUT Delay t21 100 130 150 ns SCLK to DOUT Delay t22 240 260 280 ns SCLK to SSTRB Delay t23 260 310 350 ns Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: Note 14: Note 15: Note 16: ns ns Performance at power-supply tolerance limits guaranteed by power-supply rejection test. VDD = 5V, VSS = 0V, FS = VREF. FS = VREF, offset nulled, ideal last-code transition = FS - 3/2 LSB. Gain-Error Tempco = GE is the gain-error change from TA = +25C to TMIN or TMAX. Conversion time defined as the number of clock cycles times the clock period; clock has a 50% duty cycle. Guaranteed by design, not production tested. AIN+, AIN- must not exceed supplies for specified accuracy. VREF TC = T, where VREF is reference-voltage change from TA = +25C to TMIN or TMAX. Output current should not change during conversion. This current is in addition to the current required by the internal DAC. REFADJ adjustment range is defined as the allowed voltage excursion on REFADJ relative to its unadjusted value of 2.4V. This will typically result in a 1.7 times larger change in the REF output (Figure 19a). This current is included in the PD supply current specification. Floating the PD pin guarantees external compensation mode. VREF = 4.096V, external reference. All input control signals are specified with tr = tf = 5ns (10% to 90% of 5V) and timed from a voltage level of 1.6V. t3 and t6 are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V. t7 is defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 2. _______________________________________________________________________________________ 5 MAX191 TIMING CHARACTERISTICS (Figures 6-10) (continued) __________________________________________Typical Operating Characteristics CLOCK FREQUENCY vs. TIMING CAPACITOR IDD 15 ISS (A) SUPPLY CURRENT (A) 0.1 GR191-C 20 20 1 25 GR191-B 25 GR191-A SEE FIGURE 5 TA = +25C CLOCK FREQUENCY (MHz) NEGATIVE SUPPLY CURRENT vs. TEMPERATURE POWER-DOWN SUPPLY CURRENT vs. TEMPERATURE 10 VDD = +5V VSS = -5V PD = 0V 10 15 10 5 5 ISS 0 0 10 1 -60 -30 TIMING CAPACITOR (nF) 60 30 90 120 1.5 1.0 0 -60 -80 -94.3dB -96.1dB-98.0dB -93.8dB -100 60 90 TEMPERATURE (C) 120 150 150 -40 -60 -86.0dB -80 -90.8dB -100 -120 -140 30 120 fIN = 10kHz fS = 100kHz SNR = 71.2dB TA = +25C -20 -120 0.5 90 0 SIGNAL AMPLITUDE (dB) 2.0 -40 60 30 10kHz FFT PLOT fIN = 1kHz fS = 100kHz SNR = 72dB TA = +25C -20 SIGNAL AMPLITUDE (dB) 2.5 0 0 1kHz FFT PLOT 3.0 -30 -30 TEMPERATURE (C) 0 GR191-D 3.5 -60 -60 150 TEMPERATURE (C) POSITIVE SUPPLY CURRENT vs. TEMPERATURE 6 0 GR191-E 0.1 GR191-F 0.01 IDD (mA) MAX191 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down -140 0 1 2 3 4 FREQUENCY (kHz) 5 6 0 5 10 15 20 25 FREQUENCY (kHz) _______________________________________________________________________________________ 30 35 40 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down PIN NAME FUNCTION 1 PD Power-Down Input. A logic low at PD deactivates the ADC--only the bandgap reference is active. A logic high selects normal operation, internal-reference compensation mode. An open-circuit condition selects normal operation, external-reference compensation mode. 2 VSS Negative Supply, 0V to -5.25V 3 AIN+ Sampled Analog Input 4 AIN- Analog Input Return. Pseudo-differential (see Gain and Offset Adjustment section). 5 VREF Reference-Buffer Output for Internal Reference. Input for external reference when REFADJ is connected to VDD. 6 REFADJ 7 AGND 8 BIP 9 BUSY BUSY Output is low during a conversion. 10 D0/D8 Three-State Data Outputs: LSB = D0 11 D1/D9 Three-State Data Outputs 12 DGND Digital Ground 13 D2/D10 Three-State Data Outputs 14 D3/D11 Three-State Data Outputs: MSB = D11 15 D4 16 D5/SSTRB Three-State Data Output/Serial Strobe Output in serial mode 17 D6/SCLKOUT Three-State Data Output/Serial Clock Output in serial mode 18 D7/DOUT 19 RD Read Input. In parallel mode, a low signal starts a conversion when CS and HBEN are low (memory mode). RD also enables the outputs when CS is low. In serial mode, RD = low enables SCLKOUT and SSTRB when CS is low. RD = high forces SCLKOUT and SSTRB into a high-impedance state. 20 CS Chip-Select Input must be low for the ADC to recognize RD and HBEN inputs in parallel mode. The falling edge of CS starts a conversion in serial mode. CS = high in serial mode forces SCLKOUT, SSTRB, and DOUT into a high-impedance state. 21 HBEN 22 PAR 23 CLK/SCLK 24 VDD Reference Adjust. Connect to VDD to use an extended reference at VREF. Analog Ground BIP = low selects unipolar mode BIP = high selects bipolar mode (see Gain and Offset Adjustment section) Three-State Data Output Three-State Data Output/Data Output in serial mode High-Byte Enable Input. In parallel mode, HBEN = high multiplexes the 4 MSBs of the conversion result into the lower bit outputs. HBEN = high also disables conversion starts. HBEN = low places the 8 LSBs onto the data bus. In serial mode, HBEN = low enables SCLKOUT to operate during the conversion only, HBEN = high enables SCLKOUT to operate continuously, provided CS is low. Sets the output mode. PAR = high selects parallel output mode. PAR = low selects serial output mode. Clock Input/Serial Clock Input in serial mode. An external TTL-/CMOS-compatible clock may be applied to this pin, or a capacitor (120pF nominal) may be connected between CLK and DGND to operate the internal oscillator. Positive Supply, +5V 5% _______________________________________________________________________________________ 7 MAX191 Pin Description MAX191 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down +5V 3k OPEN DN DN CL CL 3k DGND DGND a. High-Z to VOH and VOL to VOH b. High-Z to VOL and VOH to VOL Figure 1. Load Circuits for Access Time +5V 3k DN DN 4.7F 1 PD VDD CLK/SCLK 3 AIN+ PAR 4 AINHBEN 5 CS VREF MAX191 0.1F 6 RD REFADJ 7 D7/DOUT AGND 0.1F 8 BIP D6/SCLKOUT OUTPUT 9 BUSY D5/SSTRB STATUS 10 DO/DB D4 11 D1/D9 D3/D11 12 D2/D10 DGND VSS 24 +5V 23 C1 22 21 SERIAL/PARALLEL INTERFACE MODE 20 P CONTROL INPUTS 19 18 17 16 15 14 13 2 0V TO -5V 10pF 3k 10pF DGND DGND a. VOH to High-Z P DATA BUS NOTE: C1 120pF GENERATES 1MHz NOMINAL CLOCK. b. VOL to High-Z Figure 2. Load Circuits for Bus-Relinquish Time Figure 3. Operational Diagram _______________Detailed Description disconnects from the input during the conversion. In unbuffered applications, an input filter capacitor reduces conversion noise, but also may limit input bandwidth. The MAX191 uses successive approximation and input track/hold (T/H) circuitry to convert an analog input signal to a 12-bit digital output. Flexible control logic provides easy interface to microprocessors (Ps), so most applications require only the addition of passive components. No external hold capacitor is required for the T/H. Figure 3 shows the MAX191 in its simplest operational configuration. Pseudo-Differential Input The sampling architecture of the ADC's analog comparator is illustrated in the Equivalent Input Circuit (Figure 4). A capacitor switching between the AIN+ and AIN- inputs acquires the signal at the ADC's analog input. At the end of the conversion, the capacitor reconnects to AIN+ and charges to the input signal. An external input buffer is usually not needed for lowbandwidth input signals (<100Hz) because the ADC 8 When converting a single-ended input signal, AINshould be connected to AGND. If a differential signal is connected, consider that the configuration is pseudo differential--only the signal side to the input channel is held by the T/H. The return side (AIN-) must remain stable within 0.5LSB (0.1LSB for best results) with respect to AGND during a conversion. Accomplish this by connecting a 0.1F capacitor from AIN- to AGND. Analog Input--Track/Hold The T/H enters its tracking mode when the ADC is deselected (CS pin is held high and BUSY pin is high). Hold mode starts approximately 25ns after a conversion is initiated. The variation in this delay from one conversion to the next (aperture jitter) is about 50ps. Figures 6-10 detail the T/H and interface timing for the _______________________________________________________________________________________ Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down TRACK CPACKAGE 5pF COMPARATOR CHOLD HOLD 32pF MAX191 AIN + MAX191 RIN CSWITCH 10pF CLK HOLD CLOCK CEXT AIN - +1.6V DGND 12-BIT DAC NOTE: CEXT = 120pF GENERATES 1MHz NOMINAL CLOCK Figure 4. Equivalent Input Circuit Figure 5. Internal Clock Circuit various interface modes. tection diodes are even slightly forward biased. The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal's source impedance is high, the acquisition time lengthens and more time must be allowed between conversions. Acquisition time is calculated by: tACQ = 10(RS + RIN)CHOLD (but never less than 2s), where RIN = 2k, RS = source impedance of the input signal, and CHOLD = 32pF (see Figure 4). Input Bandwidth The ADC's input tracking circuitry has a 1MHz typical large-signal bandwidth characteristic, and a 30V/s slew rate. It is possible to digitize high-speed transients and measure periodic signals with bandwidths exceeding the ADC's sample rate of 100ksps by using undersampling techniques. Note that if undersampling is used to measure high-frequency signals, special care must be taken to avoid aliasing errors. Without adequate input bandpass filtering, out-of-band signals and noise may be aliased into the measurement band. Input Protection Internal protection diodes, which clamp the analog input to VDD and VSS , allow AIN+ to swing from (VSS - 0.3V) to (V DD + 0.3V) with no risk of damage to the ADC. However, for accurate conversions near full scale, AIN+ should not exceed the power supplies by more than 50mV because ADC accuracy is affected when the pro- Digital Interface Starting a Conversion In parallel mode, the ADC is controlled by the CS, RD, and HBEN inputs, as shown in Figure 6. The T/H enters hold mode and a conversion starts at the falling edge of CS and RD while HBEN (not shown) is low. BUSY goes low as soon as the conversion starts. On the falling edge of the 13th input clock pulse after the conversion starts, BUSY goes high and the conversion result is latched into three-state output buffers. In serial mode, the falling edge of CS initiates a conversion, and the T/H enters hold mode. Data is shifted out serially as the conversion proceeds (Figure 10). See the Parallel Digital-Interface Mode and Serial-Interface Mode sections for details. Internal/External Clock Figure 5 shows the MAX191 clock circuitry. The ADC includes internal circuitry to generate a clock with an external capacitor. As indicated in the Typical Operating Characteristics , a 120pF capacitor connected between the CLK and DGND pins generates a 1MHz nominal clock frequency (Figure 5). Alternatively, an external clock (between 100kHz and 1.6MHz) can be applied to CLK. When using an external clock source, acceptable clock duty cycles are _______________________________________________________________________________________ 9 MAX191 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down CLK t17 t16 CS + RD t13 t2 tCONV BUSY t2 tCONV Figure 6. CS, RD, and CLK Synchronous Operation between 45% and 55%. Clock and Control Synchronization For best analog performance on the MAX191, the clock should be synchronized to the conversion start signals (CS and RD) as shown in Figure 6. A conversion should not be started in the 50ns before a clock edge nor in the 100ns after it. This ensures that CLK transitions are not coupled to the analog input and sampled by the T/H. The magnitude of this feedthrough can be a few millivolts. When the clock and conversion start signals are synchronized, small end-point errors (offset and full-scale) are the most that can be generated by clock feedthrough. Even these errors (which can be trimmed out) can be avoided by ensuring that the start of a conversion (RD or CS falling edge) does not occur close to a clock transition (Figure 6), as described above. Parallel Digital-Interface Mode Output-Data Format The data output from the MAX191 is straight binary in the unipolar mode. In the bipolar mode, the MSB is inverted (see Figure 22). The 12 data bits can be output either in two 8-bit bytes or as a serial output. Table 1 shows the data-bus output format. A 2-byte read uses outputs D7-D0. Byte selection is controlled by HBEN. When HBEN is low, the lower 8 bits appear at the data outputs. When HBEN is high, the upper 4 bits appear at D0-D3 with the leading 4 bits low in locations D4-D7. Timing and Control Conversion-start and data-read operations are controlled by the HBEN, CS, and RD digital inputs. A logic low is required on all three inputs to start a conversion, and once the conversion is in progress it cannot be 10 restarted. BUSY remains low during the entire conversion cycle. The timing diagrams of Figures 7-10 outline two parallel-interface modes and one serial mode. Slow-Memory Mode In slow-memory mode, the device appears to the P as a slow peripheral or memory. Conversion is initiated with a read instruction (see Figure 7 and Table 2). Set the PAR pin high for parallel interface mode. Beginning with HBEN low, taking CS and RD low starts the conversion. The analog input is sampled on the falling edge of RD. BUSY remains low while the conversion is in progress. The previous conversion result appears at the digital outputs until the end of conversion, when BUSY returns high. The output latches are then updated with the newest results of the 8 LSBs on D7-D0. A second read operation with HBEN high places the 4 MSBs, with 4 leading 0s, on data outputs D7-D0. The second read operation does not start a new conversion because HBEN is high. ROM Mode As in slow-memory mode, D7-D0 are used for 2-byte reads. A conversion starts with a read instruction with HBEN and CS low. The T/H samples the input on the falling edge of RD (see Figure 8 and Table 3). PAR is set high. At this point the data outputs contain the 8 LSBs from the previous conversion. Two more read operations are needed to access the conversion result. The first occurs with HBEN high, where the 4 MSBs with 4 leading 0s are accessed. The second read, with HBEN low, outputs the 8 LSBs and also starts a new conversion. Figure 9 and Table 4 show how to read output data within one conversion cycle without starting another conversion. Trigger the falling edge of a read on the ris- ______________________________________________________________________________________ Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down MAX191 HBEN t8 t9 t8 t9 CS t1 t5 t1 t4 t5 RD tCONV t2 t10 t10 BUSY t11 t3 t6 OLD DATA D7-D0 DATA t7 t3 t7 NEW DATA D7-D0 NEW DATA D11-D8 t12 t12 HOLD* TRACK *INTERNAL SIGNAL. TRACKING INPUT SIGNAL WHEN HOLD = Low, HOLDING WHEN HOLD = High. Figure 7. Slow-Memory Mode Timing HBEN t8 t9 t8 t9 t8 t9 CS t1 t4 t5 t1 t4 t5 t1 t4 t5 RD t2 tCONV t10 t2 BUSY t11 t3 t7 t3 OLD DATA D7-D0 DATA t12 t7 t3 NEW DATA D11-D8 t7 NEW DATA D7-D0 t12 HOLD* TRACK *INTERNAL SIGNAL. TRACKING INPUT SIGNAL WHEN HOLD = Low, HOLDING WHEN HOLD = High. Figure 8. ROM Mode Timing ______________________________________________________________________________________ 11 MAX191 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down HBEN t8 t9 t8 CLK CS t1 t4 t5 RD t2 t10 tCONV BUSY t7 t3 t3 t7 OLD DATA D7-D0 DATA NEW DATA D7-D0 t3 t7 NEW DATA D11-D8 t12 HOLD* TRACK *INTERNAL SIGNAL. TRACKING INPUT SIGNAL WHEN HOLD = Low, HOLDING WHEN HOLD = High Figure 9. ROM Mode Timing, Reading Data without Starting a Conversion SCLK t22 THREE STATE SCLKOUT t20 t20 THREE STATE t17 t16 CS t23 t23 THREE STATE SSTRB t14 t15 t21 THREE STATE DOUT t12 t22 HOLD TRACK t19 12 SCLK CYCLES Figure 10. Serial-Interface Mode Timing Diagram (RD = low) 12 ______________________________________________________________________________________ Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down PIN NAME D7/DOUT D6/SCLKOUT D5/SSTRB D4 D3/D11 D2/D10 D1/D9 D0/D8 D7 D6 D5 D4 D3 D2 D1 D0 Low Low Low Low D11 D10 D9 D8 DOUT SCLKOUT SSTRB Low Low Low Low Low DOUT ThreeStated ThreeStated Low Low Low Low Low HBEN = 0, PAR = 1, PARALLEL MODE HBEN = 1, PAR = 1, PARALLEL MODE HBEN = X, PAR = 0, SERIAL MODE, RD = 0 HBEN = X, PAR = 0, SERIAL MODE, RD = 1 Note: MAX191 Table 1. Data-Bus Output, CS = RD = Low D7/DOUT-D0/D8 are the ADC data output pins. D11-D0 are the 12-bit conversion results. D11 is the MSB. DOUT = Three-state data output. Data output in serial mode. SCLKOUT = Three-state data output. Clock output in serial mode. SSTRB = Three-state data output. Strobe output in serial mode. Table 2. Slow-Memory Mode, 2-Byte Read Data-Bus Status PIN NAME D7/DOUT D6/SCLKOUT D5/SSTRB D4 D3/D11 D2/D10 D1/D9 D0/D8 FIRST READ (New Data) D7 D6 D5 D4 D3 D2 D1 D0 SECOND READ (New Data) Low Low Low Low D11 D10 D9 D8 Table 3. ROM Mode, 2-Byte Read Data-Bus Status PIN NAME D7/DOUT D6/SCLKOUT D5/SSTRB D4 D3/D11 D2/D10 D1/D9 D0/D8 FIRST READ (Old Data) D7 D6 D5 D4 D3 D2 D1 D0 SECOND READ (New Data) Low Low Low Low D11 D10 D9 D8 THIRD READ (New Data) D7 D6 D5 D4 D3 D2 D1 D0 Table 4. ROM Mode, 2-Byte Read Data-Bus Status without Starting a Conversion Cycle PIN NAME D7/DOUT D6/SCLKOUT D5/SSTRB D4 D3/D11 D2/D10 D1/D9 D0/D8 FIRST READ (Old Data) D7 D6 D5 D4 D3 D2 D1 D0 SECOND READ (New Data) D7 D6 D5 D4 D3 D2 D1 D0 THIRD READ (New Data) Low Low Low Low D11 D10 D9 D8 ______________________________________________________________________________________ 13 MAX191 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down +5V 23 20 19 +5V QA SCLK 1 CS DOUT RD MAX191 SCLKOUT HBEN 18 2 17 8 QB A B 74HC164 QC QD CLOCK 21 QE QF QG SSTRB 16 9 QH CLEAR QA 1 +5V 2 8 QB A B 74HC164 QC QD CLOCK QE QF QG 9 LOGIC INPUT QH CLEAR CS SCLK SCLKOUT t19 DOUT D11 DO SSTRB NOTE: USE SSTRB TO GATE PARALLEL DATA TRANSFER FROM SHIFT REGISTER, OR TO CLEAR SHIFT REGISTERS IF DESIRED. Figure 11. Simple Serial-to-Parallel Interface 14 ______________________________________________________________________________________ 3 4 5 6 10 11 12 13 3 4 5 6 10 11 12 13 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down Serial-Interface Mode The serial mode is compatible with Microwire, SPI and QSPI serial interfaces. In addition, a framing signal (SSTRB) is provided that allows the devices to interface with the TMS320 family of DSPs. Set PAR low for serial mode. A falling edge on CS causes the T/H to sample the input (Figure 10). Conversion always begins on the next falling edge of SCLK, regardless of where CS occurs. The DOUT line remains high-impedance until a conversion begins. During the MSB decision, DOUT remains low (leading 0), while SSTRB goes high to indicate that a data frame is beginning. The data is available at DOUT on the rising edge of SCLK (SCLKOUT when using an internal clock) and transitions on the falling edge. DOUT remains low after all data bits have been shifted out, inserting trailing 0s in the data stream until CS returns high. The SCLKOUT signal is synchronous with the internal or external clock. For interface flexibility, DOUT, SCLKOUT and SSTRB signals enter a high-impedance state when CS is high. When CS is low, RD controls the status of SCLKOUT and SSTRB outputs. A logic low RD enables SCLKOUT and SSTRB, while a logic high forces both outputs into a high-impedance state. Also, with CS low and HBEN high, SCLKOUT drives continuously, regardless of conversion status. This is useful with Ps that require a continuous serial clock. If CS and HBEN are low, SCLKOUT is output only during the conversion cycle, while the converter internal clock runs continuously. This is useful for creating a simple serial-to-parallel interface without shift-register overflow (Figure 11). Maximum Clock Rate in Serial Mode The maximum SCLK rate depends on the minimum setup time required at the serial data input to the P and the ADC's DOUT to SCLK delay (t22) (see Figure 12). The maximum fSCLK is as follows: CS I/O SCLK SCK DOUT MISO +5V MAX191 SS a. SPI CS CS SCK MISO SCLK DOUT +5V MAX191 SS b. QSPI I/O CS SK SCLK SI DOUT MAX191 SCLK c. MICROWIRE t22 I/O DOUT CLKX 1 --------- tSU(M) + t22 ( ) tSU(M) IS THE SETUP TIME REQUIRED AT THE SERIAL DATA INPUT TO THE P. t22 IS THE MAXIMUM SCLK TO DOUT DELAY. SCLK MAX191 tSETUP (MIN) 1 fSCLK (MAX) = -- 2 CS CLKR DR DOUT FSR SSTRB d. TMS320 SERIAL INTERFACE Figure 12. fSCLK(MAX) is limited by the setup time required by the serial data input to the P. Figure 13. Common Serial-Interface Connections to the MAX191 ______________________________________________________________________________________ 15 MAX191 ing edge of the first clock cycle after conversion end (when BUSY goes high). As mentioned previously, two more read operations (after BUSY goes high) are needed to access the conversion results. The only difference is that now the low byte can be read first. This happens by allowing the first read operation to occur with HBEN low, where the 8 LSBs are accessed. The second read, with HBEN high, accesses the 4 MSBs with 4 leading 0s. MAX191 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down fSCLK(MAX) = (1/2) x 1/ (tsu(M) + t22) where t su (M) is the minimum data-setup time required at the serial data input to the P. For example, Motorola's MC68HC11A8 data book specifies a 100ns minimum data-setup time. Using the worst case for a military grade part of t 22 = 280ns (see Timing Characteristics) and substituting in the above equation indicates a maximum SCLK frequency of 1.3MHz. Using the MAX191 with SPI, QSPI and MICROWIRE Serial Interfaces Figure 13 shows interface connections to the MAX191 for common serial-interface standards. SPI and MICROWIRE (CPOL=0, CPHA=0) The MAX191 is compatible with SPI, QSPI and MICROWIRE serial-interface standards. When using SPI or QSPI, two modes are available to interface with the MAX191. You can set CPOL = 0 and CPHA = 0 (Figure 14a), or set CPOL = 1 and CPHA = 1 (Figure 14b). When using CPOL = 0 and CPHA = 0, the conversion begins on the first falling edge of SCLK following CS going low. Data is available from DOUT on the rising edge of SCLK, and transitions on the falling edge. Two consecutive 1-byte reads are required to get the full 12 bits from the ADC. The first byte contains the following, in this order: a leading unknown bit (DOUT will still be high-impedance on the first bit), a 0, and the six MSBs. The second byte contains the remaining six LSBs and two trailing 0s. SPI (CPOL=1, CPHA=1) Setting CPOL = 1 and CPHA = 1 starts the clock high during a read instruction. The MAX191 will shift out a leading 0 followed by the 12 data bits and three trailing 0s (Figure 14b). QSPI Unlike SPI, which requires two 1-byte reads to acquire the 12 bits of data from the ADC, QSPI allows the minimum number of clock cycles required to clock in the data (Figure 15). TMS320 Serial Interface Figure 13d shows the pin connections to interface the MAX191 to the TMS320. Since the MAX191 makes data available on the rising edge of SCLK and the TMS320 shifts data in on the falling edge of CLKR, use CLKX of the DSP to drive SCLK, and CLKX to drive the DSP's CLKR input. The inverter's propagation delay also provides more data-setup time at the DSP. For example, with no inverter delay, and using t22 = 280ns and fSCLK = 1.6MHz, the available setup time before the SCLK transition is: setup time = 1/ (2 x fSCLK) - t22 = 1/ (2 x 1.6E6) - 280ns = 32ns This still exceeds the 13ns minimum DR setup time before the CLKR goes low (tsu(DR)), however, a generic 74HC04 provides an additional 20ns setup time (see Figure 13d). Figure 16 shows the DSP interface timing characteristics. The DSP begins clocking data in on the falling edge of CLKR after the falling edge of SSTRB. 2ND BYTE READ 1ST BYTE READ SCLK CS DOUT HIGH-Z a. CPOL = 0, CPHA = 0 LEADING ZERO MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB LEADING ZERO MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB HIGH-Z SCLK CS DOUT HIGH-Z b. CPOL = 1, CPHA = 1 Figure 14. SPI/MICROWIRE Serial-Interface Timing 16 ______________________________________________________________________________________ HIGH-Z Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down MAX191 SCLK CS DOUT HIGH-Z MSB D10 D10 D9 D9 D8 D7 D6 D4 D5 D3 D2 D1 LSB HIGH-Z a. CPOL = 0, CPHA = 0 SCLK CS DOUT HIGH-Z HIGH-Z MSB D8 D7 D6 D4 D5 D3 D2 D1 LSB b. CPOL = 1, CPHA = 1 Figure 15. QSPI Serial-Interface Timing SCLK CLKR CS SSTRB HIGH-Z DOUT HIGH-Z HIGH-Z MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB HIGH-Z Figure 16. TMS320 Interface Timing ______________________________________________________________________________________ 17 MAX191 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down Following the data transfer, the DSP receive shift register (RSR) contains a 16-bit word consisting of the 12 data bits, MSB first, followed by four trailing 0s. Applications Information Power-On Initialization When the +5V power supply is first applied to the MAX191, perform a single conversion to initialize the ADC (the BUSY signal status is undefined at power-on). Disregard the data outputs. Power-Down Mode In some battery-powered systems, it is desirable to power down or remove power from the ADC during inactive periods. To power down the MAX191, drive PD low. In this mode, all internal ADC circuitry is off except the reference, and the ADC consumes less than 50A max (assuming all signals CS, RD, CLK, and HBEN are static and within 200mV of the supplies). Figure 17 shows a practical way to drive the PD pin. If using inter- MAX191 1 PD nal reference compensation, drive PD between VDD and DGND with a P I/O pin or other logic device (Figure 17a). For external-reference compensation mode, use the circuit in Figure 17b to drive PD between DGND and the floating voltage of PD. An alternative is to drive PD with three-state logic or a switch, provided the off leakage does not exceed 100nA. Internal Reference The internal 4.096V reference is available at VREF and must be bypassed to AGND with a 4.7F low-ESR capacitor (less than 1/2) in parallel with a 0.1F capacitor, unless internal-reference compensation mode is used (see the Internal Reference Compensation section). This minimizes noise and maintains a low reference impedance at high frequencies. The reference output can be disabled by connecting REFADJ to VDD when using an external reference. Reference-Compensation Modes Power-down performance can be optimized for a given conversion rate by selecting either internal or external reference compensation. Internal Compensation The connection for internal compensation is shown in Figure 18a. In this mode, the reference stabilizes quickly enough so that a conversion typically starts within 35s after the ADC is reactivated (PD pulled high). In this compensation mode, the reference buffer requires longer recovery time from SAR transients, therefore requiring a slower clock (and conversion time). With internal reference compensation, the typical conversion time rises to 25s (Figure 18b). Figure 18c illustrates the typical average supply current vs. conversion rate, a. INTERNAL-REFERENCE COMPENSATION MODE +5V 1 PD MAX191 MAX191 5 1 6 VREF REFADJ PD OPEN-DRAIN BUFFER 0.1F b. EXTERNAL-REFERENCE COMPENSATION MODE Figure 17. Drive Circuits for PD Pin 18 Figure 18a. Internal-Compensation Mode Circuit ______________________________________________________________________________________ Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down fg18c MAX191 10,000 1 SUPPLY CURRENT (A) PD 0 VREF 15s 20s 25s 1000 100 RD 10 10 50 200 1k 5k 20k 100k CONVERSIONS PER SECOND Figure 18b. Low Average-Power Mode Operation (Internal Compensation) Figure 18c. Average Supply Current vs. Conversion Rate, Powering Down Between Conversions which can be achieved using power-down between conversions. External Compensation Figure 19a shows the connection for external compensation with reference adjustment. In this mode, an external 4.7F capacitor compensates the reference output amplifier, allowing for maximum conversion speed and lowest conversion noise. However, when reactivating the ADC after power-down, the reference takes typically 2ms to fully charge the 4.7F capacitor, so more time is required before a conversion can start (Figure 19b). Thus, the average current consumed in power-up/powerdown operations is higher in external compensation mode than in internal compensation mode. 1 5 PD VREF 11k 0.1F 4.7F MAX191 100k 5k 15k 6 REFADJ 0.01F Gain and Offset Adjustment Figure 20 depicts the nominal, unipolar input/output (I/O) transfer function, and Figure 22 shows the bipolar I/O transfer function. Code transitions occur halfway between successive integer LSB values. Note that 1LSB = 1.00mV (4.096V/4096) for unipolar operation and 1LSB = 1.00mV ((4.096V/2 - -4.096V/2)/4096) for bipolar operation. Figures 19a and 21a show how to adjust the ADC gain in applications that require full-scale range adjustment. The connection shown in Figure 21a provides 0.5% for 20LSBs of adjustment range and is recommended for applications that use an external reference. On the other hand, Figure 19a is recommended for applications that use the internal reference, because it uses fewer external components. If both offset and full scale need adjustment, the circuit in Figure 21b is recommended. For single-supply Figure 19a. External-Compensation Mode with Internal Reference Adjustment Circuit ADCs, it is virtually impossible to null system negative offset errors. However, the MAX191 input configuration is pseudo-differential--only the difference in voltage between AIN+ and AIN- will be converted into its digital representation. By applying a small positive voltage to AIN-, the 0 input voltage at AIN+ can be adjusted to above or below AIN- voltage, thus nulling positive or negative system offset errors. R9 and R10 can be removed for applications that require only positive system errors to be nulled. To trim the offset error of the MAX191, apply 1/2LSB to the analog input and adjust R6 so the digital output code changes between 000 (hex) and 001 (hex). To adjust full scale, apply FS - 1 1/2LSBs and adjust R2 until the output code changes ______________________________________________________________________________________ 19 MAX191 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down OUTPUT CODE OPEN CIRCUIT (FLOAT) PD 0 FULL-SCALE TRANSITION 11 . . . 111 11 . . . 110 11 . . . 101 VREF 2ms RD 200ms 12.5s FS = VREF 1LSB = FS 4096 00 . . . 011 00 . . . 010 Figure 19b. Low Average-Power Mode Operation (External Compensation) 00 . . . 001 00 . . . 000 between FFE (hex) and FFF (hex). Because interaction occurs between adjustments, offset should be adjusted before gain. For an input gain of two, remove R7 and R8. The MAX191 accepts input voltages from AGND to VDD while operating from a single supply, and VSS to VDD when operating from dual supplies. Figure 22 shows the bipolar input transfer function with AIN- connected to midscale for single-supply operation and connected to GND operating from dual supplies. When operating from a single supply, the MAX191 can be configured for bipolar operation on its pseudo-differential input. Instead of using AIN- as an analog input return, AINcan be set to a different positive potential voltage above ground (BIP pin is set high). The sampled analog input (AIN+) can swing to any positive voltage above and below AIN-, and the ADC performs bipolar conversions with respect to AIN-. When operating from dual supplies, the MAX191 full-scale range is from -VREF/2 to +VREF/2. 0 1 2 3 FS AIN INPUT VOLTAGE (LSB) FS-1LSB Figure 20. Unipolar Transfer Function VIN MAX480 R1 100 R2 49.9 TO AIN+ R3 10k R4 10k Digital Bus Noise If the data bus connected to the ADC is active during a conversion, crosstalk from the data pins to the ADC comparator may generate errors. Slow-memory mode avoids this problem by placing the P in a wait state during the conversion. In ROM mode, if the data bus is active during the conversion, it should be isolated from the ADC using three-state drivers. The ADC generates considerable digital noise in ROM mode when RD or CS go high and the output data drivers are disabled after a conversion has started. This noise can cause large errors if it occurs when the SAR latches a comparator decision. To avoid this problem, 20 Figure 21a. Trim Circuit for Gain (0.5%) RD and CS should be active for less than one clock cycle. If this is not possible, RD or CS should go high at the rising edge of CLK, since the comparator output is always latched on falling edges of CLK. Layout, Grounding, Bypassing Use printed circuit boards for best system performance. ______________________________________________________________________________________ Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down MAX191 R7 10k MAX480 VIN AIN + R8 10k 01 . . . 111 R1 10k 01 . . . 110 MAX191 R2 100 VREF 00 . . . 010 D0-D11 00 . . . 001 00 . . . 000 R5 10k R6 10k R3 10k 11 . . . 111 11 . . . 110 11 . . . 101 R4 49.9 VREF 10 . . . 001 10 . . . 000 R9* 20k AIN 0.1F* R10* 49.9 SINGLE SUPPLY VREF AIN- = ---- 2 0V VREF ---- 2 DUAL SUPPLY AIN- = 0V -VREF ---- 2 0V ( ) VREF - 1LSB VREF ---- - 1LSB 2 * CONNECT AIN- TO AGND WHEN USING DUAL SUPPLIES Figure 21b. Offset (10mV) and Gain (1%) Trim Circuit Figure 22. Bipolar Transfer Function Wire-wrap boards are not recommended. Board layout should ensure that digital- and analog-signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another, or digital lines underneath the ADC package. Figure 23 shows the recommended system ground connections. Establish a single-point ground ("star" ground point) at AGND, separate from the logic ground. Connect all other analog grounds and DGND to it. No other digital-system ground should be connected to this single-point analog ground. The ground return to the power supply for this star ground should be low impedance and as short as possible for noisefree operation. High-frequency noise in the VDD power supply may affect the high-speed comparator in the ADC. Bypass these supplies to the single-point analog ground with SUPPLIES +5V GND -5V R* = 10 VDD AGND MAX191 VSS DGND +5V DGND DIGITAL CIRCUITRY *OPTIONAL Figure 23. Power-Supply Grounding Connection ______________________________________________________________________________________ 21 MAX191 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down 0.01F and 10F bypass capacitors. Minimize capacitor lead lengths for best supply-noise rejection. If the +5V power supply is very noisy, a 10 resistor can be connected as a lowpass filter to filter out supply noise (Figure 23). The theoretical minimum A/D noise is caused by quantization error and is a direct result of the ADC's resolution: SNR = (6.02n + 1.76) dB, where n is the number of bits of resolution. 74dB is the SNR of a perfect 12-bit ADC. _____________Dynamic Performance By transposing the equation that converts resolution to SNR we can compute the effective resolution or the "effective number of bits" the ADC provides from the measured SNR: High-speed sampling capability and throughput make the MAX191 ideal for wideband signal processing. To support these and other related applications, Fast Fourier Transform (FFT) test techniques guarantee the ADC's dynamic frequency response, distortion, and noise at the rated throughput. Specifically, this involves applying a low-distortion sine wave to the ADC input and recording the digital conversion results for a specified time. The data is then analyzed using an FFT algorithm, which determines its spectral content. Conversion errors are then seen as spectral elements outside the fundamental input frequency. FFT plots are shown in the Typical Operating Characteristics. ADCs have traditionally been evaluated by specifications such as zero and full-scale error, integral nonlinearity (INL), and differential nonlinearity (DNL). Such parameters are widely accepted for specifying performance with DC and slowly varying signals, but are less useful in signal-processing applications where the ADC's impact on the system transfer function is the main concern. The significance of various DC errors does not translate well to the dynamic case, so different tests are required. Signal-to-Noise Ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other A/D output signals, except signal harmonics. Signal-to-Noise + Distortion ratio (SINAD) is the same as the SNR, but includes signal harmonics. 22 n = (SNR - 1.76)/6.02 Total Harmonic Distortion Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal (in the frequency band above DC and below one-half the sample rate) to the fundamental itself. This expressed as: THD = 20log [ (V22 + V32 + V42 + V52 + . . . + Vn2) /V1] where V1 is the fundamental RMS amplitude and V2 to Vn are the amplitudes of the 2nd through nth harmonics. Spurious-Free Dynamic Range Spurious-free dynamic range is the ratio of the fundamental RMS amplitude to the amplitude of the next largest spectral component (in the frequency band above DC and below one-half the sample rate). Usually this peak occurs at some harmonic of the input frequency. But if the ADC is exceptionally linear, it can occur at a random peak in the ADC's noise floor. Opto-Isolated A/D Interface Many industrial applications require isolation to prevent excessive current flow where ground disparities exist between the ADC and the rest of the system. In Figure 24, a MAX250 and four 6N136 opto-couplers create an ______________________________________________________________________________________ Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down D1 V CC D2 MAX191 5V T1 602117970 (SCHOTT) 2 IN 100F 16V IC4 OUT 74L05 14 13 5V 100F 6V GND IC2-3 HCPL2630 (QUALITY TECHNOLOGIES) 1k 9 1k 1 8 Q1 2N3906 2 7 10 0.1F VDD 18 IC2 TTL/CMOS OUTPUTS 24 DOUT 1k IC1 MAX250 1k 4 AIN+ 3 AIN- 4 1k 6 11 12 VIN Q2 2N3906 3 16 SSTRB 1k 1 IC5 MAX191 5 SHDN 1k 8 1 4 3 HBEN 1k 2 7 20 RD CS IC3 TTL/CMOS INPUTS 1k PAR 4 1k 5 6 EN 8 BIP 6 3 4.7F GND 23 CLK 5 VREF AGND 0.1F 21 19 22 8 7 5 7 ISOLATION BARRIER 6 0.1F REFADJ V SS 2 DGND 12 Figure 24. Isolated Data-Acquisition Circuit ______________________________________________________________________________________ 23 PD V DD CLK/SCLK PAR AINAIN+ AGND ___________________Chip Topography HBEN CS RD VREF REFADJ 0.198" (5.0292mm) AGND D7/DOUT D6/SCLK OUT D5/SSTRB D3/D11 D4 D1/D9 DGND D2/D10 D0/D8 BIP BUSY 0.142" (3.6065mm) SUBSTRATE CONNECTED TO VDD ________________________________________________________Package Information PDIPN.EPS MAX191 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down 24 ______________________________________________________________________________________