19-1478; Rev 1; 9/02 Low-Power, Serial, 14-Bit DACs with Voltage Output The MAX5170/MAX5172 low-power, serial, voltage-output, 14-bit digital-to-analog converters (DACs) feature a precision output amplifier in a space-saving 16-pin QSOP package. The MAX5170 operates from a +5V single supply and the MAX5172 operates from a +3V single supply. Both devices draw only 280A of supply current, which reduces to 1A in shutdown. In addition, the programmable power-up reset feature allows for a user-selectable power-up output voltage of either 0 or midscale. The 3-wire serial interface is compatible with SPITM, QSPITM, and MICROWIRETM standards. An input register followed by a DAC register provides a doublebuffered input, allowing the input and DAC registers to be updated independently or simultaneously with a 16bit serial word. Additional features include software and hardware shutdown, shutdown lockout, a hardware clear pin, and a reference input capable of accepting DC and offset AC signals. These devices provide a programmable digital output pin for added functionality and a serial-data output pin for daisy-chaining. All logic inputs are TTL/CMOS-compatible and are internally buffered with Schmitt triggers to allow direct interfacing to optocouplers. The MAX5170/MAX5172 incorporate a proprietary on-chip circuit that keeps the output voltage virtually "glitch free," limiting the glitches to a few millivolts during power-up. Both devices are available in 16-pin QSOP packages and are specified for the extended (-40C to +85C) temperature range. For 100% pin-compatible DACS with internal reference, see the 13-bit MAX5130/MAX5131 and the 12bit MAX5120/MAX5121 data sheets. Applications Industrial Process Controls Digital Offset and Gain Adjustment Motion Control Automatic Test Equipment (ATE) Remote Industrial Controls P-Controlled Systems Features 1 LSB INL 1A Shutdown Current "Glitch Free" Output Voltage at Power-Up Single-Supply Operation +5V (MAX5170) +3V (MAX5172) Full-Scale Output Range +2.048V (MAX5172, VREF = +1.25V) +4.096V (MAX5170, VREF = +2.5V ) Rail-to-Rail(R) Output Amplifier Adjustable Output Offset Low THD (-80dB) in Multiplying Operation SPI/QSPI/MICROWIRE-Compatible 3-Wire Serial Interface Programmable Shutdown Mode and Power-Up Reset (0 or Midscale) Buffered Output Capable of Driving 5k || 100pF Loads User-Programmable Digital Output Pin Allows Serial Control of External Components Pin-Compatible Upgrade to the 12-Bit MAX5174/MAX5176 Ordering Information TEMP RANGE PIN-PACKAGE MAX5170AEEE -40C to +85C 16 QSOP 1 MAX5170BEEE MAX5172AEEE MAX5172BEEE -40C to +85C -40C to +85C -40C to +85C 16 QSOP 16 QSOP 16 QSOP 2 2 4 Pin Configuration TOP VIEW OS 1 16 VDD OUT 2 15 N.C. RS 3 PDL 4 CLR 5 Functional Diagram appears at end of data sheet. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. INL (LSB) PART 14 REF MAX5170 MAX5172 13 AGND 12 SHDN CS 6 11 UPO DIN 7 10 DOUT 9 SCLK 8 DGND QSOP ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX5170/MAX5172 General Description MAX5170/MAX5172 Low-Power, Serial, 14-Bit DACs with Voltage Output ABSOLUTE MAXIMUM RATINGS VDD to AGND, DGND ............................................-0.3V to +6.0V AGND to DGND.....................................................-0.3V to +0.3V Digital Inputs to DGND..........................................-0.3V to +6.0V DOUT, UPO to DGND ................................-0.3V to (VDD + 0.3V) OUT, REF to AGND ...................................-0.3V to (VDD + 0.3V) OS to AGND ...............................(AGND - 4.0V) to (VDD + 0.3V) Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70C) 16-Pin QSOP (derate 8mW/C above +70C)..............667mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS--MAX5170 (VDD = +5V 10%, VREF = 2.5V, OS = AGND = DGND, RL = 5k, CL = 100pF referenced to ground, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution 14 Bits MAX5170A 1 MAX5170B 2 Integral Nonlinearity (Note 1) INL Differential Nonlinearity DNL 1 LSB Offset Error (Note 2) VOS 10 mV Gain Error Power-Supply Rejection Ratio GE RL = -0.6 4 RL = 5k -1.6 8 10 120 PSRR Output Noise Voltage f = 100kHz Output Thermal Noise Density LSB LSB V/V 1 LSBp-p 80 nV/Hz REFERENCE Reference Input Range VREF 0 Reference Input Resistance RREF 18 VDD - 1.4 V k MULTIPLYING-MODE PERFORMANCE Reference -3dB Bandwidth VREF = 0.5Vp-p + 1.5VDC, slew-rate limited 350 kHz Reference Feedthrough VREF = 3.6Vp-p + 1.8VDC, f = 1kHz, code = all 0s -80 dB VREF = 1.5 Vp-p + 1.5VDC, f = 10kHz, code = 3FFF hex 82 dB Signal-to-Noise Plus Distortion Ratio SINAD DIGITAL INPUTS Input High Voltage VIH Input Low Voltage VIL Input Hysteresis 3 VHYS Input Leakage Current IIN Input Capacitance CIN V 0.8 200 VIN = 0 or VDD 0.001 V mV 1 8 A pF DIGITAL OUTPUTS Output High Voltage VOH ISOURCE = 2mA Output Low Voltage VOL ISINK = 2mA 2 VDD - 0.5 V 0.13 _______________________________________________________________________________________ 0.4 V Low-Power, Serial, 14-Bit DACs with Voltage Output (VDD = +5V 10%, VREF = 2.5V, OS = AGND = DGND, RL = 5k, CL = 100pF referenced to ground, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DYNAMIC PERFORMANCE Voltage Output Slew Rate SR Output Settling Time 0.6 To 0.5LSB, from 10mV to full-scale 18 Output Voltage Swing (Note 3) 0 OS Pin Input Resistance 80 Time Required to Exit Shutdown CS = VDD, f SCLK = 100kHz, VSCLK = 5Vp-p Digital Feedthrough V/s s VDD V 120 k 40 s 1 nV-s POWER SUPPLIES Positive Supply Voltage VDD Power-Supply Current (Note 4) IDD 4.5 Shutdown Current (Note 4) 5.5 V 0.28 0.4 mA 1 10 A TIMING CHARACTERISTICS SCLK Clock Period tCP 100 ns SCLK Pulse Width High tCH 40 ns SCLK Pulse Width Low tCL 40 ns CS Fall to SCLK Rise Setup Time tCSS 40 ns SCLK Rise to CS Rise Hold Time tCSH 0 ns DIN Setup Time tDS 40 ns DIN Hold Time tDH 0 ns SCLK Rise to DOUT Valid Propagation Delay tDO1 CLOAD = 200pF 80 ns SCLK Fall to DOUT Valid Propagation Delay tDO2 CLOAD = 200pF 80 ns SCLK Rise to CS Fall Delay tCS0 10 ns CS Rise to SCLK Rise Hold Time tCS1 40 ns CS Pulse Width High tCSW 100 ns _______________________________________________________________________________________ 3 MAX5170/MAX5172 ELECTRICAL CHARACTERISTICS--MAX5170 (continued) MAX5170/MAX5172 Low-Power, Serial, 14-Bit DACs with Voltage Output ELECTRICAL CHARACTERISTICS--MAX5172 (VDD = +2.7V to +3.6V, VREF = 1.25V, OS = AGND = DGND, RL = 5k, CL = 100pF referenced to ground, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C). PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution 14 Bits MAX5172A 2 MAX5172B 4 Integral Nonlinearity (Note 5) INL Differential Nonlinearity DNL 1 LSB Offset Error (Note 2) VOS 10 mV Gain Error Power-Supply Rejection Ratio GE RL = -0.6 4 RL = 5k -1.6 8 10 120 PSRR Output Noise Voltage f = 100kHz Output Thermal Noise Density LSB LSB V/V 2 LSBp-p 80 nV/Hz REFERENCE Reference Input Range VREF 0 Reference Input Resistance RREF 18 VDD - 1.4 V k MULTIPLYING-MODE PERFORMANCE Reference -3dB Bandwidth VREF = 0.5Vp-p + 0.75VDC, slew-rate limited 350 kHz Reference Feedthrough VREF = 1.6Vp-p + 0.8VDC, f = 1kHz, code = all 0s -80 dB VREF = 0.6Vp-p + 0.9VDC, f = 10kHz, code = 3FFF hex 78 dB Signal-to-Noise Plus Distortion Ratio SINAD DIGITAL INPUT Input High Voltage VIH Input Low Voltage VIL Input Hysteresis 2.2 VHYS Input Leakage Current IIN Input Capacitance CIN V 0.8 200 VIN = 0 or VDD 0.001 V mV 1 8 A pF DIGITAL OUTPUT Output High Voltage VOH ISOURCE = 2mA Output Low Voltage VOL ISINK = 2mA 4 VDD - 0.5 V 0.13 _______________________________________________________________________________________ 0.4 V Low-Power, Serial, 14-Bit DACs with Voltage Output (VDD = 2.7V to 3.6V, VREF = 1.25V, OS = AGND = DGND, RL = 5k, CL = 100pF referenced to ground, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C). PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DYNAMIC PERFORMANCE Voltage Output Slew Rate SR Output Settling Time To 0.5LSB from 10mV to full-scale Output Voltage Swing (Note 3) 0 OS Pin Input Resistance 80 Time Required to Exit Shutdown CS = VDD, f SCLK = 100kHz, VSCLK = 3Vp-p Digital Feedthrough 0.6 V/s 18 s VDD 120 V k 40 s 1 nV-s POWER SUPPLIES Positive Supply Voltage VDD Power-Supply Current (Note 4) IDD 2.7 Shutdown Current (Note 4) 3.6 V 0.28 0.4 mA 1 10 A TIMING CHARACTERISTICS SCLK Clock Period tCP 150 ns SCLK Pulse Width High tCH 75 ns SCLK Pulse Width Low tCL 75 ns tCSS 60 ns tCSH 0 ns DIN Setup Time tDS 60 ns DIN Hold Time tDH 0 ns SCLK Rise to DOUT Valid Propagation Delay tDO1 CLOAD = 200pF 200 ns SCLK Fall to DOUT Valid Propagation Delay tDO2 CLOAD = 200pF 200 ns SCLK Rise to CS Fall Delay tCS0 10 ns CS Rise to SCLK Rise Hold Time tCS1 75 ns CS Pulse Width High tCSW 150 ns CSB Fall to SCLK Rise Setup Time SCLK Rise to CS Rise Hold Time Note 1: Note 2: Note 3: Note 4: Note 5: INL guaranteed between codes 40 and 16383. Offset is measured at the code that comes closest to 10mV. Accuracy is better than 1.0 LSB for VOUT = 10mV to VDD - 180mV. Guaranteed by PSR test on end points. RL = open and digital inputs are either VDD or DGND. INL guaranteed between codes 80 and 16383. _______________________________________________________________________________________ 5 MAX5170/MAX5172 ELECTRICAL CHARACTERISTICS--MAX5172 (continued) Typical Operating Characteristics (MAX5170: VDD = +5V, VREF = 2.5V; MAX5172: VDD = +3V, VREF = 1.25V; CL = 100pF, OS = AGND, code = 3FFF hex, TA = +25C, unless otherwise noted.) MAX5170 300 290 280 270 260 250 240 286 284 282 280 278 276 274 272 1.4 MAX5170/72 toc03 288 1.3 SHUTDOWN CURRENT (A) 310 290 MAX5170/72 toc02 320 NO-LOAD SU0PPLY CURRENT (A) MAX5170/72 toc01 330 1.2 1.1 1 0.9 270 268 230 4.6 4.8 5.0 5.2 SUPPLY VOLTAGE (V) 5.4 -50 5.6 70 90 0.8 -50 4.0 3.5 OUTPUT VOLTAGE (V) 4.0966 4.0964 -30 -10 10 30 50 TEMPERATURE (C) 70 DYNAMIC RESPONSE 5V VCS 5v/div 0 3.0 4.096V 2.5 VOUT 1v/div 2.0 1.5 1.0 4.0962 10mV 0.5 0 -30 -10 10 30 50 TEMPERATURE (C) 70 10 90 1k 10k 2s/div 100k RL () TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY DYNAMIC RESPONSE MAX5170/72 toc07 -75 5V -76 0 -77 4.096V VOUT 1V/div THD + NOISE (dB) VCS 5V/div 100 MAX5170/72 toc08 4.0960 -50 90 MAX5170/72 toc06 4.5 MAX5170/72 toc04 4,0968 -10 10 30 50 TEMPERATURE (C) OUTPUT VOLTAGE vs. LOAD RESISTANCE OUTPUT VOLTAGE vs. TEMPERATURE 4.0970 -30 REFERENCE FEEDTHROUGH 0 VREF = 1.8VDC + 3.6Vp-p at f = 1kHz VOUT/VREF MAX5170/72 toc9 4.4 MAX5170/72 TOC05 NO-LOAD SUPPLY CURRENT (A) SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE NO-LOAD SUPPLY CURRENT vs. TEMPERATURE NO-LOAD SUPPLY CURRENT vs. SUPPLY VOLTAGE OUTPUT VOLTAGE (V) MAX5170/MAX5172 Low-Power, Serial, 14-Bit DACs with Voltage Output -78 -79 -80 12.5dB/div -81 -82 10mV -83 -84 2s/div 6 10 100 1k 10k FREQUENCY (Hz) 100k 20 FREQUENCY (Hz) _______________________________________________________________________________________ 10k Low-Power, Serial, 14-Bit DACs with Voltage Output (MAX5170: VDD = +5V, VREF = 2.5V; MAX5172: VDD = +3V, VREF = 1.25V; CL = 100pF, OS = AGND, code = 3FFF hex, TA = +25C, unless otherwise noted.) MAX5170 FFT PLOT DIGITAL FEEDTHROUGH MAX5170/72 toc12 MAX5170/72 toc11 VREF = 1.25VDC + 1.13Vp-p, at f = 10kHz MAX5170/72 toc10 MAJOR-CARRY TRANSITION 0 VCS 2V/div VOUT 2mV/div VOUT/VREF 12.5dB/div ACCOUPLED VOUT 100mV/div 20 FREQUENCY (Hz) VSCLK 5V/div 100k 400ns/div 5s/div START-UP GLITCH MAX5170/72 toc13 5 MAX5170/72 toc14 REFERENCE INPUT FREQUENCY RESPONSE 0 VDD 1V/div GAIN (dB) -5 -10 -15 -20 VOUT 10mV/div AC-COUPLED VREF = 0.67Vp-p + 1.5VDC -25 0 500 1000 1500 2000 FREQUENCY (kHz) 2500 50ms/div 3000 MAX5172 280 275 270 265 260 285 280 275 270 250 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 SUPPLY VOLTAGE (V) 260 -50 0.58 0.56 0.54 0.52 0.5 0.48 275 255 MAX5170/72 toc17 290 0.60 SUPPLY CURRENT (A) 285 MAX5170/72 toc16 290 295 NO-LOAD SUPPLY CURRENT (A) NO-LOAD SUPPLY CURRENT (A) 295 MAX5170/72 toc15 300 SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE NO-LOAD SUPPLY CURRENT vs. TEMPERATURE NO-LOAD SUPPLY CURRENT vs. SUPPLY VOLTAGE 0.46 -30 -10 10 30 50 TEMPERATURE (C) 70 90 0.44 -50 -30 -10 10 30 50 TEMPERATURE (C) 70 _______________________________________________________________________________________ 90 7 MAX5170/MAX5172 Typical Operating Characteristics (continued) Typical Operating Characteristics (continued) (MAX5170: VDD = +5V, VREF = 2.5V; MAX5172: VDD = +3V, VREF = 1.25V; CL = 100pF, OS = AGND, code = 3FFF hex, TA = +25C, unless otherwise noted.) MAX5172 OUTPUT VOLTAGE vs. TEMPERATURE 2.0486 2.0484 2.0482 MAX5170/72 toc19 3V VCS 3V/div 0 1.5 2.048V 1.0 VOUT 500mV/div 0.5 0 10mV -0.5 -10 10 30 50 TEMPERATURE (C) 70 90 10 1k RL () 10k 2s/div 100k TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY DYNAMIC RESPONSE MAX5170/72 toc21 -78.0 3V -78.5 0 -79.0 2.048V VOUT 500mV/div THD + NOISE (dB) VCS 3V/div 100 REFERENCE FEEDTHROUGH 0 VREF = 0.8VDC + 1.6Vp-p at f = 1kHz MAX5170/72 toc23 -30 MAX5170/72 toc22 2.0480 -50 MAX5170/72 toc20 2.0 OUTPUT VOLTAGE (V) 2.0488 DYNAMIC RESPONSE OUTPUT VOLTAGE vs. LOAD RESISTANCE 2.5 MAX5170/72 toc18 2.0490 OUTPUT VOLTAGE (V) -79.5 VOUT/VREF 12.5dB/div -80.0 -80.5 -81.0 10mV -81.5 -82.0 10 100 1k 10k FREQUENCY (Hz) 20 100k MAJOR-CARRY TRANSITION VREF = 0.9VDC + 0.424Vp-p at f = 10kHz 10k DIGITAL FEEDTHROUGH (SCLK, OUT) MAX5170/72 toc25 FFT PLOT 0 FREQUENCY (Hz) MAX5170/72 toc26 2s/div MAX5170/72 toc24 MAX5170/MAX5172 Low-Power, Serial, 14-Bit DACs with Voltage Output CS 2V/div SCLK 2V/div VOUT/VREF 12.5dB/div OUT 100mV/div 20 8 FREQUENCY (Hz) 100k OUT 500V/div 5s/div AC-COUPLED 2s/div AC-COUPLED _______________________________________________________________________________________ Low-Power, Serial, 14-Bit DACs with Voltage Output (MAX5170: VDD = +5V, VREF = 2.5V; MAX5172: VDD = +3V, VREF = 1.25V; CL = 100pF, OS = GND, code = 3FFF hex, TA = +25C, unless otherwise noted.) MAX5172 START-UP GLITCH MAX5170/72 toc27 0 -5 GAIN (dB) MAX5170/72 toc28 REFERENCE INPUT FREQUENCY RESPONSE 5 VDD 1V/div -10 -15 -20 VOUT 10mV/div VREF = 0.67Vp-p + 0.75VDC -25 -30 0 500 1000 1500 2000 FREQUENCY (kHz) 2500 3000 50ms/div AC-COUPLED Pin Description PIN NAME 1 OS FUNCTION 2 OUT 3 RS Reset Mode Select (digital input). Connect to VDD to select midscale reset output voltage. Connect to DGND to select 0 reset output voltage. 4 PDL Power-Down Lockout (digital input). Connect to VDD to allow shutdown. Connect to DGND to disable software and hardware shutdown. 5 CLR Clear DAC (digital input). Clears the DAC to either zero or midscale as determined by RS. Offset Adjustment. Connect to AGND for no offset. Voltage Output. High impedance when in shutdown. The output voltage is limited to VDD. 6 CS Chip Select Input (digital input). DIN ignored when CS is high. 7 DIN Serial-Data Input (digital input). Data is clocked in on the rising edge of SCLK. 8 SCLK Serial Clock Input (digital input) 9 DGND Digital Ground 10 DOUT Serial-Data Output 11 UPO 12 SHDN Shutdown (digital input). Pulling SHDN high when PDL = VDD places the chip in shutdown with a maximum shutdown current of 10A. 13 AGND Analog Ground 14 REF Reference Input. Maximum VREF is VDD - 1.4V. 15 N.C. No Connection 16 VDD Positive Supply. Bypass to AGND with a 4.7F capacitor in parallel with a 0.1F capacitor. User-Programmable Output. State is set by the serial input. _______________________________________________________________________________________ 9 MAX5170/MAX5172 Typical Operating Characteristics (continued) MAX5170/MAX5172 Low-Power, Serial, 14-Bit DACs with Voltage Output Detailed Description The MAX5170/MAX5172 14-bit, serial, voltage-output DACs operate with a 3-wire serial interface. These devices include a 16-bit shift register and a doublebuffered input composed of an input register and a DAC register (see Functional Diagram). In addition, these devices employ a rail-to-rail output amplifier and internally trimmed resistors to provide a gain of +1.638V/V, maximizing the output voltage swing. The MAX5170/MAX5172's offset adjust pin allows for a DC shift in the DAC output. The DACs are designed with an inverted R-2R ladder network (Figure 1) which produces a weighted voltage proportional to the reference voltage. Reference Inputs The reference input accepts both AC and DC values with a voltage range extending from 0 to VDD - 1.4V. The following equation represents the resulting output voltage: VOUT = VREF x N x Gain 16384 where N is the numeric value of the DAC's binary input code (0 to 16383), VREF is the reference voltage, and Gain is the internal set voltage gain (+1.638V/V if OS = AGND). The maximum output voltage is VDD. The reference pin has a minimum impedance of 18k and is code dependent. Output Amplifier With OS connected to AGND, the output amplifier employs an internal, trimmed resistor-divider setting the gain to +1.638V/V and minimizing gain error. The output amplifier has a typical slew rate of 0.6V/s and settles to 0.5LSB from a full-scale transition within 18s, when loaded with 5k in parallel with 100pF. Loads less than 2k degrade performance. For alternative output amplifier setups, refer to the Applications Information section. Shutdown Mode The MAX5170/MAX5172 feature a software- and hardware-programmable shutdown mode that reduces the typical supply current to 1A. Enter shutdown by writing the appropriate input-control word as shown in Table 1 or by using the hardware shutdown. In shutdown mode, the reference input and the amplifier output become high-impedance and the serial interface remains active. Data in the input register is saved, allowing the MAX5170/MAX5172 to recall the prior output state when returning to normal operation. Exit shutdown by 10 OS R R R 2R 2R D0 R 2R D10 OUT R 2R 2R D11 D12 REF AGND SHOWN FOR ALL 1s ON DAC Figure 1. Simplified DAC Circuit Diagram reloading the DAC register from the shift register, by simultaneously loading the input and DAC registers, or by toggling PDL. When returning from shutdown, wait 40s for the output to settle. Power-Down Lockout Power-Down Lockout disables the software/hardware shutdown mode. A high-to-low transition brings the device out of shutdown and returns the output to its previous state. Shutdown Pulling SHDN high while PDL is high places the MAX5170/MAX5172 in shutdown. Pulling SHDN low will not return the device to normal operation. A high-to-low transition on PDL or an appropriate command from the serial data line (see Table 1 for commands) is required to exit shutdown. Serial-Interface The MAX5170/MAX5172 3-wire serial interface is compatible with SPI, QSPI (Figure 2) and MICROWIRE (Figure 3) interface standards. The 16-bit serial input word consists of two control bits and 14 bits of data (MSB to LSB). The control bits determine the MAX5170/MAX5172's operation as outlined in Table 1. The MAX5170/ MAX5172's digital inputs are double buffered, which allows any of the following: * Loading the input register without updating the DAC register * Updating the DAC register from the input register * Updating the input and DAC registers simultaneously. ______________________________________________________________________________________ Low-Power, Serial, 14-Bit DACs with Voltage Output SS MOSI DIN MAX5170 MAX5172 SCLK SCK CS I/O SPI/QSPI PORT CPOL = 0, CPHA = 0 Figure 2. Connections for SPI and QSPI Interface The MAX5170/MAX5172 accepts one 16-bit packet or two 8-bit packets sent while CS remains low. The MAX5170/MAX5172 allow the following to be configured: * Clock edge on which serial data output (DOUT) is clocked out * State of the user-programmable logic output * Configuration of the reset state. Specific commands for setting these are shown in Table 1. The general timing diagram in Figure 4 illustrates how the MAX5170/MAX5172 acquire data. CS must go low at least tCSS before the rising edge of the serial clock (SCLK). With CS low, data is clocked into the register on the rising edge of SCLK. The maximum serial clock frequency guaranteed for proper operation is 10MHz for MAX5170 and 6MHz for MAX5172. See Figure 5 for a detailed timing diagram of the serial interface. Serial Data Output (DOUT) MAX5170 MAX5172 SCLK SK DIN SO CS I/O MICROWIRE PORT The serial-data output, DOUT, is the internal shift register's output and allows for daisy-chaining of multiple devices as well as data readback (see Applications Information). By default upon start-up, data shifts out of DOUT on the serial clock's rising edge (Mode 0) and provides a lag of 16 clock cycles, thus maintaining SPI, QSPI, and MICROWIRE compatibility. However, if the device is programmed for Mode 1, the output data lags DIN by 16.5 clock cycles and is clocked out on the serial clock's rising edge. During shutdown, DOUT retains its last digital state prior to shutdown. Figure 3. Connections for MICROWIRE Interface Standards Table 1. Serial-Interface Programming Commands 16-BIT SERIAL WORD FUNCTION C1 C0 D13..................D0 0 0 14-bit DAC data Load input register; DAC registers are unchanged. 0 1 14-bit DAC data Load input register; DAC registers are updated (start-up DAC with new data). 1 0 x x x xxx xxxx xxxx Update DAC register from input register (start-up DAC with data previously stored in the input registers). 1 1 0 0 x xxx xxxx xxxx No operation (NOP). 1 1 0 1 x xxx xxxx xxxx Shut down DAC (provided PDL = 1). 1 1 1 0 0 xxx xxxx xxxx UPO goes low (default). 1 1 1 0 1 xxx xxxx xxxx UPO goes high. 1 1 1 1 0 xxx xxxx xxxx Mode 1, DOUT clocked out on SCLK's rising edge. 1 1 1 1 1 xxx xxxx xxxx Mode 0, DOUT clocked out on SCLK's falling edge (default). ______________________________________________________________________________________ 11 MAX5170/MAX5172 +5V MAX5170/MAX5172 Low-Power, Serial, 14-Bit DACs with Voltage Output CS COMMAND EXECUTED SCLK 1 DIN C1 8 C0 9 D13 D12 D11 D10 D09 D08 D07 16 D06 D05 D04 D03 D02 D01 D00 Figure 4. Serial-Interface Timing Diagram tCSW CS tCSO tCSS tCSH tCS1 SCLK tCH tCL tCP DIN tDS tD01 tD02 tDH DOUT Figure 5. Detailed Serial-Interface Timing Diagram User-Programmable Logic Output (UPO) Reset (RS) and Clear (CLR) The UPO allows control of an external device through the serial interface, thereby reducing the number of microcontroller I/O pins required. During power-down, this output retains its digital state prior to shutdown. When CLR is pulled low, UPO resets to its programmed default state. See Table 1 for specific commands to control the UPO. The MAX5170/MAX5172 offers a clear pin which resets the output voltage. If RS = DGND, then CLR resets the output voltage to the minimum voltage (0 if OS = AGND). If RS = VDD, then CLR resets the output voltage to midscale. In either case, CLR resets UPO to its programmed default state. 12 ______________________________________________________________________________________ Low-Power, Serial, 14-Bit DACs with Voltage Output OS +5V/+3V Unipolar Output MAX5170/MAX5172 Applications Information REF Figure 6 shows the MAX5170/MAX5172 configured for unipolar, rail-to-rail operation with a gain of +1.638V/V. Table 2 lists the codes for unipolar output voltages. The maximum output voltage is limited to VDD. Use the OS pin to introduce an offset voltage as shown in Figure 7 and described in the Offset and Buffer Configurations section. VOS VDD MAX5170 MAX5172 DAC Bipolar Output OUT AGND DGND Figure 8 shows the MAX5170/MAX5172 configured for bipolar output operation. The output voltage is given by the following equation (OS = AGND): 2 X N VOUT = VREF - 1 16,384 Figure 7. Setting OS for Output Offset where N represents the numeric value of the DAC's binary input code, VREF is the voltage of the external reference. Table 3 shows digital codes and the corresponding output voltage for Figure 8's circuit. +5V/+3V REF 10k 10k OS VDD OS +5V/+3V REF VDD VOUT MAX5170 MAX5172 DAC DAC OUT AGND V+ MAX5170 MAX5172 OUT DGND V- AGND DGND Figure 8. Bipolar Output Circuit Figure 6. Unipolar Output Circuit (Rail-to-Rail) Table 3. Bipolar Code Table (Circuit of Figure 8) Table 2. Unipolar Code Table (Circuit of Figure 6) DAC CONTENTS MSB LSB ANALOG OUTPUT DAC CONTENTS MSB LSB ANALOG OUTPUT 11 1111 1111 1111 +VREF (16383/16384) * 1.638 11 1111 1111 1111 +VREF [(2 * 16383/16384) - 1] 10 0000 0000 0001 +VREF (8193/16384) * 1.638 10 0000 0000 0001 +VREF [(2 * 8193/16384) - 1] 10 0000 0000 0000 +VREF (8192/16384) * 1.638 10 0000 0000 0000 +VREF [(2 * 8192/16384) - 1] 01 1111 1111 1111 +VREF (8191/16384) * 1.638 01 1111 1111 1111 +VREF [(2 * 8191/16384) - 1] 00 0000 0000 0001 +VREF (1/16384) * 1.638 00 0000 0000 0001 +VREF [(2 * 1/16384) - 1] 00 0000 0000 0000 0 00 0000 0000 0000 -VREF ______________________________________________________________________________________ 13 MAX5170/MAX5172 Low-Power, Serial, 14-Bit DACs with Voltage Output Offset and Buffer Configurations Power-Supply and Layout Considerations The simple circuit of Figure 7 illustrates how to introduce an offset to the output voltage. The amount of offset introduced by a voltage at the OS pin is shown in the following equation: Wire-wrap boards are not recommended. For optimum system performance, use printed circuit boards with separate analog and digital ground planes. Connect the two ground planes together at the low-impedance power-supply source. Connect DGND and AGND pins together at the IC. The best ground connection is achieved by connecting the DAC's DGND and AGND pins together and connecting that point to the system analog ground plane. This is useful because if the DAC's DGND is connected to the system digital ground, digital noise may get through to the DAC's analog portion. Bypass the power supply with a 4.7F capacitor in parallel with a 0.1F capacitor to AGND. Minimize their lead lengths to reduce inductance. If noise becomes an issue, use shielding and/or ferrite beads to increase isolation. To maintain INL and DNL performance as well as gain drift, it is extremely important to provide the lowest possible reference output impedance at the DAC reference input pin. INL degrades if the series resistance on REF pin exceeds 0.1. The same consideration must be made for the AGND pin. VOFFSET = VOS x (1 - Gain) where Gain = 1.638. However, the total output voltage of the device cannot exceed VDD regardless of the voltage on the OS pin. To set the gain of the output amplifier to 1, connect OS to OUT. Daisy-Chaining Devices The serial data output pin (DOUT) allows multiple MAX5170/MAX5172s to be daisy-chained together, as shown in Figure 9. The advantage of this is that only two lines are needed to control all the DACs on the line. The disadvantage is that it takes n commands to program the DACs. Figure 10 shows several MAX5170/MAX5172s sharing one common DIN signal line. In this configuration, the data bus is common to all devices. However, more I/O lines are required for this configuration because each device requires a dedicated CS line. The advantage of this configuration is that only one command is needed to program any DAC. Using an AC Reference The MAX5170/MAX5172 accepts reference voltages with AC components as long as the reference voltage remains between 0 and VDD - 1.4V. Figure 11 shows a technique for applying an offset sine wave signal to REF. The reference voltage must remain above AGND. SCLK SCLK MAX5170 MAX5172 DIN DOUT CS SCLK MAX5170 MAX5172 DIN CS DOUT MAX5170 MAX5172 DIN DOUT CS Figure 9. Daisy-Chaining MAX5170/MAX5172 Devices 14 ______________________________________________________________________________________ TO OTHER SERIAL DEVICES Low-Power, Serial, 14-Bit DACs with Voltage Output MAX5170/MAX5172 DIN SCLK CS1 CS2 TO OTHER SERIAL DEVICES CS3 CS CS MAX5170 MAX5172 CS MAX5170 MAX5172 MAX5170 MAX5172 SCLK SCLK SCLK DIN DIN DIN Figure 10. Multiple MAX5170/MAX5172s Sharing Common DIN and SCLK Lines Chip Information +5V/ +3V +5V/+3V R1 AC REFERENCE INPUT 500mVp-p TRANSISTOR COUNT: 3457 MAX495 R2 VDD REF OS OUT DAC AGND MAX5170 MAX5172 GND Figure 11. AC Reference Input Circuit ______________________________________________________________________________________ 15 Functional Diagram CS PDL SHDN VDD AGND DGND DIN SCLK SERIAL CONTROL DOUT 16-BIT SHIFT REGISTER RS LOGIC OUTPUT UPO OS DECODE CONTROL CLR MAX5170 MAX5172 INPUT REGISTER DAC REGISTER DAC OUT REF Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) QSOP.EPS MAX5170/MAX5172 Low-Power, Serial, 14-Bit DACs with Voltage Output Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.