General Description
The MAX5170/MAX5172 low-power, serial, voltage-out-
put, 14-bit digital-to-analog converters (DACs) feature a
precision output amplifier in a space-saving 16-pin
QSOP package. The MAX5170 operates from a +5V
single supply and the MAX5172 operates from a +3V
single supply. Both devices draw only 280µA of supply
current, which reduces to 1µA in shutdown. In addition,
the programmable power-up reset feature allows for a
user-selectable power-up output voltage of either 0 or
midscale.
The 3-wire serial interface is compatible with SPI™,
QSPI™, and MICROWIRE™ standards. An input regis-
ter followed by a DAC register provides a double-
buffered input, allowing the input and DAC registers to
be updated independently or simultaneously with a 16-
bit serial word. Additional features include software and
hardware shutdown, shutdown lockout, a hardware
clear pin, and a reference input capable of accepting
DC and offset AC signals. These devices provide a pro-
grammable digital output pin for added functionality
and a serial-data output pin for daisy-chaining. All logic
inputs are TTL/CMOS-compatible and are internally
buffered with Schmitt triggers to allow direct interfacing
to optocouplers.
The MAX5170/MAX5172 incorporate a proprietary on-chip
circuit that keeps the output voltage virtually “glitch free,”
limiting the glitches to a few millivolts during power-up.
Both devices are available in 16-pin QSOP packages and
are specified for the extended (-40°C to +85°C) tempera-
ture range. For 100% pin-compatible DACS with internal
reference, see the 13-bit MAX5130/MAX5131 and the 12-
bit MAX5120/MAX5121 data sheets.
Applications
Industrial Process Controls
Digital Offset and Gain Adjustment
Motion Control
Automatic Test Equipment (ATE)
Remote Industrial Controls
µP-Controlled Systems
Features
♦±1 LSB INL
♦1µA Shutdown Current
♦“Glitch Free” Output Voltage at Power-Up
♦Single-Supply Operation
+5V (MAX5170)
+3V (MAX5172)
♦Full-Scale Output Range
+2.048V (MAX5172, VREF = +1.25V)
+4.096V (MAX5170, VREF = +2.5V )
♦Rail-to-Rail®Output Amplifier
♦Adjustable Output Offset
♦Low THD (-80dB) in Multiplying Operation
♦SPI/QSPI/MICROWIRE-Compatible 3-Wire
Serial Interface
♦Programmable Shutdown Mode and Power-Up
Reset (0 or Midscale)
♦Buffered Output Capable of Driving 5kΩ|| 100pF
Loads
♦User-Programmable Digital Output Pin Allows
Serial Control of External Components
♦Pin-Compatible Upgrade to the 12-Bit
MAX5174/MAX5176
MAX5170/MAX5172
Low-Power, Serial, 14-Bit DACs
with Voltage Output
________________________________________________________________ Maxim Integrated Products 1
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
OS VDD
N.C.
REF
AGND
PDL
UPO
DOUT
DGND
TOP VIEW
MAX5170
MAX5172
QSOP
OUT
RS
CS
SHDN
CLR
DIN
SCLK
19-1478; Rev 1; 9/02
PART
MAX5170AEEE
MAX5170BEEE
MAX5172AEEE -40°C to +85°C
-40°C to +85°C
-40°C to +85°C
TEMP RANGE PIN-PACKAGE
16 QSOP
16 QSOP
16 QSOP
Pin Configuration
Ordering Information
MAX5172BEEE -40°C to +85°C 16 QSOP
INL
(LSB)
±1
±2
±2
±4
Functional Diagram appears at end of data sheet.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
MAX5170/MAX5172
Low-Power, Serial, 14-Bit DACs
with Voltage Output
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS—MAX5170
(VDD = +5V ±10%, VREF = 2.5V, OS = AGND = DGND, RL= 5kΩ, CL= 100pF referenced to ground, TA= TMIN to TMAX, unless
otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to AGND, DGND............................................-0.3V to +6.0V
AGND to DGND.....................................................-0.3V to +0.3V
Digital Inputs to DGND..........................................-0.3V to +6.0V
DOUT, UPO to DGND ................................-0.3V to (VDD + 0.3V)
OUT, REF to AGND ...................................-0.3V to (VDD + 0.3V)
OS to AGND ...............................(AGND - 4.0V) to (VDD + 0.3V)
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (TA= +70°C)
16-Pin QSOP (derate 8mW/°C above +70°C)..............667mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
CONDITIONS UNITSMIN TYP MAXSYMBOLPARAMETER
Bits14Resolution
MAX5170A ±1
MAX5170B LSB
±2
INLIntegral Nonlinearity (Note 1)
LSB±1DNLDifferential Nonlinearity
mV±10VOS
Offset Error (Note 2)
RL= ∞LSB
-0.6 ±4
GEGain Error RL= 5kΩ-1.6 ±8
µV/V10 120PSRRPower-Supply Rejection Ratio
f = 100kHz LSBp-p1Output Noise Voltage
nV/√Hz
80Output Thermal Noise Density
V0V
DD - 1.4VREF
Reference Input Range
kΩ18RREF
Reference Input Resistance
VREF = 0.5Vp-p + 1.5VDC, slew-rate limited kHz350Reference -3dB Bandwidth
VREF = 1.5 Vp-p + 1.5VDC, f = 10kHz,
code = 3FFF hex dB82SINAD
Signal-to-Noise Plus Distortion
Ratio
V3VIH
Input High Voltage
V0.8VIL
Input Low Voltage
mV200VHYS
Input Hysteresis
VIN = 0 or VDD µA0.001 ±1IIN
Input Leakage Current
pF8CIN
Input Capacitance
ISOURCE = 2mA VVDD - 0.5VOH
Output High Voltage
ISINK = 2mA V0.13 0.4VOL
Output Low Voltage
VREF = 3.6Vp-p + 1.8VDC, f = 1kHz,
code = all 0s dB-80Reference Feedthrough
STATIC PERFORMANCE
REFERENCE
MULTIPLYING-MODE PERFORMANCE
DIGITAL INPUTS
DIGITAL OUTPUTS
MAX5170/MAX5172
Low-Power, Serial, 14-Bit DACs
with Voltage Output
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS—MAX5170 (continued)
(VDD = +5V ±10%, VREF = 2.5V, OS = AGND = DGND, RL = 5kΩ, CL= 100pF referenced to ground, TA= TMIN to TMAX, unless
otherwise noted. Typical values are at TA= +25°C.)
CONDITIONS
V/µs0.6SRVoltage Output Slew Rate
V0V
DD
Output Voltage Swing (Note 3)
kΩ80 120OS Pin Input Resistance
µs40Time Required to Exit Shutdown
UNITSMIN TYP MAXSYMBOLPARAMETER
CS = VDD, fSCLK = 100kHz, VSCLK = 5Vp-p nV-s1Digital Feedthrough
V4.5 5.5VDD
Positive Supply Voltage
mA0.28 0.4IDD
Power-Supply Current (Note 4)
µA110Shutdown Current (Note 4)
ns100tCP
SCLK Clock Period
ns40tCH
SCLK Pulse Width High
ns40tCL
SCLK Pulse Width Low
ns40tCSS
CS Fall to SCLK Rise Setup
Time
ns40tDS
DIN Setup Time
ns0tDH
DIN Hold Time
CLOAD = 200pF ns80tDO1
SCLK Rise to DOUT Valid
Propagation Delay
CLOAD = 200pF ns80tDO2
SCLK Fall to DOUT Valid
Propagation Delay
ns10tCS0
SCLK Rise to CS Fall Delay
ns100tCSW
CS Pulse Width High
ns0tCSH
SCLK Rise to CS Rise Hold
Time
ns40tCS1
CS Rise to SCLK Rise Hold Time
To ±0.5LSB, from 10mV to full-scale µs18Output Settling Time
DYNAMIC PERFORMANCE
POWER SUPPLIES
TIMING CHARACTERISTICS
MAX5170/MAX5172
Low-Power, Serial, 14-Bit DACs
with Voltage Output
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS—MAX5172
(VDD = +2.7V to +3.6V, VREF = 1.25V, OS = AGND = DGND, RL= 5kΩ, CL= 100pF referenced to ground, TA= TMIN to TMAX, unless
otherwise noted. Typical values are at TA= +25°C).
Bits14Resolution
MAX5172A ±2
VREF = 1.6Vp-p + 0.8VDC, f = 1kHz,
code = all 0s dB
MAX5172B LSB
±4
INLIntegral Nonlinearity (Note 5)
LSB±1DNLDifferential Nonlinearity
mV±10
CONDITIONS
VOS
Offset Error (Note 2)
RL= ∞LSB
-0.6 ±4
GEGain Error RL= 5kΩ-1.6 ±8
-80
µV/V10 120PSRRPower-Supply Rejection Ratio
f = 100kHz LSBp-p2Output Noise Voltage
nV/√Hz
80Output Thermal Noise Density
V0V
DD - 1.4VREF
Reference Input Range
kΩ18RREF
Reference Input Resistance
VREF = 0.5Vp-p + 0.75VDC, slew-rate limited kHz350Reference -3dB Bandwidth
VREF = 0.6Vp-p + 0.9VDC, f = 10kHz,
code = 3FFF hex dB78SINAD
Signal-to-Noise Plus Distortion
Ratio
Reference Feedthrough
V2.2VIH
Input High Voltage
V0.8VIL
Input Low Voltage
mV200VHYS
Input Hysteresis
VIN = 0 or VDD µA0.001 ±1IIN
Input Leakage Current
UNITSMIN TYP MAXSYMBOLPARAMETER
pF8CIN
Input Capacitance
ISOURCE = 2mA VVDD - 0.5VOH
Output High Voltage
ISINK = 2mA V0.13 0.4VOL
Output Low Voltage
STATIC PERFORMANCE
REFERENCE
MULTIPLYING-MODE PERFORMANCE
DIGITAL INPUT
DIGITAL OUTPUT
MAX5170/MAX5172
Low-Power, Serial, 14-Bit DACs
with Voltage Output
_______________________________________________________________________________________ 5
Note 1: INL guaranteed between codes 40 and 16383.
Note 2: Offset is measured at the code that comes closest to 10mV.
Note 3: Accuracy is better than 1.0 LSB for VOUT = 10mV to VDD - 180mV. Guaranteed by PSR test on end points.
Note 4: RL= open and digital inputs are either VDD or DGND.
Note 5: INL guaranteed between codes 80 and 16383.
ELECTRICAL CHARACTERISTICS—MAX5172 (continued)
(VDD = 2.7V to 3.6V, VREF = 1.25V, OS = AGND = DGND, RL= 5kΩ, CL= 100pF referenced to ground, TA= TMIN to TMAX, unless
otherwise noted. Typical values are at TA= +25°C).
µA110Shutdown Current (Note 4)
ns150tCP
SCLK Clock Period
ns75tCH
SCLK Pulse Width High
ns75
CONDITIONS
tCL
SCLK Pulse Width Low
ns60tCSS
CSB Fall to SCLK Rise Setup
Time
ns0tCSH
SCLK Rise to CS Rise Hold
Time
ns60tDS
DIN Setup Time
ns0tDH
DIN Hold Time
CLOAD = 200pF ns200tDO1
SCLK Rise to DOUT Valid
Propagation Delay
ns75tCS1
CS Rise to SCLK Rise Hold Time
CLOAD = 200pF ns200tDO2
SCLK Fall to DOUT Valid
Propagation Delay
To ±0.5LSB from 10mV to full-scale µs18Output Settling Time
ns10tCS0
SCLK Rise to CS Fall Delay
ns150tCSW
CS Pulse Width High
V/µs0.6SRVoltage Output Slew Rate
V0 VDD
Output Voltage Swing (Note 3)
kΩ80 120OS Pin Input Resistance
µs40Time Required to Exit Shutdown
UNITSMIN TYP MAXSYMBOLPARAMETER
CS = VDD, fSCLK = 100kHz, VSCLK = 3Vp-p nV-s1Digital Feedthrough
V2.7 3.6VDD
Positive Supply Voltage
mA0.28 0.4IDD
Power-Supply Current (Note 4)
DYNAMIC PERFORMANCE
POWER SUPPLIES
TIMING CHARACTERISTICS
MAX5170/MAX5172
Low-Power, Serial, 14-Bit DACs
with Voltage Output
6 _______________________________________________________________________________________
Typical Operating Characteristics
(MAX5170: VDD = +5V, VREF = 2.5V; MAX5172: VDD = +3V, VREF = 1.25V; CL = 100pF, OS = AGND, code = 3FFF hex, TA= +25°C,
unless otherwise noted.)
230
260
250
240
270
280
290
300
310
320
330
4.4 4.84.6 5.0 5.2 5.4 5.6
NO-LOAD SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX5170/72 toc01
SUPPLY VOLTAGE (V)
NO-LOAD SUPPLY CURRENT (µA)
268
270
272
274
276
278
280
282
284
286
288
290
-50 -30 -10 10 30 50 70 90
NO-LOAD SUPPLY CURRENT
vs. TEMPERATURE
MAX5170/72 toc02
TEMPERATURE (°C)
NO-LOAD SU0PPLY CURRENT (µA)
0.8
1
0.9
1.2
1.1
1.3
1.4
-50 10 30-30 -10 50 70 90
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX5170/72 toc03
TEMPERATURE (°C)
SHUTDOWN CURRENT (µA)
4.0960
4.0962
4.0966
4.0964
4,0968
4.0970
-50 -10-30 10 30 50 70 90
OUTPUT VOLTAGE vs. TEMPERATURE
MAX5170/72 toc04
TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
VOUT
1V/div
VCS
5V/div
5V
4.096V
10mV
0
DYNAMIC RESPONSE
MAX5170/72 toc07
2µs/div
4.5
0
10 1k 10k100 100k
OUTPUT VOLTAGE vs. LOAD RESISTANCE
0.5
MAX5170/72 TOC05
RL (Ω)
OUTPUT VOLTAGE (V)
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VOUT
1v/div
VCS
5v/div
5V
4.096V
10mV
0
DYNAMIC RESPONSE
MAX5170/72 toc06
2µs/div
10k 100k
-84
-83
-82
-81
-79
-80
-78
-77
-76
-75
10 100 1k
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
MAX5170/72 toc08
FREQUENCY (Hz)
THD + NOISE (dB)
VOUT/VREF
12.5dB/div
20
0
10k
REFERENCE FEEDTHROUGH
MAX5170/72 toc9
FREQUENCY (Hz)
VREF = 1.8VDC + 3.6Vp-p at f = 1kHz
MAX5170
MAX5170/MAX5172
Low-Power, Serial, 14-Bit DACs
with Voltage Output
_______________________________________________________________________________________ 7
VOUT/VREF
12.5dB/div
20
0
100k
FFT PLOT
MAX5170/72 toc10
FREQUENCY (Hz)
VREF = 1.25VDC + 1.13Vp-p, at f = 10kHz
VCS
2V/div
VOUT
100mV/div
MAJOR-CARRY TRANSITION
MAX5170/72 toc11
5µs/div
VOUT
2mV/div
AC-
COUPLED
VSCLK
5V/div
DIGITAL FEEDTHROUGH
MAX5170/72 toc12
400ns/div
-25
-15
-20
-5
-10
0
5
0 1000 1500500 2000 2500 3000
REFERENCE INPUT FREQUENCY RESPONSE
MAX5170/72 toc13
FREQUENCY (kHz)
GAIN (dB)
VREF = 0.67Vp-p + 1.5VDC
VDD
1V/div
VOUT
10mV/div
AC-COUPLED
START-UP GLITCH
MAX5170/72 toc14
50ms/div
MAX5170
MAX5172
260
270
275
280
275
290
285
295
-50 -10 10-30 30 50 70 90
NO-LOAD SUPPLY CURRENT
vs. TEMPERATURE
MAX5170/72 toc16
TEMPERATURE (°C)
NO-LOAD SUPPLY CURRENT (µA)
250
260
255
270
265
280
275
285
295
290
300
2.5 2.7 2.8 2.92.6 3 3.1 3.2 3.43.3 3.5
NO-LOAD SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
NO-LOAD SUPPLY CURRENT (µA)
MAX5170/72 toc15
0.44
0.48
0.46
0.52
0.5
0.58
0.56
0.54
0.60
-50 -10-30 10 30 50 70 90
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX5170/72 toc17
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
Typical Operating Characteristics (continued)
(MAX5170: VDD = +5V, VREF = 2.5V; MAX5172: VDD = +3V, VREF = 1.25V; CL = 100pF, OS = AGND, code = 3FFF hex, TA= +25°C,
unless otherwise noted.)
MAX5170/MAX5172
Low-Power, Serial, 14-Bit DACs
with Voltage Output
8 _______________________________________________________________________________________
2.5
-0.5
10 100 1k 10k 100k
OUTPUT VOLTAGE vs. LOAD RESISTANCE
0
1.0
2.0
MAX5170/72 toc19
RL (Ω)
OUTPUT VOLTAGE (V)
0.5
1.5
VCS
3V/div
3V
10mV
2.048V
0
VOUT
500mV/div
DYNAMIC RESPONSE
MAX5170/72 toc21
2µs/div
-78.0
10 100 1k 10k 100k
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
-81.0
-80.5
-80.0
-79.5
-79.0
-78.5
-81.5
-82.0
MAX5170/72 toc22
FREQUENCY (Hz)
THD + NOISE (dB)
OUT
100mV/div
5µs/div
MAJOR-CARRY TRANSITION
MAX5170/72 toc25
CS
2V/div
AC-COUPLED
VOUT/VREF
12.5dB/div
20
0
10k
REFERENCE FEEDTHROUGH
MAX5170/72 toc23
FREQUENCY (Hz)
VREF = 0.8VDC + 1.6Vp-p at f = 1kHz
FFT PLOT
MAX5170/72 toc24
FREQUENCY (Hz)
VOUT/VREF
12.5dB/div
20
0
100k
VREF = 0.9VDC + 0.424Vp-p
at f = 10kHz
OUT
500µV/div
2µs/div
SCLK
2V/div
DIGITAL FEEDTHROUGH (SCLK, OUT)
MAX5170/72 toc26
AC-COUPLED
2.0480
2.0482
2.0484
2.0488
2.0486
2.0490
-50 -30 -10 10 30 50 70 90
OUTPUT VOLTAGE vs. TEMPERATURE
MAX5170/72 toc18
TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
MAX5172
Typical Operating Characteristics (continued)
(MAX5170: VDD = +5V, VREF = 2.5V; MAX5172: VDD = +3V, VREF = 1.25V; CL = 100pF, OS = AGND, code = 3FFF hex, TA= +25°C,
unless otherwise noted.)
MAX5170/MAX5172
Low-Power, Serial, 14-Bit DACs
with Voltage Output
_______________________________________________________________________________________ 9
-30
-20
-25
-10
-15
0
-5
5
0 1000 1500500 2000 2500 3000
REFERENCE INPUT FREQUENCY RESPONSE
MAX5170/72 toc27
FREQUENCY (kHz)
GAIN (dB)
VREF = 0.67Vp-p + 0.75VDC
VDD
1V/div
VOUT
10mV/div
START-UP GLITCH
MAX5170/72 toc28
50ms/div
AC-COUPLED
MAX5172
9DGND Digital Ground
13 AGND Analog Ground
15 N.C. No Connection
NAME FUNCTION
1OS Offset Adjustment. Connect to AGND for no offset.
16 VDD Positive Supply. Bypass to AGND with a 4.7µF capacitor in parallel with a 0.1µF capacitor.
PIN
14 REF Reference Input. Maximum VREF is VDD - 1.4V.
11 UPO User-Programmable Output. State is set by the serial input.
12 SHDN Shutdown (digital input). Pulling SHDN high when PDL = VDD places the chip in shutdown with a maximum
shutdown current of 10µA.
10 DOUT Serial-Data Output
5CLR Clear DAC (digital input). Clears the DAC to either zero or midscale as determined by RS.
7DIN Serial-Data Input (digital input). Data is clocked in on the rising edge of SCLK.
8SCLK Serial Clock Input (digital input)
6CS Chip Select Input (digital input). DIN ignored when CS is high.
3RS Reset Mode Select (digital input). Connect to VDD to select midscale reset output voltage. Connect to
DGND to select 0 reset output voltage.
4PDL Power-Down Lockout (digital input). Connect to VDD to allow shutdown. Connect to DGND to disable
software and hardware shutdown.
2OUT Voltage Output. High impedance when in shutdown. The output voltage is limited to VDD.
Pin Description
Typical Operating Characteristics (continued)
(MAX5170: VDD = +5V, VREF = 2.5V; MAX5172: VDD = +3V, VREF = 1.25V; CL = 100pF, OS = GND, code = 3FFF hex,
TA= +25°C, unless otherwise noted.)
MAX5170/MAX5172
Low-Power, Serial, 14-Bit DACs
with Voltage Output
10 ______________________________________________________________________________________
Detailed Description
The MAX5170/MAX5172 14-bit, serial, voltage-output
DACs operate with a 3-wire serial interface. These
devices include a 16-bit shift register and a double-
buffered input composed of an input register and a
DAC register (see Functional Diagram). In addition,
these devices employ a rail-to-rail output amplifier and
internally trimmed resistors to provide a gain of
+1.638V/V, maximizing the output voltage swing. The
MAX5170/MAX5172’s offset adjust pin allows for a DC
shift in the DAC output. The DACs are designed with an
inverted R-2R ladder network (Figure 1) which pro-
duces a weighted voltage proportional to the reference
voltage.
Reference Inputs
The reference input accepts both AC and DC values
with a voltage range extending from 0 to VDD - 1.4V.
The following equation represents the resulting output
voltage:
where N is the numeric value of the DAC’s binary input
code (0 to 16383), VREF is the reference voltage, and
Gain is the internal set voltage gain (+1.638V/V if OS =
AGND). The maximum output voltage is VDD. The refer-
ence pin has a minimum impedance of 18kΩand is
code dependent.
Output Amplifier
With OS connected to AGND, the output amplifier
employs an internal, trimmed resistor-divider setting the
gain to +1.638V/V and minimizing gain error. The out-
put amplifier has a typical slew rate of 0.6V/µs and set-
tles to ±0.5LSB from a full-scale transition within 18µs,
when loaded with 5kΩin parallel with 100pF. Loads
less than 2kΩdegrade performance.
For alternative output amplifier setups, refer to the
Applications Information section.
Shutdown Mode
The MAX5170/MAX5172 feature a software- and hard-
ware-programmable shutdown mode that reduces the
typical supply current to 1µA. Enter shutdown by writing
the appropriate input-control word as shown in Table 1
or by using the hardware shutdown. In shutdown mode,
the reference input and the amplifier output become
high-impedance and the serial interface remains active.
Data in the input register is saved, allowing the
MAX5170/MAX5172 to recall the prior output state
when returning to normal operation. Exit shutdown by
reloading the DAC register from the shift register, by
simultaneously loading the input and DAC registers, or
by toggling PDL. When returning from shutdown, wait
40µs for the output to settle.
Power-Down Lockout
Power-Down Lockout disables the software/hardware
shutdown mode. A high-to-low transition brings the
device out of shutdown and returns the output to its
previous state.
Shutdown
Pulling SHDN high while PDL is high places the
MAX5170/MAX5172 in shutdown. Pulling SHDN low will
not return the device to normal operation. A high-to-low
transition on PDL or an appropriate command from the
serial data line (see Table 1 for commands) is required
to exit shutdown.
Serial-Interface
The MAX5170/MAX5172 3-wire serial interface is com-
patible with SPI, QSPI (Figure 2) and MICROWIRE
(Figure 3) interface standards. The 16-bit serial input
word consists of two control bits and 14 bits of data
(MSB to LSB).
The control bits determine the MAX5170/MAX5172’s
operation as outlined in Table 1. The MAX5170/
MAX5172’s digital inputs are double buffered, which
allows any of the following:
• Loading the input register without updating the DAC
register
• Updating the DAC register from the input register
• Updating the input and DAC registers simultaneously.
VV x N x Gain
OUT REF
=
16384
OUT
OS
R
R
SHOWN FOR ALL 1s ON DAC
D0 D10 D11 D12
2R 2R 2R 2R 2R
RRR
REF
AGND
Figure 1. Simplified DAC Circuit Diagram
MAX5170/MAX5172
Low-Power, Serial, 14-Bit DACs
with Voltage Output
______________________________________________________________________________________ 11
The MAX5170/MAX5172 accepts one 16-bit packet or
two 8-bit packets sent while CS remains low. The
MAX5170/MAX5172 allow the following to be config-
ured:
• Clock edge on which serial data output (DOUT) is
clocked out
• State of the user-programmable logic output
• Configuration of the reset state.
Specific commands for setting these are shown in
Table 1.
The general timing diagram in Figure 4 illustrates how
the MAX5170/MAX5172 acquire data. CS must go low
at least tCSS before the rising edge of the serial clock
(SCLK). With CS low, data is clocked into the register
on the rising edge of SCLK. The maximum serial clock
frequency guaranteed for proper operation is 10MHz
for MAX5170 and 6MHz for MAX5172. See Figure 5 for
a detailed timing diagram of the serial interface.
Serial Data Output (DOUT)
The serial-data output, DOUT, is the internal shift regis-
ter’s output and allows for daisy-chaining of multiple
devices as well as data readback (see Applications
Information). By default upon start-up, data shifts out of
DOUT on the serial clock’s rising edge (Mode 0) and
provides a lag of 16 clock cycles, thus maintaining SPI,
QSPI, and MICROWIRE compatibility. However, if the
device is programmed for Mode 1, the output data lags
DIN by 16.5 clock cycles and is clocked out on the ser-
ial clock’s rising edge. During shutdown, DOUT retains
its last digital state prior to shutdown.
Load input register; DAC registers are updated (start-up DAC with new data).10
Load input register; DAC registers are unchanged.00
14-bit DAC data
14-bit DAC data
16-BIT SERIAL WORD
D13..................D0C1 FUNCTION
C0
No operation (NOP).11 0 0 x xxx xxxx xxxx
x x x xxx xxxx xxxx Update DAC register from input register (start-up DAC with data previously
stored in the input registers).
01
UPO goes low (default).11 1 0 0 xxx xxxx xxxx
0 1 x xxx xxxx xxxx
Mode 1, DOUT clocked out on SCLK’s rising edge.11 1 1 0 xxx xxxx xxxx
1 0 1 xxx xxxx xxxx UPO goes high.11
Shut down DAC (provided PDL = 1).
11
Mode 0, DOUT clocked out on SCLK’s falling edge (default).11 1 1 1 xxx xxxx xxxx
SCLK
DIN
CS
MOSI
SCK
+5V
I/O
CPOL = 0, CPHA = 0
SPI/QSPI
PORT
SS
MAX5170
MAX5172
Figure 2. Connections for SPI and QSPI Interface
SCLK
DIN
CS
SK
SO
I/O
MICROWIRE
PORT
MAX5170
MAX5172
Figure 3. Connections for MICROWIRE Interface Standards
Table 1. Serial-Interface Programming Commands
MAX5170/MAX5172
Low-Power, Serial, 14-Bit DACs
with Voltage Output
12 ______________________________________________________________________________________
User-Programmable Logic Output (UPO)
The UPO allows control of an external device through
the serial interface, thereby reducing the number of
microcontroller I/O pins required. During power-down,
this output retains its digital state prior to shutdown.
When CLR is pulled low, UPO resets to its programmed
default state. See Table 1 for specific commands to
control the UPO.
Reset (RS) and Clear (
CLR
)
The MAX5170/MAX5172 offers a clear pin which resets
the output voltage. If RS = DGND, then CLR resets the
output voltage to the minimum voltage (0 if OS =
AGND). If RS = VDD, then CLR resets the output volt-
age to midscale. In either case, CLR resets UPO to its
programmed default state.
CS
SCLK
DIN
COMMAND
EXECUTED
9
816
1
C0
C1 D00
D13 D12 D11 D10 D09 D06 D05 D04 D03 D02 D01D08 D07
Figure 4. Serial-Interface Timing Diagram
CS
SCLK
DIN
DOUT
t
CSW
t
CS1
t
CSH
t
CSS
t
CSO
t
D02
t
CH
t
CL
t
CP
t
D01
t
DS
tDH
Figure 5. Detailed Serial-Interface Timing Diagram
MAX5170/MAX5172
Low-Power, Serial, 14-Bit DACs
with Voltage Output
______________________________________________________________________________________ 13
Applications Information
Unipolar Output
Figure 6 shows the MAX5170/MAX5172 configured for
unipolar, rail-to-rail operation with a gain of +1.638V/V.
Table 2 lists the codes for unipolar output voltages. The
maximum output voltage is limited to VDD. Use the OS pin
to introduce an offset voltage as shown in Figure 7 and
described in the Offset and Buffer Configurations section.
Bipolar Output
Figure 8 shows the MAX5170/MAX5172 configured for
bipolar output operation. The output voltage is given by
the following equation (OS = AGND):
where N represents the numeric value of the DAC’s
binary input code, VREF is the voltage of the external
reference. Table 3 shows digital codes and the corre-
sponding output voltage for Figure 8’s circuit.
VV N
OUT REF
=−
,
2
16 384 1
X
AGNDDGND
MAX5170
MAX5172
DAC
REF
OS
OUT
10k 10k
V-
V+
VDD
VOUT
+5V/+3V
Figure 8. Bipolar Output Circuit
Figure 7. Setting OS for Output Offset
MAX5170
MAX5172
DAC
AGND DGND
REF
OUT
OS
VOS
+5V/+3V
VDD
Table 2. Unipolar Code Table
(Circuit of Figure 6)
MAX5170
MAX5172
DAC
REF
OUT
OS
DGNDAGND
+5V/+3V
VDD
Figure 6. Unipolar Output Circuit (Rail-to-Rail)
Table 3. Bipolar Code Table
(Circuit of Figure 8)
DAC CONTENTS
MSB LSB ANALOG OUTPUT
+VREF [(2 · 16383/16384) - 1]11 1111 1111 1111
10 0000 0000 0001 +VREF [(2 · 8193/16384) - 1]
+VREF [(2 · 8192/16384) - 1]10 0000 0000 0000
01 1111 1111 1111 +VREF [(2 · 8191/16384) - 1]
+VREF [(2 · 1/16384) - 1]00 0000 0000 0001
00 0000 0000 0000 -VREF
ANALOG OUTPUT
+VREF (16383/16384) ·1.638
+VREF (8193/16384) ·1.638
+VREF (8192/16384) ·1.638
+VREF (8191/16384) ·1.638
+VREF (1/16384) ·1.638
000 0000 0000 0000
00 0000 0000 0001
01 1111 1111 1111
10 0000 0000 0000
10 0000 0000 0001
11 1111 1111 1111
DAC CONTENTS
MSB LSB
MAX5170/MAX5172
Low-Power, Serial, 14-Bit DACs
with Voltage Output
14 ______________________________________________________________________________________
Offset and Buffer Configurations
The simple circuit of Figure 7 illustrates how to intro-
duce an offset to the output voltage. The amount of off-
set introduced by a voltage at the OS pin is shown in
the following equation:
VOFFSET = VOS x (1 - Gain)
where Gain = 1.638. However, the total output voltage
of the device cannot exceed VDD regardless of the volt-
age on the OS pin.
To set the gain of the output amplifier to 1, connect OS
to OUT.
Daisy-Chaining Devices
The serial data output pin (DOUT) allows multiple
MAX5170/MAX5172s to be daisy-chained together, as
shown in Figure 9. The advantage of this is that only two
lines are needed to control all the DACs on the line. The
disadvantage is that it takes ncommands to program the
DACs. Figure 10 shows several MAX5170/MAX5172s
sharing one common DIN signal line. In this configura-
tion, the data bus is common to all devices. However,
more I/O lines are required for this configuration because
each device requires a dedicated CS line. The advan-
tage of this configuration is that only one command is
needed to program any DAC.
Using an AC Reference
The MAX5170/MAX5172 accepts reference voltages with
AC components as long as the reference voltage
remains between 0 and VDD - 1.4V. Figure 11 shows a
technique for applying an offset sine wave signal to REF.
The reference voltage must remain above AGND.
Power-Supply and Layout Considerations
Wire-wrap boards are not recommended. For optimum
system performance, use printed circuit boards with
separate analog and digital ground planes. Connect the
two ground planes together at the low-impedance
power-supply source. Connect DGND and AGND pins
together at the IC. The best ground connection is
achieved by connecting the DAC’s DGND and AGND
pins together and connecting that point to the system
analog ground plane. This is useful because if the DAC’s
DGND is connected to the system digital ground, digital
noise may get through to the DAC’s analog portion.
Bypass the power supply with a 4.7µF capacitor in paral-
lel with a 0.1µF capacitor to AGND. Minimize their lead
lengths to reduce inductance. If noise becomes an
issue, use shielding and/or ferrite beads to increase iso-
lation.
To maintain INL and DNL performance as well as gain
drift, it is extremely important to provide the lowest possi-
ble reference output impedance at the DAC reference
input pin. INL degrades if the series resistance on REF
pin exceeds 0.1Ω. The same consideration must be
made for the AGND pin.
TO OTHER
SERIAL DEVICES
MAX5170
MAX5172
DIN
SCLK
CS
MAX5170
MAX5172
MAX5170
MAX5172
DINDOUT DOUT DOUT
SCLK
CS
DIN
SCLK
CS
Figure 9. Daisy-Chaining MAX5170/MAX5172 Devices
MAX5170/MAX5172
Low-Power, Serial, 14-Bit DACs
with Voltage Output
______________________________________________________________________________________ 15
TO OTHER
SERIAL DEVICES
MAX5170
MAX5172
DIN
SCLK
CS
MAX5170
MAX5172
DIN
SCLK
CS
MAX5170
MAX5172
DIN
SCLK
CS
DIN
SCLK
CS1
CS2
CS3
Figure 11. AC Reference Input Circuit
DAC OUT
MAX5170
MAX5172
R2
R1
OS
REF VDD
GNDAGND
+5V/
+3V
AC
REFERENCE
INPUT
500mVp-p
MAX495
+5V/+3V
Figure 10. Multiple MAX5170/MAX5172s Sharing Common DIN and SCLK Lines
Chip Information
TRANSISTOR COUNT: 3457
MAX5170/MAX5172
Low-Power, Serial, 14-Bit DACs
with Voltage Output
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
SHDN
PDL
RS
CLR
SCLKDINCS
MAX5170
MAX5172
SERIAL
CONTROL
16-BIT
SHIFT REGISTER
DECODE
CONTROL
INPUT
REGISTER
DAC
REGISTER
LOGIC
OUTPUT
DAC
DOUT
UPO
OS
OUT
REF
DGNDAGND
VDD
Functional Diagram
QSOP.EPS
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)