1
LTC1148
LTC1148-3.3/LTC1148-5
114835fd
High Efficiency Synchronous
Step-Down Switching Regulators
LOAD CURRENT (A)
0.02
80
EFFICIENCY (%)
85
90
100
0.2 2
LTC1148 • TA01
95
V
IN
= 6V
V
IN
= 10V
LTC1148-5 Efficiency
■
Ultrahigh Efficiency: Over 95% Possible
■
Current-Mode Operation for Excellent Line and Load
Transient Response
■
High Efficiency Maintained Over Three Decades of
Output Current
■
Low 160µA Standby Current at Light Loads
■
Logic Controlled Micropower Shutdown: I
Q
< 20µA
■
Wide V
IN
Range: 3.5V* to 20V
■
Short-Circuit Protection
■
Very Low Dropout Operation: 100% Duty Cycle
■
Synchronous FET Switching for High Efficiency
■
Adaptive Nonoverlap Gate Drives
■
Output Can Be Externally Held High in Shutdown
■
Available in 14-Pin Narrow SO Package
The LTC
®
1148 series is a family of synchronous step-
down switching regulator controllers featuring automatic
Burst Mode
TM
operation to maintain high efficiencies at
low output currents. These devices drive external comple-
mentary power MOSFETs at switching frequencies up to
250kHz using a constant off-time current-mode architec-
ture providing constant ripple current in the inductor.
The operating current level is user-programmable via an
external current sense resistor. Wide input supply range
allows operation from 3.5V* to 18V (20V maximum).
Constant off-time architecture provides low dropout regu-
lation limited by only the R
DS(ON)
of the external MOSFET
and resistance of the inductor and current sense resistor.
The LTC1148 series combines synchronous switching for
maximum efficiency at high currents with an automatic low
current operating mode, called Burst Mode
operation, which
reduces switching losses. Standby power is reduced to only
2mW at V
IN
= 10V (at I
OUT
= 0). Load currents in Burst Mode
operation are typically 0mA to 300mA.
For operation up to 48V input, see the LTC1149 and
LTC1159 data sheets and Application Note 54.
Figure 1. High Efficiency Step-Down Converter
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode
is a trademark of Linear Technology Corporation.
* LTC1148L and LTC1148L-3.3 only.
Protected by U.S. Patents, including 6580258, 5481178.
■
Notebook and Palmtop Computers
■
Portable Instruments
■
Battery-Operated Digital Devices
■
Cellular Telephones
■
DC Power Distribution Systems
■
GPS Systems
0V = NORMAL
>1.5V = SHUTDOWN
P-CHANNEL
Si4431DY
+
1µF
L*
62µH
R
SENSE
**
0.05ΩV
OUT
5V/2A
+C
IN
100µF
V
IN
(5.2V TO 18V)
I
TH
C
T
SGND
C
T
470pF
C
C
3300pF
R
C
1k
+C
OUT
390µF
D1
MBRS140T3
LT1148 • TA01
N-DRIVE
PGND
N-CHANNEL
Si4412DY
V
IN
P-DRIVE
LTC1148HV-5
SHUTDOWN
SENSE
+
SENSE
–
1000pF
COILTRONICS CTX62-2-MP
KRL SL-1-C1-0R050J
*
**
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATIO
U
2
LTC1148
LTC1148-3.3/LTC1148-5
114835fd
A
U
G
W
A
W
U
W
ARBSOLUTEXI T
IS
ORDER PART
NUMBER
LTC1148CN
LTC1148HVCN
LTC1148CN-3.3
LTC1148HVCN-3.3
LTC1148CN-5
LTC1148HVCN-5
LTC1148CS
LTC1148HVCS
LTC1148LCS
LTC1148CS-3.3
LTC1148HVCS-3.3
LTC1148LCS-3.3
LTC1148CS-5
LTC1148HVCS-5
LTC1148HVIS-5
WU
U
PACKAGE/ORDER I FOR ATIO
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
9
Feedback Voltage (LTC1148, LTC1148L, V
IN
= 9V ●1.21 1.25 1.29 V
LTC1148HV)
I
9
Feedback Current (LTC1148, LTC1148L, ●0.2 1 µA
LTC1148HV)
V
OUT
Regulated Output Voltage V
IN
= 9V
LTC1148-3.3, LTC1148HV-3.3, LTC1148L-3.3 I
LOAD
= 700mA ●3.23 3.33 3.43 V
LTC1148-5, LTC1148HV-5 I
LOAD
= 700mA ●4.90 5.05 5.20 V
∆V
OUT
Output Voltage Line Regulation V
IN
= 7V to 12V, I
LOAD
= 50mA – 40 0 40 mV
Output Voltage Load Regulation
LTC1148-3.3, LTC1148HV-3.3, LTC1148L-3.3 5mA < I
LOAD
< 2A ●40 65 mV
LTC1148-5, LTC1148HV-5 5mA < I
LOAD
< 2A ●60 100 mV
Output Ripple (Burst Mode) I
LOAD
= 0A 50 mV
P-P
I
Q
Input DC Supply Current (Note 3) (Note 7)
LTC1148 Series
Normal Mode 4V < V
IN
< 12V 1.6 2.1 mA
Sleep Mode 4V < V
IN
< 12V 160 230 µA
Sleep Mode (LTC1148-5) 6V < V
IN
< 12V 160 230 µA
Shutdown V
SHUTDOWN
= 2.1V, 4V < V
IN
< 12V 10 20 µA
LTC1148HV Series
Normal Mode 4V < V
IN
< 18V 1.6 2.3 mA
Sleep Mode 4V < V
IN
< 18V 160 250 µA
Sleep Mode (LTC1148HV-5) 6V < V
IN
< 18V 160 250 µA
Shutdown V
SHUTDOWN
= 2.1V, 4V < V
IN
< 18V 10 22 µA
LTC1148L Series
Normal Mode 3.5V < V
IN
< 12V 1.6 2.1 mA
Sleep Mode 3.5V < V
IN
< 12V 160 230 µA
Shutdown V
SHUTDOWN
= 2.1V, 3.5V < V
IN
< 12V 10 20 µA
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 10V, VSHUTDOWN = 0V unless otherwise noted.
ELECTRICAL C CHARA TERISTICS
1
2
3
4
5
6
7
TOP VIEW
S PACKAGE
14-LEAD PLASTIC SO
N PACKAGE
14-LEAD PDIP
14
13
12
11
10
9
8
P-DRIVE
NC
V
IN
C
T
INTV
CC
I
TH
SENSE
–
N-DRIVE
NC
PGND
SGND
SHUTDOWN
V
FB
*
SENSE
+
*FIXED OUTPUT VERSIONS = NC
T
JMAX
= 125°C,
θ
JA
= 70°C/ W (N)
T
JMAX
= 125°C,
θ
JA
= 110°C/ W (S)
(Note 1)
Input Supply Voltage (Pin 3)
LTC1148 and LTC1148L Series ............ 16V to –0.3V
LTC1148HV Series ............................... 20V to – 0.3V
Continuous Output Current (Pins 1, 14) .............. 50mA
Sense Voltages (Pins 7, 8)
LTC1148HV (Adjustable Only)
V
IN
≥ 12.7V ...................................... 13V to – 0.3V
V
IN
< 12.7V ......................... (V
IN
+ 0.3V) to –0.3V
Operating Ambient Temperature Range ...... 0°C to 70°C
Extended Commercial and Industrial
Temperature Range ............................... – 40°C to 85°C
Junction Temperature (Note 2)............................ 125°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
3
LTC1148
LTC1148-3.3/LTC1148-5
114835fd
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
8
– V
7
Current Sense Threshold Voltage
LTC1148, LTC1148HV, LTC1148L V
SENSE –
= 5V, V
9
= V
OUT
/4 + 25mV (Forced) 25 mV
V
SENSE –
= 5V, V
9
= V
OUT
/4 – 25mV (Forced) ●130 150 170 mV
LTC1148-3.3, LTC1148HV-3.3 V
SENSE –
= V
OUT
+ 100mV (Forced) 25 mV
LTC1148L-3.3 V
SENSE –
= V
OUT
– 100mV (Forced) ●130 150 170 mV
LTC1148-5, LTC1148HV-5 V
SENSE –
= V
OUT
+ 100mV (Forced) 25 mV
V
SENSE –
= V
OUT
– 100mV (Forced) ●130 150 170 mV
V
10
Shutdown Pin Threshold 0.5 0.8 2 V
I
10
Shutdown Pin Input Current 0V < V
SHUTDOWN
< 8V, V
IN
= 16V 1.2 5 µA
I
4
C
T
Pin Discharge Current V
OUT
in Regulation, V
SENSE –
= V
OUT
50 70 90 µA
V
OUT
= 0V 2 10 µA
t
OFF
Off Time (Note 5) C
T
= 390pF, I
LOAD
= 700mA 4 5 6 µs
t
R
, t
F
Driver Output Transition Times C
L
= 3000pF (Pins 1, 14), V
IN
= 6V 100 200 ns
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
9
Feedback Voltage (LTC1148, LTC1148HV V
IN
= 9V 1.20 1.25 1.30 V
LTC1148L)
∆V
OUT
Regulated Output Voltage V
IN
= 9V
LTC1148-3.3, LTC1148HV-3.3, LTC1148L-3.3 I
LOAD
= 700mA 3.17 3.33 3.43 V
LTC1148-5, LTC1148HV-5 I
LOAD
= 700mA 4.85 5.05 5.20 V
I
Q
Input DC Supply Current (Note 3) (Note 7)
LTC1148 Series
Normal Mode 4V < V
IN
< 12V 1.6 2.4 mA
Sleep Mode 4V < V
IN
< 12V 160 260 µA
Sleep Mode 6V < V
IN
< 12V 160 260 µA
Shutdown V
SHUTDOWN
= 2.1V, 4V < V
IN
< 12V 10 22 µA
LTC1148HV Series
Normal Mode 4V < V
IN
< 18V 1.6 2.6 mA
Sleep Mode 4V < V
IN
< 18V 160 280 µA
Sleep Mode 6V < V
IN
< 18V 160 280 µA
Shutdown V
SHUTDOWN
= 2.1V, 4V < V
IN
< 18V 10 24 µA
LTC1148L Series
Normal Mode 3.5V < V
IN
< 12V 1.6 2.4 mA
Sleep Mode 3.5V < V
IN
< 12V 160 260 µA
Shutdown V
SHUTDOWN
= 2.1V, 3.5V < V
IN
< 12V 10 22 µA
V
8
– V
7
Current Sense Threshold Voltage
LTC1148, LTC1148HV, LTC1148L (Note 4) V
SENSE –
= 5V, V
9
= V
OUT
/4 – 25mV (Forced) 25 mV
V
SENSE –
= 5V, V
9
= V
OUT
/4 + 25mV (Forced) 125 150 175 mV
LTC1148-3.3, LTC1148HV-3.3, LTC1148L-3.3 V
SENSE –
= V
OUT
+ 100mV (Forced) 25 mV
V
SENSE –
= V
OUT
– 100mV (Forced) 125 150 175 mV
LTC1148-5, LTC1148HV-5 V
SENSE –
= V
OUT
+ 100mV (Forced) 25 mV
V
SENSE –
= V
OUT
– 100mV (Forced) 125 150 175 mV
V
10
Shutdown Pin Threshold 0.55 0.8 2 V
t
OFF
Off Time (Note 5) C
T
= 390pF, I
LOAD
= 700mA 3.8 5 6 µs
–40°C ≤ TA ≤ 85°C (Note 5), VIN = 10V, unless otherwise noted.
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 10V, VSHUTDOWN = 0V unless otherwise noted.
ELECTRICAL C CHARA TERISTICS
4
LTC1148
LTC1148-3.3/LTC1148-5
114835fd
ELECTRICAL C CHARA TERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: T
J
is calculated from the ambient temperature T
A
and power
dissipation P
D
according to the following formulas:
LTC1148CN, LTC1148CN-3.3, LTC1148CN-5: T
J
= T
A
+ (P
D
× 70°C/W)
LTC1148CS, LTC1148CS-3.3, LTC1148CS-5: T
J
= T
A
+ (P
D
× 110°C/W)
Note 3: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note 4: The LTC1148 and LTC1148HV versions are tested with external
feedback resistors resulting in a nominal output voltage of 5V. The
LTC1148L version is tested with external feedback resistors resulting in a
nominal output voltage of 2.5V.
Note 5: In applications where R
SENSE
is placed at ground potential, the off
time increases approximately 40%.
Note 6: The LTC1148, LTC1148HV and LTC1148L series are not tested
and not quality assurance sampled at –40°C and 85°C. These
specifications are guaranteed by design and/or correlation. The
LTC1148HVI-5 is guaranteed over the full –40°C to 85°C operating
temperature range.
Note 7: The LTC1148L and LTC1148L-3.3 allow operation to V
IN
= 3.5V.
CCHARA TERISTICS
UW
ATYPICALPER
FORCE
Line RegulationEfficiency vs Input Voltage
LOAD CURRENT (A)
0
–100
∆VOUT (mV)
–80
–60
–40
–20
0
20
0.5 1 1.5 2
LTC1148 • TPC03
2.5
FIGURE 1 CIRCUIT
RSENSE = 0.05Ω
VIN = 6V
VIN = 12V
INPUT VOLTAGE (V)
0
80
EFFICIENCY (%)
82
86
88
90
100
94
48
LTC1148 • TPC01
84
96
98
92
12 16 20
I
LOAD
= 100mA
FIGURE 1 CIRCUIT
I
LOAD
= 1A
DC Supply Current Supply Current in Shutdown
Load Regulation
Operating Frequency
vs (VIN – VOUT)
(V
IN
– V
OUT
) VOLTAGE (V)
0
NORMALIZED FREQUENCY
0.6
1.0
8
LTC1148 • TPC06
0.4
0246
0.2
1.2
0.8
10 12
1.4
1.6
V
OUT
= 5V
0°C
70°C
25°C
INPUT VOLTAGE
0
0
SUPPLY CURRENT (mA)
0.3
0.9
1.2
1.5
4
LTC1148 • TPC04
0.6
26
1.8
2.1
8 10 12 14 16 18
SLEEP MODE
ACTIVE MODE
NOT INCLUDING
GATE CHARGE CURRENT
20
INPUT VOLTAGE (V)
0
0
SUPPLY CURRENT (µA)
2
6
8
10
20
14
4810 18
LTC1148 • TPC05
4
16
18
12
26 12 14 16
V
SHUTDOWN
= 2V
20
INPUT VOLTAGE (V)
0
∆V
OUT
(mV)
0
10
20
16
LTC1148 • TPC02
–10
–20
–40
4812
–30
40
30
FIGURE 1 CIRCUIT
I
LOAD
= 1A
20
5
LTC1148
LTC1148-3.3/LTC1148-5
114835fd
CCHARA TERISTICS
UW
ATYPICALPER
FORCE
Current Sense Threshold Voltage
TEMPERATURE (°C)
0
0
SENSE VOLTAGE (mV)
25
50
75
175
125
20 40
150
100
60 80 100
MAXIMUM
THRESHOLD
MINIMUM
THRESHOLD
LTC1148 • TPC09
Off Time vs VOUT
OUTPUT VOLTAGE (V)
0
OFF TIME (µs)
40
50
60
4
LTC1148 • TPC08
30
20
0123
10
80
70
5
LTC1148-5
LTC1148-3.3
VSENSE– = VOUT
Gate Charge Supply Current
OPERATING FREQUENCY (kHz)
20
0
GATE CHARGE CURRENT (mA)
4
8
12
28
20
80 140
24
16
200 260
Q
N
+ Q
P
= 100nC
Q
N
+ Q
P
= 50nC
LTC1148 • TPC07
P-DRIVE (Pin 1): High Current Drive for Top P-Channel
MOSFET. Voltage swing at this pin is from V
IN
to ground.
NC (Pin 2): No Connection. Can connect to power ground.
V
IN
(Pin 3): Main Supply Pin. Must be closely decoupled
to power ground Pin 12.
C
T
(Pin 4): External capacitor C
T
from Pin 4 to ground sets
the operating frequency. The actual frequency is also
dependent upon the input voltage.
INTV
CC
(Pin 5): Internal Supply Voltage, Nominally 3.3V.
Can be decoupled to signal ground. Do not externally load
this pin.
I
TH
(Pin 6): Gain Amplifier Decoupling Point. The current
comparator threshold increases with the Pin 6 voltage.
SENSE
–
(Pin 7): Connects to internal resistive divider
which sets the output voltage in LTC1148-3.3 and
LTC1148-5 versions. Pin 7 is also the (–) input for the
current comparator.
SENSE
+
(Pin 8): The (+) Input to the Current Comparator.
A built-in offset between Pins 7 and 8 in conjunction with
R
SENSE
sets the current trip threshold.
V
FB
(Pin 9): For the LTC1148 adjustable version, Pin 9
serves as the feedback pin from an external resistive
divider used to set the output voltage. On LTC1148-3.3
and LTC1148-5 versions this pin is not used.
SHUTDOWN (Pin 10): When grounded, the LTC1148
series operates normally. Pulling Pin 10 high holds both
MOSFETs off and puts the LTC1148 series in micropower
shutdown mode. Requires CMOS logic signal with t
R
,
t
F
< 1µs, should not be left floating.
SGND (Pin 11): Small-Signal Ground. Must be routed
separately from other grounds to the (–) terminal of C
OUT
.
PGND (Pin 12): Driver Power Ground. Connects to source
of N-channel MOSFET and the (–) terminal of C
IN
.
NC (Pin 13): No Connection. Can connect to power ground.
N-DRIVE (Pin 14): High Current Drive for Bottom
N-Channel MOSFET. Voltage swing at Pin 14 is from
ground to V
IN
.
PI FU CTIO S
U
UU
6
LTC1148
LTC1148-3.3/LTC1148-5
114835fd
+
–
1 P-DRIVE
14
3V
IN
12 PGND
N-DRIVE
R
S
Q
–
+
C25mV TO 150mV
6
13k
ITH
1.25V
10 5
REFERENCE
–
+
SHUTDOWN INTVCC
VOS
–
+
V
G
8
SENSE+
9
ADJUSTABLE
VERSION
VFB
100k
5pF
–
+
VTH1
T
–
+
VTH2
S
SLEEP
11
SGND
4
CT
OFF-TIME
CONTROL
VIN
SENSE–
VFB
SENSE–
7
LTC1148 • FD
FU CTIO AL DIAGRA
UUW
Pin 9 connection shown for LTC1148-3.3 and LTC1148-5; changes create LTC1148.
TEST CIRCUIT
+
1
2
3
4
5
6
7
14
13
12
11
10
9
8
P-DRIVE
NC
V
IN
C
T
INTV
CC
I
TH
SENSE
–
N-DRIVE
NC
PGND
SGND
SHUTDOWN
NC (V
FB)
SENSE
+
1000pF V
7
TO
V
8
+
V
10
R
SENSE
0.05Ω75k
25k 100pF
+
V
OUT
440µF
50µH
1µF
IRFZ34
1N5818 330µF
+
IRF9Z34
+
V
IN
+
V
7
1k
3300pF10nF390pF
LTC1148
+
7
LTC1148
LTC1148-3.3/LTC1148-5
114835fd
OPERATIO
U
The LTC1148 series uses a current mode, constant off-
time architecture to synchronously switch an external
pair of complementary power MOSFETs. Operating fre-
quency is set by an external capacitor at the timing
capacitor Pin 4.
The output voltage is sensed by an internal voltage
divider connected to SENSE– Pin 7 (LTC1148-3.3 and
LTC1148-5) or external divider returned to VFB Pin 9
(LTC1148). A voltage comparator V, and a gain block G,
compare the divided output voltage with a reference
voltage of 1.25V. To optimize efficiency, the LTC1148
series automatically switches between two modes of
operation, burst and continuous. The voltage compara-
tor is the primary control element when the device is in
Burst Mode
operation, while the gain block controls the
output voltage in continuous mode.
During the switch “ON” cycle in continuous mode, current
comparator C monitors the voltage between Pins 7 and 8
connected across an external shunt in series with the
inductor. When the voltage across the shunt reaches its
threshold value, the P-drive output is switched to V
IN
,
turning off the P-channel MOSFET. The timing capacitor
connected to Pin 4 is now allowed to discharge at a rate
determined by the off-time controller. The discharge cur-
rent is made proportional to the output voltage (measured
by Pin 7) to model the inductor current, which decays at
a rate which is also proportional to the output voltage.
While the timing capacitor is discharging, the N-drive
output goes to V
IN
, turning on the N-channel MOSFET.
When the voltage on the timing capacitor has discharged
past V
TH1
, comparator T trips, setting the flip-
flop. This
causes the N-drive output to go low (turning off the N-
channel MOSFET) and the P-drive output to also go low
(turning the P-channel MOSFET back on). The cycle
then repeats.
As the load current increases, the output voltage de-
creases slightly. This causes the output of the gain stage
(Pin 6) to increase the current comparator threshold, thus
tracking the load current.
The sequence of events for Burst Mode
operation is very
similar to continuous operation with the cycle interrupted
by the voltage comparator. When the output voltage is at
or above the desired regulated value, the P-channel MOSFET
is held off by comparator V and the timing capacitor
continues to discharge below V
TH1
. When the timing
capacitor discharges past V
TH2
, voltage comparator S
trips, causing the internal sleep line to go low and the N-
channel MOSFET to turn off.
The circuit now enters sleep mode with both power
MOSFETs turned off. In sleep mode, a majority of the
circuitry is turned off, dropping the quiescent current
from 1.6mA to 160µA. The load current is now being
supplied from the output capacitor. When the output
voltage has dropped by the amount of hysteresis in
comparator V, the P-channel MOSFET is again turned on
and the process repeats.
To avoid the operation of the current loop interfering with
Burst Mode
operation, a built-in offset (V
OS
) is incorpo-
rated in the gain stage. This prevents the current compara-
tor threshold from increasing until the output voltage has
dropped below a minimum threshold.
To prevent both the external MOSFETs from ever being
turned on at the same time, feedback is incorporated to
sense the state of the driver output pins. Before the
N-drive output can go high, the P-drive output must also
be high. Likewise, the P-drive output is prevented from
going low while the N-drive output is high.
Using constant off-time architecture, the operating fre-
quency is a function of the input voltage. To minimize the
frequency variation as dropout is approached, the off-time
controller increases the discharge current as V
IN
drops
below V
OUT
+ 1.5V. In dropout the P-channel MOSFET is
turned on continuously (100% duty cycle), providing
extremely low dropout operation.
8
LTC1148
LTC1148-3.3/LTC1148-5
114835fd
APPLICATIO S I FOR ATIO
WUU U
The basic LTC1148 series application circuit (fixed
output versions) is shown in Figure 1. External compo-
nent selection is driven by the load requirement, and
begins with the selection of RSENSE. Once RSENSE is
known, CT and L can be chosen. Next, the power
MOSFETs and D1 are selected. Finally, CIN and COUT are
selected and the loop is compensated. The circuit
shown in Figure 1 can be configured for operation up to
an input voltage of 20V. If the application requires
higher input voltage, then the LTC1149 or LTC1159
should be used.
R
SENSE
Selection for Output Current
R
SENSE
is chosen based on the required output current.
The LTC1148 series current comparator has a threshold
range which extends from a minimum of 25mV/R
SENSE
to
a maximum of 150mV/R
SENSE
. The current comparator
threshold sets the peak of the inductor ripple current,
yielding a maximum output current I
MAX
equal to the peak
value less half the peak-to-peak ripple current. For proper
Burst Mode
operation, I
RIPPLE(P-P)
must be less than or
equal to the minimum current comparator threshold.
Since efficiency generally increases with ripple current,
the maximum allowable ripple current is assumed, i.e.,
IRIPPLE(P-P) = 25mV/RSENSE (See CT and L Selection for
Operating Frequency). Solving for RSENSE and allowing
a margin for variations in the LTC1148 series and
external component values yields:
RSENSE = 100mV
IMAX
A graph for selecting RSENSE versus maximum output
current is given in Figure 2.
The load current below which Burst Mode
operation com-
mences (I
BURST
) and the peak short-circuit current (I
SC(PK)
)
both track I
MAX
. Once R
SENSE
has been chosen, I
BURST
and
I
SC(PK)
can be predicted from the following:
IBURST ≈ 15mV
RSENSE
ISC(PK) = 150mV
RSENSE
Figure 2. Selecting RSENSE
MAXIMUM OUTPUT CURRENT (A)
0
RSENSE (Ω)
0.15
0.20
4
LTC1148 • F02
0.10
0.05
01235
The LTC1148 series automatically extends t
OFF
during a
short circuit to allow sufficient time for the inductor
current to decay between switch cycles. The resulting
ripple current causes the average short-circuit current
I
SC(AVG)
to be reduced to approximately I
MAX
.
L and C
T
Selection for Operating Frequency
The LTC1148 series uses a constant off-time architecture
with t
OFF
determined by an external timing capacitor C
T
.
Each time the P-channel MOSFET switch turns on, the
voltage on C
T
is reset to approximately 3.3V. During the off
time, C
T
is discharged by a current which is proportional
to V
OUT
. The voltage on C
T
is analogous to the current in
inductor L, which likewise decays at a rate proportional to
V
OUT
. Thus the inductor value must track the timing
capacitor value.
The value of C
T
is calculated from the desired continuous
mode operating frequency, f:
CT = 1
2.6(104)f
Assumes V
IN
= 2V
OUT
, Figure 1 circuit.
A graph for selecting C
T
versus frequency including the
effects of input voltage is given in Figure 3.
As the operating frequency is increased the gate charge
losses will be higher, reducing efficiency (see Efficiency
Considerations). The complete expression for operating
frequency of the circuit in Figure 1 is given by:
9
LTC1148
LTC1148-3.3/LTC1148-5
114835fd
APPLICATIO S I FOR ATIO
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Inductor Core Selection
Once the minimum value for L is known, the type of
inductor must be selected. The highest efficiency will be
obtained using ferrite, Kool Mµ
®
on molypermalloy (MPP)
cores. Lower cost powdered iron cores provide suitable
performance but cut efficiency by 3% to 7%. Actual core
loss is independent of core size for a fixed inductor value,
but it is very dependent on inductance selected. As induc-
tance increases, core losses go down. Unfortunately,
increased inductance requires more turns of wire and
therefore copper losses increase.
Ferrite designs have very low core loss, so design goals
can concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design cur-
rent is exceeded. This results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple which can cause Burst Mode
operation to be falsely
triggered. Do not allow the core to saturate!
Kool Mµ (from Magnetics, Inc.) is a very good, low loss
core material for toroids, with a “soft” saturation charac-
teristic. Molypermalloy is slightly more efficient at high
(>200kHz) switching frequencies, but quite a bit more
expensive. Toroids are very space efficient, especially
when you can use several layers of wire. Because they
generally lack a bobbin, mounting is more difficult. How-
ever, new designs for surface mount are available from
Coiltronics and Beckman Industrial Corp. which do not
increase the height significantly.
Power MOSFET and D1 Selection
Two external power MOSFETs must be selected for use
with the LTC1148 series: a P-channel MOSFET for the
main switch, and an N-channel MOSFET for the synchro-
nous switch. The main selection criteria for the power
MOSFETs are the threshold voltage V
GS(TH)
and on resis-
tance R
DS(ON)
.
The minimum input voltage determines whether standard
threshold or logic-level threshold MOSFETs must be used.
For V
IN
> 8V, standard threshold MOSFETs (V
GS(TH)
< 4V)
may be used. If V
IN
is expected to drop below 8V, logic-
FREQUENCY (kHz)
0
0
CAPACITANCE (pF)
200
400
600
100 200
LTC1148 • F03
800
1000
300
V
SENSE–
= V
OUT
= 5V
V
IN
= 12V
V
IN
= 10V
V
IN
= 7V
Figure 3. Timing Capacitor Value
f = 1
t
OFF
)
)
1 – V
OUT
V
IN
where:
tOFF = 1.3(104)CT
)
)
VREG
VOUT
V
REG
is the desired output voltage (i.e., 5V, 3.3V). V
OUT
is
the measured output voltage. Thus V
REG
/V
OUT
= 1 in
regulation.
Note that as VIN decreases, the frequency decreases.
When the input to output voltage differential drops
below 1.5V, the LTC1148 series reduces tOFF by in-
creasing the discharge current in CT. This prevents
audible operation prior to dropout.
Once the frequency has been set by CT, the inductor L
must be chosen to provide no more than 25mV/RSENSE
of peak-to-peak inductor ripple current. This results in
a minimum required inductor value of:
LMIN = 5.1(105)RSENSE(CT)VREG
As the inductor value is increased from the minimum
value, the ESR requirements for the output capacitor
are eased at the expense of efficiency. If too small an
inductor is used, the inductor current will decrease past
zero and change polarity.
A consequence of this is that
the LTC1148 series may not enter Burst Mode
operation
and efficiency will be severely degraded at low currents.
Kool Mµ
is a registered trademark of Magnetics, Inc.
10
LTC1148
LTC1148-3.3/LTC1148-5
114835fd
APPLICATIO S I FOR ATIO
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level threshold MOSFETs (V
GS(TH)
< 2.5V) are strongly
recommended. The LTC1148/LTC1148HV series supply
voltage must always be less than the absolute maximum
V
GS
ratings for the MOSFETs.
The maximum output current I
MAX
determines the R
DS(ON)
requirement for the two MOSFETs. When the LTC1148
series is operating in continuous mode, the simplifying
assumption can be made that one of the two MOSFETs is
always conducting the average load current. The duty
cycles for the two MOSFETs are given by:
P-Ch Duty Cycle = VOUT
VIN
N-Ch Duty Cycle = (VIN – VOUT)
VIN
From the duty cycles the required R
DS(ON)
for each MOS-
FET can be derived:
P-Ch RDS(ON) = VIN(PP)
VOUT(IMAX2)(1 + δP)
N-Ch RDS(ON) = VIN(PN)
(VIN – VOUT)(IMAX2)(1 + δN)
where P
P
and P
N
are the allowable power dissipations and
d
P
and d
N
are the temperature dependencies of R
DS(ON)
.
P
P
and P
N
will be determined by efficiency and/or thermal
requirements (see Efficiency Considerations). (1 + d) is
generally given for a MOSFET in the form of a normalized
R
DS(ON)
vs temperature curve, but d = 0.007/°C can be
used as an approximation for low voltage MOSFETs.
The Schottky diode D1 shown in Figure 1 only conducts
during the dead-time between the conduction of the two
power MOSFETs. D1’s sole purpose in life is to prevent the
body diode of the N-channel MOSFET from turning on and
storing charge during the dead time, which could cost as
much as 1% in efficiency (although there are no other
harmful effects if D1 is omitted). Therefore, D1 should be
selected for a forward voltage of less than 0.7V when
conducting I
MAX
.
C
IN
and C
OUT
Selection
In continuous mode, the source of the P-channel MOSFET
is a square wave of duty cycle V
OUT
/V
IN
. To prevent large
voltage transients, a low ESR input capacitor sized for the
maximum RMS current must be used. The maximum
RMS capacitor current is given by:
C
IN
Required I
RMS
≈ I
MAX
[V
OUT
(V
IN
–
V
OUT
)]
1/2
V
IN
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT/2. This simple worst-case condition is com-
monly used for design because even significant devia-
tions do not offer much relief. Note that capacitor
manufacturer’s ripple current ratings are often based on
only 2000 hours of life. This makes it advisable to further
derate the capacitor, or to choose a capacitor rated at a
higher temperature than required. Always consult the
manufacturer if there is any question. An additional 0.1µF
to 1µF ceramic capacitor is also required on VIN Pin 3 for
high frequency decoupling.
The selection of C
OUT
is driven by the required effective
series resistance (ESR).
The ESR of C
OUT
must be less
than twice the value of R
SENSE
for proper operation of the
LTC1148 series:
C
OUT
Required ESR < 2R
SENSE
Optimum efficiency is obtained by making the ESR equal
to R
SENSE
. As the ESR is increased up to 2R
SENSE
, the
efficiency degrades by less than 1%. If the ESR is greater
than 2R
SENSE
, the voltage ripple on the output capacitor
will prematurely trigger Burst Mode
operation, resulting in
disruption of continuous mode and an efficiency hit which
can be several percent.
Manufacturers such as Nichicon and United Chemicon
should be considered for high performance capacitors.
The OS-CON semiconductor dielectric capacitor available
from Sanyo has the lowest ESR/size ratio of any aluminum
electrolytic at a somewhat higher price. Once the ESR
requirement for C
OUT
has been met, the RMS current
rating generally far exceeds the I
RIPPLE(P-P)
requirement.
11
LTC1148
LTC1148-3.3/LTC1148-5
114835fd
APPLICATIO S I FOR ATIO
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In surface mount applications multiple capacitors may
have to be paralleled to meet the capacitance, ESR, or
RMS current handling requirements of the application.
Aluminum electrolytic and dry tantalum capacitors are
both available in surface mount configurations. In the
case of tantalum, it is critical that the capacitors are surge
tested for use in switching power supplies. An excellent
choice is the AVX TPS series of surface mount tantalums,
available in case heights ranging from 2mm to 4mm. For
example, if 200µF/10V is called for in an application
requiring 3mm height, two AVX 100µF/10V (P/N TPSD
107K010) could be used. Consult the manufacturer for
other specific recommendations.
At low supply voltages, a minimum capacitance at COUT
is needed to prevent an abnormal low frequency oper-
ating mode (see Figure 4). When COUT is made too
small, the output ripple at low frequencies will be large
enough to trip the voltage comparator. This causes
Burst Mode
operation to be activated when the LTC1148
series would normally be in continuous operation. The
effect is most pronounced with low values of RSENSE
and can be improved by operating at higher frequencies
with lower values of L. The output remains in regulation
at all times.
several cycles to respond to a step in DC (resistive) load
current. When a load step occurs, VOUT shifts by an
amount equal to ∆ILOAD • ESR, where ESR is the effective
series resistance of COUT. ∆ILOAD also begins to charge
or discharge COUT until the regulator loop adapts to the
current change and returns VOUT to its steady state
value. During this recovery time VOUT can be monitored
for overshoot or ringing which would indicate a stability
problem. The Pin 6 external components shown in the
Figure 1 circuit will prove adequate compensation for
most applications.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately 25
•
C
LOAD
.
Thus a 10µF capacitor would require a 250µs rise time,
limiting the charging current to about 200mA.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc., are the individual losses as a percent-
age of input power. (For high efficiency circuits only small
errors are incurred by expressing losses as a percentage
of output power).
Although all dissipative elements in the circuit produce
losses, three main sources usually account for most of the
losses in LTC1148 series circuits: 1) LTC1148 DC bias
current, 2) MOSFET gate charge current, and 3) I
2
R
losses.
1. The DC supply current is the current which flows into
V
IN
Pin 3 less the gate charge current. For V
IN
= 10V the
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
(VIN – VOUT) VOLTAGE (V)
0
COUT (µF)
600
1000
4
LTC1148 • F04
400
200
01235
800
L = 50µH
RSENSE = 0.02Ω
L = 25µH
RSENSE = 0.02Ω
L = 50µH
RSENSE = 0.05Ω
Figure 4. Minimum Value of COUT
12
LTC1148
LTC1148-3.3/LTC1148-5
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APPLICATIO S I FOR ATIO
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LTC1148 DC supply current is 160µA for no load, and
increases proportionally with load up to a constant
1.6mA after the LTC1148 series has entered continu-
ous mode. Because the DC bias current is drawn from
V
IN
, the resulting loss increases with input voltage. For
V
IN
= 10V the DC bias losses are generally less than 1%
for load currents over 30mA. However, at very low load
currents the DC bias current accounts for nearly all of
the loss.
2. MOSFET gate charge current results from switching the
gate capacitance of the power MOSFETs. Each time a
MOSFET gate is switched from low to high to low again,
a packet of charge dQ moves from V
IN
to ground. The
resulting dQ/dt is a current out of V
IN
which is typically
much larger than the DC supply current. In continuous
mode, I
GATECHG
= f (Q
N
+ Q
P
). The typical gate charge
for a 0.1Ω N-channel power MOSFET is 25nC, and for
a P-channel about twice that value. This results in
I
GATECHG
= 7.5mA in 100kHz continuous operation, for
a 2% to 3% typical mid-current loss with V
IN
= 10V.
Note that the gate charge loss increases directly with
both input voltage and operating frequency. This is the
principal reason why the highest efficiency circuits
operate at moderate frequencies. Furthermore, it ar-
gues against using larger MOSFETs than necessary to
control I
2
R losses, since overkill can cost efficiency as
well as money!
3. I
2
R losses are easily predicted from the DC resistances
of the MOSFET, inductor, and current shunt. In continu-
ous mode the average output current flows through L
and R
SENSE
, but is “chopped” between the P-channel
and N-channel MOSFETs. If the two MOSFETs have
approximately the same R
DS(ON)
, then the resistance of
one MOSFET can simply be summed with the resis-
tances of L and R
SENSE
to obtain I
2
R losses. For
example, if each R
DS(ON)
= 0.1Ω, R
L
= 0.15Ω, and
R
SENSE
= 0.05Ω, then the total resistance is 0.3Ω. This
results in losses ranging from 3% to 12% as the output
current increases from 0.5A to 2A. I
2
R losses cause the
efficiency to roll-off at high output currents.
Figure 5 shows how the efficiency losses in a typical
LTC1148 series regulator end up being apportioned.
Figure 5. Efficiency Loss
OUTPUT CURRENT (A)
0.01
EFFICIENCY/LOSS (%)
90
95
1
LTC1148 • F05
85
80 0.03 0.1 0.3 3
100
GATE CHARGE
LTC1148 I
Q
I
2
R
The gate charge loss is responsible for the majority of
the efficiency lost in the mid-current region. If Burst
Mode operation was not employed at low currents, the
gate charge loss alone would cause efficiency to drop to
unacceptable levels. With Burst Mode
operation, the
DC supply current represents the lone (and unavoid-
able) loss component which continues to become a
higher percentage as output current is reduced. As
expected, the I
2
R losses dominate at high load currents.
Other losses including C
IN
and C
OUT
ESR dissipative
losses, MOSFET switching losses, Schottky conduction
losses during dead time, and inductor core losses, gener-
ally account for less than 2% total additional loss.
Design Example
As a design example, assume V
IN
= 12V (nominal),
V
OUT
= 5V, I
MAX
= 2A, and f = 200kHz; R
SENSE
, C
T
and L
can immediately be calculated:
R
SENSE
= 100mV/2 = 0.05Ω
t
OFF
= (1/200kHz)[1 – (5/12)] = 2.92µs
C
T
= 2.92µs/[(1.3)(10
4
)] = 220pF
L
MIN
= 5.1
(
10
5
)0.05Ω(220pF)5V = 28µH
Assume that the MOSFET dissipations are to be limited to
P
N
= P
P
= 250mW.
If T
A
= 50°C and the thermal resistance of each MOSFET
is 50°C/W, then the junction temperatures will be 63°C
13
LTC1148
LTC1148-3.3/LTC1148-5
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APPLICATIO S I FOR ATIO
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To prevent stray pickup a 100pF capacitor is suggested
across R1 located close to the LTC1148.
For Figure 1 applications with V
OUT
below 2V, or when
R
SENSE
is moved to ground, the current sense comparator
inputs operate near ground. When the current comparator
is operated at less than 2V common mode, the off time
increases approximately 40%, requiring the use of a
smaller timing capacitor C
T
.
Auxiliary Windings – Suppressing Burst Mode
Operation
The LTC1148 synchronous switch removes the normal
limitation that power must be drawn from the inductor
primary winding in order to extract power from auxil-
iary windings. With synchronous switching, auxiliary
outputs may be loaded without regard to the primary
output load, providing that the loop remains in continu-
ous mode operation.
Burst Mode
operation can be suppressed at low output
currents with a simple external network which cancels the
25mV minimum current comparator threshold. This tech-
nique is also useful for eliminating audible noise from
certain types of inductors in high current (I
OUT
> 5A)
applications when they are lightly loaded.
An external offset is put in series with the SENSE
–
pin to
subtract from the built-in 25mV offset. An example of this
technique is shown in Figure 6. Two 100Ω resistors are
inserted in series with the leads from the sense resistor.
and δ
P
= δ
N
= 0.007(63 – 25) = 0.27. The required R
DS(ON)
for each MOSFET can now be calculated:
P-Ch RDS(ON) = 12(0.25)
5(2)2 (1.27) = 0.12Ω
N-Ch RDS(ON) = 12(0.25)
7(2)2 (1.27) = 0.085Ω
The P-channel requirement can be met by a Si9430DY,
while the N-channel requirement is exceeded by a
Si9410DY. Note that the most stringent requirement for
the N-channel MOSFET is with V
OUT
= 0 (i.e., short circuit).
During a continuous short circuit, the worst-case
N-channel dissipation rises to:
P
N
= I
SC(AVG)2
(R
DS(ON)
)(1 + δ
N
)
With the 0.05Ω sense resistor I
SC(AVG)
= 2A will result,
increasing the 0.085Ω N-channel dissipation to 450mW at
a die temperature of 73°C.
C
IN
will require an RMS current rating of at least 1A at
temperature, and C
OUT
will require an ESR of 0.05Ω for
optimum efficiency.
Now allow V
IN
to drop to its minimum value. At lower input
voltages the operating frequency will decrease and the
P-channel will be conducting most of the time, causing its
power dissipation to increase. At V
IN(MIN)
= 7V:
f
MIN
= (1/2.92µs)[1 – (5V/7V)] = 98kHz
PP = 5V(0.12Ω)(2A)2(1.27)
7V = 435mW
This last step is necessary to assure that the power
dissipation and junction temperature of the P-channel are
not exceeded.
LTC1148 Adjustable Applications
When an output voltage other than 3.3V or 5V is required,
the LTC1148 adjustable version is used with an external
resistive divider from V
OUT
to V
FB
Pin 9 (see Figure 9). The
regulated voltage is determined by:
VOUT = 1.25
)
)
1 + R2
R1
Figure 6. Suppression of Burst Mode Operation
RSENSE
1000pF
R2
100Ω
R1
100Ω
R3
+
COUT
VOUT
SENSE+ (PIN 8)
SENSE – (PIN 7)
LTC1148 • F06
14
LTC1148
LTC1148-3.3/LTC1148-5
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APPLICATIO S I FOR ATIO
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With the addition of R3, a current is generated through R1
causing an offset of:
VOFFSET = VOUT
)
)
R1
R1 + R3
If V
OFFSET
> 25mV, the minimum threshold will be can-
celled and Burst Mode
operation is prevented from occur-
ring. Since V
OFFSET
is constant, the maximum load current
is also decreased by the same offset. Thus, to get back to
the same I
MAX
, the value of the sense resistor must be
lower:
R
SENSE
≈75mV
I
MAX
To prevent noise spikes from erroneously tripping the
current comparator, a 1000pF capacitor is needed across
Pins 7 and 8.
Output Crowbar
An added feature to using an N-channel MOSFET as the
synchronous switch is the ability to crowbar the output
with the same MOSFET. Pulling the timing capacitor Pin
4 above 1.5V when the output voltage is greater than the
desired regulated value will turn “on” the N-channel
MOSFET.
A fault condition which causes the output voltage to go
above a maximum allowable value can be detected by
external circuitry. Turning on the N-channel MOSFET
when this fault is detected will cause large currents to flow
and blow the system fuse.
The N-channel MOSFET needs to be sized so it will safely
handle this overcurrent condition. The typical delay from
pulling the C
T
pin high and the N drive Pin 14 going high
is 250ns. Note: Under shutdown conditions, the N-chan-
nel is held OFF and pulling the C
T
pin high will not cause
the N-channel MOSFET to crowbar the output.
A simple N-channel FET can be used as an interface
between the overvoltage detect circuitry and the LTC1148
as shown in Figure 7.
Figure 7. Output Crowbar Interface
LTC1148
INTV
CC
C
T
VN2222LL
5
4
FROM CROWBAR DETECT CIRCUIT
(ACTIVE WHEN V
GATE
= V
IN
OFF WHEN V
GATE
= GROUND)
LTC1148 • F07
Troubleshooting Hints
Since efficiency is critical to LTC1148 series applications,
it is very important to verify that the circuit is functioning
correctly in both continuous and Burst Mode
operation.
The waveform to monitor is the voltage on the timing
capacitor Pin 4.
In continuous mode (I
LOAD
> I
BURST
) the voltage on the C
T
pin should be a sawtooth with a 0.9V
P-P
swing. This
voltage should never dip below 2V as shown in Figure 8a.
When load currents are low (I
LOAD
< I
BURST
) Burst Mode
operation should occur with the C
T
pin waveform periodi-
cally falling to ground as shown in Figure 8b.
3.3V
0V
(a) CONTINUOUS MODE OPERATION
3.3V
0V
(b) Burst Mode OPERATION LTC1148 • F08
Figure 8. CT Waveforms
If Pin 4 is observed falling to ground at high output
currents, it indicates poor decoupling or improper ground-
ing. Refer to the Board Layout Checklist.
15
LTC1148
LTC1148-3.3/LTC1148-5
114835fd
Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1148 series. These items are also illustrated graphi-
cally in the layout diagram of Figure 9. Check the following
in your layout:
1. Are the signal and power grounds segregated? The
LTC1148 signal ground Pin 11 must return to the (–)
plate
of COUT. The power ground returns to the
source of the N-channel MOSFET, anode of the
Schottky diode, and (–) plate of CIN, which should
have as short lead lengths as possible.
2. Does the LTC1148 SENSE
–
Pin 7 connect to a point
close to R
SENSE
and the (+) plate of C
OUT
? In adjust-
able applications, the resistive divider R1, R2 must be
connected between the (+) plate of C
OUT
and signal
ground.
3. Are the SENSE
–
and SENSE
+
leads routed together
with minimum PC trace spacing? The 1000pF capacitor
between Pins 7 and 8 should be as close as possible to
the LTC1148.
4. Does the (+) plate of C
IN
connect to the source of the
P-channel MOSFET as closely as possible? This capaci-
tor provides the AC current to the P-channel MOSFET.
5. Is the 1µF V
IN
decoupling capacitor connected closely
between Pin 3 and power ground Pin 12? This capacitor
carries the MOSFET driver peak currents.
6. Is the Shutdown Pin 10 actively pulled to ground during
normal operation? The Shutdown pin is high imped-
ance and must not be allowed to float.
Figure 9. LTC1148 Layout Diagram (See Board Layout Checklist)
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1
2
3
4
5
6
7
14
13
12
11
10
9
8
COUT
1µF
D1
P-CHANNEL
1k
3300pF10nFCT
LTC1148
R1
R2
+
RSENSE
N-CHANNEL
+
CIN
L
+
–
–
+
VOUT
VIN
OUTPUT DIVIDER REQUIRED WITH
ADJUSTABLE VERSION ONLY
BOLD LINES INDICATE HIGH CURRENT PATHS
LTC1148 • F09
SHUTDOWN
1000pF
P-DRIVE
V
IN
C
T
INTV
CC
I
TH
SENSE
–
N-DRIVE
PGND
SGND
SHDN
NC (V
FB
)
SENSE
+
NC NC
+
16
LTC1148
LTC1148-3.3/LTC1148-5
114835fd
TYPICAL APPLICATIO S
U
1
2
3
4
5
6
7
14
13
12
11
10
9
8
P-DRIVE
NC
V
IN
C
T
INTV
CC
I
TH
SENSE
–
N-DRIVE
NC
PGND
SGND
SHUTDOWN
V
FB
SENSE
+
LTC1148
1µF
0.01µFR
SENSE
**
0.033Ω
SHUTDOWN
*L
50µH
IRF7201
D1
MBRS140T3
+
V
IN
8V TO 14V
+
C
OUT
220µF
10V
×2
OS-CON
V
OUT
5V/3A
C
C
3300pF
R
C
220Ω
C
T
390pF
*COILTRONICS CTX50-2-MP
**KRL SL-1-C1-0R033J
LTC1148 • F12
10nF
IRF7204
C
IN
330µF
20V
100pF
R1
10k
1%
R2
30k
1%
()
V
OUT
= 1 + R2
R1 1.25V
VALUES SHOWN FOR V
OUT
= 5V
+
1
2
3
4
5
6
7
14
13
12
11
10
9
8
P-DRIVE
NC
V
IN
C
T
INTV
CC
I
TH
SENSE
–
N-DRIVE
NC
PGND
SGND
SHUTDOWN
NC
SENSE
+
LTC1148HV-3.3
1µF
1000pF R
SENSE
**
0.1Ω
SHUTDOWN
*L
50µH
D1
MBRS140T3
1/2 Si4532
1/2 Si4532
+
C
IN
100µF
25V
V
IN
4V TO 18V
+
C
OUT
220µF
10V
OS-CON
V
OUT
3.3V/1A
C
C
3300pF
R
C
1k
C
T
300pF
*COILTRONICS CTX50-4 Kool Mµ CORE
**IRC LR2010-01-R100-G
LTC1148 • F11
+
1
2
3
4
5
6
7
14
13
12
11
10
9
8
P-DRIVE
NC
VIN
CT
INTVCC
ITH
SENSE–
N-DRIVE
NC
PGND
SGND
SHUTDOWN
NC
SENSE+
LTC1148HV-5
1µF
1000pF RSENSE**
0.1Ω
SHUTDOWN
*L
100µH
1/2 Si4532
D1
MBRS140T3
1/2 Si4532
+CIN
100µF
25V
VIN
5.2V TO 18V
+
COUT
220µF
10V
AVX
VOUT
5V/1A
CC
3300pF
RC
1k
CT
390pF
*COILTRONICS CTX100-4 Kool Mµ CORE
**KRL SP-1/2-A1-0R100
LTC1148 • F10
+
Figure 10. 5V/1A High Efficiency Regulator
with Extended Input Voltage Range
Figure 11. High Efficiency 5V to 3.3V/1A Converter
with Extended Input Voltage Range
Figure 12. High Efficiency Adjustable 3A Regulator
17
LTC1148
LTC1148-3.3/LTC1148-5
114835fd
TYPICAL APPLICATIO S
U
1
2
3
4
5
6
7
14
13
12
11
10
9
8
P-DRIVE
NC
VIN
CT
INTVCC
ITH
SENSE–
N-DRIVE
NC
PGND
SGND
SHUTDOWN
NC
SENSE+
LTC1148L-3.3
1µF
1000pF RSENSE**
0.05Ω
SHUTDOWN
*L
25µH
MMSF5N02HD
D1
MBRS140T3
MMSF3P02HD
+CIN
100µF
20V
VIN
3.5V TO 14V
+
COUT
220µF
10V
×2
AVX
VOUT
3.3V/2A
CC
3300pF
RC
1k
CT
270pF
*COILTRONICS CTX25-5 Kool Mµ CORE
**IRC LR2512-01-R050-G
LTC1148 • F13
+
Figure 13. 5V Input Voltage, 3.3V/2A Low Dropout, High
Efficiency Regulator
Figure 14. High Efficiency 5V to 3.3V/4.5A Converter
1
2
3
4
5
6
7
14
13
12
11
10
9
8
P-DRIVE
NC
V
IN
C
T
INTV
CC
I
TH
SENSE
–
N-DRIVE
NC
PGND
SGND
SHUTDOWN
NC
SENSE
+
LTC1148-3.3
0.1µF
1000pF R
SENSE
**
0.02Ω
SHUTDOWN
*L
10µH
Si9804DY
D1
MBRS140T3
Si9803DY
+C
IN
100µF
20V
×2
V
IN
5V
+
C
OUT
220µF
10V
AVX
×2
V
OUT
3.3V/4.5A
C
C
3300pF
R
C
470Ω
C
T
270pF
NPO
*COILTRONICS CTX10-5P
**KRL SP-1-C1-0R020
LTC1148 • F14
1
2
3
4
5
6
7
14
13
12
11
10
9
8
P-DRIVE
NC
V
IN
C
T
INTV
CC
I
TH
SENSE
–
N-DRIVE
NC
PGND
SGND
SHUTDOWN
V
FB
SENSE
+
LTC1148
1µF
1000pF R
SENSE
**
0.05Ω
1M
*L
50µH
Si4412DY
D1
MBRS140T3
+
V
IN
4V TO 9V
+
C
OUT
220µF
10V
×2
OS-CON
V
OUT
–5V/1.4A
C
C
6800pF
R
C
1k
C
T
560pF
LTC1148 • F15
10nF
Si4431DY
C
IN
220µF
20V
R1
25k
1%
R2
75k
1%
200pF
TP0610L
V
IN
: ACTIVE
0V: SHUTDOWN
*COILTRONICS CTX50-2-MP
**KRL SL-1-C1-0R050J
+
Figure 15. 4V to 9V Input Voltage to –5V/1A Regulator
18
LTC1148
LTC1148-3.3/LTC1148-5
114835fd
TYPICAL APPLICATIO S
U
1
2
3
4
5
6
7
14
13
12
11
10
9
8
P-DRIVE
NC
V
IN
C
T
INTV
CC
I
TH
SENSE
–
N-DRIVE
NC
PGND
SGND
SHUTDOWN
V
FB
SENSE
+
LTC1148
1µF
0.1µFR
SENSE
**
0.082Ω
SHUTDOWN
L2
50µH
+
V
IN
4V TO 14V
V
OUT
5V/1A
C
C
3300pF
R
C
1k
C
T
390pF
LTC1148 • F16
Si4435DY
C
IN
100µF
20V
100pF
+
220µF*
10V
OS-CON
D1
MBRS140T3
R1
25k
1%
R2
75k
1%
+
C
OUT
220µF
10V
OS-CON
L1
50µH
*LOW ESR REQUIRED
**KRL NP-1A-C1-0R082J
Si4412DY
V
OUT
1N4148
+
Figure 16. 4V to 14V Input Voltage to 5V/1A Regulator with Current Foldback
1
2
3
4
5
6
7
14
13
12
11
10
9
8
P-DRIVE
NC
V
IN
C
T
INTV
CC
I
TH
SENSE
–
N-DRIVE
NC
PGND
SGND
SHUTDOWN
V
FB
SENSE
+
LTC1148
1µF
1000pF R
SENSE
**
0.05Ω
SHUTDOWN
*L
50µH
NDS9410A
D1
MBRS140T3
+
V
IN
5.2V TO 14V
+
C
OUT
220µF
10V
×2
OS-CON
V
OUT
3.3V/2A
OR 5V/2A
C
C
3300pF
R
C
1k
C
T
390pF
*COILTRONICS CTX50-2-MP
**KRL SL-1-C1-0R050R
LTC1148 • F17
10nF
NDS9435A
C
IN
100µF
20V
100pF
R1B
43k
1%
R2
56k
1%
R1A
33k
1%
VN2222LL
0V: V
OUT
= 3.3V
5V: V
OUT
= 5V
+
Figure 17. Logic Selectable 5V/1A or 3.3V/1A High Efficiency Regulator
19
LTC1148
LTC1148-3.3/LTC1148-5
114835fd
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
S Package
14-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
N Package
14-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
PACKAGE DESCRIPTIO
U
N14 1103
.020
(0.508)
MIN
.120
(3.048)
MIN
.130 ± .005
(3.302 ± 0.127)
.045 – .065
(1.143 – 1.651)
.065
(1.651)
TYP
.018 ± .003
(0.457 ± 0.076)
.005
(0.127)
MIN
.255 ± .015*
(6.477 ± 0.381)
.770*
(19.558)
MAX
31 24567
8910
11
1213
14
.008 – .015
(0.203 – 0.381)
.300 – .325
(7.620 – 8.255)
.325 +.035
–.015
+0.889
–0.381
8.255
()
NOTE:
1. DIMENSIONS ARE INCHES
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
.100
(2.54)
BSC
1
N
234
.150 – .157
(3.810 – 3.988)
NOTE 3
14 13
.337 – .344
(8.560 – 8.738)
NOTE 3
.228 – .244
(5.791 – 6.197)
12 11 10 9
567
N/2
8
.016 – .050
(0.406 – 1.270)
.010 – .020
(0.254 – 0.508)× 45°
0° – 8° TYP
.008 – .010
(0.203 – 0.254)
S14 0502
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
.245
MIN
N
123 N/2
.160 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
.050 BSC
.030 ±.005
TYP
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
20
LTC1148
LTC1148-3.3/LTC1148-5
114835fd
© LINEAR TECHNOLOGY CORPORATION 1993
LT/TP 0604 1K REV D • PRINTED IN USA
TYPICAL APPLICATION
U
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
1
2
3
4
5
6
7
14
13
12
11
10
9
8
P-DRIVE
NC
V
IN
C
T
INTV
CC
I
TH
SENSE
–
N-DRIVE
NC
PGND
SGND
SHUTDOWN
NC
SENSE
+
LTC1148HV-5
1µF
1000pF RSENSE
**
0.01Ω
SHUTDOWN
*L
33µH
N-CH
IRFZ44
D1
1N5818
VN2222LL
+
CIN
2700µF
35V
×2
VIN
10V TO 18V
+
COUT
2200µF
16V
×3
VOUT
5V/8A
CC
3300pF
RC
510Ω
CT
820pF
LTC1148 • F18
MUR110 N-CH
IRFZ44
470nF
220Ω
220Ω
20k
1N4148
22k
100Ω
100Ω
*COILTRONICS CTX33-10-KM
**DALE LVR-3-0.01
2N3906
2N2222
+
Figure 18. All N-Channel 5V/8A High Efficiency Regulator
(Burst Mode Operation Suppressed)
Figure 19. All N-Channel 5V/8A Efficiency
LOAD CURRENT (A)
0.1
60
EFFICIENCY (%)
70
80
100
110
LTC1148 • F19
90
V
IN
= 10V
V
IN
= 14V
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC1142 Dual High Efficiency Synchronous Step-Down Switching Regulator Dual LTC1148
LTC1143 Dual High Efficiency Step-Down Switching Regulator Controller Nonsynchronous Dual Output
LTC1147 High Efficiency Step-Down Switching Regulator Controller Nonsynchronous Equivalent to LTC1148, 8-Pin
LTC1149 High Efficiency Synchronous Step-Down Switching Regulator V
IN
< 48V, Standard Threshold MOSFETs
LTC1159 High Efficiency Synchronous Step-Down Switching Regulator V
IN
< 40V, Logic Level MOSFETs
LTC1174 High Efficiency Step-Down and Inverting DC/DC Converter Nonsynchronous 8-Pin Internal Switch
LTC1265 1.2A, High Efficiency Step-Down DC/DC Converter Nonsynchronous Internal Switch
LTC1435A High Efficiency Low Noise Synchronous Step-Down Switching Regulator Synchronous N-Channel, Constant Frequency
LTC1538-AUX Dual High Efficiency, Low Noise, Synchronous Step-Down Auxiliary Linear Regulator, 5V Standby in Shutdown
Switching Regulator
For additional high efficiency application
circuits, see Application Notes 54, 58 and 66
