UTRON UT62L12916/UT62L12916(I)
Rev. 1.0 128K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80042
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
REVISION HISTORY
REVISION DESCRIPTION Date
Preliminary Rev. 0.5 Original. Mar, 2001
Rev.1.0 1. Revised Features
-Access time 70/100ns55/70/100ns
-Operating current 5mA(Icc1,max)45/35/25mA(Icc max)
-Standby current 80/25uA(max)20/2uA(typ)
-Vcc power supply 2.7~3.3V2.5~3.6V
2. Revised Function block diagram
3. Revised DC electrical characteristics table
4. Revised AC electrical characteristics table
5. Revised Timing waveforms
6. Revised Data retention characteristics table & waveform
7. Revised 48 TFBGA outline dimension, ball size 0.3mm0.35mm
8. Revised order information
May 15,2003
UTRON UT62L12916/UT62L12916(I)
Rev. 1.0 128K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80042
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 2
FEATURES
Fast access time :
55ns (max.) for Vcc=2.7V~3.6V
70/100ns (max.) for Vcc=2.5V~3.6V
CMOS low power operating
Operating current : 45/35/25mA (Icc max.)
Standby current : 20uA(max.) L–version
2uA(max.) LL-version
Single 2.5V~3.6V power supply
Operating temperature:
Commercial : 0℃~70℃
Industrial : -40℃~85℃
All TTL compatible inputs and outputs
Fully static operation
Three state outputs
Data retention voltage : 1.5V (min.)
Data byte control : LB (I/O1~I/O8)
UB(I/O9~I/O16)
Package : 48-pin 6mm × 8mm TFBGA
GENERAL DESCRIPTION
The UT62L12916 is a 2,097,152-bit low power CMOS
static random access memory organized as 131,072
words by 16 bits.
The UT62L12916 operates from a single 2.5V ~ 3.6V
power supply and all inputs and outputs are fully TTL
compatible.
The UT62L12916 is designed for low power system
applications. It is particularly well suited for use in
high-density low power system applications.
FUNCTIONAL BLOCK DIAGRAM
DECODER
I/O DA TA
CIRCUIT
CONTROL
CIRCUIT
128K X 16
MEMORY
ARRAY
COLUMN I/O
A0-A17
Vcc
Vss
I/O1-I/O8
Lower Byte
I/O9-I/O16
Upper Byte
CE2
OE
WE
LB
UB
CE
UTRON UT62L12916/UT62L12916(I)
Rev. 1.0 128K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80042
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 3
PIN CONFIGURATION
123456
H
G
C
D
E
F
A
B
TFBGA
LB A0
OE A1 CE2A2
I/O9 A3UB A4 I/O1CE
I/O10 A5I/O11 A6 I/O3I/O2
Vss NCI/O12 A7 VccI/O4
Vcc NCI/O13 A16 VssI/O5
I/O15 A14I/O14 A15 I/O7I/O6
I/O16 A12CIOS A13 I/O8WE
NC A9A8 A10 NCA11
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 - A17 Address Inputs
I/O1 - I/O16 Data Inputs/Outputs
CE, CE2 Chip Enable Input
WE Write Enable Input
OE Output Enable Input
LB Lower-byte Control
UB Upper-byte Control
VCC Power Supply
VSS Ground
NC No Connection
TRUTH TABLE
I/O OPERATION
MODE CE CE2 OE WE LB UB I/O1-I/O8 I/O9-I/O16 SUPPLY
CURRENT
Standby H
X
X
X
L
X
X
X
X
X
X
X
X
X
H
X
X
H
High – Z
High – Z
High – Z
High – Z
High – Z
High – Z ISB, ISB1
Output Disable L
L H
H H
H H
H L
X X
L High – Z
High – Z High – Z
High – Z ICC,ICC1,ICC2
Read L
L
L
H
H
H
L
L
L
H
H
H
L
H
L
H
L
L
DOUT
High – Z
DOUT
High – Z
DOUT
DOUT ICC,ICC1,ICC2
Write L
L
L
H
H
H
X
X
X
L
L
L
L
H
L
H
L
L
DIN
High – Z
DIN
High – Z
DIN
DIN ICC,ICC1,ICC2
Note: H = VIH, L=VIL, X = Don't care.
UTRON UT62L12916/UT62L12916(I)
Rev. 1.0 128K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80042
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
ABSOLUTE MAXIMUM RATINGS*
PARAMETER SYMBOL RATING UNIT
Terminal Voltage with Respect to VSS V
TERM -0.5 to 4.6 V
Commercial TA 0 to 70 ℃
Operating Temperature
Industrial TA -40 to 85 ℃
Storage Temperature TSTG -65 to 150 ℃
Power Dissipation PD 1 W
DC Output Current IOUT 50 mA
Soldering Temperature (under 10 secs) Tsolder 260 ℃
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
DC ELECTRICAL CHARACTERISTICS (TA = 0℃ to 70℃/-40℃ to 85℃(I))
PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
55 2.7 3.0 3.6 V Power Voltage VCC 70/100 2.5 - 3.6 V
Input High Voltage VIH＊1 2.2 - VCC+0.3 V
Input Low Voltage VIL＊2 -0.2 - 0.6 V
Input Leakage Current ILI VSS ≦VIN ≦VCC - 1 - 1 µA
Output Leakage Current ILO VSS ≦VI/O ≦VCC; Output Disable - 1 - 1 µA
Output High Voltage VOH I
OH= -1mA 2.2 - - V
Output Low Voltage VOL I
OL= 2.1mA - - 0.4 V
55 - 30 45 mA
70 - 25 35 mA
Operating Power
Supply Current ICC Cycle time=min, 100%duty
I/O=0mA, CE=VIL 100 - 20 25 mA
ICC1 Tcycle=
1µs - 4 5 mA
Average Operation
Current ICC2
100%duty,II/O=0mA,CE≦0.2V,
other pins at 0.2V or Vcc-0.2V Tcycle=
500ns - 8 10 mA
Standby Current (TTL) ISB CE=VIH, other pins =VIL or VIH - 0.3 0.5 mA
-L - 20 80 µA
Standby Current (CMOS) ISB1 CE=VCC-0.2V
other pins at 0.2V or Vcc-0.2V -LL - 2 20 µA
Notes:
1. Overshoot : Vcc+3.0v for pulse width less than 10ns.
2. Undershoot : Vss-3.0v for pulse width less than 10ns.
3. Overshoot and Undershoot are sampled, not 100% tested.
UTRON UT62L12916/UT62L12916(I)
Rev. 1.0 128K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80042
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 5
CAPACITANCE (TA=25℃, f=1.0MHz)
PARAMETER SYMBOL MIN. MAX UNIT
Input Capacitance CIN - 6 pF
Input/Output Capacitance CI/O - 8 pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels 0V to 3.0V
Input Rise and Fall Times 5ns
Input and Output Timing Reference Levels 1.5V
Output Load CL = 30pF, IOH/IOL = -1mA/2.1mA
AC ELECTRICAL CHARACTERISTICS (TA = 0℃ to 70℃/-40℃ to 85℃(I))
(1) READ CYCLE
PARAMETER SYMBOL UT62L12916-55 UT62L12916-70 UT62L12916-100
UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
Read Cycle Time tRC 55 - 70 - 100 - ns
Address Access Time tAA - 55 - 70 - 100 ns
Chip Enable Access Time tACE - 55 - 70 - 100 ns
Output Enable Access Time tOE - 30 - 35 - 50 ns
Chip Enable to Output in Low Z tCLZ* 10 - 10 - 10 - ns
Output Enable to Output in Low Z tOLZ* 5 - 5 - 5 - ns
Chip Disable to Output in High Z tCHZ* - 20 - 25 - 30 ns
Output Disable to Output in High Z tOHZ* - 20 - 25 - 30 ns
Output Hold from Address Change tOH 10 - 10 - 10 - ns
LB ,UB Access Time tBA - 55 - 70 - 100 ns
LB ,UB to High-Z Output tBHZ - 25 - 30 - 40 ns
LB ,UB to Low-Z Output tBLZ 10 - 10 - 10 - ns
(2) WRITE CYCLE
PARAMETER SYMBO
L
UT62L12916-55 UT62L12916-70 UT62L12916-100
UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
Write Cycle Time tWC 55 - 70 - 100 - ns
Address Valid to End of Write tAW 50 - 60 - 80 - ns
Chip Enable to End of Write tCW 50 - 60 - 80 - ns
Address Set-up Time tAS 0 - 0 - 0 - ns
Write Pulse Width tWP 45 - 55 - 70 - ns
Write Recovery Time tWR 0 - 0 - 0 - ns
Data to Write Time Overlap tDW 25 - 30 - 40 - ns
Data Hold from End of Write Time tDH 0 - 0 - 0 - ns
Output Active from End of Write tOW* 5 - 5 - 5 - ns
Write to Output in High Z tWHZ* - 30 - 30 - 40 ns
LB ,UB Valid to End of Write tBW 45 - 60 - 80 - ns
* These parameters are guaranteed by device characterization, but not production tested.
UTRON UT62L12916/UT62L12916(I)
Rev. 1.0 128K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80042
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 6
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2) tRC
tAA
Data Valid
Address
Dout
tOH tOH
Previous data valid
READ CYCLE 2 (CEand CE2 and OE Controlled) (1,3,4,5)
tRC
tAA
tACE
tBLZ
tOE tOHZ
tCLZ
tBHZ
tOH
tOLZ
High-Z Da ta Va lid High-Z
tBA
tCHZ
Address
CE2
Dout
CE
L B , UB
OE
Notes :
1. WE is high for read cycle.
2.Device is continuously selectedOE =low,CE =low, CE2=high,LB orUB =low.
3.Address must be valid prior to or coincident withCE =low, CE2=high,LB orUB =low transition; otherwise tAA is the limiting
parameter.
4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL=5pF. Transition is measured±500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ, tBHZ is less than tBLZ, tOHZ is less than tOLZ.
UTRON UT62L12916/UT62L12916(I)
Rev. 1.0 128K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80042
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 7
WRITE CYCLE 1 (WE Controlled) (1,2,3,5,6)
tWC
tAW
tCW
tAS tWP
tBW
tWHZ tOW
tWR
High-Z
(4) (4)
Address
CE2
CE
WE
LB , UB
Dout
Din D a ta V a lid
tDW tDH
WRITE CYCLE 2 (CEand CE2 Controlled) (1,2,5,6) tWC
tAW
tCW
tAS tWR
tWP
tBW
tWHZ
tDW tDH
D ata Valid
High-Z
(4)
Address
CE2
CE
WE
LB , UB
Dout
Din
UTRON UT62L12916/UT62L12916(I)
Rev. 1.0 128K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80042
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 8
WRITE CYCLE 3 (LB ,UBControlled) (1,2,5,6) tWC
tAW
tAS tWR
tCW
tWP
tBW
tWHZ
tDW tDH
D ata Valid
Address
CE
CE2
WE
LB , UB
Dout
Din
High-Z
Notes :
1. WE ,CE ,LB ,UB must be high or CE2 must be low during all address transitions.
2.A write occurs during the overlap of a lowCE , high CE2, low WE ,LB orUB =low.
3.During a WE controlled write cycle withOE low, tWP must be greater than tWHZ+tDW to allow the drivers to turn off and data to be
placed on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If theCE ,LB ,UB low transition and CE2 high transition occurs simultaneously with or after WE low transition, the outputs remain in a
high impedance state.
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
UTRON UT62L12916/UT62L12916(I)
Rev. 1.0 128K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80042
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 9
DATA RETENTION CHARACTERISTICS (TA = 0℃ to 70℃/-40℃ to 85℃(I))
PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Vcc for Data Retention
VDR CE≧VCC-0.2V or CE2≦0.2V 1.5 - 3.6 V
Data Retention Current IDR Vcc=1.5V - L - 1 50 µA
CE≧VCC-0.2V
or CE2≦0.2V - LL - 0.5 20 µA
Chip Disable to Data tCDR See Data Retention 0 - - ms
Retention Time Waveforms (below)
Recovery Time
t
R 5 - - ms
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1) (CE controlled)
VDR ≧ 1.5V
CE ≧ VCC-0.2V
Vcc(min.) Vcc(min.)
VIH VIH
VCC
tR
tCDR
CE
Low Vcc Data Retention Waveform (2) (CE2 controlled)
VDR ≧ 1.5V
VCC(min.)
VCC
tR
tCDR
CE2 ≦ 0.2V VIL
CE2
VCC(min.)
VIL
Low Vcc Data Retention Waveform (3) (LB ,UB controlled)
VDR ≧ 1.5V
LB,UB ≧ V CC-0.2V
Vcc(min.) Vcc(min.)
VIH VIH
VCC
tR
tCDR
LB,UB
UTRON UT62L12916/UT62L12916(I)
Rev. 1.0 128K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80042
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 10
PACKAGE OUTLINE DIMENSION
48 pin 6.0mmX8.0mm TFBGA Package Outline Dimension
UTRON UT62L12916/UT62L12916(I)
Rev. 1.0 128K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80042
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 11
ORDERING INFORMATION
COMMERCIAL TEMPERATURE
PART NO. ACCESS TIME
( ns ) STANDBY CURRENT
( µA ) typ. PACKAGE
UT62L12916BS-55L 55 20 48 PIN BGA
UT62L12916BS-55LL 55 2 48 PIN BGA
UT62L12916BS-70L 70 20 48 PIN BGA
UT62L12916BS-70LL 70 2 48 PIN BGA
UT62L12916BS-100L 100 20 48 PIN BGA
UT62L12916BS-100LL 100 2 48 PIN BGA
INDUSTRIAL TEMPERATURE
PART NO. ACCESS TIME
( ns ) STANDBY CURRENT
( µA ) typ. PACKAGE
UT62L12916BS-55LI 55 20 48 PIN BGA
UT62L12916BS-55LLI 55 2 48 PIN BGA
UT62L12916BS-70LI 70 20 48 PIN BGA
UT62L12916BS-70LLI 70 2 48 PIN BGA
UT62L12916BS-100LI 100 20 48 PIN BGA
UT62L12916BS-100LLI 100 2 48 PIN BGA
ORDERING INFORMATION (for lead free product)
COMMERCIAL TEMPERATURE
PART NO. ACCESS TIME
( ns ) STANDBY CURRENT
( µA ) typ. PACKAGE
UT62L12916BSL-55L 55 20 48 PIN BGA
UT62L12916BSL-55LL 55 2 48 PIN BGA
UT62L12916BSL-70L 70 20 48 PIN BGA
UT62L12916BSL-70LL 70 2 48 PIN BGA
UT62L12916BSL-100L 100 20 48 PIN BGA
UT62L12916BSL-100LL 100 2 48 PIN BGA
INDUSTRIAL TEMPERATURE
PART NO. ACCESS TIME
( ns ) STANDBY CURRENT
( µA ) typ. PACKAGE
UT62L12916BSL-55LI 55 20 48 PIN BGA
UT62L12916BSL-55LLI 55 2 48 PIN BGA
UT62L12916BSL-70LI 70 20 48 PIN BGA
UT62L12916BSL-70LLI 70 2 48 PIN BGA
UT62L12916BSL-100LI 100 20 48 PIN BGA
UT62L12916BSL-100LLI 100 2 48 PIN BGA
UTRON UT62L12916/UT62L12916(I)
Rev. 1.0 128K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80042
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 12
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