Vishay Siliconix
SiP21106, SiP21107, SiP21108
Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
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1
150-mA Low Noise, Low Dropout Regulator
DESCRIPTION
The SiP21106 BiCMOS 150 mA low noise LDO voltage
regulators are the perfect choice for low battery operated low
powered applications. An ultra low ground current and low
dropout voltage of 135 mV at 150 mA load helps to extend
battery life for portable electronics. Systems requiring a quiet
voltage source, such as RF applications, will benefit from the
SiP21106 low output noise.
The SiP21107 do not require a noise bypass capacitor and
provides an error flag pin (POK or Power OK). POK output
requires an external pull-up resistor and goes low when the
supply has not come up to voltage.
The SiP21108 output is adjusted with an external resistor
network.
The SiP21106, SiP21107, SiP21108 regulators allow stable
operation with very small ceramic output capacitors,
reducing board space and component cost. They are
designed to maintain regulation while delivering 330 mA
peak current upon turn-on. During start-up, an active
pull-down circuit improves the output transient response and
regulation. In shutdown mode, the output automatically
discharges to ground through a 100 Ω NMOS.
The SiP21106, SiP21107, SiP21108 are available in
TSOT23-5L a super thin lead (Pb)-free TSC75-6L and
SC70-5L packages for operation over the industrial operation
range (- 40 °C to 85 °C).
FEATURES
• SC70-5L (2.1 mm x 2.1 mm x 0.95 mm)
• TSOT23-5L (3.05 mm x 2.85 mm x 1.0 mm)
• TSC75-6L package (1.6 mm x 1.6 mm
x 0.55 mm), TSOT23-5L and SC70-5L
Package Options
• 1.0 % output voltage accuracy at 25 °C
• Low dropout voltage: 135 mV at 150 mA
• SiP21106 low noise: 60 µV(rms) (10 Hz to 100 kHz
bandwidth) with 10 nF over full load range
• 35 µA (typical) ground current at 1 mA load
• 1 µA maximum shutdown current at 85 °C
• Output auto discharge at shutdown mode
• Built-in short circuit (330 mA typical) and thermal
protection (160 °C typical)
• SiP21108 adjustable output voltage
• SiP21107 POK Error Flag
• - 40 °C to + 125 °C junction temperature range for
operation
• Uses low ESR ceramic capacitors
• Fixed voltage output 1.2 V to 5 V in 50 mV steps
• Compliant to RoHS Directive 2002/95/EC
APPLICATIONS
• Cellular phones, wireless handsets
•PDAs
• MP3 players
• Digital cameras
• Pagers
• Wireless modem
• Noise-sensitive electronic systems
TYPICAL APPLICATION CIRCUIT
CBypass = 10 nF
BP
EN
GND
V
IN VOUT
4
5
2
3
1
COUT = 1 µF
V
OUT
CIN = 1 µF
VIN
EN
SiP21106
TSOT23-5L/SC70-5LPackage TSC75-6L Package
CBypass = 10 nF
VOUT
NC
V
IN
GND
EN BP
COUT = 1 µF
VOUT
CIN = 1 µF
VIN
EN
SiP21106
RoHS
COMPLIANT
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Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
Vishay Siliconix
SiP21106, SiP21107, SiP21108
TYPICAL APPLICATION CIRCUIT
Notes:
a. Derate 7.6 mW/°C for TSC75-6L package, 5.5 mW/°C for TSOT23-5L and 3.4 mW/°C for SC70-5L package above TA = 70 °C.
b. Device mounted with all leads soldered or welded to multilayer 1S2P PC board.
c. Soldering for 5 s.
Stresses beyond those listed und er "Absolute Maximum Ratings" may cause per manent damage to the device. The se are stress ratings only, and f unctional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating/conditions for exte nded periods may affect devi ce reliability.
TSOT23-5L/SC70-5LPackage
POK
EN
GND
V
IN
V
OUT
C
OUT
= 1 µF
POK
C
IN
=
1
µF
SiP21107
V
OUT
TSC75L-6 Package
V
OUT
NC
V
IN
GND
EN POK
4
5
2
3
1
C
OUT
=1 µF
POK
C
IN
= 1 µF
V
IN
EN
SiP21107
V
OUT
TSC75-6L Package
VOUT
NC
V
IN
GND
EN Adj
COUT = 1 µF
VOUT
CIN= 1 µF
VIN
EN
SiP21108
Ad
j
EN
GND
VINVOUT
4
5
2
3
1
COUT = 1 µF
VOUT
CIN= 1 µF
VIN
EN
SiP21108
TSOT23-5L/SC70-5L Package
ABSOLUTE MAXIMUM RATINGS
Parameter Limit Unit
Input Voltage, VIN to GND - 0.3 to 6.5 V
VEN (See Detailed Description) - 0.3 to 6.5
Output Current (IOUT) Short Circuit Protected
Output Voltage (VOUT)- 0.3 to VIN + 0.3 V
TSC75-6L TSOT23-5L SC70-5L
Package Power Dissipation (PD)a420 305 187 mW
Package Thermal Resistance (θJA)b131 180 294 °C/W
Maximum Junction Temperature, TJ(max) 125
°CStorage Temperature, TSTG - 65 to 150
Lead Temperature, TLc260
RECOMMENDED OPERATING RANGE
Parameter Limit Unit
Input Voltage, VIN 2.2 to 6 V
Operating Ambient Temperature TA- 40 to 85 °C
Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
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Vishay Siliconix
SiP21106, SiP21107, SiP21108
SPECIFICATIONS
Parameter Symbol
Test Conditions Unless Specified
VIN = VOUT(nom) + 1.0 V = VEN
IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF
- 40 °C < TA < 85 °C for full Temp.aUnit M in .b Typ.cMax.b
Input Voltage Range VIN Full 2.2 6 V
Output Voltage Accuracy VOUT
IOUT = 1 mA Room - 1.0 1.0
%
Full - 2.5 2.5
SiP21106/7 (1.2 V) IOUT = 1 mA Room - 1.5 1.5
Full - 4 4
Feedback Voltage
(SiP21108 Version only) VAdj
Room 1.188 1.2 1.212 V
Full 1.170 1.230
Line Regulation LNR Full - 0.2 0.006 0.2 %/V
Load Regulation LDR
VOUT ≥ 2.6 V,
IOUT: 1 mA to 150 mA Room 0.003 0.006
%/mA
VOUT < 2.6 V,
IOUT: 1 mA to 150 mA Room 0.005 0.009
Ground Pin CurrenteIGND
IOUT = 1 mA Room 35 75
µA
Full 85
IOUT = 150 mA Room 39 75
Full 85
Shutdown Supply Current ICC(off) VEN = 0 V Full 0.02 1 µA
Output Noise Voltagef (RMS) eN
SiP21106
VOUT(nom) = 2.8 V, BW = 10 Hz to 100 kHz,
1 mA < IOUT < 150 mA, CBP = 0.01 µF
Room 60
µV
SiP21107/8
VOUT(nom) = 2.8 V, BW = 10 Hz to 100 kHz,
1 mA < IOUT < 150 mA
Room 350
Output Voltage Turn-On Time ton EN to VOUT delay; IOUT = 1 mA 70 µs
Ripple Rejection PSRR
SiP21106, CBP = 0.01 µF
IOUT = 10 mA
f = 1 kHz Room 75
dB
f = 10 kHz Room 56
f = 100 kHz Room 40
SiP21107/8
SiP21106, CBP = 0 µF
IOUT = 10 mA
f = 1 kHz Room 72
f = 10 kHz Room 53
f = 100 kHz Room 38
Output Current Limit IO_LIM VOUT = 0 V Room 170 330 600 mA
Auto Discharge Resistance RDIS
EN = 0 V, VOUT = 1 V Room 100 Ω
For VOUT < 2.2 V, EN = 0 V, VOUT = 1 V Room 120
Dropout Voltaged
(2.2 V ≤ VOUT(nom) < 2.6 V) VDO
IOUT = 50 mA Room 45
mV
Full 55
IOUT = 100 mA Room 90
Full 106
IOUT = 150 mA Room 135 250
Full 160 300
Dropout Voltage
(VOUT(nom) ≥ 2.6 V) VDO
IOUT = 50 mA Room 45
Full 55
IOUT = 100 mA Room 90
Full 106
IOUT = 150 mA Room 135 180
Full 160 220
EN Pin Input Voltage VENH High = Regulator On (Rising) Full 1.2 V
VENL Low = Regulator Off (Falling) Full 0.4
EN Pin Input Current IEN Room 0.009 µA
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Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
Vishay Siliconix
SiP21106, SiP21107, SiP21108
Notes:
a. Room = 25 °C, Full = - 40 to 85 °C. Derate 7.6 mW/°C for TSC75 and 5.5 mW/°C for SOT23 above TA = 70 °C.
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. Dropout voltage is defined as the input-to-output differential voltage at which the output voltage drops 2 % below its nominal
value with constant load. For outputs = 2.2 V, dropout voltage is not applicable due to 2.2 V minimum input voltage requirement.
e. Ground current is specified for normal operation as well as “drop-out” operation.
f. Output noise is proportional to output voltage. Use formula eN = 60 µV(rms)*VOUT/2.8 V.
g. POK threshold percentage is calculated by VIN/VOUT x 100 %. The POK is measured with a differential voltage across VIN and VOUT until POK
turn on (low threshold) or off (high threshold). For VOUT less than 2.2 V, POK is guaranteed functionality only.
TIMING WAVEFORMS
SPECIFICATIONS
Parameter Symbol
Test Conditions Unless Specified
VIN = VOUT(nom) + 1.0 V
IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF
- 40 °C < TA < 85 °C for full Temp.aUnit M i n . b Typ.cMax.b
Thermal Shutdown Junction Temperature TJ(S/D) Room 160 °C
Thermal Hysteresis THYST Room 20
Error Flag Section (SiP21107 Version only)
POK(OFF) Leakage IOFF RPU to VOUT or VIN Full 1 µA
POK(ON) Voltage VPOKL EN = 0 V, IPOK = 0.5 mA Full 0.4 V
POK ThresholdgVPOKLH
VOUT rising, POK goes high
VOUT(nom) ≥ 2.2 V, IOUT = 1 mA Full
90 93 96
%
VOUT rising, POK goes high
VOUT(nom) < 2.2 V, IOUT = 1 mA 91
POK Hysteresis VHYST VIN falling, IOUT = 1 mA, POK goes low Room 1.5
POK Voltage Delay Time TP_Delay VOUT to POK delay, IOUT = 1 mA 40 µs
Figure 1.
VEN
0.95 VNOM
VOUT
VNOM
tON
0 V
VIN
tr 1 µs
Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
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Vishay Siliconix
SiP21106, SiP21107, SiP21108
PIN CONFIGURATION
EN
GND
VV
NC
BP/Adj/POK
INOUT
TOP VIEW
1
2
3
4
5
6
EN
GND
V
V
NC
BP/Adj/POK
IN
OUT
BOTTOM VIEW
TSC75-6L Package (1.6 mm x 1.6 mm x 0.55 mm)
Figure 2.
EN
GND
VV
BP/Adj/POK
IN OUT
1
2
3
4
5
1
2
34
5
TOP VIEW
EN
GND
V
IN
V
BP/Adj/POK
OUT
BOTTOM VIEW
TSOT23-5L/SC70-5LPackage
PIN DESCRIPTION
Pin Number
TSC75-6L
Pin Number
TSOT23-5L/
SC70-5L
Name Function
13EN By applying less than 0.4 V to this pin, the device will be turned off. Connect this pin to
VIN if unused. Do not leave floating.
2 2 GND Ground pin. For better thermal capability, directly connected to large ground plane.
31VIN Input supply pin. Bypass this pin with a 1 µF ceramic or tantalum capacitor to ground.
45
VOUT Output voltage. Connect COUT between this pin and ground.
5 - NC No Connection.
6 4 BP/Adj/POK
- BP (SiP21106): Noise bypass pin. For low noise applications, a 10 nF ceramic capacitor
should be connected from this pin to ground.
- Adj (SiP21108): Adjust input pin. Connect feedback resistors to program the output
voltage for trim value of 1.2005 V.
- POK (SiP21107): Power OK (error flag) pin. Open-drain output, which requires
connecting a pull-up resistor to VIN or VOUT
. POK pin is actively high to indicate an output
normal operation condition on regulator and goes low to indicate under-voltage fault
condition.
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Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
Vishay Siliconix
SiP21106, SiP21107, SiP21108
ORDERING INFORMATION
Part Number Marking Voltage Temperature Range Package
SiP21108DVP-T1-E3 AA Adjustable
- 40 °C to 85 °C TSC75-6L
SiP21106DVP-12-E3 BA 1.2
SiP21106DVP-18-E3 BG 1.8
SiP21106DVP-25-E3 BP 2.5
SiP21106DVP-26-E3 BR 2.6
SiP21106DVP-28-E3 BT 2.8
SiP21106DVP-285-E3 CT 2.85
SiP21106DVP-30-E3 BV 3
SiP21106DVP-33-E3 BY 3.3
SiP21106DVP-46-E3 CM 4.6
SiP21106DVP-475-E3 CU 4.75
SiP21107DVP-12-E3 DA 1.2
SiP21107DVP-18-E3 DG 1.8
SiP21107DVP-25-E3 DP 2.5
SiP21107DVP-26-E3 DR 2.6
SiP21107DVP-28-E3 DT 2.8
SiP21107DVP-30-E3 DV 3
SiP21107DVP-33-E3 DY 3.3
SiP21107DVP-46-E3 EM 4.6
SiP21107DVP-285-E3 ET 2.85
SiP21108DT-T1-E3 N9 Adjustable
- 40 °C to 85 °C TSOT23-5L
SiP21106DT-12-E3 NP 1.2
SiP21106DT-18-E3 N1 1.8
SiP21106DT-25-E3 NA 2.5
SiP21106DT-26-E3 NC 2.6
SiP21106DT-28-E3 N2 2.8
SiP21106DT-285-E3 NE 2.85
SiP21106DT-30-E3 NG 3
SiP21106DT-33-E3 N3 3.3
SiP21106DT-45-E3 NM 4.5
SiP21106DT-46-E3 N4 4.6
SiP21106DT-475-E3 NJ 4.75
SiP21107DT-12-E3 NQ 1.2
SiP21107DT-18-E3 N5 1.8
SiP21107DT-25-E3 NB 2.5
SiP21107DT-26-E3 ND 2.6
SiP21107DT-28-E3 N6 2.8
SiP21107DT-285-E3 NF 2.85
SiP21107DT-30-E3 NH 3
SiP21107DT-33-E3 N7 3.3
SiP21107DT-46-E3 N8 4.6
SiP21106, SiP21107, SiP21108
Vishay Siliconix
Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
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Note:
Other fixed output voltage options are available. Please contact your Vishay sales representative or distributor for details.
SiP21108DR-T1-E3 N9 Adjustable
- 40 °C to 85 °C SC70-5L
SiP21106DR-12-E3 NP 1.2
SiP21106DR-18-E3 N1 1.8
SiP21106DR-25-E3 NA 2.5
SiP21106DR-26-E3 NC 2.6
SiP21106DR-28-E3 N2 2.8
SiP21106DR-285-E3 NE 2.85
SiP21106DR-30-E3 NG 3
SiP21106DR-33-E3 N3 3.3
SiP21106DR-46-E3 N4 4.6
SiP21106DR-475-E3 NJ 4.75
SiP21107DR-12-E3 NQ 1.2
SiP21107DR-18-E3 N5 1.8
SiP21107DR-25-E3 NB 2.5
SiP21107DR-26-E3 ND 2.6
SiP21107DR-28-E3 N6 2.8
SiP21107DR-285-E3 NF 2.85
SiP21107DR-30-E3 NH 3
SiP21107DR-33-E3 N7 3.3
SiP21107DR-46-E3 N8 4.6
ORDERING INFORMATION
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Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
Vishay Siliconix
SiP21106, SiP21107, SiP21108
TYPICAL CHARACTERISTICS
Output Voltage vs. Input Voltage
Dropout Voltage vs. Load Current
Dropout Voltage vs. Temperature
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0123456
VIN
(V)
VOUT
(V)
IOUT = 0 mA
IOUT = 150 mA
SiP21106: 2.8 V
0
20
40
60
80
100
120
140
160
180
0 25 50 75 100 125 150
I
OUT
(mA)
VDO (mV)
TA
= + 85 °C
TA
= + 25 °C
TA
= - 40 °C
SiP21106: 2.8 V
20
40
60
80
100
120
140
160
180
- 40 - 15 10 35 60 85
Temperature (°C)
VDO (mV)
IOUT = 150 mA
IOUT = 100 mA
IOUT = 50 mA
SiP21106: 2.8 V
Output Voltage Accuracy vs. Temperature
Dropout Voltage vs. Input Voltage
Ground Current vs. Temperature
- 1.50
- 1.00
- 0.50
0.00
0.50
1.00
- 40 - 15 10 35 60 85
Temperature (°C)
Deviation (%)
IOUT = 1 mA
SiP21106: 2.8 V
60
80
100
120
140
160
180
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VIN (V)
V
DO
(mV)
IOUT = 150 mA
IOUT = 100 mA
SiP21106: 2.8 V
34
35
36
37
38
39
40
41
- 40 - 15 10 35 60 85
Temperature (°C)
IOUT = 150 mA
IOUT = 1 mA
SiP21106: 2.8 V
SiP21106, SiP21107, SiP21108
Vishay Siliconix
Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
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TYPICAL CHARACTERISTICS
Ground Current vs. Output Current
PSRR
25
30
35
40
45
50
0 25 50 75 100 125 150
IOUT (mA)
IGND (µA)
VIN
= 5.5 V
VIN
= 3.8 V
SiP21106: 2.8 V
0
10
20
30
40
50
60
70
80
10 100 1000 10 000 100 000 1 000 000
Frequency (Hz)
PSRR (dB)
SiP21106
CBP = 10 nF
IOUT = 10 mA
Ground Current vs. Input Voltage at 25 °C
Output Voltage Accuracy vs. Load Current
V
IN
(V)
I
GND
(µA)
I
OUT
= 150 mA
I
OUT
= 1 mA
SiP21106: 2.8 V
0
10
20
30
40
50
0123456
V
OUT
(V)
2.720
2.740
2.760
2.780
2.800
2.820
- 40 - 15 10 35 60 85
Temperature (°C)
IOUT = 1 mA
IOUT = 150 mA
IOUT = 50 mA
SiP21106: 2.8 V
VIN = 3.8 V
Output Noise vs. BP Capacitance
Output Noise (µV)
0 0.001 0.0056 0.01 0.056 0.1
BP Capacitance (µF)
SiP21106: 2.8 V
50
100
150
200
250
300
350
400
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Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
Vishay Siliconix
SiP21106, SiP21107, SiP21108
TYPICAL OPERATING WAVEFORMS
50 µs/DIV
Load Transient Response
200 µs/DIV
Line Transient Response
200 µs/DIV
Line Transient Response
IOUT (100 mA/DIV)
VOUT (50 mV/DIV)
SiP21106: 4.6 V
VIN = 5.5 V
VOUT = 4.6 V
CIN = 1 µF
COUT = 1 µF
CBP = 10 nF
VOUT (10 mV/DIV)
VIN (200 mV/DIV)
AC Coupling
SiP21106: 4.6 V
VIN = 5.0 to 5.5 V
IOUT = 150 mA
C
BP
= 10 nF
V
OUT
= 4.6 V
COUT = 1 µF
CIN = 1 µF
VOUT (10 mV/DIV)
VIN (200 mV/DIV)
AC Coupling
SiP21106: 4.6 V
VIN = 5.0 to 5.5 V
IOUT = 1 mA
CIN = 1 µF
C
BP
= 10 nF
V
OUT
= 4.6 V
COUT = 1 µF
50 µs/DIV
Load Transient Response
200 µs/DIV
Line Transient Response
200 µs/DIV
Line Transient Response
IOUT (100 mA/DIV)
VOUT (50 mV/DIV)
SiP21106: 2.8 V
VIN = 3.8 V
VOUT = 2.8 V
CIN = 1 µF
COUT = 1 µF
CBP = 10 nF
SiP21106: 2.8 V
VIN = 3.8 to 4.8 V
V
OUT
= 2.8 V
IOUT = 150 mA
CIN = 1 µF
COUT = 1 µF
C
BP
= 10 nF
VIN (1 V/DIV)
AC Coupling
VOUT (10 mV/DIV)
VIN (1 V/DIV)
AC Coupling
SiP21106: 2.8 V
VIN = 3.8 to 4.8 V
V
OUT
= 2.8 V
IOUT = 1 mA
CIN = 1 µF
COUT = 1 µF
CBP = 10 nF
VOUT (10 mV/DIV)
SiP21106, SiP21107, SiP21108
Vishay Siliconix
Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
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TYPICAL OPERATING WAVEFORMS
50 ms/DIV
Output Short Circuit Current
20 µs/DIV
Output Voltage Power-Down
20 ms/DIV
POK pin goes low to indicate output under-voltage
fault condition
SiP21106: 2.8 V
VIN = 3.8 V
VOUT = 2.8 V
CIN = 1 µF
COUT = 1 µF
CBP = 10 nF
IOUT (50 mA/DIV)
SiP21106: 2.8 V
VIN = 3.8 V
VOUT = 2.8 V
CIN = 1 µF
C
OUT
= 1 µF
CBP = 10 nF
IOUT = 150 mA
VEN (500 mV/DIV)
VOUT (500 mV/DIV)
SiP21107: 1.8 V
VIN = 2.8 V
V
OUT
= 1.8 V
C
IN
= 1 µF
COUT = 1 µF
CBP = 10 nF
IOUT = 1 mA
POK (1 V/DIV)
VOUT (500 mV/DIV)
50 ms/DIV
Output Short Thermal Cycling
20 µs/DIV
Output Voltage Start-Up
20 ms/DIV
POK pin goes low to indicate output under-voltage
fault condition
SiP21106: 2.8 V
VIN = 3.8 V
VOUT = 2.8 V
CIN = 1 µF
COUT = 1 µF
C
BP
= 10 nF
IOUT (100 mA/DIV)
SiP21106: 2.8 V
VIN = 3.8 V
V
OUT
= 2.8 V
C
IN
= 1 µF
COUT = 1 µF
CBP = 10 nF
IOUT = 150 mA
VOUT (500 mV/DIV)
VEN (1 V/DIV)
SiP21107: 2.8 V
VIN = 3.8 V
V
OUT
= 2.8 V
C
IN
= 1 µF
COUT = 1 µF
CBP = 10 nF
IOUT = 1 mA
VOUT (500 mV/DIV)
POK (1 V/DIV)
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Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
Vishay Siliconix
SiP21106, SiP21107, SiP21108
TYPICAL OPERATING WAVEFORMS
TYPICAL WAVEFORMS
FUNCTIONAL BLOCK DIAGRAM
20 µs/DIV
POK pin is actively high to indicate an output normal
operation condition on regular
SiP21107: 1.8 V
VIN = 2.8 V
V
OUT
= 1.8 V
COUT = 1 µF
CBP = 10 nF
IOUT = 1 mA
VOUT (500 mV/DIV)
POK (1 V/DIV)
C
IN
= 1 µF
20 µs/DIV
POK pin is actively high to indicate an output normal
operation condition on regular
SiP21107: 2.8 V
V
IN
= 3.8 V
COUT = 1 µF
CBP = 10 nF
IOUT = 1 mA
VOUT (500 mV/DIV)
POK (1 V/DIV)
V
OUT
= 2.8 V
C
IN
= 1 µF
2 ms/DIV
Output Noise
SiP21106: 2.8 V
VIN = 4.5 V
VOUT = 2.8 V
CIN = 1 µF
COUT = 1 µF
CBP = 10 nF
IOUT = 150 mA
VOUT (100 µV/DIV)
VNOISE = 60 µVRMS
Output Noise Spectral Density
1
0.01
0.1
Noise Spectral Density (µV/√Hz)
Frequency (Hz)
10K 1M1K10010 100K
COUT = 1 µF
C
BP
= 10 nF
IOUT = 100 mA
V
OUT
= 2.8 V
C
IN
= 1 µF
SiP21106: 2.8 V
V
IN
= 3.8 V
Figure 3.
V
IN
EN
*
** ***
BP/Adj/POK
V
OUT
Enable
Current Limit and
Thermal
Bandgap
Reference
Error-Amp
GND
POK
0.94
SiP21106: BP
SiP21107: POK
SiP21108: Adj
SiP21106: BP
SiP21107: POK
SiP21108: Adj
*
***
**
+
-V
OUT
SiP21106, SiP21107, SiP21108
Vishay Siliconix
Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
www.vishay.com
13
DETAILED DESCRIPTION
As shown in the block diagram, the circuit consists of a
bandgap reference, error amplifier, P-channel pass
transistor and an internal feedback resistor voltage divider,
which is used to monitor and control the output voltage.
A constant 1.2 V bandgap reference voltage is applied to the
non-inverting input of the error amplifier. The error amplifier
compares this reference with the feedback voltage on its
inverting input and amplifies the difference. If the feedback
voltage is lower than the reference voltage, the
pass-transistor gate is pulled low. This increases the
PMOS's gate to source voltage and allows more current to
pass through the transistor to the output which increases the
output voltage. Conversely, if the feedback voltage is higher
than the reference voltage, the pass transistor gate is pulled
high, decreasing the gate-to-source voltage, thereby
allowing less current to pass to the output and causing it to
drop.
Internal P-Channel Pass Transistor
A 0.9 Ω (typical) P-channel MOSFET is used as the pass
transistor for the SiP21106, SiP21107, SiP21108 part series.
The MOSFET transistor offers many advantages over the
more, formerly, common PNP pass transistor designs, which
ultimately result in longer battery lifetime. The main
disadvantage of PNP pass transistors is that they require a
certain base current to stay on, which significantly increases
under heavy load conditions. In addition, during dropout,
when the pass transistor saturates, the PNP regulators
waste considerable current. In contrast, P-channel
MOSFETS require virtually zero-base drive and do not suffer
from the stated problems. These savings in base drive
current translate to lower quiescent current which is typical
around 35 µA as shown in the Typical Characteristics.
Shutdown and Auto-Dischage/No-Discharge
Bringing the EN voltage low will place the part in shutdown
mode where the device output enters a high-impedance
state and the quiescent current is reduced to below 1 µA,
reducing the drain on the battery in standby mode and
increasing standby time. Connect EN pin to input for normal
operation. The output has an internal pull down to discharge
the output to ground when the EN pin is low. The internal pull
down is a 100 Ω typical resistor, which can discharge a 1 µF
in less than 1 ms. Refer to Typical Operating Waveforms for
turn-off waveforms.
Output Voltage Selection
The SiP21106 has fixed voltage outputs that are preset to
voltages from 1.2 V to 4.6 V (see Ordering Information).
The SiP21108 has a user-adjustable output that can be set
through the resistor feedback network consisting of R1 and
R2. R2 range of 100K to 400K is recommended to be
consistent with ground current specification. R1 can then be
determined by the following equation:
Where Vref is typically 1.2005 V. Use 1 % or better resistors
for better output voltage accuracy (see Figure 4).
Current Limit
The SiP21106, SiP21107, SiP21108 include a current limit
block which monitors the current passing through the pass
transistor through a current mirror and controls the gate
voltage of the MOSFET, limiting the output current to 330 mA
(typical). This current limit feature allows for the output to be
shorted to ground for an indefinite amount of time without
damaging the device.
Thermal-Overload Protection
The thermal overload protection limits the total power
dissipation and protects the device from being damaged.
When the junction temperature exceeds TJ = 150 °C, the
device turns the P-channel pass transistor off allowing the
device to cool down. Once the temperature drops by about
20 °C, the thermal sensor turns the pass transistor on again
and resumes normal operation. Consequently, a continuous
thermal overload condition will result in a pulsed output. It is
generally recommended to not exceed the junction
temperature rating of 125 °C for continuous operation.
Noise Reduction in SiP21106
For the SiP21106, an external 10 nF bypass capacitor at BP
pin is used to create a low pass filter for noise reduction. The
startup time is fast, since a power-on circuit pre-charges the
bypass capacitor. After the power-up sequence the
pre-charge circuit is switched to standby mode in order to
save current. It is therefore not recommended to use larger
bypass capacitor values than 50 nF. When the circuit is used
without a capacitor, stable operation is guaranteed.
Figure 4.
Error-Amp
-
+
1.2 V
Reference
V
R
R
OUT
1
2
VIN
R = R x - 1
1 2
V
OUT
V
ref
( )
www.vishay.com
14
Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
Vishay Siliconix
SiP21106, SiP21107, SiP21108
POK Status in SiP21107
The POK comparator monitors the output until the supply
comes up to specified percentage of VIN. This open drain
NMOS output requires an external pull-up resistor to either
VOUT or VIN. The internal NMOS can drive up to 0.5 mA
loads. POK pin is active high to indicate that output is within
percentage tolerance. POK goes low when output is outside
of this tolerance as when in dropout, over current and
thermal shutdown.
APPLICATION INFORMATION
Input/Output Capacitor Selection and Regulator Stability
It is recommended that a low ESR 1 µF capacitor be used on
the SiP21106, SiP21107, SiP21108 input. A larger input
capacitance with lower ESR would improve noise rejection
and line-transient response. A larger input bypass capacitor
may be required in applications involving long inductive
traces between the source and LDO. The circuit is stable with
only a small output capacitor equal to 6 nF/mA (≈ 1 µF at
150 mA) of load. Since the bandwidth of the error amplifier is
around 1 MHz - 3 MHz and the dominant pole is at the output
node, the capacitor should be capacitive in this range, i.e., for
150 mA load current, an ESR < 0.4 Ω is necessary. Parasitic
inductance of about 10 nH can be tolerated. Applying a larger
output capacitor would increase power supply rejection and
improve load-transient response. Some ceramic dielectrics
such as the Z5U and Y5V exhibit large capacitance and ESR
variation over temperature. If such capacitors are used, a
2.2 µF or larger value may be needed to ensure stability over
the industrial temperature range. If using higher quality
ceramic capacitors, such as those with X7R and Y7R
dielectrics, a 1 µF capacitor will be sufficient at all operating
temperatures.
Operating Region and Power Dissipation
An important consideration when designing power supplies
is the maximum allowable power dissipation of a part. The
maximum power dissipation in any application is dependant
on the maximum junction temperature, TJ(max) = 125 °C, the
ambient temperature, TA, and the junction-to-ambient
thermal resistance for the package, which is the summation
of θJ-C, the thermal resistance of the package, and θC-A, the
thermal resistance through the PC board and copper traces.
Power dissipation may be expressed as:
The GND pin of the SiP2110 acts as both the electrical
connection to GND as well as a path for channeling away
heat. Connect this pin to a GND plane to maximize heat
dissipation. Once maximum power dissipation is calculated
using the equation above, the maximum allowable output
current for any input/output potential can be calculated as
PCB Layout
The component placement around the LDO should be done
carefully to achieve good dynamic line and load response.
The input and noise capacitor should be kept close to the
LDO. The rise in junction temperature depends on how
efficiently the heat is carried away from junction-to-ambient.
The junction-to-lead thermal impedance is a characteristic of
the package and is fixed. The thermal impedance between
lead-to-ambient can be reduced by increasing the copper
area on PCB. Increase the input, output and ground trace
area to reduce the junction-to-ambient thermal impedance.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?74442.
P
(max)
= T
(max)
- T
J
θ +
J-C θ C-A
A
I
OUT(max)
=
P
(max)
V -
IN
V
OUT
e1
E1 E
−B−
C
M
0.15 B A
b
e
54
132132
645
e1
E1 E
−B−
C
M
0.15 B A
b
e
D
−C−A1
A2 A
Seating Plane
−A−
C0.08 L
R
R
Q
4xq10.17 Ref
C
Seating Plane
Gauge Plane
L
2
(L1)
4xq1
SOT23-5L Format SOT23-6L Format
Package Information
Vishay Siliconix
Document Number: 72821
29-Jan-04
www.vishay.com
1
THIN SOT-23 : 5- AND 6-LEAD (POWER IC ONLY)
MILLIMETERS INCHES
Dim Min Nom Max Min Nom Max
A0.91 1.00 1.10 0.036 0.039 0.043
A1 0.01 0.05 0.10 0.0004 0.002 0.004
A2 0.90 0.95 1.00 0.035 0.037 0.039
b0.30 0.32 0.45 0.012 0.013 0.018
c0.10 0.15 0.20 0.004 0.006 0.008
D2.90 3.05 3.10 0.114 0.120 0.122
E2.70 2.85 2.98 0.106 0.112 0.117
E1 1.525 1.65 1.70 0.060 0.065 0.067
e0.95 BSC 0.0374 BSC
e1 1.80 1.90 2.00 0.070 0.075 0.080
L0.30 0.40 0.60 0.012 0.016 0.024
L1 0.60 REF 0.024 REF
L2 0.25 BSC 0.010 BSC
R0.10 − − 0.004 − −
Q0_4_8_0_4_8_
Q14_10_ NOM 12_4_10_ NOM 12_
ECN: S-40083—Rev. A, 02-Feb-04
DWG: 5926
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. Controlling dimensions: millimeters converted to inch dimensions are
not necessarily exact.
3. Dimension “D” does not include mold flash, protrusion or gate burr.
Mold flash, protrusion or gate burr shall not exceed 0.15 mm
(0.006 inch) per side.
4. The package top shall be smaller than the package bottom.
Dimension “D” and “E1” are determined at the outer most extremes
of the plastic body exclusive of mold flash, tie bar burrs, gate burrs
and interlead flash, but including any mismatch between the top and
bottom of the plastic body.
C0.15 (0.006)
D
eB
D
e1
N5 N4 N3
N1 N2
E
E/2
b
Pin 1
E/1
E1/2
C0.15 (0.006)
C0.10 (0.004) MA BC
C0.10 (0.004)
A
C
SEATING
PLANE
A1
A2
SECTIION A-A
Base Metal
(b)
b1
c1 c
A A
DETAIL A
See Detail A
GAGE PLANE
0.15 (0.0059)
H
LU
U1
Package Information
Vishay Siliconix
Document Number: 73201
19-Nov-04
www.vishay.com
1
SC-70: 3/4/5/6-LEADS (PIC ONLY)
Pin LEAD COUNT
Pin
Code 3 4 5 6
N1 − − 2 2
N2 2 2 3 3
N3 −3 4 4
N4 3− − 5
N5 −4 5 6
Package Information
Vishay Siliconix
www.vishay.com
2Document Number: 73201
19-Nov-04
MILLIMETERS INCHES
Dim Min Nom Max Min Nom Max
A0.80 −1.10 0.031 −0.043
A1 0.00 −0.10 0.000 −0.004
A2 0.80 0.90 1.00 0.031 0.035 0.040
b0.15 −0.30 0.006 −0.012
b1 0.15 0.20 0.25 0.006 0.008 0.010
c0.08 −0.25 0.003 −0.010
c1 0.08 0.13 0.20 0.003 0.005 0.008
D1.90 2.10 2.15 0.074 0.082 0.084
E2.00 2.10 2.20 0.078 0.082 0.086
E11.15 1.25 1.35 0.045 0.050 0.055
e0.65 BSC 0.0255 BSC
e11.30 BSC 0.0512 BSC
L0.26 0.36 0.46 0.010 0.014 0.018
U0_−8_0_−8_
U1 4_10_4_10_
ECN: S-42145—Rev. A, 22-Nov-04
DWG: 5941
Vishay Siliconix
Package Information
Document Number: 74416
02-Oct-06
www.vishay.com
1
DIM
MILLIMETERS INCHES
Min Nom Max Min Nom Max
A 0.50 0.55 0.65 0.020 0.022 0.026
A1 0 - 0.05 0 - 0.002
b 0.20 0.25 0.30 0.008 0.010 0.012
C 0.10 0.15 0.20 0.006 0.008 0.010
D 1.55 1.60 1.65 0.0061 0.063 0.065
D1 0.95 1.00 1.05 0.037 0.039 0.041
E 1.55 1.60 1.65 0.061 0.063 0.065
E1 0.55 0.60 0.65 0.022 0.024 0.026
e 0.50 BSC 0.020 BSC
e1 1.00 BSC 0.039 BSC
K 0.15 - - 0.006 - -
K2 0.20 - - 0.008
L 0.20 0.25 0.30 0.008 0.010 0.012
ECN: S-61919-Rev. A, 02-Oct-06
DWG: 5955
PowerPAK TSC75-6L (Power IC only)
®
Top View
Pin 1 Dot
By Marking
PPAK TSC75
(1.6 x 1.6 mm)
K2 K2
Bottom View
e1
Side View
A
A1
C
D
E
e
b
D1
Exposed pad
E1
Exposed pad
K
K
Pin3 Pin 2 Pin1
L
Pin4 Pin 5 Pin6
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Revision: 12-Mar-12 1Document Number: 91000
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