General Description
The MAX8686 current-mode, synchronous PWM step-
down regulator with integrated MOSFETs operates from
a 4.5V to 20V input supply and generates an adjustable
output voltage from 0.7V to 5.5V while delivering up to
25A per phase.
The MAX8686 employs a peak current-mode architec-
ture that operates with an adjustable switching frequency
from 300kHz to 1MHz. An adjustable current-limit thresh-
old allows for optimization for different applications with
different load currents. Inductor current sense is
achieved either using an external sense resistor or using
a lossless inductor current-sense scheme. The foldback
and hiccup current limit reduces the power dissipation
during overload or short-circuit conditions and allows for
autorecovery when the fault condition is removed.
The MAX8686 offers the ability to start up monotonically
even when there is a prebias output voltage. In addi-
tion, an adjustable soft-start capability allows for a con-
trolled turn-on. The MAX8686 features an accurate 1%
reference and offers a reference input that allows for a
higher accuracy reference to be used for voltage track-
ing applications such as DDR memory.
The MAX8686 can be paralleled (up to eight) together
in a true multiphase mode to deliver up to 200A of out-
put current. When operating in this mode, this device
achieves better than 10% current balance between
phases at full load. The MAX8686 supports program-
mable phase shedding to improve system efficiency
during light load conditions.
Other features include an enable input and a power-OK
(POK) indicator used for power sequencing. The
MAX8686 also features latch overvoltage protection
that turns on the low-side MOSFET when the output
voltage exceeds 120% of the nominal voltage. The
MAX8686 is offered in a thermally enhanced 40-pin,
6mm x 6mm TQFN package.
Applications
POL Power Supplies
Module Replacements
Telecom Equipment
Networking Equipment
Servers
DDR Memory
Features
oOperating Range from 4.5V to 20V Input Supply
o1% Reference Voltage Accuracy Over Temperature
oReference Input (REFIN) for Output Tracking or
System Reference Voltage
oAdjustable Switching Frequency from 300kHz
to 1MHz
oSingle/Multiphase Operation Delivers Up to
25A/200A with Integrated MOSFETs
oAdjustable Current Limit
oMonotonic Output Voltage at Startup (Prebias)
oOutput Sink and Source Current Capability
oAdjustable Soft-Start
oThermal-Overload Protection
oOutput Overvoltage Protection
oThermally Enhanced 6mm x 6mm TQFN
Package (4W)
MAX8686
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
________________________________________________________________
Maxim Integrated Products
1
IN
POK
OUTPUT
ENABLE
INPUT
BST
LX
VIN = 12V
VOUT = 1.2V/25A
PGND
PHASE/REFO
COMP
EN/SLOPE
FREQ SS GND ILIM
MAX8686
REFIN RS+
RS-
CS+
CS-
POK
Typical Application Circuit
Ordering Information
19-4113; Rev 1; 10/10
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
PART TEMP RANGE
PIN-PACKAGE
MAX8686ETL+ -40°C to +85°C 40 TQFN-EP*
+
Denotes a lead-free package.
*
EP = Exposed pad.
Pin Configuration appears at end of data sheet.
MAX8686
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VIN = VINA = 12V, VL = AVL, VREFIN = 1V, VRS+ - VRS- = 1V, VRS- = 0V, VEN/SLOPE = 1.25V, VCS+ = VCS- = 1V, RILIM = 122kΩ, CVL = 1μF,
CAVL = 0.22μF, CFREQ = 270pF, TA= +25°C, unless otherwise noted.) (Note 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
IN, INA to PGND.....................................................-0.3V to +22V
BST, DH to LX...........................................................-0.3V to +6V
BST to PGND..........................................................-0.3V to +28V
LX to PGND...........................-0.3V to (VIN + 0.3V) (-2V for 50ns)
BST to VL................................................................-0.3V to +22V
AVL to GND.................................................-0.3V to (VVL + 0.3V)
COMP, ILIM, FREQ, PHASE/REFO, RS+, RS-, POK, REFIN,
CS+, CS- to GND ..................................-0.3V to (VAVL + 0.3V)
VL to PGND ..............................................................-0.3V to +6V
EN/SLOPE to GND ...................................................-0.3V to +6V
RTN to PGND to GND to GFREQ ..........................-0.3V to +0.3V
IN Continuous Current.....................................................20ARMS
LX Continuous Current ....................................................25ARMS
Continuous Power Dissipation (TA= +70°C) (Note 1)
40-Pin TQFN (derate 50mW/°C above +70°C) ..........4000mW
θJC (thermal resistance from junction to exposed pad)
(Note 1) ......................................................................3.5°C/W
θJT (thermal resistance from junction to top) (Note 1) ...3.9°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
PARAMETER CONDITIONS MIN TYP MAX UNITS
GENERAL
Operating Input-Voltage Range VINA = VIN , TA = -40°C to +85°C 6 20 V
Operating Input-Voltage Range VIN = VINA = VVL = VAVL, TA = -40°C to +85°C 4.5 5.5 V
TA = +25°C 450
IN/INA Shutdown Supply Current VEN/SLOPE = 0V,
VIN = VINA = 20V TA = +85°C 500 μA
IN/INA Quiescent Supply Current VRS+ = 1.1V, no switching; VIN = VINA = 20V,
TA = -40°C to +85°C 5.5 6.6 mA
Rising, TA = -40°C to +85°C 4.2 4.35 4.45
AVL Undervoltage Lockout Trip
Level Falling 4.03 V
VL Output Voltage 6V ≤ VIN = VINA ≤ 20V, 1mA ≤ IVL ≤ 30mA,
TA = -40°C to +85°C 5.2 5.4 5.5 V
SOFT-START (SS)
SS Shutdown Resistance VEN/SLOPE = 0V (master mode) 20 100 Ω
SS Soft-Start Current VSS = 0.4V and 1.1V, TA = -40°C to +85°C 19 25 31 μA
PHASE COMPARATOR AND REFERENCE (PHASE/REFO)
Reference Output Voltage Measured at PHASE/REFO (master mode),
TA = -40°C to +85°C 3.267 3.300 3.333 V
PHASE Comparator Offset VRS- = VAVL (slave mode), VPHASE = 0.3V and 2.5V,
TA = -40°C to +85°C -20 +20 mV
REFIN INPUT
REFIN Input Bias Current VREFIN = 0.7V or 3.3V -500 +500 nA
REFIN Input Voltage Range 0 3.3 V
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations see www.maxim-ic.com/thermal-tutorial.
MAX8686
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VINA = 12V, VL = AVL, VREFIN = 1V, VRS+ - VRS- = 1V, VRS- = 0V, VEN/SLOPE = 1.25V, VCS+ = VCS- = 1V, RILIM = 122kΩ, CVL = 1μF,
CAVL = 0.22μF, CFREQ = 270pF, TA= +25°C, unless otherwise noted.) (Note 2)
PARAMETER CONDITIONS MIN TYP MAX UNITS
ERROR AMPLIFIER
VREFIN = 3.3V 3.267 3.3 3.333
Remote-Sense Accuracy
(Including Error Amplifier Offset)
Measure as VRS+ - VRS-
(TA = -40°C to +85°C) VREFIN = 0.7V 0.693 0.7 0.707 V
Transconductance TA = -40°C to +85°C 1.1 1.7 2.6 mS
COMP Source Current VRS+ - VRS- = 1.3V 220 300 μA
COMP Sink Current VRS+ - VRS- = 0.7V 220 300 μA
COMP Shutdown Resistance VEN/SLOPE = 0V 20 100 Ω
RS+/RS- Input Leakage Current 0.2 1.5 μA
RS+ Input Common-Mode Range VIN = VINA = VVL = VAVL = 4.5V, VRS- = 100mV 0 3.4 V
RS- Input Common-Mode Range -100 +100 mV
CURRENT-SENSE AMPLIFIER
Input Offset Voltage Measure at CS+ and CS-, VCS+ = VCS- = 0.7V and 5.5V
(TA = -40°C to +85°C) -1.5 +1.5 mV
Current-Sense Amplifier Gain VCS- = 0 to 5V, VCS+ - VCS- = 30mV,
TA = -40°C to +85°C 29.0 30.5 32.0 V/V
Input Bias Current VCS+ = VCS- = 5.5V and 0V -4 +4 μA
CURRENT LIMIT
ILIM Output Current VILIM = 2V, TA = -40°C to +85°C 9 10 11 μA
RILIM = 122kΩ16 20 23
Current-Limit Threshold Measure as VCS+ - VCS-
(TA = -40°C to +85°C) RILIM = 275kΩ38 45 52 mV
COMP Clamp Voltage High RILIM = 275kΩ, VREFIN = 3.3V, VRS+ - VRS- = 2V 3.6 3.8 4.0 V
COMP Clamp Voltage Low VREFIN = 3.3V, VRS+ - VRS- = 3.35V 0.54 0.6 0.66 V
Maximum Peak Positive Current
Threshold RILIM = 275kΩ, no slope compensation 54 mV
MAX8686
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VINA = 12V, VL = AVL, VREFIN = 1V, VRS+ - VRS- = 1V, VRS- = 0V, VEN/SLOPE = 1.25V, VCS+ = VCS- = 1V, RILIM = 122kΩ, CVL = 1μF,
CAVL = 0.22μF, CFREQ = 270pF, TA= +25°C, unless otherwise noted.) (Note 2)
Note 2: Specifications to TA= -40°C are guaranteed by design and not production tested.
PARAMETER CONDITIONS MIN TYP MAX UNITS
OSCILLATOR (FREQ)
Source Current VFREQ = 2V, TA = -40°C to +85°C 480 500 520 μA
CFREQ = 180pF 0.8 1 1.2 MHz
Switching Frequency CFREQ = 580pF 240 300 360 kHz
Minimum On-Time 100 ns
FREQ Discharge Resistance 10 50 Ω
Ramp Peak Voltage 2.60 VAVL/2 2.85 V
SLOPE COMPENSATION (EN/SLOPE)
VSLOPE Range 1.25 2.50 V
SLOPE Source Current 81012μA
THERMAL PROTECTION
Thermal Shutdown Rising temperature 160 °C
Thermal-Shutdown Hysteresis 30 °C
POWER-OK (POK)
VOUT rising 87 90 93
POK Threshold VOUT falling 87 %VOUT
POK Output Voltage Low VRS+ - VRS- = 0.8V, IPOK = 2mA 25 200 mV
POK Leakage Current VPOK = 5.5V 0.001 1 μA
OVERVOLTAGE OUTPUT PROTECTION (OVP)
Overvoltage Fault Trip Level VREFIN = 3.3V, VRS+ rising, percentage of VOUT in
regulation 115 120 125 %
ENABLE (EN/SLOPE)
EN Logic-High 1.2 V
EN Logic-Low 0.7 V
BST
Internal PMOS On-Resistance 8Ω
MAX8686
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
_______________________________________________________________________________________ 5
SINGLE-PHASE EFFICIENCY
vs. LOAD CURRENT
MAX8686 toc01
LOAD CURRENT (A)
EFFICIENCY (%)
20155 10
77.5
80.0
82.5
85.0
90.0
87.5
92.5
95.0
75.0
025
VOUT = 3.3V
VOUT = 1.8V
VOUT = 2.5V
AIRFLOW = 300 LFM
SINGLE-PHASE EFFICIENCY
vs. LOAD CURRENT (VIN = 5V)
MAX8686 toc02
LOAD CURRENT (A)
EFFICIENCY (%)
20155 10
77.5
80.0
82.5
85.0
90.0
87.5
92.5
95.0
75.0
025
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
CIRCUIT OF FIGURE 3
AIRFLOW = 300 LFM
EFFICIENCY vs. LOAD CURRENT
MAX8686 toc03
LOAD CURRENT (A)
EFFICIENCY (%)
17148 11
80
81
82
83
85
84
86
87
79
520
270kHz
379kHz
467kHz
564kHz
AIRFLOW = 300 LFM
SWITCHING FREQUENCY
vs. CFREQ CAPACITANCE
MAX8686 toc04
CFREQ CAPACITANCE (pF)
SWITCHING FREQUENCY (kHz)
650600500 550200 250 300 350 400 450150
300
400
500
600
700
800
900
1000
1100
1200
1300
200
100 700
CLOSED-LOOP FREQUENCY RESPONSE
(IOUT = 160A, 8 PHASES)
FREQUENCY (kHz)
GAIN (dB)
10 100
-40
-30
-20
-10
0
10
20
30
40
50
-50
PHASE (DEGREES)
-144
-108
-72
-36
0
36
72
108
144
180
-180
11k
MAX8686 toc05
PHASE
GAIN
OUTPUT VOLTAGE vs. OUTPUT CURRENT
MAX8686 toc06
OUTPUT CURRENT (A)
OUTPUT VOLTAGE (V)
20155 10
1.2005
1.2010
1.2015
1.2020
1.2030
1.2025
1.2035
1.2040
1.2000
025
AIRFLOW = 300 LFM
OUTPUT VOLTAGE vs. INPUT VOLTAGE
MAX8686 toc07
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
19181716151413121110987
1.20
1.25
1.30
1.15
620
IOUT = 10A
OUTPUT LOAD TRANSIENT
MAX8686 toc08
100μs/div
VOUT
200mV/div
AC-COUPLED
IOUT
42A/div
CIRCUIT OF FIGURE 4
AIRFLOW = 300 LFM
SOFT-START WITH EN CONTROL
(IOUT = 10A)
MAX8686 toc09
1ms/div
EN
2V/div
SS
2V/div
POK
5V/div
VOUT
500mV/div
CIRCUIT OF FIGURE 4
Typical Operating Characteristics
(VIN = 12V, fSW = 500kHz, single phase, circuit of Figure 2, unless otherwise noted.)
MAX8686
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VIN = 12V, fSW = 500kHz, single phase, circuit of Figure 2, unless otherwise noted.)
SOFT-START WITH EN CONTROL
(IOUT = 10A)
MAX8686 toc10
1ms/div
EN
2V/div
SS
2V/div
POK
5V/div
VOUT
500mV/div
CIRCUIT OF FIGURE 4
SHUTDOWN WITH EN CONTROL
(IOUT = 10A)
MAX8686 toc11
200μs/div
EN
2V/div
SS
5V/div
POK
5V/div
VOUT
500mV/div
CIRCUIT OF FIGURE 4
SHUTDOWN WITH EN CONTROL
(IOUT = 100A)
MAX8686 toc12
200μs/div
EN
2V/div
SS
5V/div
POK
5V/div
VOUT
500mV/div
CIRCUIT OF FIGURE 4
SHORT-CIRCUIT PROTECTION
MAX8686 toc13a
400μs/div
IOUT
42A/div
SS
500mV/div
POK
5V/div
VOUT
500mV/div
SHORT-CIRCUIT RECOVERY
MAX8686 toc13b
400μs/div
IOUT
42A/div
SS
500mV/div
POK
5V/div
VOUT
500mV/div
CURRENT-SHARING ACCURACY
MAX8686 toc14
LOAD CURRENT (A)
PHASE CURRENT (A)
130120100110
30 40 50 60 70 80 9010 20
2.5
5.0
7.5
10.0
12.5
15.0
17.5
20.0
22.5
25.0
0
0
140
CIRCUIT OF FIGURE 4
AIRFLOW = 300 LFM
LX_ SWITCHING WAVEFORM FOR
PHASES 1, 2, 3, AND 4
MAX8686 toc15
200ns/div
LX1
5V/div
LX2
5V/div
LX3
5V/div
LX4
5V/div
CIRCUIT OF FIGURE 4
PHASE SHEDDING FROM 6 PHASES
TO 2 PHASES (IOUT = 30A)
MAX8686 toc18
1μs/div
PS
2V/div
LX1
10V/div
LX5
10V/div
LX2
10V/div
CIRCUIT OF FIGURE 4
MAX8686
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
_______________________________________________________________________________________ 7
PHASE RECOVERY FROM 2 PHASES
TO 6 PHASES (IOUT = 30A)
MAX8686 toc19
1μs/div
PS
2V/div
LX1
10V/div
LX5
10V/div
LX2
10V/div
CIRCUIT OF FIGURE 4
SAFE OPERATING AREA
MAX8686 toc20
AMBIENT TEMPERATURE (°C)
IOUT (A)
807565 7035 40 45 50 55 6030
11
13
15
17
19
21
23
25
9
25 85
400 LFM
300 LFM
200 LFM
100 LFM
0 LFM
TJ = +125°C, VOUT = 1.2V
SAFE OPERATING AREA
MAX8686 toc21
AMBIENT TEMPERATURE (°C)
IOUT (A)
807565 7035 40 45 50 55 6030
11
13
15
17
19
21
23
25
9
25 85
400 LFM
300 LFM
200 LFM
100 LFM
0 LFM
TJ = +125°C, VOUT = 3.3V
LX_ SWITCHING WAVEFORM FOR
PHASES 4, 5, 6, AND 1
MAX8686 toc16
200ns/div
LX4
5V/div
LX5
5V/div
LX6
5V/div
LX1
5V/div
CIRCUIT OF FIGURE 4
REFO OUTPUT vs. TEMPERATURE
MAX8686 toc17
TEMPERATURE (°C)
REFO OUTPUT (V)
80706050403020100-10-20-30
3.28
3.29
3.30
3.31
3.32
3.33
3.27
-40 90
Typical Operating Characteristics (continued)
(VIN = 12V, fSW = 500kHz, single phase, circuit of Figure 2, unless otherwise noted.)
MAX8686
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
8 _______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1 CS- Negative Differential Current-Sense Input. Connect CS- to the output side of the inductor for lossless
current sense or to the load side of the current-sense resistor.
2 CS+ Positive Differential Current-Sense Input. Connect CS+ to the inductor through an RC network for
lossless current sense or to the inductor side of the current-sense resistor.
3 GFREQ CFREQ Capacitor Return Terminal. Connect the frequency-setting capacitor CFREQ to GFREQ as close
as possible to the device.
4 EN/SLOPE
Enable and Slope Compensation Input. Connect a resistor from EN/SLOPE to GND to set the desired
slope compensation ramp voltage. An internal 10μA current source pulls up EN/SLOPE. The device
shuts down when the voltage at EN/SLOPE is less than 0.7V. Connect EN/SLOPE to an open-drain or
open-collector output for system enable or phase-shedding function.
5, 16 LX Inductor Connection. LX is high impedance during shutdown.
6 RTN Power Ground for Low-Side Gate Driver. Connect RTN to PGND plane at the return terminal of the IN
bypass capacitor.
7–15 PGND Power Ground. Low-side MOSFET source connection.
17 N.C. No Connection. Not internally connected.
18–26 IN Power Input. Connect IN to the input voltage source. Connect input bypass capacitor from IN to PGND
as close as possible to the device. Connect IN, INA, and VL together for 5V operation (see Figure 3).
27 INA Input of the Internal VL Linear Regulator. Bypass INA with a 0.1μF capacitor to PGND.
28 GND Analog Ground
29 AVL Input Voltage to the Device’s Internal Analog Circuitry. Connect AVL to VL through a lowpass RC filter.
30 VL
Internal 5.4V Linear Regulator Output. Connect a ceramic capacitor of at least 1μF from VL to RTN. INA
is the input to this linear regulator. Connect VL to INA when VINA is less than 5.5V. VL provides power
for the MOSFET drivers.
31 BST Boost Capacitor Connection. Connect a 0.22μF ceramic capacitor from BST to LX.
32 POK
Power-Good Output. POK is an open-drain output that is high impedance when the output voltage is at
its nominal regulated voltage. The POK rising threshold is 90% of the reference voltage at REFIN. POK
is internally pulled low during shutdown. Connect POK to GND for slave mode operation.
MAX8686
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
_______________________________________________________________________________________ 9
Pin Description (continued)
PIN NAME FUNCTION
33 FREQ
Frequency-Setting Input. Connect a capacitor from FREQ to GFREQ to set the switching frequency.
The triangle ramp runs between 0 and AVL/2. In multiphase applications, connect FREQ of the master
and all slave devices together. FREQ is internally pulled to GFREQ during shutdown.
34 SS
Soft-Start Input. For master-mode or single-phase operation, connect a capacitor from SS to GND to
set the soft-start time. A 25μA internal current source charges the capacitor. SS is pulled to GND in
shutdown. Connect SS to GND for slave mode operation.
35 ILIM
Analog Programmable Current Limit. Connect a resistor from ILIM to GND to set the current limit. A
10μA current source through this resistor sets the current-limit threshold. In multiphase applications,
connect ILIM of the master and all slave devices together.
36 REFIN
Voltage Error-Amplifier Reference Input. For master-mode or single-phase operation, connect REFIN to
PHASE/REFO through a resistor-divider to set the output voltage from 0 to 3.3V. To use an external
reference, connect REFIN to the system reference voltage, and use an RC network at REFIN to
implement soft-start if the external reference does not provide this function. Connect REFIN to GND for
slave mode operation.
37 P H AS E /RE FO
Phase Selection Input/Reference Voltage Output. For single-phase or master-mode operation, the 3.3V
output with 1% accuracy can be used as a reference voltage. For multiphase operation, connect
PHASE/REFO of each slave device to the center tap of a resistor-divider from the master AVL to GND.
The resistor values are selected to set phase delay between phases. The PWM cycle starts 60ns after
the rising edge of VFREQ crosses VPHASE.
38 COMP
Compensation and Output of the Voltage-Error Amplifier. Connect a Type II compensation network at
COMP. COMP is internally pulled to GND in shutdown. In multiphase applications, connect COMP of
the master and all slave devices together.
39 RS+
Positive Input of the Output-Voltage Remote Sense. For master-mode or single-phase operation,
connect RS+ to the output-voltage sense point at the load. Connect RS+ to AVL (slave) for slave mode
operation.
40 RS- Negative Input of the Output-Voltage Remote Sense. For master-mode or single-phase operation,
connect RS- to the remote ground at the load. Connect RS- to AVL (slave) for slave mode operation.
— GND_EP Ground Exposed Paddle. Connect GND_EP to GND.
— IN_EP Input Exposed Paddle. Connect IN_EP to IN.
— LX_EP LX Exposed Paddle. Connect LX_EP to LX.
MAX8686
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
10 ______________________________________________________________________________________
VL
500μA
S2
TO S4
PGND
RTN
10μA
LX
IN
LEVEL
SHIFT
BST
INA
UVLO
THERMAL
SHDN
RAMP
GENERATOR
5.4V LDO
GENERATOR
PWM
CONTROL
LOGIC
CURRENT-LIMIT
CONTROL LOGIC
VOLTAGE
REFERENCE
SLAVE MODE
DETECTION
SLAVE MODE = S1, S2, S3, S5, S6 OPEN
MASTER MODE = S1, S2, S5, S6 CLOSE
10μA
AVL
FREQ
UV
OV
PHASE/REFO
VREF
SOFT-START
CIRCUITRY
EN/SLOPE
EN/SLOPE
VL
AVL
SS
S6
CLOCK
GENERATOR
0.9
1.2
REFIN FB
POK
EN/SLOPE
gM
ERROR
AMPLIFIER PWM
COMPARATOR
PEAK CURRENT-
LIMIT COMPARATOR
S1
S3
S4
AVL
AVL
S5
VSUM
REFIN
RS+
RS-
FB
COMP
CS+
CS-
SLOPE
COMP
1/2
CURRENT-
SENSE
AMPLIFIER
30.5
30.5
ILIM
GND
MAX8686
GFREQ
Functional Diagram
Detailed Description
DC-DC Converter Control Architecture
The MAX8686 step-down regulator uses a PWM, cur-
rent-mode control scheme. An internal transconduc-
tance amplifier establishes an integrated error voltage.
The heart of the PWM controller is a PWM comparator
that compares the integrated voltage-feedback signal
against the amplified current-sense signal plus an
adjustable slope-compensation ramp, which is
summed with the current signal to ensure stability. At
each rising edge of the internal clock, the internal high-
side MOSFET turns on until the PWM comparator trips
or the maximum duty cycle is reached. During this on-
time, current ramps up through the inductor, storing
energy in the inductor while sourcing current to the
output. The current-mode feedback system regulates the
peak inductor current as a function of the output-voltage
error signal. The circuit acts as a switch-mode transcon-
ductance amplifier and pushes an output LC filter pole
normally found in a voltage-mode PWM to a higher fre-
quency. See the
Functional Diagram
.
During the second half of the cycle, the internal high-side
MOSFET turns off and the internal low-side MOSFET
turns on. The inductor releases the stored energy as the
current ramps down, providing current to the load. The
output capacitor stores charge when the inductor cur-
rent exceeds the required load current and discharges
when the inductor current is lower, smoothing the volt-
age across the load. Under soft-overload conditions,
when the peak inductor current exceeds the selected
current limit (see the
Current-Limit Circuit
section), the
high-side MOSFET is turned off immediately and the
low-side MOSFET is turned on and remains on to let the
inductor current ramp down until the next clock cycle.
Under severe-overload or short-circuit conditions, the
foldback/hiccup current limit is enabled to reduce
power dissipation.
The MAX8686 operates in a forced-PWM mode. The
converter maintains a constant switching frequency,
regardless of load, to allow for easier filtering of the
switching noise.
Internal Linear Regulator (VL)
The MAX8686 contains an internal LDO regulator that
provides a 5.4V supply for the MOSFET gate drivers.
Connect at least a 1μF ceramic capacitor from VL to
RTN. VL also provides power to the internal analog cir-
cuit through AVL. Connect an RC lowpass filter (R =
10Ω, C = 0.22μF) from VL to AVL.
Undervoltage Lockout
When AVL drops below 4.03V, the MAX8686 assumes
that the supply voltage is too low to make valid deci-
sions, so the undervoltage-lockout (UVLO) circuitry
inhibits switching and turns off both power MOSFETs.
When AVL rises above 4.35V, the regulator enters the
startup sequence and then resumes normal operation.
When operating in a multiphase configuration, the AVL
of all the devices must exceed the UVLO threshold
before any switching begins. This is achieved through
the shared ILIM pin, which is pulled low in UVLO.
Startup, Soft-Start, and Prebias Operation
The internal soft-start circuitry gradually ramps up the
reference voltage in order to control the rate of rise of
the output voltage and reduce input surge currents dur-
ing startup. The soft-start time is determined by the
value of the capacitor from SS to GND and is approxi-
mately equal to 50ms per microfarad of the capacitor.
In addition, the MAX8686 features monotonic output-
voltage rise (prebias); therefore, both power MOSFETs
are kept off if the voltage between the remote sense
input (RS+, RS-) is higher than the voltage at REFIN.
This allows the MAX8686 to start up into a prebiased
output without pulling the output voltage down.
Before the MAX8686 can begin the soft-start and
power-up sequence, the following conditions must be
met: AVL exceeds the 4.35V UVLO threshold, EN is at
logic-high, and the thermal limit is not exceeded.
Reference Output
(PHASE/REFO)/Reference Input (REFIN)
The reference voltage REFO can be used to set the out-
put voltage by scaling this voltage down with a resistive
divider and using it as the input voltage to the reference
input, REFIN. The 3.3V reference voltage is 1% accurate
over temperature and can source up to 20μA.
The reference input REFIN allows the reference value of
the device to be set by an external reference. In most
applications, the 3.3V voltage with 1% accuracy from
the PHASE/REFO pin should be used as the reference.
This can be achieved by dividing the 3.3V voltage to
the desired output voltage.
MAX8686
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
______________________________________________________________________________________ 11
MAX8686
For using an external reference on REFIN, SS needs to
be tied to REFIN either directly or indirectly through a
resistor for soft-start. For REFIN voltage lower than
1.25V, connect a resistor between SS and REFIN such
that the voltage drop across the resistor due to the soft-
start current (31μA max) coming out of SS, causing the
final SS voltage to be at least 1.25V (see Figure 1a).
The external reference should be able to sink at least
31μA. Calculate RREFIN as follows:
where VEXT is the external reference voltage.
In a multiphase converter, only REFIN of the master
device is connected to a reference voltage, and the
REFIN of all slave devices should be tied to GND.
The REFIN also allows for coincident voltage tracking of
multiple converters during power-up/power-down by
applying the same voltage on REFIN of the master
device in each converter.
Enable, Phase Shedding, and
Slope Compensation Input (EN/SLOPE)
An internal 10μA current source pulls the EN/SLOPE
input high. The device shuts down when the voltage at
the EN/SLOPE falls below 0.7V. By connecting an
open-drain or open-collector switch to the EN/SLOPE,
this pin can be used to enable/disable a single-phase
or multiphase converter system.
A separate system signal can be used to shed some
phases of the converter at light load to eliminate all the
power loss from these phases and thus improve the sys-
tem efficiency. The phase shedding signal is connected
to the EN/SLOPE pins of the slave devices to be shed.
The right timing of the phase shedding signal from the
system is critical for the safe operation of the multiphase
converter. Only after the load current drops below a cer-
tain level, should the phase shedding signal become
high. When the open-drain or open-collector switch is
logic-low, it shuts down the slave phases connected to
the switch to reduce power loss. Before the load current
increases to a certain level, the phase shedding signal
should become logic-high to release the EN/SLOPE of
these slave devices, thus turning these phases back on
again to prepare for the higher load current. A minimum
load of 2A per phase in the remaining phases is
required for the shedded phase(s) to turn on.
The transfer function of the power stage is different with a
different number of phases. As the number of phases
increases, the power stage gain increases. The compen-
sation network should be designed such that the convert-
er is always stable with the maximum number of phases.
The EN/SLOPE input is also used to set the slope com-
pensation ramp voltage by connecting a resistor from this
input to GND. The slope compensation is used to stabi-
lize the converters when the duty cycle is more than 40%.
High-Side Gate-Drive Supply (BST)
A flying capacitor between BST and LX generates the
gate-drive voltage for the internal high-side n-channel
MOSFET. When the low-side MOSFET is turned on, the
capacitor is charged by VL to 5.4V minus the drop
across the internal boost switch. When the low-side
MOSFET is turned off, the stored voltage of the capaci-
tor is stacked above LX to provide the necessary turn-
on voltage (VGS) for the high-side MOSFET. An internal
switch between BST and the internal high-side MOSFET’s
gate closes to turn the MOSFET on.
Current-Sense Amplifier
The current-sense circuit amplifies the differential current-
sense voltage (VCS+ - VCS-). This amplified current-sense
signal and the internal-slope-compensation signal are
summed (VSUM) together and fed into the PWM com-
parator’s inverting input. The high-side MOSFET is turned
on by the clock in the device and is shut off when VSUM
exceeds the error-amplifier output voltage (VCOMP) at
the noninverting input of the PWM comparator. The dif-
ferential current sense is also used to provide peak
inductor current limiting. The limit can be set by adjust-
ing the analog current-limit input (ILIM).
The current-sense amplifier is used to measure the cur-
rent across the inductor by connecting to the inductor
through an RC network for lossless current sensing or
connecting to a current-sense resistor for higher accu-
racy. The input common-mode voltage range of the
current-sense amplifier is from 0 to 5.5V.
RV
μA
REFIN EXT
.
=−125
19
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
12 ______________________________________________________________________________________
MAX8686
REFIN
RREFIN
VEXT
SS
Figure 1a. Using an External Reference
MAX8686
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
______________________________________________________________________________________ 13
Current-Limit Circuit
The current-limit threshold is set by a resistor between
ILIM and GND. Under soft-overload conditions, when
the peak inductor current exceeds the selected current
limit, the high-side MOSFET is turned off immediately
and the low-side MOSFET is turned on and remains on
to let the inductor current ramp down until the next
clock cycle. The converter does not stop switching and
the output voltage regulation is not guaranteed. Under
severe-overload or short-circuit conditions, the foldback
and hiccup current limit is simultaneously activated to
reduce power dissipation in the inductor, internal power
MOSFETs, and the upstream power source. Thus, the
circuit can withstand short-circuit conditions continu-
ously without causing overheating of any component. If
the device experiences a persistent overload condition,
the device will autoretry with a soft-start. The converter
will resume normal operation after the overload condi-
tion is removed.
The current-limit input is also used to communicate faults
between the devices in a multiphase configuration. With
any fault on the slave or master device (such as UVLO or
overtemperature), the ILIM input is pulled low, which
causes the other devices to turn off both MOSFETs.
Current Sharing
Accurate current sharing is required in a multiphase con-
verter to prevent some phases from overheating during
soft-start, steady-state, and load transient. For a convert-
er with current-mode control, the current is proportional
to the error-amplifier output in the voltage feedback loop.
The error-amplifier output (COMP) of the master is con-
nected to the current comparator input of all slave
devices. The current-sharing accuracy is determined by
the tolerances of the inductance and inductor DCR, the
input offset voltage, the gain of the current-sense ampli-
fiers, and the slope compensation circuits.
The peak current-mode control is an open-loop current-
sharing scheme, and therefore no compensation for
current sharing is needed and no stability issue exists.
Switching Frequency and
Ramp Generation (FREQ)
The MAX8686 has an adjustable internal oscillator that
can be set to any frequency from 300kHz to 1MHz. To set
the switching frequency, connect a capacitor from the
FREQ to GFREQ (see
Setting the Switching Frequency
section).
A triangle ramp from 0 to AVL/2 is generated across
FREQ capacitor. In a multiphase application, the
capacitor needs to be connected to the master device.
The FREQ inputs of the master and slave devices need
to be connected together. FREQ is internally pulled
down to GFREQ during shutdown.
Phase Selection Input (PHASE/REFO)
For single-phase or master device operation, the
PHASE/REFO can be used as a reference for the con-
verter output voltage (see the
Reference Output
(PHASE/REFO)/Reference Input (REFIN)
section). For
multiphase operation, connect the PHASE/REFO of
each slave device to the center tap of the resistor-
divider from AVL of the master to GND. The resistor val-
ues are selected to set delay time between phases (see
the
Calculating the Phase Voltage
section). The PWM
clock cycle of slave devices starts 60ns after the rising
edge of the voltage at FREQ crosses the voltage at
PHASE/REFO. The PWM clock cycle of the master
device starts at the beginning of the ramp.
Remote Sense Input (RS+, RS-)
For single-phase or master operation, connect RS+ to
the sense point at the load and RS- to the GND sense
point of the load. The connections should be at the out-
put regulation point to eliminate the voltage-sense error
caused by voltage drop between the device and load.
The RS+ and RS- traces should be laid out in parallel to
reduce noise coupling. A common-mode filter to each
sense trace should be added if further noise reduction
is needed.
For an output voltage higher than 3.3V, tie
PHASE/REFO to REFIN and use a resistor-divider from
the output regulation point to the remote sense inputs
(RS+, RS-), as shown in Figure 1b.
For multiphase operation, connect RS+ and RS- to AVL
(slave) to select the slave mode.
MAX8686
VOUT
LOAD
RS+
REFIN R1
R2
PHASE/REFO
RS-
Figure 1b. Output Voltage Above 3.3V
MAX8686
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
14 ______________________________________________________________________________________
Overvoltage Protection
The MAX8686 provides output overvoltage protection
(OVP). The OVP threshold is set at 20% above the set
output voltage. When the overvoltage condition is expe-
rienced, the output is latched to PGND through the low-
side MOSFET. To clear the latch, the EN/SLOPE input
should be pulled logic-low and then reinitialized. The
output starts up in a soft-start mode. To prevent the
overvoltage protection from initializing during power-up,
some consideration should be given to the soft-start
timing to reduce the inrush current. In addition, the
proper compensation network would prevent overshoot
during power-up.
Power-OK (POK) Signal
POK is an open-drain output that monitors the output volt-
age. When the output is above 90% of its nominal regula-
tion voltage, POK goes high impedance. There is a 3%
hysteresis to prevent the POK output from chattering. The
POK indicator can be used for sequencing.
Thermal-Overload Protection
Thermal-overload protection limits total power dissipa-
tion in the MAX8686. When the junction temperature
exceeds +160°C, an internal thermal sensor shuts
down the device, allowing it to cool down. The thermal
sensor turns the device on again after the junction tem-
perature cools by 30°C, resulting in a pulsed output
during continuous thermal-overload conditions. See
Figures 2, 3, and 4.
BST
31
32
33
34
35
36
37
38
39
40
+
LX
GFREQ
POWER-
OK C1
330pF
C17
1μF
C18
0.22μF
C16
0.22μF
C15
0.1μF
C3
10nF
C4
2.2nF
C4
150pF
R5
5.6kΩ
R1
10kΩ
R16
162kΩ
R3
200kΩ
R4
115kΩ
R2
150kΩ
C13
10μF
C12
10μF
C6
220μF
C7
220μF
C14
1μF
C11
10μF
INPUT
6V TO 20V
30
29
28
27
26
25
24
23
22
21
POK
SS
ILIM
COMP
RS+
RS-
LX
GFREQ
REFIN
PHASE/REFO
FREQ IN
N.C.
LX
PGND
U1
PGND
PGND
PGND
PGND
IN
IN
LX
RTN
PGND
PGND
PGND
EN/SLOPE
GFREQ
CS+
CS-
AVL
GND
INA
IN
IN
IN
IN
IN
IN
VL
PGND
5
6
7
9
10
4
3
2
1
8
15
16
17
19
20
14
13
12
11
18
R11
270Ω
R13
10Ω
ENABLE
(EN)
OUTPUT
1.2V/25A
L11
0.56μH
C2
15pF
R12
10Ω
MAX8686
R14
270Ω
Figure 2. Single-Phase Application Circuit Operating at VIN = 12V
MAX8686
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
______________________________________________________________________________________ 15
BST
31
32
33
34
35
36
37
38
39
40
LX
GFREQ
POWER-
OK C1
330pF
C17
1μF
C18
0.22μF
C16
0.22μF
C15
0.1μF
C3
10nF
C5
2.2nF
C4
150pF
R5
5.6kΩ
R16
162kΩ
R3
200kΩ
R4
115kΩ
R2
130kΩ
C13
10μF
C12
10μF
C6
220μF
C7
220μF
C14
1μF
C11
10μF
INPUT
4.5V TO 5.5V
30
29
28
27
26
25
24
23
22
21
POK
SS
ILIM
COMP
RS+
RS-
LX
GFREQ
REFIN
PHASE/REFO
FREQ IN
N.C.
LX
PGND
U1
PGND
PGND
PGND
PGND
IN
IN
LX
RTN
PGND
PGND
PGND
EN/SLOPE
GFREQ
CS+
CS-
AVL
GND
INA
IN
IN
IN
IN
IN
IN
VL
PGND
5
6
7
9
10
4
3
2
1
8
15
16
17
19
20
14
13
12
11
18
R11
270Ω
R13
10Ω
R1
10kΩ
ENABLE
(EN)
OUTPUT
1.2V/25A
L11
0.56μH
MAX8686
R14
270Ω
C2
15pF
+
Figure 3. Single-Phase Application Circuit Operating at VIN = 5V
MAX8686
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
16 ______________________________________________________________________________________
BST
31
32
33
34
35
36
37
38
39
40
LX1
GFREQ
POWER
OK
C1
270pF
C17
1μF
C18
0.22μF
C16
0.22μF
C15
0.1μF
C2
33nF
C4
2.2nF
C3
150pF
R5
5.6kΩ
R16
124kΩ
R3
200kΩ
R4
115kΩ
R2
150kΩ
C12
10μF
C11
10μF
INPUT: 6V-20V
30
29
28
27
26
25
24
23
22
21
POK
SS
ILIM
COMP
RS+
RS-
LX1
GFREQ
REFIN
PHASE/REFO
FREQ IN
N.C.
LX
PGND
U1
PGND
PGND
PGND
PGND
IN
IN
LX
RTN
PGND
PGND
PGND
EN/SLOPE
GFREQ
CS+
CS-
AVL
GND
INA
IN
IN
IN
IN
IN
IN
VL
PGND
5
6
7
9
10
4
3
2
1
8
15
16
17
19
20
14
13
12
11
18
R13
10Ω
R1
10kΩ
ENABLE
(EN)
OUTPUT: 1.2V/150A
R46
124kΩ
R12
10Ω
C42
10μF
C71–C94
100μF x 24
C41
10μF
MAX8686
BST
31
32
33
34
35
36
37
38
39
40
PHASE
SHEDDING
(PS)
LX4
C47
1μF
C48
0.22μF
C46
0.22μF
C45
0.1μF
C49
10pF R45
16.5kΩ
R44
54.9kΩ
30
29
28
27
26
25
24
23
22
21
POK
SS
ILIM
COMP
RS+
RS-
LX4
GFREQ
REFIN
PHASE/REFO
FREQ IN
N.C.
LX
PGND
U4
PGND
PGND
PGND
PGND
IN
IN
LX
RTN
PGND
PGND
PGND
EN/SLOPE
GFREQ
CS+
CS-
AVL
GND
INA
IN
IN
IN
IN
IN
IN
VL
PGND
5
6
7
9
10
4
3
2
1
8
15
16
17
19
20
14
13
12
11
18
R43
10Ω
AVL4
AVL1
AVL4
R42
10Ω
MAX8686
R56
124kΩ
C52
10μF
C51
10μF
C54
1μF
R51
270ΩL51
0.56μH
BST
31
32
33
34
35
36
37
38
39
40
LX5
C57
1μF
C58
0.22μF
C56
0.22μF
C55
0.1μF
C59
10pF R55
16.5kΩ
R54
35.7kΩ
30
29
28
27
26
25
24
23
22
21
POK
SS
ILIM
COMP
RS+
RS-
LX5
GFREQ
REFIN
PHASE/REFO
FREQ IN
N.C.
LX
PGND
U5
PGND
PGND
PGND
PGND
IN
IN
LX
RTN
PGND
PGND
PGND
EN/SLOPE
GFREQ
CS+
CS-
AVL
GND
INA
IN
IN
IN
IN
IN
IN
VL
PGND
5
6
7
9
10
4
3
2
1
8
15
16
17
19
20
14
13
12
11
18
R53
10Ω
AVL5
AVL1
AVL5
R52
10Ω
MAX8686
R66
124kΩ
C62
10μF
C61
10μF
C64
1μF
R61
270Ω
L61
0.56μH
BST
31
32
33
34
35
36
37
38
39
40
LX6
C67
1μF
C68
0.22μF
C66
0.22μF
C65
0.1μF
C69
10pF R65
16.5kΩ
R64
24.3kΩ
30
29
28
27
26
25
24
23
22
21
POK
SS
ILIM
COMP
RS+
RS-
LX6
GFREQ
REFIN
PHASE/REFO
FREQ IN
N.C.
LX
PGND
U6
PGND
PGND
PGND
PGND
IN
IN
LX
RTN
PGND
PGND
PGND
EN/SLOPE
GFREQ
CS+
CS-
AVL
GND
INA
IN
IN
IN
IN
IN
IN
VL
PGND
5
6
7
9
10
4
3
2
1
8
15
16
17
19
20
14
13
12
11
18
R63
10Ω
AVL6
AVL1
AVL6
R62
10Ω
MAX8686
R26
124kΩ
C2
10μF
C21
10μF
C24
1μF
R21
270ΩL21
0.56μH
BST
31
32
33
34
35
36
37
38
39
40
LX2
C27
1μF
C28
0.22μF
C26
0.22μF
C25
0.1μF
C29
10pF R25
16.5kΩ
R24
267kΩ
30
29
28
27
26
25
24
23
22
21
POK
SS
ILIM
COMP
RS+
RS-
LX2
GFREQ
REFIN
PHASE/REFO
FREQ IN
N.C.
LX
PGND
U2
PGND
PGND
PGND
PGND
IN
IN
LX
RTN
PGND
PGND
PGND
EN/SLOPE
GFREQ
CS+
CS-
AVL
GND
INA
IN
IN
IN
IN
IN
IN
VL
PGND
5
6
7
9
10
4
3
2
1
8
15
16
17
19
20
14
13
12
11
18
R23
10Ω
AVL2
AVL1
AVL2
R22
10Ω
MAX8686
R36
124kΩ
C32
10μF
C31
10μF
C34
1μF
R31
270Ω
L31
0.56μH
BST
31
32
33
34
35
36
37
38
39
40
LX2
C37
1μF
C38
0.22μF
C36
0.22μF
C35
0.1μF
C39
10pF R35
16.5kΩ
R34
97.6kΩ
30
29
28
27
26
25
24
23
22
21
POK
SS
ILIM
COMP
RS+
RS-
LX3
GFREQ
REFIN
PHASE/REFO
FREQ IN
N.C.
LX
PGND
U3
PGND
PGND
PGND
PGND
IN
IN
LX
RTN
PGND
PGND
PGND
EN/SLOPE
GFREQ
CS+
CS-
AVL
GND
INA
IN
IN
IN
IN
IN
IN
VL
PGND
5
6
7
9
10
4
3
2
1
8
15
16
17
19
20
14
13
12
11
18
R33
10Ω
AVL3
AVL1
AVL3
R32
10Ω
MAX8686
R57
270Ω
C44
1μF
R48
270ΩL41
0.56μH
R47
270Ω
R37
270Ω
R67
270Ω
R27
270Ω
C14
1μF
R11
270ΩL11
0.56μH
R17
270Ω
Figure 4. Multiphase Application at VIN = 12V
RxR
fxV
SLOPE DC
SW xL OUT
..=−
122 10 01
7882 _
xV
IN MIN
()
Cxf
xf
FREQ
xSW
SW
.
=−510
27
530
I
N
LIR xR mV
OUT MAX DC
_1245+
⎡
⎣
⎢⎤
⎦
⎥≤
I
NLIR R mV
OUT MAX DC
_×× ≥10
II
N
LIR
PEAK OUT MAX
=×+
⎛
⎝
⎜⎞
⎠
⎟
_12
LVDN
LIR f I
OUT
SW OUT MAX
≥×−×
××
()
_
1
RR VOUT
34 33 1=× −
⎛
⎝
⎜
⎞
⎠
⎟
.
RX RX VV
V
PHASE X
PHASE X
45
54
=× −.()
()
Vtxx
C
PHASEX PHASEX
FREQ
=−510 30
8
tX
fx xN
PHASEX SW
=103
I
NxLIR xR x R
RR
OUT MAX DC
_12
2
1
+
⎛
⎝
⎜⎞
⎠
⎟+22 45≤mV
RxL
RxC
DC
112 1
1
.
=
IV
R
I
LIM TH
DC
PP
=−−
2
VV V xR
TH CS CS ILIM
=−=
+−
10
61
MAX8686
VOUT
L1
C1
R1
R2
LX
CS+
CS-
ripple-current requirement (IRMS) imposed by the
switching currents as defined by the following equations:
for (N x D) ≤1:
for (N x D) > 1.
where N is the number of phases, D is the duty cycle,
and IOUT_MAX is the maximum output current.
Use the minimum input voltage for calculating the duty
cycle to obtain the worst-case input-capacitor RMS rip-
ple current. Low-ESR aluminum electrolytic, polymer, or
ceramic capacitors should be used to avoid large volt-
age transients at the input during a large step load
change at the output. The ripple-current specifications
provided by the manufacturer should be carefully
reviewed for temperature derating. Additional small-
value, low-ESL ceramic capacitors (1μF to 10μF with
proper voltage rating) can be used in parallel to reduce
any high-frequency ringing.
Output Capacitor
The minimum output capacitance, COUT(MIN), is
required to meet load-dump requirements. The worst-
case load dump is a sudden transition from full load
current (I2OUT_MAX) to minimum load current
(I2OUT_MIN). COUT(MIN) is estimated based on energy
balance from:
where I2OUT_MAX and I2OUT_MIN are the initial and final
values of the load current during the worst-case load
dump, VINIT2is the voltage prior to the load dump, VFIN
is the steady-state voltage after the load dump, and
VOV is the allowed voltage overshoot above VFIN. The
term (VFIN + VOV) represents the maximum transient
output voltage reached during the load dump. The
above equation is an approximation, and the output
capacitance value obtained serves as a good starting
point. The final value should be obtained from actual
measurements. For ceramic output capacitors, the out-
put capacitor requirement is determined mostly by load
dump requirements due to their low ESR and ESL. See
Figures 7 and 8.
Compensation Design
The MAX8686 uses an internal transconductance error
amplifier whose output compensates the control loop.
The external inductor, output capacitor, compensation
C
L
NII
VV
OUT MIN
OUT MAX OUT MIN
FIN OV
()
__
≥
×−
()
+
(
22
))
−
22
V
INIT
IDI ND ND
RMS OUT MAX
=× × ×−
×
−
_
()
32
1
2
IDI ND
RMS OUT MAX
=× × ×−
_
11
MAX8686
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
______________________________________________________________________________________ 19
MAX8686
RC
CC
COMP
CF
Figure 6. Compensation Components
GAIN
(dB)
FREQUENCY (Hz)
fpMOD
fzMOD
fC
CLOSED LOOP
ERROR
AMPLIFIER
0
VOLTAGE-
DIVIDER
POWER
MODULATOR
Figure 7. Simplified Gain Plot for the fzMOD > fCCase
GAIN
(dB)
FREQUENCY (Hz)
fpMOD
fzMOD fC
0
POWER
MODULATOR
CLOSED LOOP
ERROR
AMPLIFIER
VOLTAGE-
DIVIDER
Figure 8. Simplified Gain Plot for the fzMOD < fCCase
MAX8686
resistor, and compensation capacitors determine the
loop stability. The inductor and output capacitor are
chosen based on performance, size, and cost.
Additionally, the compensation resistor and capacitors
are selected to optimize control-loop stability. The compo-
nent values, shown in Figures 2, 3, and 4, yield stable
operation over the given range of input-to-output voltages.
The regulator uses a current-mode control scheme that
regulates the output voltage by forcing the required
current through the external inductor. The voltage drop
across the DC resistance of the inductor or the alter-
nate series current-sense resistor is used to measure
the inductor current. Current-mode control eliminates
the double pole in the feedback loop caused by the
inductor and output capacitor resulting in a smaller
phase shift and requiring a less elaborate error-amplifi-
er compensation than voltage-mode control. A simple
series RCand CCis all that is needed to have a stable,
high-bandwidth loop in applications where ceramic
capacitors are used for output filtering. For other types
of capacitors, due to the higher capacitance and ESR,
the frequency of the zero created by the capacitance
and ESR is lower than the desired closed-loop crossover
frequency. To stabilize a nonceramic output-capacitor
loop, add another compensation capacitor from COMP
to GND to cancel this ESR zero. See Figure 6.
The basic regulator loop is modeled as a power modula-
tor, an output feedback divider, and an error amplifier.
The power modulator has DC gain set by gmc x RLOAD,
with a pole and zero pair set by RLOAD, the output capac-
itor (COUT), and its equivalent series resistance (ESR).
Below are equations that define the power modulator:
where RLOAD = VOUT/[IOUT(MAX)/N], fSW is the switch-
ing frequency, L is the output inductance, gmc =
1/(AVCS x RDC), where AVCS is the gain of the current-
sense amplifier (30.5 typ), RDC is the DC resistance of
the inductor, the duty cycle D = VOUT/VIN. KSis a slope
compensation factor calculated from the following
equation:
Find the pole and zero frequencies created by the
power modulator as follows:
when COUT comprises “n” identical capacitors in paral-
lel, the resulting COUT = n x COUT(EACH), and ESR =
ESR(EACH)/n. Note that the capacitor zero for a parallel
combination of like capacitors is the same as for an
individual capacitor.
The transconductance error amplifier has a DC gain,
GEA(DC) = gmEA x RO, where gmEA is the error-amplifi-
er transconductance, which is equal to 1.7mS, and RO
is the output resistance of the error amplifier, which is
30MΩ. A dominant pole (fpdEA) is set by the compen-
sation capacitor (CC), the amplifier output resistance
(RO), and the compensation resistor (RC); a zero (fzEA)
is set by the compensation resistor (RC) and the com-
pensation capacitor (CC). There is an optional pole
(fpEA) set by CFand RCto cancel the output capacitor
ESR zero if it occurs near the crossover frequency (fC).
Thus:
The crossover frequency, fC, should be much higher
than the power-modulator pole fPMOD. Also, fCshould
fCRR
fCR
f
pdEA COC
zEA CC
pEA
=×× +
=××
=×
1
2
1
2
1
2
π
π
π
()
CCR
FC
×
fC ESR
zMOD OUT
=××
1
2π
fN
RC
N
Lf C KD
pMOD LOAD OUT SW OUT S
=××
+×× × ××−
22 1
ππ ()).−
[]
⎡
⎣
⎢⎤
⎦
⎥
05
KVxV
fxLxV
SOUT IN MIN
SW IN
=+ −
−
10 182.
(
_
VVOUT)
Gg R
R
Lf KD
MOD DC mc LOAD
LOAD
SW S
()
=×
+×××−
()
()
−110..5
⎡
⎣⎤
⎦
⎡
⎣
⎢⎤
⎦
⎥
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
20 ______________________________________________________________________________________
MAX8686
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
______________________________________________________________________________________ 21
be less than or equal to 1/5 the switching frequency.
Select a value for fCin the range:
The feedback voltage-divider gain (VREF/VOUT) should
be included for an output voltage higher than 3.3V,
where VREFIN is equal to 3.3V.
At the crossover frequency, the total loop gain must
equal 1, and is expressed as:
For the case where fzMOD is greater than fC:
Then RCcan be calculated as:
where gmEA = 1.7mS.
The error-amplifier compensation zero formed by RC
and CCshould be set at the modulator pole fPMOD.
Calculate the value of CCas follows:
If fPMOD is less than 5 x fC, add a second capacitor CF
from COMP to GND. The value of CFis:
As the load current decreases, the modulator pole also
decreases; however, the modulator gain increases
accordingly and the crossover frequency remains the
same.
For the case where fzMOD is less than fC:
The power modulator gain at fCis:
The error-amplifier gain at fCis:
RCis calculated as:
where gmEA = 1.7mS.
CCis calculated from:
CFis calculated from:
The current-mode control model on which the above
design procedure is based requires an additional high-
frequency term, GS(s), to account for the effect of sam-
pling the peak inductor current. The term GS(s) produces
additional phase lag at crossover and should be modeled
to estimate the phase margin obtainable by the selected
compensation components. As a final step, it is useful to
plot the dB gain and phase of the following loop-gain
transfer function and check the obtained phase margin. A
phase margin of at least 45° is recommended:
where the sampling effect quality factor is:
QKD
CS
=××−−
[]
1
105π(().)
Gs
s
Qf
s
f
S
cSW SW
()=
+×× +
×
()
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
1
1
2
2
ππ
Gs Rg
R
Lf Ks D
LOOP LOAD MC
LOAD
SW
()
()
=×
+×××−
()
−11005
12
12
.
(/ )
(/ )
⎡
⎣⎤
⎦
⎡
⎣
⎢⎤
⎦
⎥
×+×
+×
sf
sf
zMOD
pMOD
π
π××
+×
+××+×
(/ )
(/ )(/ )
12
12 12
sf
sf sf
zEA
pEA pdEA
π
ππ
×× ××gRoV
VG
mEA REFIN
OUT S
(
CRf
FCzMOD
=××
1
2π
CfR
CpMOD C
=××
1
2π
RV
V
f
gG f
COUT
FB
C
mEA MOD fc zMOD
=×
××
()
GgR
f
f
EA fc mEA C zMOD
C
()
=××
GG f
f
MOD fc MOD dc
pMOD
zMOD
() ( )
=×
CRf
FCzMOD
=××
1
2π
CfR
CpMOD C
=××
1
2π
RV
gV G
COUT
mEA REFIN MOD fc
=××
()
GgR
GG f
f
EA fc mEA C
MOD fc MOD dc
pMOD
C
()
() ( )
=×
=×
GG V
V
EA fc MOD fc REFIN
OUT
() ()
××=1
ff
f
pMOD C SW
<< ≤ 5
MAX8686
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
22 ______________________________________________________________________________________
Applications Information
PCB Layout Guidelines
Careful PCB layout is critical to achieve low switching
losses and clean, stable operation. The switching
power stage requires particular attention. Follow these
guidelines for good PCB layout:
1) Place IC decoupling capacitors as close to the IC
pins as possible. Separate the power and analog
ground planes. Place the input ceramic decoupling
capacitor directly across and as close as possible
to IN and PGND. This is to help contain the high
switching current within this small loop.
2) For output current greater than 10A, a four-layer
PCB is recommended. Pour an analog ground
plane in the second layer underneath the IC to min-
imize noise coupling.
3) Connect input and output capacitor to the PGND
plane and the VL capacitor to RTN. Connect all
analog signals to GND. The frequency-setting
capacitor should be connected to GFREQ.
4) Connect PGND, GND, and RTN at the return path
of the input bypass capacitor.
5) Signals shared by the master and slave (ILIM,
COMP, and FREQ) should not run close to switch-
ing signals.
6) Place the inductor current-sense resistor and
capacitor as close to the inductor as possible.
Make a Kelvin connection to minimize the effect of
PCB trace resistance.
7) Connect the exposed pad sections to the corre-
sponding IC pins and allow sufficient copper area
to help cooling the device.
8) Place the REFIN and compensation components
as close to the IC pins as possible.
9) Connect remote-sense input RS+ and RS- directly
to the load voltage regulation point and use Kelvin
connection for the two traces.
10) Refer to the MAX8686 Evaluation Kit for an exam-
ple layout.
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package draw-
ings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
40 TQFN T4066M+1 21-0177
40 TQFN T4066MN+1 21-0177
MAX8686
TQFN
+
TOP VIEW
35
36
34
33
12
11
13
CS+
EN/SLOPE
LX
RTN
PGND
14
CS-
INA
IN
IN
GND
AVL
VL
IN
IN
12
SS
4567
27282930 26 24 23 22
ILIM
REFIN
IN
N.C.
LX
PGND
GFREQ
IN
3
25
37
PHASE/REFO PGND
38
39
40
COMP
RS+
RS-
PGND
PGND
PGND
FREQ
32
15
IN
POK
31
16
17
18
19
20 IN
GND_EP
IN_EP
LX_EP
PGND
PGND
PGND IN
8910
21
BST
Pin Configuration Chip Information
PROCESS: BiCMOS
MAX8686
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
23
© 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 5/08 Initial release —
1 10/10 Modified TOC 5, Figure 4, Setting the Switching Frequency section, Calculating
the Phase Voltage section, and the Compensation Design section 5, 16, 17, 18, 21