AM79C961AKI/W - Advanced Micro Devices

Publicatio n# 19364 Rev: DAmendment/0

Issue Date: March 2000

Am79C961A

PCnet™-ISA II Jumperless, Full Duplex Single-Chip

Ethernet Controller for ISA

DISTINCTIVE CHARACTERISTICS

■Single-chip Ethernet controller for the Indus try

Standard Archit ecture (ISA) and Exte nded

Industry Standard Architecture (E ISA) buses

■Supports IEEE 802.3/ANSI 8802-3 and Ethernet

standards

■Supports full duplex operation on the

10BASE-T, AUI, and GPSI ports

■Direct interface to the ISA or EISA bus

■Pin compatible to Am79C9 61 PCnet- ISA +

Jumperless Single-Chip Ethernet Controller

■Software compatible with AMD’s Am7990

LANCE register and descriptor architecture

■Low power, CMOS design with sleep mode

allows reduce d power consumption for critical

battery powered applications

■Individual 136-byte transmit and 128-byte

receive FIFOs provide packet buffering for

increased system latency, and support the

following features:

— Automatic retransmission with no FIFO

reload

— A utomatic receive stripping and transmit

padding (individually programmable)

— Automatic runt pack et rejection

— A utomatic deletion of received collision

frames

■Dynamic transmit FCS generation

programmable on a frame-by -frame basis

■Single +5 V power supply

■Internal/external loopback capabilities

■Supports 8K, 16K, 32K, and 64K Boot PR OMs or

Flash for diskless node applications

■Supports Microsoft’s Plug and Play System

configuration for jumperless designs

■Supports staggered AT bus drive for reduced

noise and ground bounce

■Integrated Magic Packet™ support for remote

wake up of Green PCs

■Supports 8 interrupts on chip

■Look Ahead Packet Processing (LAPP)

allows protocol analysis to begin before

end of receive frame

■Supports 4 DMA channels on chip

■Supports 16 I/O locations

■Supports 16 boot PROM locations

■Provides integrated Attachment Unit Interface

(AUI) and 10BASE-T transceiver with 2 modes of

port selection:

—Automatic selection of AUI or 10BASE-T

—Software selection of AUI or 10BASE-T

■Automatic Twisted Pair receive polarity

detection and automatic correction of the

receive polarity

■Supports bus-master, programmed I/O, and

shared-memory architectures to fit in any PC

application

■Supports edge and level-sensitive interrupts

■DMA Buffer Management Unit f or reduced CPU

intervention which allow s higher thr oughput by

by-passing the platform DMA

■JTAG Boundary Scan (IEEE 1149.1) test access

port interface for board level production test

■Integrated Manchester Encoder/Decoder

■Supports the following types of network

interfaces:

—AUI to external 10BASE2, 10BASE5,

10BASE-T or 10BASE-F MAU

—Interna l 10BASE-T transceiver with Smart

Squelch to Twisted Pair medium

■Supports LANCE General Purpose Serial

Interface (GPSI)

■132-pi n PQFP and 144-pi n TQFP packag es

■Supports Shared Memory and PIO modes

■Supports PCMCIA mode (144-TQFP version

only)

■Support for operation in indus trial temperature

range (–40°C to +85°C) available in both

packages

2 Am79C961A

GENERAL DESCRIPTION

The PCnet-ISA II controller , a single-chip Ethernet con-

troller, is a highly integrated system solution for the

PC-AT Industry Standard Architecture (ISA) architec-

ture. It is de si gne d to pr ovide flexibility an d c om pati bi l-

ity with any existing PC application. This highly

integrated VLSI device is specifically designed to re-

duce parts count and cost, and addresses applications

where higher system throughput is desired. The PC-

net-ISA II controller is f abricated with AMD’s advanced

low-power CMOS proc ess to provide low standby cur-

rent for power sensitive applications.

The PCnet-ISA II controller can be configured into one

of three different architecture modes to suit a particular

PC application. In the Bus Master mode, all transfers

are performed using the integrated DMA controller.

This configuration enhances system performance by

allowing the PC net- IS A II contr oll er to bypas s the pl at-

f orm DMA controller and directly address the full 24-bit

memory space. The implementation of Bus Master

mode allows minimum par ts count for the majority of

PC applications. The PCnet-ISA II can also be config-

ured as a Bus Slave with either a Shared Memor y or

Programmed I/O architecture for compatibility with

low-end machines, such as PC/XTs that do not support

Bus Masters, and high-end machines that require local

packet buffering for increased system latency.

The PCnet-ISA II controller is designed to directly inter-

face with the ISA or EISA system bus. It contains an

ISA Plug and Play b us interface unit, DMA Buff er Man-

agement Unit, 802.3 Media Access Control function,

individual 136-byte transmit and 128-byte receive

FIFOs, IEEE 802.3 defined Attachment Unit Interface

(AUI), and a Twisted Pair Transceiver Media Attach-

ment Unit. Full duplex network operation can be

enabled on any of the device’s network ports. The PC-

net-ISA II controller is also register compatible with the

LANCE (Am7990) Ethernet controller and PCnet-ISA

(Am79C9 60). The DM A Buffer Manag ement Unit sup-

por ts the LANCE descriptor software model. Exter nal

remote boot and Ethernet physical address PROMs

and Electrically Erasable Proms are also supported.

This advanced Ethernet controller has the built-in

capability of automatically selecting either the AUI port

or the Twisted Pair transceiver. Only one interface is

active at any one time. The individual 136-byte transmit

and 128-byte receive FIFOs optimize system over-

head, providing sufficient latency during packet trans-

mission and reception, and minimizing intervention

during normal network error recovery. The integrated

Manchester encoder/decoder eliminates the need for

an external Serial Interface Adapter (SIA) in the node

system. If support for an external encoding/decoding

scheme is desired, the embedded General Purpose

Serial Interface (GPSI) allows direct access to/from the

MAC. In addition, the device provides programmable

on-chip LED drivers for transmit, receive, collision,

receive polarity, link integrity and activity, or jabber

status. The PCnet-ISA II controller also provides an

External Address Detection InterfaceTM (EADITM) to

allow external hardware address filtering in internet-

working applications.

For power sensitive applications where low stand-by

current is desired, the device incorporates a sleep

function to reduce over-all system power consumption,

ex cellent f or notebooks and Green PCs. In conjunction

with this low power mode, the PCnet-ISA II controller

also has integrated functions to support Magic Pack et,

an inexpensive technology that allows remote wake up

of Green PCs.

With the rise of embedded networking applications

operating in harsh environments where temperatures

may excee d the nor mal commer cial temperature ( 0°C

to +70°C) wind ow, an industrial temp eratu re (–40°C to

+85°C) version is available in all two packages; 132-pin

PQFP and 144-pin TQFP. The industrial temperature

version of the PCnet-ISA II Ethernet controller is

characterized across the industrial temperature range

(–40°C to +85°C) within the published power supply

specification (4.75 V to 5.25 V; i.e., ±5% VCC).

Am79C961A 3

BLOCK DIAGRAM: BUS MASTER MODE

19364B-1

ISA Bus

Interface

Unit

RCV

FIFO

XMT

FIFO

Control

Buffer

Management

Unit

EEPROM

Interface

Unit

802.3

MAC

Core

Encoder/

Decoder

(PLS) &

AUI Port

10BASE-T

MAU

Private

Bus

Control

JTAG

Port

Control

AEN

DACK[3, 5–7]

DRQ[3, 5–7]

IOCHRDY

IOCS16

IOR

IOW

IRQ[3, 4, 5, 9,

10, 11, 12]

MASTER

MEMR

MEMW

REF

RESET

SBHE

BALE

SD[0-15]

LA[17-23]

SA[0-19]

SLEEP

SHFBUSY

EEDO

EEDI

EESK

EECS

DVDD[1-7]

DVSS[1-13]

AVDD[1-4]

AVSS[1-2]

DXCVR/EAR

CI+/–

DI+/–

XTAL1

XTAL2

DO+/–

RXD+/–

TXD+/–

TXPD+/–

IRQ15/APCS

BPCS

LED[0–3]

PRDB[0–7]

TDO

TMS

TDI

TCK

4 Am79C961A

TABLE OF CONTENTS

Am79C961A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

BLOCK DIAGRAM: BUS MASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

TABLE OF CONTENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Standard Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

CONNECTION DIAGRAMS: BUS MASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

PQFP 132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

PIN DESIGNATIONS: BUS MASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Listed by Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

PIN DESIGNATIONS: BUS MASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Listed by Pin Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

PIN DESIGNATIONS: BUS MASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Listed by Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Listed by Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

PIN DESCRIPTION: BUS MASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

IEEE P996 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

ISA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

AEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

BALE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

DACK 3, 5-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

DRQ 3, 5-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

IOCHRDY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

IOCS16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

IOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

IOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

IRQ 3, 4, 5, 9, 10, 11, 12, 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

LA17-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

MASTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

MEMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

MEMW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

REF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

SA0-19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

SBHE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

SD0-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Board Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

IRQ12/FlashWE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

IRQ15/APCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

BPCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

DXCVR/EA R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

LEDO-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

PRDB3-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

PRDB2/EEDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

PRDB1/EEDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

PRDB0/EESK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

SHFBUSY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

EECS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

SLEEP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

XTAL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

CONNECTION DIAGRAMS: BUS SLAVE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

PQFP 132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

BLOCK DIAGRAM: BUS SLAVE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

PIN DESIGNATIONS: BUS SLAVE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Am79C961A 5

LISTED BY PIN NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

PIN DESIGNATIONS: BUS SLAVE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Listed by Pin Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

PIN DESIGNATIONS: BUS SLAVE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Listed by Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

PIN DESIGNATIONS: BUS SLAVE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Listed by Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

PIN DESCRIPTION: BUS SLAVE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

ISA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

AEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

IOCHRDY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

IOCS16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

IOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

IOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

IRQ3, 4, 5, 9, 10, 11, 12, 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

MEMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

MEMW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

REF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

SA0-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

SBHE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

SD0-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Board Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

APCS/IRQ15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

BPAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

BPCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

DXCVR/EA R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

LED0-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

PRAB0-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

PRDB3-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

PRDB2/EEDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

PRDB1/EEDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

PRDB0/EESK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

SHFBUSY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

EECS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

SLEEP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

SMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

SMAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

SROE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

SRCS/IRQ12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

SRWE/WE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

XTAL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

PIN DESCRIPTION: NETWORK INTERFACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

AUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

DI+, DI– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Twisted Pair Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

RXD+, RXD– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

TXD+, TXD– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

TXP+, TXP– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

PIN DESCRIPTION: IEEE 1149.1 (JTAG) TEST ACCESS PORT . . . . . . . . . . . . . . . . . . . . . . . . . . .31

TCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

TDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

TDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

TMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

PIN DESCRIPTION: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

POWER SUPPLIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

AVDD1–4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

6 Am79C961A

AVSS1–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

DVDD1–7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

DVSS1–13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

CONNECTION DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

TQFP 144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

PIN DESIGNATIONS: BUS MASTER MODE (TQFP 144) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Listed by Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

PIN DESIGNATIONS: BUS MASTER MODE (TQFP 144) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Listed by Pin Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

PIN DESIGNATIONS: BUS SLAVE (PIO AND SHARED MEMORY) MODES (TQFP 144) . . . . . . .35

Listed by Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

PIN DESIGNATIONS: BUS SLAVE (PIO AND SHARED MEMORY) MODES (TQFP 144) . . . . . . .36

Listed by Pin Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

BLOCK DIAGRAM: PCMCIA MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

PIN DESIGNATIONS: PCMCIA MODE (TQFP 144) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Listed by Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

PIN DESIGNATIONS: PCMCIA MODE (TQFP 144) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Listed by Pin Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

PIN DESCRIPTION: PCMCIA MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

PCMCIA vs. ISA Pinout Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

PCMCIA Pin Specification Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

PCMCIA MODE BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

PCMCIA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Serial EEPROM Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Flash Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Flash Memory Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Shared Memory vs. Programmed I/O Implications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

FLASH MEMORY MAP AND CARD REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Important Note About The EEPROM Byte Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Bus Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Bus Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

PLUG AND PLAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Auto-Configuration Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

ADDRESS PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

WRITE_DATA PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

READ_DATA PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Initiation Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Isolation Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Hardware Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Software Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Plug and Play Card Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Plug and Play Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

PLUG AND PLAY LOGICAL DEVICE CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . .54

DETAILED FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 5

EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Important Note About The EEPROM Byte Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Basic EEPROM Byte Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

AMD Device Driver Compatible EEPROM Byte Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Plug and Play Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

PCnet–ISA II’s Legacy Bit Feature Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Plug & Play Register Locations Detailed Description

(Refer to the Plug & Play Register Map above) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Am79C961A 7

Vendor Defined Byte (PnP 0xF0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Checksum Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Use Without EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

External Scan Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Flash PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Optional IEEE Address PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

EISA Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Bus Interface Unit (BIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

1. Initialization Block DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

2. Descriptor DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

3. FIFO DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Buffer Management Unit (BMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Reinitialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Buffer Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Descriptor Rings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Descriptor Ring Access Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Transmit Descriptor Table Entry (TDTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Receive Descriptor Table Entry (RDTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Media Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Transmit and Receive Message Data Encapsulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Media Access Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Manchester Encoder/Decoder (MENDEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

External Crystal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

External Clock Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

MENDEC Transmit Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Transmitter Timing and Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Receive Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Input Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Clock Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

PLL Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Carrier Tracking and End of Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Data Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Differential Input Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Collision Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Jitter Tolerance Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Attachment Unit Interface (AUI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Twisted Pair Transceiver (T-MAU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7

Twisted Pair Transmit Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Twisted Pair Receive Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Link Test Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Polarity Detection and Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Twisted Pair Interface Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 8

Collision Detect Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Signal Quality Error (SQE) Test (Heartbeat) Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Jabber Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Full Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

EADI (External Address Detection Interf ace) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

General Purpose Serial Interface (GPSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Boundary Scan Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

TAP FSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Supported Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

8 Am79C961A

Instruction Register and Decoding Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Boundary Scan Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Other Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Access Operations (Software) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

I/O Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

IEEE Address Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Boot PROM Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Static RAM Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Bus Cycles (Hardware) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Bus Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

Address PROM Cycles External PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

Address PROM Cycles Using EEPROM Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Ethernet Controller Register Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Transmit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

Transmit Function Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

Automatic Pad Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

Transmit FCS Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

Transmit Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

Receive Function Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

Automatic Pad Stripping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

Receive FCS Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3

Receive Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

Loopback Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

MAGIC PACKET OPER ATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

Magic Packet Mode Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

Magic Packet Receive Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

PCNET-ISA II CONTROLLER REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

RAP: Register Address Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

CSR0: PCnet-ISA II Controller Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

CSR1: IADR[15:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

CSR2: IADR[23:16] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

CSR3: Interrupt Masks and Deferral Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

CSR4: Test and Features Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

CSR5: Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

CSR6: RCV/XMT Descriptor Table Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102

CSR8: Logical Address Filter, LADRF[15:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102

CSR9: Logical Address Filter, LADRF[31:16] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102

CSR10: Logical Address Filter, LADRF[47:32] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102

CSR11: Logical Address Filter, LADRF[63:48] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102

CSR12: Physical Address Register, PADR[15:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

CSR13: Physical Address Register, PADR[31:16] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

CSR14: Physical Address Register, PADR[47:32] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

CSR15: Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

CSR16: Initialization Block Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

CSR17: Initialization Block Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

CSR18-19: Current Receive Buffer Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

CSR20-21: Current Transmit Buffer Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

CSR22-23: Next Receive Buffer Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

CSR24-25: Base Address of Receive Ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

CSR26-27: Next Receive Descriptor Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

CSR28-29: Current Receive Descriptor Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

CSR30-31: Base Address of Transmit Ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

Am79C961A 9

CSR32-33: Next Transmit Descriptor Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

CSR34-35: Current Transmit Descriptor Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

CSR36-37: Next Next Receive Descriptor Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

CSR38-39: Next Next Transmit Descriptor Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

CSR40-41: Current Receive Status and Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

CSR42-43: Current Transmit Status and Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

CSR44-45: Next Receive Status and Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

CSR46: Poll Time Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

CSR47: Polling Interval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

CSR48-49: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

CSR50-51: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

CSR52-53: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

CSR54-55: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

CSR56-57: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

CSR58-59: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

CSR60-61: Previous Transmit Descriptor Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

CSR62-63: Previous Transmit Status and Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

CSR64-65: Next Transmit Buffer Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

CSR66-67: Next Transmit Status and Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

CSR70-71: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

CSR72: Receive Ring Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

CSR74: Transmit Ring Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

CSR76: Receive Ring Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

CSR78: Transmit Ring Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

CSR80: Burst and FIFO Threshold Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

CSR82: Bus Activity Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

CSR84-85: DMA Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

CSR86: Buffer Byte Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

CSR88-89: Chip ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

CSR92: Ring Length Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

CSR94: Transmit Time Domain Reflectometry Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

CSR96-97: Bus Interface Scratch Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

CSR98-99: Bus Interface Scratch Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

CSR104-105: SWAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

CSR108-109: Buffer Management Scratch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

CSR112: Missed Frame Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

CSR114: Receive Collision Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

CSR124: Buffer Management Unit Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

ISACSR0: Master Mode Read Active/SRAM Data Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

ISACSR1: Master Mode Write Active/SRAM Address Pointer . . . . . . . . . . . . . . . . . . . . . . . .114

ISACSR2: Miscellaneous Configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

ISACSR3: EEPROM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116

ISACSR4: LED0 Status (Link Integrity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

ISACS R 5: L ED 1 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

ISACS R 6: L ED 2 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118

ISACS R 7: L ED 3 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

ISACSR8: Software Configuration Register (Read-Only Register) . . . . . . . . . . . . . . . . . . . . .120

ISACSR9: Miscellaneous Configuration 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120

Initialization Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120

RLEN and TLEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120

RDRA and TDRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

LADRF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

PADR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

Receive Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122

RMD0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122

RMD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122

RMD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122

10 Am79C961A

RMD3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

Transmit Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

TMD0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

TMD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

TMD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124

TMD3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124

Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

Ethernet Controller Registers (Accessed via RDP Port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

REGISTER SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

ISACSR—ISA Bus Configuration Registers (Accessed via IDP Port) . . . . . . . . . . . . . . . . . .128

SYSTEM APPLICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

ISA Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

Compatibility Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

Bus Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

Shared Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

Optional Address PROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

Boot PROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

Static RAM Interface (for Shared Memory Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

AUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

10BASE-T Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

Commercial (C) Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

Industrial (I) Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

DC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

SWITCHING CHARACTERISTICS: BUS MASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

SWITCHING CHARACTERISTICS: BUS MASTER MODE—FLASH READ CYCLE . . . . . . . . . . 140

SWITCHING CHARACTERISTICS: BUS MASTER MODE—FLASH WRITE CYCLE . . . . . . . . . .140

SWITCHING CHARACTERISTICS: SHARED MEMORY MODE . . . . . . . . . . . . . . . . . . . . . . . . . 141

SWITCHING CHARACTERISTICS: SHARED MEMORY MODE—FLASH READ CYCLE . . . . . .144

SWITCHING CHARACTERISTICS: SHARED MEMORY MODE—FLASH WRITE CYCLE . . . . . .144

SWITCHING CHARACTERISTICS: EADI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

SWITCHING CHARACTERISTICS: JTAG (IEEE 1149.1) INTERFACE . . . . . . . . . . . . . . . . . . . . .145

SWITCHING CHARACTERISTICS: GPSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146

SWITCHING CHARACTERISTICS: AUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147

SWITCHING CHARACTERISTICS: 10BASE-T INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . .148

SWITCHING CHARACTERISTICS: SERIAL EEPROM INTERFACE . . . . . . . . . . . . . . . . . . . . . .148

SWITCHING TEST CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149

SWITCHING WAVEFORMS: BUS MASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152

SWITCHING WAVEFORMS: SHARED MEMORY MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162

SWITCHING WAVEFORMS: GPSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172

SWITCH IN G WAVEFORMS: EAD I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

SWITCHING WAVEFORMS: JTAG (IEEE 1149.1) INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . .173

SWITCHING WAVEFORMS: AUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174

SWITCHING WAVEFORMS: 10BASE-T INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178

PHYSICAL DIMENSIONS* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180

PQB132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180

PHYSICAL DIMENSIONS* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181

PQB132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181

PCnet-ISA II Compatible Media Interface Modules . . . . . . . . . . . . . . . . . . . . . . . . . .183

PCNET-ISA II COMPATIBLE 10BASE-T FILTERS AND TRANSFORMERS . . . . . . . . . . . . . . . . .183

PCNET-ISA II COMPATIBLE AUI ISOLATION TRANSFORMERS . . . . . . . . . . . . . . . . . . . . . . . . .183

PCNET-ISA II COMPATIBLE DC/DC CONVERTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184

MANUFACTURER CONTACT INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184

Am79C961A 11

Layout Recommendations for Reducing Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

DECOUPLING LOW-PASS R/C FILTER DESIGN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

Digital Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

Analog Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

AVSS1 and AVDD3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

AVSS2 and AVDD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

AVSS2 and AVDD2/AVDD4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186

Sample Plug and Play Configuration Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187

SAMPLE CONFIGURATION FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187

Alternative Method for Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

Introduction of the Look-Ahead Packet Processing (LAPP) Concept . . . . . . . . . .191

Outline of the LAPP Flow: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191

SETUP: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192

FLOW: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192

LAPP Enable Software Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194

LAPP Enable Rules for Parsing of Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194

Some Examples of LAPP Descriptor Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195

Buffer Size Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196

Some Characteristics of the XXC56 Serial EEPROMs . . . . . . . . . . . . . . . . . . . . . . .201

SWITCHING CHARACTERISTICS OF A TYPICAL XXC56 SERIAL EEPROM INTERFACE . . . .201

INSTRUCTION SET FOR THE XXC56 SERIES OF EEPROMS . . . . . . . . . . . . . . . . . . . . . . . . . . .202

Am79C961A PCnet-ISA II Silicon Errata Report . . . . . . . . . . . . . . . . . . . . . . . . . . . .203

AM79C961A REV FD SILICON STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203

12 Am79C961A

ORDERING INFORMATION

Standard Products

AMD stan dard produ cts are a vail able in sev eral pa ckages and oper ating rang es. The o rder numbe r (V ali d Combinatio n) is f ormed

by a combination of:

Valid Combinations

Valid Combinations list configurations planned to be sup-

ported in volume for this d evice. Cons ul t the local AM D sa le s

office to confirm av ailability of specific v alid com binations and

to check on newly released combinations.

AM79C961A K C \W

ALTERNATE PACKAGING OPTION

\W=Trimmed and Formed (PQB132)

OPTIONAL PROCESSING

Blank=St and ard Proc ess in g

TEMPERATURE RANGE

C=Commercial (0°C to +70°C)

I =Industrial (–40°C to +85°C)

PACKAGE TYPE (per Prod. Nomenclature/16-038)

K=132-pin Plastic Quad Flat Pack (PQR132)

V=144-pin Thin Quad Flat Package (PQT144)

SPEED

Not Applicable

DEVICE NUMBER/DESCRIPTION

Am79C961A

PCnet-ISA II Jumperless Single-Chip Ethernet Controller for ISA

Valid Combinations

AM79C961A KC, KC\W

VC, VC\W

AM79C961A KI, KI\W

VI, VI\W

Am79C961A 13

CONNECTION DIAGRAMS: BUS MASTER MODE

PQFP 132

19364B-2

132

DVDD2

TCK

131 TMS

130 TDO

129 TDI

128 EECS

127 BPCS

126 SHFBUSY

125 PRDB0/EESK

124 PRDB1/EEDI

123 PRDB2/EEDO

122 PRDB3

121 DVSS2

120 PRDB4

119 PRDB5

118 PRDB6

117 PRDB7

116 DVDD1

115 LED0

114 LED1

113 DVSS1

112 LED2

111 LED3

110 DXCVR/EAR

109 AVDD2

108 CI+

107 CI–

106 DI+

105 DI–

104 AVDD1

103 DO+

102 DO–

101 AVSS1

100

XTAL299 AVSS298 XTAL197 AVDD396 TXD+95 TXPD+94 TXD–93 TXPD–92 AVDD491 RXD+90 RXD–89 DVSS1388 SD1587 SD786 SD1485 SD684 DVSS983 SD1382 SD581 SD1280 SD479 DVDD778 SD1177 SD376 SD1075 SD274 DVSS873 SD972 SD171 SD870 SD069

SLEEP68 DVDD667

DVDD4 35

SA12 36

SA13 37

SA14 38

SA15 39

SA16 40

SA17 41

SA18 42

SA19 43

AEN 44

IOCHRDY 45

MEMW 46

MEMR 47

DVSS11 48

IRQ15/APCS 49

IRQ12/FLASHWE 50

IRQ11 51

DVDD5 52

IRQ10 53

IOCS16 54

BALE 55

IRQ3 56

IRQ4 57

IRQ5 58

DVSS12 60

DRQ3 61

DACK3 62

IOR 63

IOW 64

IRQ9 65

RESET 66

DVSS3 2MASTER

3DRQ7 4DRQ6 5DRQ5 6DVSS10 7DACK7

8DACK6

9DACK5

10LA17 11LA18 12LA19 13LA20 14DVSS4 15LA21 16LA22 17LA23 18SBHE

19DVDD3 20SA0 21SA1 22SA2 23DVSS5 24SA3 25SA4 26SA5 27SA6 28SA7 29SA8 30SA9 31DVSS6 32SA10 33SA11

Am79C961AKC

REF

DVSS7

14 Am79C961A

PIN DESIGNATIONS: BUS MASTER MO DE

Listed by Pin Number

Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name

1 DVSS3 34 DVDD4 67 DVDD6 100 AVSS1

2 MASTER 35 SA12 68 SLEEP 101 DO–

3 DRQ7 36 SA13 69 SD0 102 DO+

4 DRQ6 37 SA14 70 SD8 103 AVDD1

5 DRQ5 38 SA15 71 SD1 104 DI–

6 DVSS10 39 DVSS7 72 SD9 105 DI+

7DACK740 SA16 73 DVSS8 106 CI–

8DACK641 SA17 74 SD2 107 CI+

9DACK542 SA18 75 SD10 108 AVDD2

10 LA17 43 SA19 76 SD3 109 DXCVR/EAR

11 LA18 44 AEN 77 SD11 110 LED3

12 LA19 45 IOCHRDY 78 DVDD7 111 LED2

13 LA20 46 MEMW 79 SD4 112 DVSS1

14 DVSS4 47 MEMR 80 SD12 113 LED1

15 LA21 48 DVSS11 81 SD5 114 LED0

16 LA22 49 IRQ15/APCS 82 SD13 115 DVDD1

17 LA23 50 IRQ12/FlashWE 83 DVSS9 116 PRDB7

18 SBHE 51 IRQ11 84 SD6 117 PRDB6

19 DVDD3 52 DVDD5 85 SD14 118 PRDB5

20 SA0 53 IRQ10 86 SD7 119 PRDB4

21 SA1 54 IOCS16 87 SD15 120 DVSS2

22 SA2 55 BALE 88 DVSS13 121 PRDB3

23 DVSS5 56 IRQ3 89 RXD–122 PRDB2/EEDO

24 SA3 57 IRQ4 90 RXD+ 123 PRDB1/EEDI

25 SA4 58 IRQ5 91 AVDD4 124 PRDB0/EESK

26 SA5 59 REF 92 TXPD–125 SHFBUSY

27 SA6 60 DVSS12 93 TXD–126 BPCS

28 SA7 61 DRQ3 94 TXPD+ 127 EECS

29 SA8 62 DACK3 95 TXD+ 128 TDI

30 SA9 63 IOR 96 AVDD3 129 TDO

31 DVSS6 64 IOW 97 XTAL1 130 TMS

32 SA10 65 IRQ9 98 AVSS2 131 TCK

33 SA11 66 RESET 99 XTAL2 132 DVDD2

Am79C961A 15

PIN DESIGNATIONS: BUS MASTER MO DE

Listed by Pin Name

Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No.

AEN 44 DVSS12 60 LED2 111 SA6 27

AVDD1 103 DVSS13 88 LED3 110 SA7 28

AVDD2 108 DVSS2 120 MASTER 2 SA8 29

AVDD3 96 DVSS3 1 MEMR 47 SA9 30

AVDD4 91 DVSS4 14 MEMW 46 SBHE 18

AVSS1 100 DVSS5 23 PRDB0/EESK 124 SD0 69

AVSS2 98 DVSS6 31 PRDB1/EEDI 123 SD1 71

BALE 55 DVSS7 39 PRDB2/EEDO 122 SD10 75

BPCS 126 DVSS8 73 PRDB3 121 SD11 77

CI–106 DVSS9 83 PRDB4 119 SD12 80

CI+ 107 DXCVR/EAR 109 PRDB5 118 SD13 82

DACK3 62 EECS 127 PRDB6 117 SD14 85

DACK5 9 IOCHRDY 45 PRDB7 116 SD15 87

DACK6 8IOCS1654 REF 59 SD2 74

DACK7 7IOR63 RESET 66 SD3 76

DI–104 IOW 64 RXD–89 SD4 79

DI+ 105 IRQ10 53 RXD+ 90 SD5 81

DO–101 IRQ11 51 SA0 20 SD6 84

DO+ 102 IRQ12/FlashWE 50 SA1 21 SD7 86

DRQ3 61 IRQ15/APCS 49 SA10 32 SD8 70

DRQ5 5 IRQ3 56 SA11 33 SD9 72

DRQ6 4 IRQ4 57 SA12 35 SHFBUSY 125

DRQ7 3 IRQ5 58 SA13 36 SLEEP 68

DVDD1 115 IRQ9 65 SA14 37 TCK 131

DVDD2 132 LA17 10 SA15 38 TDI 128

DVDD3 19 LA18 11 SA16 40 TDO 129

DVDD4 34 LA19 12 SA17 41 TMS 130

DVDD5 52 LA20 13 SA18 42 TXD–93

DVDD6 67 LA21 15 SA19 43 TXD+ 95

DVDD7 78 LA22 16 SA2 22 TXPD–92

DVSS1 112 LA23 17 SA3 24 TXPD+ 94

DVSS10 6 LED0 114 SA4 25 XTAL1 97

DVSS11 48 LED1 113 SA5 26 XTAL2 99

16 Am79C961A

PIN DESIGNATIONS: BUS MASTER MO DE

Listed by Group

Pin Name Pin Function I/O Driver

ISA Bus Interface

AEN

BALE

DACK[3, 5–7]

DRQ[3, 5–7]

IOCHRDY

IOCS16

IOR

IOW

IRQ[3, 4, 5, 9, 10, 11, 12, 15]

LA[17-23]

MASTER

MEMR

MEMW

REF

RESET

SA[0 –19]

SBHE

SD[0 –15]

Address Enable

Bus Address Latch Enable

DMA Acknowledge

DMA Request

I/O Channel Ready

I/O Chip Sele ct 16

I/O Read Select

I/O Write Select

Interrupt Request

Unlatched Address Bus

Master Transfer in Progress

Memory Read Select

Memory Write Select

Memory Refresh Active

Syst em R ese t

System Addre ss Bus

System Byte High Enable

System Data Bus

I/O

TS3

OD3

TS3/OD3

TS3

OD3

TS3

Board Interfaces

IRQ15/APCS

BPCS

DXCVR/EAR

LED0

LED1

LED2

LED3

PRDB[3–7]

SLEEP

XTAL1

XTAL2

SHFBUSY

PRDB(0)/EESK

PRDB(1)/EEDI

PRDB(2)/EEDO

EECS

IRQ15 or Address PROM Chip Select

Boot PROM Chip Select

Disable Transceiver

LED0/LNKST

LED1/SFBD/RCVACT

LED2/SRD/RXDATPOL

LED3/SRDCLK/XMTACT

PROM Data Bus

Sleep Mode

Crystal Input

Crystal Output

Read access from EEPROM in process

Serial Shift Clock

Serial Shift Data In

Serial Shift Data Out

EEPROM Chip Select

I/O

TS1

TS2

TS1

Am79C961A 17

PIN DESIGNATIONS: BUS MASTER MODE (continued)

Listed by Group

Output Driver Types

Pin Name Pin Function I/O Driver

Attachment Unit Interface (AUI)

CI±

DI±

DO±

Collision Inputs

Receive Data

Transmit Data

Twisted Pair Transceiver Interface (10BASE-T)

RXD±

TXD±

TXPD±

10BASE-T Receive Data

10BASE-T Transmit Data

10BASE-T Predist ortion Control

IEEE 1149.1 Test Access Port Interface (JTAG)

TCK

TDI

TDO

TMS

Test Clock

Test Data Input

Test Data Output

Test Mode Select

ITS2

Power Supplies

AVDD

AVSS

DVDD

DVSS

Analog Power [1-4]

Analog Ground [1-2]

Digital Power [1-7]

Digital Ground [1-13]

Name Type IOL (mA) IOH (mA) pF

TS1 Tri-State 4 –150

TS2 Tri-State 12 –450

TS3 Tri-State 24 –3120

OD3 Open Dra in 24 –3120

18 Am79C961A

PIN DESCRIPTION: BUS MASTER MODE

These pins are part of the bus master mode. In order to

understand the pin descriptions, definition of some

terms from a draft of IEEE P996 are included.

IEEE P996 Terminology

Alternate Master: Any device that can take control of

the bus through assertion of the MASTER signal. It has

the ability to generate addresses and bus control sig-

nals in order to perform bus operations. All Alternate

Masters must be 16 bit devices and drive SBHE.

Bus Ownership: The Current Master possesses bus

ownership and can assert any bus control, address and

data lines.

Current Master: The Permanent Master, Temporary

Master or Alternate Master which currently has owner-

ship of the bus.

P ermanent Master: E ach P996 bu s will hav e a d e vice

known as th e Pe rman ent Master that pr ov ides cer tain

signals and bus contr ol func tions as descr ib ed in Sec -

tion 3.5 (of the IEEE P996 spec.), “P ermanent Master”.

The Permanent Master function can reside on a Bus

Adapter or on the backplane itself.

T emporary Master: A de vice that is capable of gener-

ating a DMA request to obtain control of the bus and

directly asserting only the memory and I/O strobes

during bus transfer. Addresses are generated by the

DMA device on the Permanent Master.

ISA Interface

AEN

Address Enable Input

This signal must be driven LOW when the bus performs

an I/O access to the device.

BALE

Used to latch the LA20–23 address line s.

DACK 3, 5-7

DMA Ack n owledge Input

Asser ted LOW when the Per manent Master acknowl-

edges a DMA request. When DACK is asserted the

PCnet-ISA II controller becomes the Current Master b y

asserting the MASTER signal.

DRQ 3, 5-7

DMA Request Input/Output

When the PCnet-ISA II controller needs to perform a

DMA transfer, it asser ts DRQ. The Per manent Mas ter

acknowledges DRQ with the assertion of D A CK. When

the PCnet-ISA II does not need the bus it desserts

DRQ. The PCnet-ISA II provides for fair bus bandwidth

sharing between two b us mastering devices on the ISA

bus through an adaptive delay which is inserted

between back-to-back DMA requests. See the

Back-to-Back DMA Requests section for details.

Because of the operation of the Plug and Play regis-

ters, the DMA Channels on the PCnet-ISA II must be

attached to the specific DRQ and D ACK signals on the

PC/AT bus as indicated by the pin names.

IOCHRDY

I/O Channel Ready Input/Output

When the PCnet-ISA II controller is being accessed,

IOCHRDY HIGH indicates that valid data exists on the

data bus for reads and that data has been latched for

writes. When the PCnet-ISA II controller is the Current

Master on the ISA bus, it extends the bus cycle as long

as IOCHRDY is LOW.

IOCS16

I/O Chip Select 16 Output

When an I/O read or wr ite operati on is perfor med, the

PCnet-IS A II cont roller will drive the IO CS16 pin LOW

to indica te that the chip su ppor ts a 16-bit operation at

this ad dres s. (If th e motherboa rd do es n ot re cei ve this

signal, then the motherboard will convert a 16-bit

access to two 8-bit accesses).

The PCnet-ISA II controller follows the IEEE P996 spec-

ification that recommends this function be implemented

as a pure decode of SA0-9 and AEN, with no depen-

dency on IOR, or IO W; h owe ver , some PC/AT clone s ys-

tems are not compatible with this approach. For this

reason, the PCnet-ISA II controller is recommended to

be configured to run 8-bit I/O on all machines. Since data

is moved by memory cycles there is virtually no perfor-

mance l oss in curred by runn ing 8-bi t I/O and compa tibil -

ity problems are vir tually eliminated. The PCnet-ISA II

controller can be configured to run 8-bit-only I/O by

clearing Bit 0 in Plug and Play reg ist er F0 .

IOR

I/O Read Input

IOR is driven LOW b y the host to indicate that an Input/

Output Read operation is taking place. IOR is only valid

if the AEN signal is LOW and the external address

matches the PCnet-ISA II controller’s predefined I/O

address location. If valid, IOR indicates that a slave

read operation is to be performed.

IOW

I/O Write Input

IOW is driven LOW b y the host to indicate that an Input/

Output Write operation is taking place. IO W is only valid

if AEN signal is LOW and the external address matches

the PCnet-ISA II controller’s predefined I/O address

location. If valid, IO W indicates that a slave write oper-

ation is to be performed.

Am79C961A 19

IRQ 3, 4, 5, 9, 10, 11, 12, 15

Interrupt Reques t Output

An attention signal which indicates that one or more of

the following status flags is set: BABL, MISS, MERR,

RINT, IDON, RCVCCO, JAB, MPCO, or TXDATSTRT.

All status flags have a mask bit which allows for sup-

pression of IRQ assertion. These flags have the

following meaning:

Because of the operation of the Plug and Play regis-

ters, the interrupts on the PCnet-ISA II must be

attached to specific IRQ signals on the PC/AT bus.

LA17-23

Unlatched Address Bus Input/Output

The unlatched address bus is driven by the PCnet-ISA

II controller during bus master cycle.

The functions of these unlatched address pins will

change when GPSI mode is invoked. The following

table shows the pin configuration in GPSI mode. Please

ref er to the section on General Purpose Serial Interf ace

for detailed information on accessing this mode.

MASTER

Master Mode Input/Output

This signal indicates that the PCnet-ISA II controller

has become the Current Master of the ISA bus. After

the PCnet-ISA II controller has received a DMA

Acknowledge (DACK) in response to a DMA Request

(DRQ), the Ethernet controller asserts the MASTER

signal to indicate to the P ermanent Master that the PC-

net-ISA II controller is becoming the Current Master.

MEMR

Memory Read Input/Output

MEMR goes LO W to perform a mem ory read op erat ion .

MEMW

Memory Write Input/Output

MEMW goes LOW to perform a memory write

operation.

REF

Memory Refresh Input

When REF is asserted, a memory refresh is active. The

PCnet-ISA II controller uses this signal to mask inad-

vertent DMA Acknowledge assertion during memory

refresh periods. If DACK is asserted when REF is

active, DA CK assertion is ignored. REF is monitored to

eliminate a bus arbitration problem obser ved on some

ISA platforms.

RESET

Reset Input

When RESET is asserted HIGH the PCne t-ISA II con-

troller performs an internal system reset. RESET must

be held for a minimum of 10 XTAL1 periods before

being deasserted. While in a reset state, the PCnet-ISA

II controller will tristate or deassert all outputs to pre-

defined reset le vels. The PCnet-ISA II controller resets

itself upon power-up.

SA0-19

System Address Bus Input/Output

This bus c on tai ns address i nfor ma tio n, whi ch i s s table

during a bus operation, regardless of the source.

SA17-19 contain the same values as the unlatched

address LA17-19. When th e PCnet-ISA II controller is

the Current Master, SA0-19 will be driven actively.

When the PCnet-ISA II controller is not the Current

Master, the SA0-19 lines are continuously monitored to

determine if an address match exists for I/O slave

transfers or Boot PROM accesses.

SBHE

System Byte High Enable Input/Output

This signal indicates the high byte of the system dat a

bus is to be used. SBHE is dr iven by the PCnet-ISA II

controller when performing bus mastering operations.

SD0-15

System Data Bus Input/Output

These pins are used to transfer data to and from the

PCnet-ISA II controller to system resources via the ISA

data bus. SD0-15 is driven by the PCnet-ISA II control-

BABL Babble

RCVCCO Receive Collision Coun t Overflow

JAB Jabber

MISS Mis sed Frame

MERR Memory Error

MPCO Missed Packet Count Overflow

RINT Receive Interrupt

IDON Initializ ati on D one

TXDATSTRT Transmit Start

Number Pin Function in Bus

Master Mode Pin Function in

GPSI Mode

10 LA17 RXDAT

11 LA18 SRDCLK

12 LA19 RXCRS

13 LA20 CLSN

15 LA21 STDCLK

16 LA22 TXEN

17 LA23 TXDAT

20 Am79C961A

ler when pe rfor m ing bus master wri tes and sl ave read

operations. Likewise, the data on SD0-15 is latched by

the PCnet-ISA II controller when performing bus

master reads and slave write operations.

Board Interfac e

IRQ12/FlashWE

Flash Write Enable Output

Optional interface to the Flash memory boot PROM

Write Enable.

IRQ15/APCS

Address PROM Chip Select Output

When programmed as APCS in Plug and Pla y Regist er

F0, this signal is asser ted when the external Address

PROM is read. When an I/O read operation is

performed on the first 16 bytes in the PCnet-ISA II con-

troller’s I/O space, APCS is asserted. The outputs of

the e xternal Address PR OM drive the PROM Data Bus.

The PCnet-IS A II controll er buffers the contents of th e

PROM data bus and drives them on the lower eight bits

of the System Data Bus.

When programmed to IRQ15 (default), this pin has the

same function as IRQ 3, 4, 5, 9, 10, 11, or 12.

BPCS

Boot PROM Ch ip Select Output

This signal is asserted when the Boot PROM is read. If

SA0-19 lines match a predefined address block and

MEMR is acti ve and RE F inactive , the BPCS signal will

be asser ted. The outputs of the external Boot PROM

dri ve the PROM Data Bus. The PCnet-IS A II contr oll er

buffers the conte nts of the P ROM data bus and dr ives

them on the lower eight bits of the System Data Bus.

DXCVR/EAR

Disable Transceiver/

External Addres s Reject Input/Output

This pin can be used to disable external transceiver

circuitry attached to the A UI interface when the internal

10BASE -T por t is active. The polari ty of this pin is set

by the DXCVRP bit (PnP register 0xF0, bit 5). When

DXCVRP is cleared (default), the DXCVR pin is driven

HIGH when the Twisted Pair port is active or SLEEP

mode has been entered and driven LOW when the A UI

port is activ e . When DXCVRP is set, the DXCVR pin is

driven LOW when the Twisted Pair port is active or

SLEEP mode has been entered and driven HIGH when

the AUI port is active.

If EADI mode is selected, this pin becomes the EAR

input.

The incoming frame will be checked against the inter-

nally active address detection mechanisms and the

result of this check will be OR’d with the value on the

EAR pin. The EAR pin is defined as REJECT. (See the

EADI section for details regarding the function and

timing of this signal).

LEDO-3

LED Drivers Output

These pins sink 12 mA each for driving LEDs. Their

meaning is software configurable (see section The ISA

Bus Configuration Registers) and they are active LOW.

When EADI mode is selected, the pins named LED1,

LED2, and LED3 change in function while LED0

continues to indicate 10BASE-T Link Status.

PRDB3-7

Private Data Bus Input/Output

This is the data bus for the Boot PROM and the

Addres s PROM.

PRDB2/EEDO

Private data bus bit 2/Data Out Input/Output

A multifunction pin which serves as PRDB2 of the

private data bus and, when ISACSR3 bit 4 is set,

changes to become DATA OUT from the EEPROM.

PRDB1/EEDI

Private data bus bit 1/Data In Input/Output

A multifunction pin which serves as PRDB1 of the

private data bus and, when ISACSR3 bit 4 is set,

changes to become DATA In to the EEPROM.

PRDB0/EESK

Private data bus bit 0/

Serial Clock Input/Output

A multifunction pin which serves as PRDB0 of the

private data bus and, when ISACSR3 bit 4 is set,

changes to become Serial Clock to the EEPROM.

LED EADI Function

1SF/BD

2SRD

3 SRDCLK

Am79C961A 21

SHFBUSY

Shift Busy Input/Output

This pin indicates that a read from the external

EEPROM is in progress. It is active only when data is

being shifted out of the EEPROM due to a hardware

RESET or assertion of the EE_LOAD bit (ISACSR3, bit

14). If this pin is left unconnected or pulled low with a

pull-down resistor, an EEPROM checksum error is

fo rced. Nor mally, this pin s hould be connec ted to VCC

through a 10K Ω pull- up resistor.

EECS

EEPROM CHIP SELECT Output

This signal is asser ted when read or write accesses

are being performed to the EEPROM. It is controlled by

ISACSR3. It is driven at Reset during EEPROM Read.

SLEEP

Sleep Input

When SLEEP pin is asserted (active LOW), the PC-

net-ISA II cont roller p erfo rm s an inte rn al syste m reset

and proceeds into a power savings mode. All outputs

will be placed in their normal reset condition. All PC-

net-ISA II controller inputs will be ignored ex cept f or the

SLEEP pin itself. Deasser tion of SLEEP results in the

device waking up. The sys tem must delay th e s tar ting

of the network contr ol ler by 0.5 sec ond s to a ll ow inter-

nal analog circuits to stabilize.

XTAL1

Crystal Connection Input

The internal clock generator uses a 20 MHz crystal that

is attached to pins XTAL1 and XTAL2. Alternatively, an

external 20 MHz CMOS-compatible clock signal can be

used to dr ive this pin. Refer to the section on Exter nal

Crystal Characteristics for more details.

XTAL2

Crystal Connection Output

The internal clock generator uses a 20 MHz crystal that

is attached to pins XTAL1 and XTAL2. If an external

clock is used, this pin should be left unconnected.

22 Am79C961A

CONNECTION DIAGRAMS: BUS SLA V E MODE

PQFP 132

132

DVDD2

TCK

131 TMS

130 TDO

129 TDI

128 EECS

127 BPCS

126 SHFBUSY

125 PRDB0/EESK

124 PRDB1/EEDI

123 PRDB2/EEDO

122 PRDB3

121 DVSS2

120 PRDB4

119 PRDB5

118 PRDB6

117 PRDB7

116 DVDD1

115 LED0

114 LED1

113 DVSS1

112 LED2

111 LED3

110 DXCVR/EAR

109 AVDD2

108 CI+

107 CI–

106 DI+

105 DI–

104 AVDD1

103 DO+

102 DO–

101 AVSS1

100

DVDD4 35

PRAB12 36

PRAB13 37

PRAB14 38

PRAB15 39

SA13 40

SA14 41

SA15 42

SRWE 43

AEN 44

IOCHRDY 45

MEMW 46

MEMR 47

DVSS11 48

APCS/IRQ15 49

SRCS/IRQ12 50

IRQ11 51

DVDD5 52

IRQ10 53

IOCS16 54

BPAM 55

IRQ3 56

IRQ4 57

IRQ5 58

DVSS12 60

SROE 61

SMAM 62

IOR 63

IOW 64

IRQ9 65

RESET 66

DVSS3 2SMA 3SA0 4SA1 5SA2 6DVSS10 7SA3 8SA4 9SA5 10SA6 11SA7 12SA8 13SA9 14DVSS4 15SA10 16SA11 17SA12 18SBHE 19DVDD3 20PRAB0 21PRAB1 22PRAB2 23DVSS5 24PRAB3 25PRAB4 26PRAB5 27PRAB6 28PRAB7 29PRAB8 30PRAB9 31DVSS6 32PRAB10 33PRAB11

Am79C961AKC

REF

DVSS7

19364B-3

Am79C961A 23

BLOCK DIAGRAM: BUS SLAVE MODE

19364B-4

LED[0-3]

ISA Bus

Interface

Unit

RCV

FIFO

XMT

FIFO

Control

Buffer

Management

Unit

EEPROM

Interface

Unit

802.3

MAC

Core

Encoder/

Decoder

(PLS) &

AUI Port

10BASE-T

MAU

Private

Bus

Control

JTAG

Port

Control

AEN

IOCHRDY

IOR

IOW

IRQ[3, 4, 5, 9,

10, 11, 12]

IOCS16

MEMR

MEMW

REF

RESET

SBHE

SD[0-15]

SA[0-15]

SLEEP

SHFBUSY

EEDO

EEDI

EESK

EECS

DXCVR/EAR

CI+/-

DI+/-

XTAL1

XTAL2

DO+/-

RXD+/-

TXD+/-

TXPD+/-

TDO

TMS

TDI

TCK

SMA

IRQ15/APCS

BPCS

PRAB[0-15]

PRDB[0-7]

SROE

SRWE

SMAM

BPAM

DVDD[1-7]

DVSS[1-13]

AVDD[1-4]

AVSS[1-2]

24 Am79C961A

PIN DESIGNATIONS: BUS SLAVE MODE

Listed by Pin Number

Pin # Name Pin # Name Pin # Name

1 DVSS3

SMA

SA0

SA1

SA2

DVSS10

SA3

SA4

SA5

SA6

SA7

SA8

45 IOCHRDY 89 RXD-

RXD+

AVDD4

TXPD-

TXD-

TXPD+

TXD+

AVDD3

XTAL1

AVSS2

XTAL2

AVSS1

DO-

DO+

AVDD1

DI-

DI+

CI-

CI+

AVDD2

DXCVR/EAR

LED3

LED2

DVSS1

LED1

LED0

246MEMW90

347MEMR91

4 48 DVSS11 92

5 49 IRQ15 93

6 50 IRQ12 94

7 51 IRQ11 95

8 52 DVDD5 96

9 53 IRQ10 97

10 54 IOCS16 98

11 55 BPAM 99

12 56 IRQ3 100

13 SA9

DVSS4

SA10

SA11

SA12

SBHE

DVDD3

PRAB0

PRAB1

PRAB2

DVSS5

PRAB3

PRAB4

PRAB5

PRAB6

PRAB7

PRAB8

PRAB9

DVSS6

PRAB10

PRAB11

DVDD4

PRAB12

PRAB13

57 IRQ4 101

14 58 IRQ5 102

15 59 REF 103

16 60 DVSS12 104

17 61 SROE 105

18 62 SMAM 106

19 63 IOR 107

20 64 IOW 108

21 65 IRQ9 109

22 66 RESET 110

23 67 DVDD6 111

24 68 SLEEP 112

25 69 SD0 113

26 70 SD8 114

27 71 SD1 115 DVDD1

PRDB7

PRDB6

PRDB5

PRDB4

DVSS2

PRDB3

PRDB2/EEDO

PRDB1/EEDI

PRDB0/EESK

SHFBUSY

BPCS

EECS

TDI

TDO

TMS

TCK

DVDD2

28 72 SD9 116

29 73 DVSS8 117

30 74 SD2 118

31 75 SD10 119

32 76 SD3 120

33 77 SD11 121

34 78 DVDD7 122

35 79 SD4 123

36 80 SD12 124

37 PRAB14

PRAB15

DVSS7

SA13

SA14

SA15

SRWE

AEN

81 SD5 125

38 82 SD13 126

39 83 DVSS9 127

40 84 SD6 128

41 85 SD14 129

42 86 SD7 130

43 87 SD15 131

44 88 DVSS13 132

Am79C961A 25

PIN DESIGNATIONS: BUS SLAVE MODE

Listed by Pin Name

Name Pin# Name Pin# Name Pin#

AEN

AVDD1

AVDD2

AVDD3

AVDD4

AVSS1

AVSS2

BPAM

BPCS

CI-

CI+

DI-

DI+

DO-

DO+

DVDD1

DVDD2

DVDD3

DVDD4

DVDD5

DVDD6

DVDD7

DVSS1

DVSS10

DVSS11

DVSS12

44 IRQ15 49 SA13

SA14

SA15

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SBHE

SD0

SD1

SD10

SD11

SD12

SD13

SD14

SD15

SD2

SD3

SD4

103 IRQ3 56 41

108 IRQ4 57 42

96 IRQ5 58 5

91 IRQ9 65 7

100 LED0 114 8

98 LED1 113 9

55 LED2 111 10

126 LED3 110 11

106 MEMR 47 12

107 MEMW 46 13

104 PRAB0 20 18

105 PRAB1 21 69

101 PRAB10 32 71

102 PRAB11 33 75

115 PRAB12 35 77

132 PRAB13 36 80

19 PRAB14 37 82

34 PRAB15 38 85

52 PRAB2 22 87

67 PRAB3 24 74

78 PRAB4 25 76

112 PRAB5 26 79

6 PRAB6 27 SD5

SD6

SD7

SD8

SD9

SHFBUSY

SLEEP

SMA

SMAM

SROE

SRWE

TCK

TDI

TDO

TMS

TXD-

TXD+

TXPD-

TXPD+

XTAL1

XTAL2

48 PRAB7 28 84

60 PRAB8 29 86

DVSS13

DVSS2

DVSS3

DVSS4

DVSS5

DVSS6

DVSS7

DVSS8

DVSS9

DXCVR/EAR

EECS

IOCHRDY

IOCS16

IOR

IOW

IRQ10

IRQ11

IRQ12

88 PRAB9 30 70

120 PRDB0/DO 124 72

1 PRDB0/D1 123 125

14 PRDB0/SCLK 122 68

23 PRDB3 121 2

31 PRDB4 119 62

39 PRDB5 118 61

73 PRDB6 117 43

83 PRDB7 116 131

109 REF 59 128

127 RESET 66 129

45 RXD- 89 130

54 RXD+ 90 93

63 SA0 3 95

64 SA1 4 92

53 SA10 15 94

51 SA11 16 97

50 SA12 17 99

26 Am79C961A

PIN DESIGNATIONS: BUS SLAVE MODE

Listed by Group

Pin Name Pin Function I/O Driver

ISA Bus Interface

AEN Address Enable I

IOCHRDY I/O Channel Ready O OD3

IOCS16 I/O Chip Select 16 O OD3

IOR I/O Read Select I

IOW I/O Write Select I

IRQ[3, 4, 5, 9, 10, 11, 12, 15] Interrupt Request O TS3/OD3

MEMR Me mory Read Select I

MEMW Memory Write Select I

REF Memory Refresh Active I

RESET System Reset I

SA[0–15] System Address Bus I

SBHE System Byte High Enable I

SD[0–15] System Data Bus I/O TS3

Board Interfaces

IRQ15/APCS IRQ15 or Address PROM Chip Select O TS1

BPCS Boot PROM Chip Select O TS1

BPAM Boot PROM Address Match I

DXCVR/EAR Disable Transceiver I/O TS1

LED0 LED0/LNKST OTS2

LED1 LED1/SFBD/RCVACT OTS2

LED2 LED2/SRD/RXDATD01 OTS2

LED3 LED3/SRDCLK/XMTACT OTS2

PRAB[0–15] PRivate Address Bus I/O TS3

PRDB[3–7] PRivate Data Bus I/O TS1

SLEEP Sleep Mode I

SMA Slave Mode Architecture I

SMAM Shared Memory Address Match I

SROE Static RAM Output Enable O TS3

SRWE Static RAM Write Enable O TS1

XTAL1 Crystal Oscillator Input I

XTAL2 Crystal Oscillator OUTPUT O

SHFBUSY Read access from EEPROM in process O

PRDB(0)/EESK Serial Shift Clock I/O

PRDB(1)/EEDI Serial Shift Data In I/O

PRDB(2)/EEDO Serial Shift Data Out I/O

EECS EEPROM Chip Select O

Am79C961A 27

PIN DESIGNATIONS: BUS SLAVE MODE

Listed by Group

Output Driver Types

Pin Name Pin Function I/O Driver

Attachment Unit Interface (AUI)

CI±

DI±

DO±

Collision Inputs

Receive Data

Transmit Data

Twisted Pair Transceiver Interface (10BASE-T)

RXD±

TXD±

TXPD±

10BASE-T Receive Data

10BASE-T Transmit Data

10BASE-T Predist ortion Control

IEEE 1149.1 Test Access Port Interface (JTAG)

TCK

TDI

TDO

TMS

Test Clock

Test Data Input

Test Data Output

Test Mode Select

ITS2

Power Supplies

AVDD

AVSS

DVDD

DVSS

Analog Power [1-4]

Analog Ground [1-2]

Digital Power [1-7]

Digital Ground [1-13]

Name Type IOL (mA) IOH (mA) pF

TS1 Tri-State 4 –150

TS2 Tri-State 12 –450

TS3 Tri-State 24 –3120

OD3 Open Dra in 24 –3120

28 Am79C961A

PIN DESCRIPTION: BUS SLAVE MODE

ISA Interface

AEN

Address Enable Input

This signal must be driven LOW when the bus performs

an I/O access to the device.

IOCHRDY

I/O Channel Ready Output

When the PCnet-ISA II cont roller is being ac cess ed, a

HIGH on IO CHRDY i ndicates that valid data exists o n

the data bus for reads and that dat a has been latche d

for wri tes .

IOCS16

I/O Chip Select 16 Input/Output

When an I/O read or wr ite operati on is perfor med, the

PCnet-ISA II controller will drive this pin LOW to indi-

cate that the chip supports a 16-bit operation at this

address. (If the motherboard does not receive this

signal, then the motherboard will convert a 16-bit

access to two 8-bit accesses).

The PCnet-I SA II con trol ler f ollo ws th e IEEE P 996 spe c-

ification that recommends this fu nction be implemented

as a pure decode of SA0-9 and AEN, with no depen-

dency on IOR, or IOW; however, some PC/AT clone

systems are not compatible with this approach. For this

reason, the PCnet-ISA II controller is recommended to

be configured to run 8-bit I/O on all machines. Since data

is moved by memory cycles there is virtually no

performance loss incurred by running 8-bit I/O and

compatibility problems are vir tually eliminated. The PC-

net-ISA II controller can be configured to run 8-bit-only I/

O b y cl ea ring Bi t 0 in Plug an d Play Register F0.

IOR

I/O Read Input

To perform an Input/Output Read operation on the

device IOR must be asserted. IOR is only valid if the

AEN sig nal is LOW and th e external addre ss matc hes

the PCnet-ISA II controller’s predefined I/O address

location. If valid, IOR indicates that a slav e read opera-

tion is to be performed.

IOW

I/O Write Input

To perform an Input/Output write operation on the

device IOW must be asserted. IOW is on ly valid if A EN

signal is LOW and the external address matches the

PCnet-ISA II controller’s predefined I/O address loca-

tion. If valid, IOW indicates that a slave write operation

is to be performed.

IRQ3, 4, 5, 9, 10, 11, 12, 15

Interrupt Request Output

An attention signal which indicates that one or more of

the following status flags is set: BABL, MISS, MERR,

RINT, IDON or TXSTRT. All status flags have a mask

bit which allows for suppression of IRQ assertion.

These flags have the following meaning:

MEMR

Memory Read Input

MEMR goes LOW to perform a memory read

operation.

MEMW

Memory Write Input

MEMW goes LOW to perform a memor y write opera-

tion.

REF

Memory Refresh Input

When REF is asserted, a memor y refresh cycle is in

progress. During a refresh cycle, MEMR assertion

is ignored.

RESET

Reset Input

When RESET is asserted HIGH, the PCnet-ISA II

controller performs an internal system reset. RESET

must be held f or a minimum of 10 XTAL1 periods before

being deasserted. While in a reset state, the PCnet-ISA

II controller will tristate or deassert all outputs to

predefined reset levels. The PCnet-ISA II controller

resets itself upon power-up.

SA0-15

System Address Bus Input

This bus carries the address inputs from the system

address bus. Address data is stable during command

active cycle.

BABL Babble

RCVCCO Receive Collision Count Overflow

JAB Jabber

MISS Missed Fram e

MERR Memory Error

MPCO Missed Packet Count Overflow

RINT Receive Interrupt

IDON Initialization Done

TXSTRT Transmit Start

Am79C961A 29

SBHE

System Bus High Enable Input

This signal indicates the HIGH byte of the system data

bus is to be used. There is a weak pull-up resistor on

this pin. If the P Cnet-ISA II contr oller is installe d in an

8-bit on ly system l ike the PC/XT, SBH E will always be

HIGH and the P Cnet-IS A II cont roller w ill perform on ly

8-bit operations. There must be at least one LOW going

edge on this signal before the PCnet-ISA II controller

will perform 16-bit operations.

SD0-15

System Data Bus Input/Output

This bus is used to transfer data to and from the PC-

net-ISA II controller to system resources via the ISA

data bus. SD0-15 is driven by the PCnet-ISA II

controller when perf orming slave read operations.

Likewise, the data on SD0-15 is latched by the PC-

net-ISA II controller when performing slave write

operations.

Board Interfac e

APCS/IRQ15

Address PROM Chip Select Output

This signal is asserted when the external Address

PROM is read. When an I/O read operation is per-

formed on the first 16 bytes in the PCnet-ISA II

controller’s I/O space, APCS is asser ted. Th e outputs

of the external Address PROM drive the PROM Data

Bus. The PCnet-ISA II controller b uffers the contents of

the PROM data bus and drives them on the lower eight

bits of the System Data Bus. IOCS16 is not asserted

duri ng this cycl e.

BPAM

Boot PROM Address Ma tch Input

This pin indicates a Boot PROM access cycle. If no

Boot PROM is in stall ed, thi s pi n has a de fa ult value of

HIGH and thus may be left connected to VDD.

BPCS

Boot PROM Ch ip Select Output

This signal is asserted when the Boot PROM is read. If

BPAM is active and MEMR is active, the BPCS signal

will be asserted. The outputs of the external Boot

PROM drive the PROM Data Bus. The PCnet-ISA II

controller buffers the contents of the PROM data bus

and drives them on the System Data Bus. IOCS16 is

not asserted during this cycle. If 16-bit cycles are

performed, it is the responsibility of external logic to

assert MEMCS16 signal.

DXCVR/EAR

Disable Transceiver/

External Address Reject Input/Output

This pin disables the transceiv er . The DXCVR output is

configured in the initialization sequence. A high level

indicates the Twisted Pair Interface is active and the

AUI is inactive, or SLEEP mode has been entered. A

low lev el indicates the A UI is active and the Twisted Pair

interface is inactive.

If EADI mode is selected, this pin becomes the EAR

input.

The incoming frame will be checked against the inter-

nally active address detection mechanisms and the

result of this check will be OR’d with the value on the

EAR pin. The EAR pin is defined as REJECT. (See the

EADI section for details regarding the function and tim-

ing of this signal).

LED0-3

LED Drivers Output

These pins sink 12 mA each for driving LEDs. Their

meaning is software configurable (see section The ISA

Bus Configuration Registers) and they are active LOW.

When EADI mode is selected, the pins named LED1,

LED2, and LED3 change in function while LED0

continues to indicate 10BASE-T Link Status. The

DXCVR input becomes the EAR input.

PRAB0-15

Private Address Bus Input/Output

The Private Address Bus is the address bus used to

drive the Address PROM, Remote Boot PROM, and

SRAM.

PRDB3-7

Private Data Bus Input/Output

This is the data bus for the static RAM, the Boot PROM,

and the Address PROM.

PRDB2/EEDO

Private Data Bus Bit 2/Data Out Input/Output

A multifunction pin which serves as PRDB2 of the

private data bus and, when ISACSR3 bit 4 is set,

changes to become DATA OUT from the EEPROM.

LED EADI Function

1SF/BD

2SRD

3 SRDCLK

30 Am79C961A

PRDB1/EEDI

Private Data Bus Bit 1/Data In Input/Output

A multifunction pin which serves as PRDB1 of the

private data bus and, when ISACSR3 bit 4 is set,

changes to become DATA In to the EEPROM.

PRDB0/EESK

Private Data Bus Bit 0/

Serial Clock Input/Output

A multifunction pin which serves as PRDB0 of the

private data bus and, when ISACSR3 bit 4 is set,

changes to become Serial Clock to the EEPROM.

SHFBUSY

Shift Busy Input/Output

This pin indicates that a read from the external

EEPROM is in progress. It is active only when data is

being shifted out of the EEPROM due to a hardware

RESET or assertion of the EE_LOAD bit (ISACSR3, bit

14). If this pin is left unconnected or pulled low with a

pull-down resistor, an EEPROM checksum error is

fo rced. Nor mally, t his pin should be connected to V CC

through a 10K Ω pull- up resistor.

EECS

EEPROM CHIP SELECT Output

This signal is asser ted when read or write accesses

are being performed to the EEPROM. It is controlled by

ISACSR3. It is driven at Reset during EEPROM Read.

SLEEP

Sleep Input

When SLEEP input is asser t ed (active LOW ), the PC-

net-ISA II cont roller p erfo rm s an inte rn al syste m reset

and proceeds into a power savings mode. All outputs

will be placed in their normal reset condition. All PC-

net-ISA II controller inputs will be ignored except f or the

SLEEP pin itself. Deasser tion of SLEEP results in the

device waking up. T he system must delay the star ting

of the networ k co ntr olle r by 0.5 sec ond s to a ll ow inter-

nal analog circuits to stabilize.

SMA

Slave Mode Archit ectu re Input

This pin must be permanently pulled LOW f or operation

in the Bus Slav e mode. It is sampled after the hardware

RESET sequence. In the Bus Slave mode, the PC-

net-ISA II can be programm ed for Shared Mem ory ac-

cess or Programmed I/O access through the PIOSEL

bit (ISACSR2, bit 13).

SMAM

Shared Memory

Address Match Input

When the Shared Memory architecture is selected

(ISACSR2, bit 13), this pin is an input that indicates an

access to shar ed memory w hen asserted. Th e type of

access is decided by MEMR or MEMW.

When the Programmed I/O architecture is selected,

this pin should be permanently tied HIGH.

SROE

Static RAM Output Enable Output

This pin directly controls the external SRAM’s OE pin.

SRCS/IRQ12

Static RAM Chip Select Output

This pin directly controls the external SRAM’s chip

select (CS) pin when the Flash boot ROM option is

selected.

When F lash boot ROM option is not sel ected, this pi n

becomes IRQ12.

SRWE/WE

Static RAM Write Enable/

Write Enable Output

This pin (SRWE) directly controls the external SRAM’s

WEpin when a Flash memory device is not

implemented.

When a Flash me mory device is impl em ente d, thi s pin

becomes a global write enable (WE) pin.

XTAL1

Crystal Connection Input

The internal clock generator uses a 20 MHz crystal that

is attached to pins XTAL1 and XTAL2. Alternatively, an

external 20 MHz CMOS-compatible clock signal can be

used to dr ive this pin. Refer to the section on Exter nal

Crystal Characteristics for more details.

XTAL2

Crystal Connection Output

The internal clock generator uses a 20 MHz crystal that

is attached to pins XTAL1 and XTAL2. If an external

clock is used, this pin should be left unconnected.

Am79C961A 31

PIN DESCRIPTION:

NETWORK INTERFACES

AUI

CI+, CI–

Control Input Input

This is a di fferent ial input pa ir used to detect Co llision

(Signal Quality Error Signal).

DI+, DI–

Data In Input

This is a differen tial receive data input pair to the PC-

net-ISA II controller.

DO+, DO–

Data Out Output

This is a differentia l tran smit data outpu t pair from the

PCnet-ISA II controller.

Twisted Pair Interface

RXD+, RXD–

Receive Data Input

This is the 10BASE-T port differential receive input

pair.

TXD+, TXD–

Transmit Data Output

These are the 10BASE-T port differential transmit

drivers.

TXP+, TXP–

Transmit Predistortion Control Output

These are 10BASE-T transmit w aveform pre-distortion

control differential outputs.

PIN DESCRIPTION:

IEEE 1149.1 (JTAG) TEST ACCESS PORT

TCK

Test Clock Input

This is the clock input for the boundary scan test mode

operation. TCK can operate up to 10 MHz. TCK does

not have an inter nal pull-up res istor and must be con-

nected to a valid TTL lev el of high or low . TCK must not

be left unconnec ted .

TDI

Test Data Input Input

This is the test data input path to the PCnet-ISA II con-

troller. If left unconnected, this pin has a default valu e

of HIGH.

TDO

Test Data Output Output

This is the test d ata out put path from the PC net-IS A II

controller . TDO is tri-stated when JTAG port is inactive .

TMS

Test Mode Select Input

This is a serial input bit stream used to define the spe-

cific boundary scan test to be executed. If left uncon-

nected, this pin has a default value of HIGH.

PIN DESCRIPTION:

POWER SUPPLIES

All power pins with a “D” prefix are digital pins con-

nected to the digita l circu itr y an d digi tal I/O buffers. All

power pins with an “A” prefix are analog power pins

connected to the analog circuitry. Not all analog pins

are quiet and special precaution must be taken when

doing boar d layout. Som e analog pins ar e more noisy

than others and must be separated from the other

analog pins.

AVDD1–4

Analog Power (4 Pins) Power

Supplie s power to an alog por ti ons of the PCnet-IS A II

controller. Special attention should be paid to the

printed circuit board la y out to a v oid e xcessive noise on

these lines.

AVSS1–2

Analog Ground (2 Pins) Power

Supplies ground reference to analog portions of PC-

net-ISA II controller . Special attention should be paid to

the p rint ed circui t board lay out to av oid e xcess ive n oise

on these lines.

DVDD1–7

Digital Power (7 Pins) Power

Supplie s power to di gi tal po rtions of P C net -ISA II c on-

troller. Four pins are used by Input/Output buffer drivers

and two are used by the internal digital circuitry.

DVSS1–13

Digital Ground (13 Pins) Power

Supplies ground reference to digital portions of PC-

net-ISA II controller. Ten pins are used b y Input/Output

buffer drivers and two are used by the internal digital

circuitry.

32 Am79C961A

CONNECTION DIAGRAM

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

Am79C961AVC

TQFP 144

19364B-5

Am79C961A 33

PIN DESIGNATIONS: BUS MASTER MODE (TQFP 144)

Listed by Pin Number

Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name

1 NC 37 NC 73 NC 109 NC

2 DVSS3 38 DVDD4 74 DVDD6 110 AVSS1

3 MASTER 39 SA12 75 SLEEP 111 DO–

4 DRQ7 40 SA13 76 SD0 112 DO+

5 DRQ6 41 SA14 77 SD8 113 AVDD1

6 DRQ5 42 SA15 78 SD1 114 DI–

7 DVSS10 43 DVSS7 79 SD9 115 DI+

8DACK7

44 SA16 80 DVSS8 116 CI–

9DACK6

45 SA17 81 SD2 117 CI+

10 DACK5 46 SA18 82 SD10 118 AVDD2

11 LA17 47 SA19 83 SD3 119 DXCVR/EAR

12 LA18 48 AEN 84 SD11 120 LED3

13 LA19 49 IOCHRDY 85 DVDD7 121 LED2

14 LA20 50 MEMW 86 SD4 122 DVSS1

15 DVSS4 51 MEMR 87 SD12 123 LED1

16 LA21 52 DVSS11 88 SD5 124 LED0

17 LA22 53 IRQ15/APCS 89 SD13 125 DVDD1

18 LA23 54 IRQ12/FlashWE 90 DVSS9 126 PRDB7

19 SBHE 55 IRQ11 91 SD6 127 PRDB6

20 DVDD3 56 DVDD5 92 SD14 128 PRDB5

21 SA0 57 IRQ10 93 SD7 129 PRDB4

22 SA1 58 IOCS16 94 SD15 130 DVSS2

23 SA2 59 BALE 95 DVSS13 131 PRDB3

24 DVSS5 60 IRQ3 96 RXD–132 PRDB2/EEDO

25 SA3 61 IRQ4 97 RXD+ 133 PRDB1/EEDI

26 SA4 62 IRQ5 98 AVDD4 134 PRDB0/EESK

27 SA5 63 REF 99 TXPD–135 SHFBUSY

28 SA6 64 DVSS12 100 TXD–136 BPCS

29 SA7 65 DRQ3 101 TXPD+ 137 EECS

30 SA8 66 DACK3 102 TXD+ 138 TDI

31 SA9 67 IOR 103 AVDD3 139 TDO

32 DVSS6 68 IOW 104 XTAL1 140 TMS

33 SA10 69 IRQ9 105 AVSS2 141 TCK

34 SA11 70 RESET 106 XTAL2 142 DVDD2

35 NC 71 NC 107 NC 143 NC

36 NC 72 NC 108 NC 144 NC

34 Am79C961A

PIN DESIGNATIONS: BUS MASTER MODE (TQFP 144)

Listed by Pin Name

Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No.

AEN 48 DVSS3 2 NC 37 SA3 25

AVDD1 113 DVSS4 15 NC 71 SA4 26

AVDD2 118 DVSS5 24 NC 72 SA5 27

AVDD3 103 DVSS6 32 NC 73 SA6 28

AVDD4 98 DVSS7 43 NC 107 SA7 29

AVSS1 110 DVSS8 80 NC 108 SA8 30

AVSS2 105 DVSS9 90 NC 109 SA9 31

BALE 59 DXCVR/EAR 119 NC 143 SBHE 19

BPCS 136 EECS 137 NC 144 SD0 76

CI+ 117 IOCHRDY 49 PRDB0/EESK 134 SD1 78

CI–116 IOCS16 58 PRDB1/EEDI 133 SD10 82

DACK3 66 IOR 67 PRDB2/EEDO 132 SD11 84

DACK5 10 IOW 68 PRDB3 131 SD12 87

DACK6 9 IRQ10 57 PRDB4 129 SD13 89

DACK7 8 IRQ11 55 PRDB5 128 SD14 92

DI+ 115 IRQ12/FlashWE 54 PRDB6 127 SD15 94

DI–114 IRQ15/APCS 53 PRDB7 126 SD2 81

DO+ 112 IRQ3 60 REF 63 SD3 83

DO–111 IRQ4 61 RESET 70 SD4 86

DRQ3 65 IRQ5 62 RXD+ 97 SD5 88

DRQ5 6 IRQ9 69 RXD–96 SD6 91

DRQ6 5 LA17 11 SA0 21 SD7 93

DRQ7 4 LA18 12 SA1 22 SD8 77

DVDD1 125 LA19 13 SA10 33 SD9 79

DVDD2 142 LA20 14 SA11 34 SHFBUSY 135

DVDD3 20 LA21 16 SA12 39 SLEEP 75

DVDD4 38 LED0 124 SA13 40 TCK 141

DVDD5 56 LED1 123 SA14 41 TDI 138

DVDD6 74 LED2 121 SA15 42 TDO 139

DVDD7 85 LED3 120 SA16 44 TMS 140

DVSS1 122 MASTER 3 SA17 45 TXD+ 102

DVSS10 7 MEMR 51 SA18 46 TXD–100

DVSS11 52 MEMW 50 SA19 47 TXPD+ 101

DVSS12 64 NC 1 SA2 23 TXPD–99

DVSS13 95 NC 35 SA22 17 XTAL1 104

DVSS2 130 NC 36 SA23 18 XTAL2 106

Am79C961A 35

PIN DESIGNATIONS: BUS SLAVE (PIO AND SHARED MEMORY ) MODES (TQFP 144)

Listed by Pin Number

Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name

1NC37 NC 73NC109NC

2 DVSS3 38 DVDD4 74 DVDD6 110 AVSS1

3SMA

39 PRAB12 75 SLEEP 111 DO-

4 SA0 40 PRAB13 76 SD0 112 DO+

5 SA1 41 PRAB14 77 SD8 113 AVDD1

6 SA2 42 PRAB15 78 SD1 114 DI-

7 DVSS10 43 DVSS7 79 SD9 115 DI+

8 SA3 44 SA13 80 DVSS8 116 CI-

9 SA4 45 SA14 81 SD2 117 CI+

10 SA5 46 SA15 82 SD10 118 AVDD2

11 SA6 47 SRWE 83 SD3 119 DXCVR/EAR

12 SA7 48 AEN 84 SD11 120 LED3

13 SA8 49 IOCHRDY 85 DVDD7 121 LED2

14 SA9 50 MEMW 86 SD4 122 DVSS1

15 DVSS4 51 MEMR 87 SD12 123 LED1

16 SA10 52 DVSS11 88 SD5 124 LED0

17 SA11 53 IRQ15 89 SD13 125 DVDD1

18 SA12 54 IRQ12 90 DVSS9 126 PRDB7

19 SBHE 55 IRQ11 91 SD6 127 PRDB6

20 DVDD3 56 DVDD5 92 SD14 128 PRDB5

21 PRAB0 57 IRQ10 93 SD7 129 PRDB4

22 PRAB1 58 IOCS16 94 SD15 130 DVSS2

23 PRAB2 59 BPAM 95 DVSS13 131 PRDB3

24 DVSS5 60 IRQ3 96 RXD- 132 PRDB2/

EEDO

25 PRAB3 61 IRQ4 97 RXD+ 133 PRDB1/EEDI

26 PRAB4 62 IRQ5 98 AVDD4 134 PRDB0/EESK

27 PRAB5 63 REF 99 TXPD- 135 SHFBUSY

28 PRAB6 64 DVSS12 100 TXD- 136 BPCS

29 PRAB7 65 SROE 101 TXPD+ 137 EECS

30 PRAB8 66 SMAM 102 TXD+ 138 TDI

31 PRAB9 67 IOR 103 AVDD3 139 TDO

32 DVSS6 68 IOW 104 XTAL1 140 TMS

33 PRAB10 69 IRQ9 105 AVSS2 141 TCK

34 PRAB11 70 RESET 106 XTAL2 142 DVDD2

35 NC 71 PCMCIA_MODE 107 NC 143 NC

36 NC 72 NC 108 NC 144 NC

36 Am79C961A

PIN DESIGNATIONS: BUS SLAVE (PIO AND SHARED MEMORY ) MODES (TQFP 144)

Listed by Pin Name

Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No.

AEN 48 EECS 137 PRAB13 40 SA7 12

AVDD1 113 IOCHRDY 49 PRAB14 41 SA8 13

AVDD2 118 IOCS16 58 PRAB15 42 SA9 14

AVDD3 103 IOR 67 PRAB2 23 SBHE 19

AVDD4 98 IOW 68 PRAB3 25 SD0 76

AVSS1 110 IRQ10 57 PRAB4 26 SD1 78

AVSS2 105 IRQ11 55 PRAB5 27 SD10 82

BPAM 59 IRQ12 54 PRAB6 28 SD11 84

BPCS 136 IRQ15 53 PRAB7 29 SD12 87

CI+ 117 IRQ3 60 PRAB8 30 SD13 89

CI–116 IRQ4 61 PRAB9 31 SD14 92

DI+ 115 IRQ5 62 PRDB0/EESK 134 SD15 94

DI–114 IRQ9 69 PRDB1/EEDI 133 SD2 81

DO+ 112 LED0 124 PRDB2/EEDO 132 SD3 83

DO–111 LED1 123 PRDB3 131 SD4 86

DVDD1 125 LED2 121 PRDB4 129 SD5 88

DVDD2 142 LED3 120 PRDB5 128 SD6 91

DVDD3 20 MEMR 51 PRDB6 127 SD7 93

DVDD4 38 MEMW 50 PRDB7 126 SD8 77

DVDD5 56 NC 1 REF 63 SD9 79

DVDD6 74 NC 35 RESET 70 SHFBUSY 135

DVDD7 85 NC 36 RXD+ 97 SLEEP 75

DVSS1 122 NC 37 RXD–96 SMAM 66

DVSS10 7 NC 72 SA0 4 SMA 3

DVSS11 52 NC 73 SA1 5 SROE 65

DVSS12 64 NC 107 SA10 16 SRWE 47

DVSS13 95 NC 108 SA11 17 TCK 141

DVSS2 130 NC 109 SA12 18 TDI 138

DVSS3 2 NC 143 SA13 44 TDO 139

DVSS4 15 NC 144 SA14 45 TMS 140

DVSS5 24 PCMCIA_MODE 71 SA15 46 TXD+ 102

DVSS6 32 PRAB0 21 SA2 6 TXD–100

DVSS7 43 PRAB1 22 SA3 8 TXPD+ 101

DVSS8 80 PRAB10 33 SA4 9 TXPD–99

DVSS9 90 PRAB11 34 SA5 10 XTAL1 104

DXCVR/EAR 119 PRAB12 39 SA6 11 XTAL2 106

Am79C961A 37

BLOC K DIAGRAM: PCMCIA MODE

19364B-6

PCMCIA Bus

Interface

Unit

RCV

FIFO

XMT

FIFO

Control

Buffer

Management

Unit

EEPROM

Interface

Unit

802.3

MAC

Core

Encoder/

Decoder

(PLS) &

AUI Port

10BASE-T

MAU

Private

Bus

Control

JTAG

Port

Control

REG

CE2

CE1

WAIT

INPACK

STSCHG

IORD

IOWR

IREQ

IOIS16

VCC

RESET

A[0-15]

D[0-15]

PCMCIA_MODE

SMA

SMAM

SHFBUSY

EEDO

EEDI

EESK

DVDD[1-7]

DVSS[1-13]

AVDD[1-4]

AVSS[1-2]

DXCVR/EAR

CI±

DI±

XTAL1

XTAL2

DO±

RXD±

TXD±

TXPD±

FLCS

LED[0-3]

PRAB[0-15]

PRDB[0–7]

TDO

TMS

TDI

TCK

SLEEP

EECS

SROE

SRWE

SRCS

Optional

38 Am79C961A

PIN DESIGNATIONS: PCMCIA MODE (TQFP 144)

Listed by Pin Number

Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name

1 NC 37 NC 73 NC 109 NC

2 DVSS3 38 DVDD4 74 DVDD6 110 AVSS1

3SMA

39 PRAB12 75 SLEEP 111 DO–

4 SA0 40 PRAB13 76 SD0 112 DO+

5 SA1 41 PRAB14 77 SD8 113 AVDD1

6 SA2 42 PRAB15 78 SD1 114 DI–

7 DVSS10 43 DVSS7 79 SD9 115 DI+

8 SA3 44 SA13 80 DVSS8 116 CI–

9 SA4 45 SA14 81 SD2 117 CI+

10 SA5 46 SA15 82 SD10 118 AVDD2

11 SA6 47 SRWE 83 SD3 119 DXCVR/EAR

12 SA7 48 REG 84 SD11 120 LED3

13 SA8 49 WAIT 85 DVDD7 121 LED2

14 SA9 50 WE 86 SD4 122 DVSS1

15 DVSS4 51 OE 87 SD12 123 LED1

16 SA10 52 DVSS11 88 SD5 124 LED0

17 SA11 53 NC 89 SD13 125 DVDD1

18 SA12 54 SRCS 90 DVSS9 126 PRDB7

19 CE2 55 INPACK 91 SD6 127 PRDB6

20 DVDD3 56 DVDD5 92 SD14 128 PRDB5

21 PRAB0 57 STSCHG 93 SD7 129 PRDB4

22 PRAB1 58 IOIS16 94 SD15 130 DVSS2

23 PRAB2 59 CE1 95 DVSS13 131 PRDB3

24 DVSS5 60 IREQ 96 RXD–132 PRDB2/EEDO

25 PRAB3 61 NC 97 RXD+ 133 PRDB1/EEDI

26 PRAB4 62 NC 98 AVDD4 134 PRDB0/EESK

27 PRAB5 63 REF 99 TXPD–135 SHFBUSY

28 PRAB6 64 DVSS12 100 TXD–136 FLCS

29 PRAB7 65 SROE 101 TXPD+ 137 EECS

30 PRAB8 66 SMAM 102 TXD+ 138 TDI

31 PRAB9 67 IORD 103 AVDD3 139 TDO

32 DVSS6 68 IOWR 104 XTAL1 140 TMS

33 PRAB10 69 NC 105 AVSS2 141 TCK

34 PRAB11 70 RESET 106 XTAL2 142 DVDD2

35 NC 71 PCMCIA_MODE 107 NC 143 NC

36 NC 72 NC 108 NC 144 NC

Am79C961A 39

PIN DESIGNATIONS: PCMCIA MODE (TQFP 144)

Listed by Pin Name

Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No.

AVDD1 113 INPACK 55 PRAB4 26 SD1 78

AVDD2 118 IOIS16 58 PRAB5 27 SD10 82

AVDD3 103 IORD 67 PRAB6 28 SD11 84

AVDD4 98 IOWR 68 PRAB7 29 SD12 87

AVSS1 110 IREQ 60 PRAB8 30 SD13 89

AVSS2 105 LED0 124 PRAB9 31 SD14 92

CE1 59 LED1 123 PRDB0/EESK 134 SD15 94

CE2 19 LED2 121 PRDB1/EEDI 133 SD2 81

CI+ 117 LED3 120 PRDB2/EEDO 132 SD3 83

CI–116 NC 1 PRDB3 131 SD4 86

DI+ 115 NC 35 PRDB4 129 SD5 88

DI–114 NC 36 PRDB5 128 SD6 91

DO+ 112 NC 37 PRDB6 127 SD7 93

DO–111 NC 53 PRDB7 126 SD8 77

DVDD1 125 NC 61 REF 63 SD9 79

DVDD2 142 NC 62 REG 48 SHFBUSY 135

DVDD3 20 NC 69 RESET 70 SLEEP 75

DVDD4 38 NC 72 RXD+ 97 SMAM 64

DVDD5 56 NC 73 RXD–96 SMAM 66

DVDD6 74 NC 107 SA0 4 SRCS 54

DVDD7 85 NC 108 SA1 5 SROE 65

DVSS1 122 NC 109 SA10 16 SRWE 47

DVSS10 7 NC 143 SA11 17 STSCHG 57

DVSS11 52 NC 144 SA12 18 TCK 141

DVSS13 95 OE 51 SA13 44 TDI 138

DVSS2 130 PCMCIA_MODE 71 SA14 45 TDO 139

DVSS3 2 PRAB0 21 SA15 46 TMS 140

DVSS4 15 PRAB1 22 SA2 6 TXD+ 102

DVSS5 24 PRAB10 33 SA3 8 TXD–100

DVSS6 32 PRAB11 34 SA4 9 TXPD+ 101

DVSS7 43 PRAB12 39 SA5 10 TXPD–99

DVSS8 80 PRAB13 40 SA6 11 VSS 3

DVSS9 90 PRAB14 41 SA7 12 WAIT 49

DXCVR/EAR 119 PRAB15 42 SA8 13 WE 50

EECS 137 PRAB2 23 SA9 14 XTAL1 104

FLCS 136 PRAB3 25 SD0 76 XTAL2 106

40 Am79C961A

PIN DESCRIPTION: PCMCIA MODE

The PCMCIA pins function as described in the

PCMCIA Specification Revision 2.1. Please refer to it

fo r more deta ils.

The non-PCMCIA pins used by the 144-pin TQFP

package have the same functions as described by “Pin

Descri pti on : Bus Sl ave Mode” for IS A o peration begin-

ning on page 26 of the Am79C961A PCnet-ISA II data

sheet (PID #19364A) with the exception of pin 71,

PCMCIA_MODE.

PCMCIA_MODE Input

Sets the device for PCMCIA operati on when tied h igh.

This pin is not avail able in the 132-pin P QFP package

option.

Am79C961A 41

PCMCIA vs. ISA Pinout Comparison

The pins listed below are pin definition changes spe-

cific to PCMCIA mode: In PCMCIA mode, a number of

the input pins have inter nal resistors tur ned on with a

resistance greater than 100 KΩ. Thes e res ist ors a re ei-

ther connected to VCC or VSS. The diagram below

shows the pin connections for the ISA slave mode and

PCMCIA mode.

PCMCIA Pin Specification Changes

In ISA mode, the IOCHRDY and IOCS16 signals are

defined as Open Drain outputs. In PCMCIA mode,

the W AIT and IOIS16 signals are full CMOS drivers . In

PCMCIA mode, the Max values for tIOR8, tMR8 and

tSFR10 change from 10 ns to –40 ns.

—PCMCIA-MODE1 should be tied to VSS in ISA

slave mode

—PCMCIA-MODE2 should be tied to VCC in

PCMCIA mode

—SLEEP3 pin remains functional in PCMCIA

mode, it is recommended to tie it to VCC

Pin Number

TQFP144 ISA

Slave Mode PCMCIA

Mode

PCMCIA

Input Pin Resistance

> 100 KΩ

19 SBHE CE2 to VCC

48 AEN REG to VCC

49 IOCHRDY WAIT

50 MEMW WE to VCC

51 MEMR OE to VCC

53 IRQ15 NC

54 IRQ12 SRCS

55 IRQ11 INPACK

57 IRQ10 STSCHG

58 IOCS16 IOIS16

59 BPAM CE1 to VCC

60 IRQ3 IREQ

61 IRQ4 NC

62 IRQ5 NC

67 IOR IORD to VCC

68 IOW IOWR to VCC

69 IRQ9 NC

70 RESET RESET to VCC

71 PCMCIA_MODE1PCMCIA_MODE2

75 SLEEP SLEEP3

SD0–SD15 D0–D15 to GND

SA0–SA15 A0–A1 5 to GND

42 Am79C961A

PCM C I A M ODE BLOCK DIAGRA M

PCnet-ISA II

Controller

PRAB[0–15]

SRCS

SRWE

SMAM

SD[0–15]

SA[0–15] PRDB[0–7]

SROE

FLCS

PCMCIA

Bus

16-Bit System

Data

System Address

Bus

D[0–7]A[1–19]

Note:

SMAM shown only for Shared Memory architecture designs. SMAM should be tied HIG H on the PCne t-ISA II for Prog ram med

I/O architecture designs in order to access th e flash memor y at common memory location zero.

SRAM

70 ns

CS OE

A[0–15]

CS OE

Flash/EPROM

120 ns

19364B-7

PCMCIA Control

A[0]

D[0–7]

(Upper Address pin)

[0]

Plug and Play Compatible with Flash Memory Support

Am79C961A 43

FUNCTIONAL DESCRIPTION

PCMCIA Operation

When a PCMCIA card is first plugged into a PCMCIA

host, all PCMCIA cards respond as a memory only

device. In the PCMCIA standar d there are two memory

spaces, common memory and attribute memory. The

REG pin deter mines which memor y space is selected.

After the host detects that the PCMCIA card is inser ted,

the host reads a section of the attribute memory called the

CIS (Card Information Structure) which provides

configuration information about the inserted card. The

attribute memory is a byte wide memor y which is only

addressable on even bytes. Consequently, odd byte

accesses are not defined f or attribute memory. Mapped in

the CIS area are f our Card Config uration Regist ers which

are physically located inside the PCnet-ISA II dev ice. In

the PCne t-ISA II de vice th ere are f our reg isters which are

located at decimal byte address 1008, 1010, 1012 and

1014, respectively. Inside the CIS data structure, there is

information which provides the base address of the Card

Config urat ion Regist ers .

Inside firs t Card Config uration Registe r is a config ura-

tion inde x region which allows programming the device

to support I/O accesses. The PCnet-ISA II suppor ts

PCMCIA’s Independent I/O address window mecha-

nism. When I/O Enabl e is set in the CCR 0 register the

PCnet-IS A II controller will respon d to I/O comma nds.

The lower 5 address bits decode register accesses.

The PCMCIA host is expe cted to decode I/O address

bits 6 and abov e and only assert CE1 and/or CE2 if the

upper I/O address lines match. After the host has

mapped the PCMCIA’s card resources to the system,

the card should be visible by the system and the driver

may be loaded.

Serial EEPROM Support

The Serial EEPROM is not required in PCMCIA mode

but can be used to hold the contents of the IEEE address

EEPROM. For cost purposes, it is recommended to

place the IEEE address in the CIS (Card Information

Structure) Attribute Memory.

Flash Memory Map

The PCnet-ISA II device supports either a single Flash or

EPROM device. The external flash device contains the

CIS area as well as an area located in common memory

used to hold software drivers. The attr ibute memory or i-

gin is located at byte 0. The common memor y region is

accessed when REG is deasser ted and an access to

common memor y occur s. SMAM is nor mally conne cted

to an upper address line on the PCMCIA card. When a

high order address is asserted the Flash Memory will be

selected. Accesses to common memory when SMAM is

low will access the Shared RAM when Shared Memo ry

mode is selected. If P rogrammed I/O mode is used, the

SMAM can be tied high which will result in the Flash’s

base address being mapped to location zero.

Flash Memory Programming

The Flash Memory device can be read at anytime. In

order to program the flash de vice, the APWEN bit must

be set in ISACSR2 register to allow write operations to

the Flash or non-volatile EEPROM device.

Shared Memory vs. Pr ogra mmed I/O

Implications

The PCnet-ISA II controller in PCMCIA modes allo ws for

the loc al packet buffe r m em ory to be map ped into com-

mon memory or indirectly accessed through I/O ac-

cesses. If shared memory is chosen, the local SRAM will

be mapped as a memory resource. Consequently, the

CIS will have to indicate this requirement to t he system.

If Programmed I/O is used no additional memory re-

sources w ill be require d t o be all oc ated b y the syst em.

44 Am79C961A

FLASH MEMORY M AP AND CARD REGISTERS

CCR 3

CCR 1

CCR 2

CCR 0

Reserved

CIS

Data

FLASH

Common

Memory

(Not Availa ble)

(Unused)

131070 Byte (1FFFEh)

1024 Byte (400h)

1022 Byte (3FEh)

1016 Byte (3F8h)

1014 Byte (3F6h)

1012 Byte (3F4h)

1010 Byte (3F2h)

1008 Byte (3F0h)

1006 Byte (3EEh)

0 Byte (0h)

Attribute Memory

Comm on Me mory

19364B-8

Am79C961A 45

FUNCTIONAL DESCRIPTION

The PCnet-ISA II controller is a highly integrated system

solution for the PC-AT ISA architecture. It provides a Full

Duplex Ethernet controller, AUI port, and 10BASE-T

tr ansceiver . The PCnet-ISA II controller can be d irectly in-

terfaced to an ISA system bus . The PC net-ISA II cont rol-

ler contains an ISA bus interface unit, DMA Buffer

Managem ent Un it, 80 2.3 Med i a Access Co nt rol f unct ion ,

separate 136-byte transmit and 128-byte receive FIFOs,

IEEE defined Attachment Unit Interface (AUI), and

Twisted-Pair Transceiver Media Att achment Unit . In addi-

tion, a Sleep function has been incor porated which pro-

vides low standby current for power sensitive applications.

The PCnet-ISA II controller is register compatible with

the LANCE (Am7990) Ethernet controller and PC-

net-ISA (Am79C960). The DMA Buffer Management

Unit supports the LANCE descriptor software model

and the PCnet-ISA II controller is software compatible

with the Novell NE2100 and NE1500T add-in cards.

External remote boot PROMs and Ethernet physical

address PROMs are supported. The location of the I/O

registers, Ethernet address PROM, and the boot PROM

are determined by the programming of the r egisters in-

ternal to PCnet-ISA II. These registers are loaded at

RESET from the EEPROM, if an EEPROM is utilized.

Normally, the Ethernet physical address will be stored in

the EEPROM with the other configuration data. This

reduces the parts count, board space requirements,

and power consumption. The option to use a standard

parallel 8 bit PROM is provided to manufactures who

are concerned about the non-volatile nature of

EEPROMs.

The PCnet-ISA II controller’s bus master architecture

brings to system manufacturers (adapter card and

motherboard makers alike) something they have not

been able to enjoy with other architectures—a low-cost

system solution that provides the lowest parts count

and highest performance. As a bus-mastering device,

costly and power-hungry external SRAMs are not

needed for packet buffering. This results in lower sys-

tem cost due to f ew er components, less real-estate and

less pow er. The PCnet-ISA II controller’s advanced b us

mastering architecture also provides high data through-

put and low CPU utilization for even better perf ormance.

To offer greater fle xibility, the PCnet-ISA II controller has

a Bus Slave mode to meet varying application needs.

The bus slave mode utilizes a local SRAM memor y to

store the descriptors and buff ers that are located in sys-

tem memory when in Bus Master mode. The SRAM can

be slave accessed on the ISA bus through memory

cycles in Shared Memory mode or I/O cycles in Pro-

grammed I/O mode. The Shared Memory and Pro-

gr ammed I/O architectures offer maximum compatibility

with low-end machines, such as PC/XTs that do not

support bus mastering, and very high end machines

which require local packet buffering for increased

system latency.

The network interface provides an Attachment Unit

Interface and Twisted-Pair Transceiver functions. Only

one interface is active at any par ticular time. The AUI

allows for connection via isolation transformer to

10BASE 5 and 10B ASE2, t hick and thin b ased co axial

cables. The Twisted-Pair Transceiver interface allows

for connection of unshielded twisted-pair cables as

specifi ed by the Sectio n 14 supp lemen t to IEEE 802. 3

Standard (Type 10BASE-T).

Impor tant Note About The EEPROM

Byte Map

The user is cautioned that while the Am79C961A (PC-

net-ISA II) and its associated EEPROM are pin compatible

to their predecessors the Am79C961 (PCnet-ISA+) and its

associated EEPROM, the byte map structure in each of

the EEPROMs are different from each other .

The EEPROM byte map structure used for the

Am79C961A PCnet-ISA II has the addition of “MISC Con-

fig 2, ISACSR9" at word location 10Hex. The EEPROM

byte map structure used for the Am79C961 PCnet-ISA+

does not ha v e th is.

Therefore, should the user intend to replace the PC-

net-ISA+ with the PCnet-ISA II, care MUST be taken to re-

program the EEPROM to reflect the new byte map

structure nee ded and used by the PCnet-ISA I I. F or addi-

tional informatio n, refer to the sectio n in this data sheet

under EEPROM and the Am79C961 PCnet-ISA+ data

sheet ( PID #1818 3) under the section s enti tled EEPROM

and Serial EEPROM Byte Map.

Bus Mast er Mode

System Interface

The PCnet-ISA II controller has two fundamental oper-

ating modes , Bus Master and Bus Sla ve . Within the Bus

Slave mode, the PCnet-ISA II can be pr ogr ammed f or a

Shared Memory or Programmed I/O architecture. The

selection of either the Bus Master mode or the Bus

Slave mode must be done through hard wiring; it is not

software configurable. When in the Bus Slave mode, the

selection of the Shared Memory or Programmed I/O

architecture is done through software with the PIOSEL

bit (ISACSR2, bit 13).

The optio nal Boot PROM is in memory address sp ace

and is expected to be 8–64K. On-chip address compar-

ators co ntrol devic e selection i s based on the value in

the EEPROM.

The address PROM, board configuration registers, and

the Ethernet controller occupy 24 bytes of I/O space

and can be located at 16 different starting addresses.

46 Am79C961A

19364B-9

EECS

ISA

Bus

16-Bit

System Data

24-Bit System

Address

PCnet-ISA II

Controller

Boot

PROM

(Optional)

SD[0-15]

SA[0-19]

LA[17-23]

BPCS CE OE

D[0-7]

A[0-15]

ORG

EEPROM

(Optional,

Common)

VCC

SHFBUSY

VCC

PRDB[2]/EEDO

PRDB[1]/EEDI

PRDB[0]/EESK

PRDB[0-7]

Bus Master Block Diagram Plug and Play Compatible

19364B-10

Bus Master Block Diagram Plug and Play Compatible

ISA

Bus

24-Bit

System

Address

PCnet-ISA II

Controller

IEEE

Address

PROM

(Optional)

SD[0-15]

SA[0-19]

LA[17-23]

PRDB[0-7]

D[0-7]

BPCS

A[0-4]

EEPROM

(Optional,

Common)

EECS

Flash

(Optional)

PRDB[0]/EESK

PRDB[1]/EEDI

PRDB[2]/EEDO

ORG

D[0-7]

A[0-15]

16-Bit

System

Data

SHFBUSY

VCC

IRQ15/APCS IRQ12/FlashWE

with Flash and parallel Address PROM Support

VCC

Am79C961A 47

Bus Sla v e Mode

System Interface

The Bus Sl ave mode is the other fundam ental operat-

ing mode available on the PCnet-ISA II controller.

Within the Bus Slave mode, the PCnet-ISA II can be

programmed for a Shared Memory or Programmed I/O

architecture. In the Bus Slave mode the PCnet-ISA II

controller uses the same descriptor and buffer architec-

ture as in the Bus Master mode, but these data s truc-

tures are stored in a static RAM controlled by the

PCnet-ISA II controller. When operating with the

Shared Memory architecture, the local SRAM is visible

as a memory resource on the PC which can be

accessed through memory cycles on the ISA bus inter-

face. When operating with the Programmed I/O archi-

tecture, the local SRAM is accessible through I/O

cycles on the ISA bus. Specifically, the SRAM is acces-

sible using the RAP and IDP I/O ports to access the

ISACSR0 and ISACSR1 regi sters, which ser ve as the

SRAM Data port and SRAM Address Pointer port,

respectively.

In the B us S lave m ode, the P Cnet-ISA II regi s ters an d

optional Ethernet physical address PROM look the

same and are accessed in the same way as in the Bus

Master mode.

The Boot PROM is selected by an external device

which drives the Boot PROM Address Match (BPAM)

input to the PCnet-ISA II controller. The PCnet-ISA II

controller can perform two 8-bit accesses from the 8-bit

Boot PROM and present 16-bits of data to accommo-

date 16 bit read accesses on the ISA bus.

When using the Shared Memory architecture mode,

access to the local SRAM works the same way as

access to the Boot PROM, with an e xternal device gen-

erating the Shared Memor y Address Match (SMAM)

signal and the PCnet-ISA II controller performing the

SRAM read or write and the 8/16 bit data conversion.

Ext ernal logi c must al so driv e ME MCS16 appropriately

for the 128Kbyte segment decoded from the LA[23:17]

signals.

The Programmed I/O architecture mode uses the RAP

and IDP ports to allow access to the local SRAM

hence, external address decoding is not necessary and

the SMAM pin is not used in Programmed I/O architec-

ture mode (SMAM should be tied HIGH in the Pro-

gr ammed I /O archit ecture m ode). Si milar to the Shar ed

Memory architecture mode, in the Programmed I/O ar-

chitecture mode, 8/16 bit conversion occurs when 16

bit rea ds an d writes a re p er formed on the S RAM Data

Port (ISACSR1).

Converting the local SRAM accesses from 8-bit cycles

to 16-bit cycles allows use of the much faster 16-bit

cycle timing while cutting the number of bus cycles in

half. This raises performance to more than 400% of

what could be achieved with 8-bit cycles. When the

Shared Memory architecture mode is used, converting

boot PROM accesses to 16-bit cycles allows the two

memor y resourc es to be in the sam e 128 Kbyte block

of memory without a clash between two devices with

different data widths.

The PCnet-ISA II prefetches data from the SRAM to

allow fast, minimum wait-state read accesses of con-

secutive SRAM addresses. In both the Shared Memory

architecture and the Programmed I/O architecture,

prefetch data is read from a speculated address that

assumes that successive reads in time will be from

adjacent ascending addresses in the SRAM. At the

beginnin g of each SRAM read c ycle, th e PCnet-ISA II

determines whether the prefetched data can be

assumed to be valid. If the prefetched data can be

assumed to be valid, it is driven onto the ISA bus

without inserting any wait states. If the prefetched data

cannot be assumed to be valid, the PCnet-ISA II will in-

sert wait states into the ISA bus read cycle until the

correct word is read from the SRAM.

48 Am79C961A

Bus Slave Block Diagram

Plug and Pla y Compatible with Flash Memory Support

EECS

ISA

Bus

24-Bit System

Address

PCnet-ISA II

Controller PRDB[2]/EEDO

PRDB[1]/EEDI

PRDB[0]/EESK

16-Bit

System Data

PRAB[0-15]

IRQ12/SRCS

VCC

D[0-7]

D[0–7]

A[0-15]

A[0–15]

MEMCS16

SA[16] LA[17-23]

VCC

Note:

SMAM shown only for Shared Memory architecture designs. SMAM should be tied HIG H on the PCne t-ISA II for Prog ram med

I/O architecture designs.

SRWE

SMAM

SHFBUSY BPAM

SD[0]

SA[0]

PRDB[0]

SROE

BPCS

SRAM

External

Glue

Logic

BPAM

SHFBUSY

SIN

CLK

EEPROM

CS OE

CS ORG

Flash

(Optional)

19364B-11

Am79C961A 49

PLUG AND PLAY

Plug and P lay is a s tan dar di zed method of c onf igu ring

jumperless adapter cards in a system. Plug and Play is

a Microsoft standard and is based on a central software

configuration program, either in the operating system

or elsewhere, which is responsible for configuring all

Plug and Play cards in a system. Plug and Play is fully

supported by the PCnet-ISA II ethernet controller.

For a copy of the Microsoft Pl ug and Play specifica tio n

contact Microsoft Inc. This specification should be

referenced in addition to PCnet-ISA II Technical

Reference Manual and this data sheet.

Operation

If the PCnet-ISA II ethernet controller is used to boot off

the networ k, the device will come u p active at RESET,

otherwise it will come up inactive. Information stored in

the ser ial EEPROM is used to identify the card and to

describe the system resources required by the card,

such as I/O space, Memory space, IRQs and DMA

channels. This information is stored in a standardized

Read Only format. Operation of the Plug and Play

system is shown as follows:

■Isolate the Plug and Play card

■Read the cards resource data

■Identify the card

■Configure its resources

The Plug and Play mode of operation allows the follow-

ing benefits to the end user.

■Eliminates all jumpers or dip switches from the

adapter card

■Ease of use is greatly enhanced

■Allows the ability to uniquely address identical cards

in a system, without conflict

■Allows the software configuration program or OS to

read out the system resource requirements

required by the card

■Defines a mechanism to set or modify the current

configuration of each card

■Maintain backward compati bilit y with other ISA bus

adapters

Auto-Configuration Ports

Three 8 bit I/O ports are used by the Plug and Play con-

figuration software on each Plug and Play device to

communicate with the Plug and Play registers. The

ports are listed in the table below. The software config-

uration space is defined as a set of 8 bit registers.

These registers are used by the Plug and Play software

configuration to issue commands, access the resource

information, check status, and configure the PCnet-ISA

II controller hardware.

The address and Write_DATA ports are located at

fixed, predefined I/O addresses. The Write_Data port is

located at an alias of the Address port. All three

auto-configuration ports use a 12-bit ISA address

decode.

The READ_DATA port is relocatable within the range

0x203–0x3FF by a command written to the

WRITE_ DATA port.

ADDRESS PORT

The internal Plug and Play registers are accessed by

writing the ad dress to the ADDRESS PORT and then

either read ing the RE AD_ DATA P ORT or wr iting to the

WRITE_DATA PORT. Once the A DDRESS PORT has

been written, any numb er of reads or writes ca n o cc ur

without having to rewrite the ADDRESS PORT.

The ADDRESS PORT is also the address to which the

initiation key is written to, which is described later.

WRITE_DATA PORT

The WRITE_DATA PORT is the address to which all

writes to the internal Plug and Pla y registers occur . The

destination of the data written to the WRITE_DATA

PORT is determined by the last value written to the

ADDR ES S PO RT.

READ_DATA PORT

The READ_DATA PORT is used to read information

from the inte rnal Plug and P lay register s. The register

to be read is determined by the last value of the

ADDR ES S PO RT.

The I/O address of the READ_DATA PORT is set by

writing the chosen I/O location to Pl ug and Play Reg-

ister 0. The isolation protocol can deter mine that the

address chosen is free from conflict with other devices

I/O ports.

Initiation Key

The PCnet-ISA II controller is disabled at reset when

operating in Pl ug and P lay mode. It will no t res po nd t o

any memory or I/ O a cces ses, nor will t he P Cnet -I SA II

controller drive any interrupts or DMA channels.

The initiation key places the PCnet-ISA II device into

the config uration mode. This is done by writing a pre-

defined pattern to the ADDRESS PORT. If the proper

sequenc e of I/O w r ites a re de tected by the P Cnet- ISA

II device, the Plug and Play auto-configuration ports

Po rt Name Locati on Type

ADDRESS 0X279 (Printer Status Port) Write-only

WRITE-DATA 0xA79 (Printer status port +

0x0800) Write-only

READ-DATA Relocatable in range

0x0203-0x03FF Read-only

50 Am79C961A

are enabled. Thi s patte r n must b e sequ ential, i.e., any

other I/O access to this I/O port will reset the state

machine which is checking the pattern. Interrupts

should be disabled during this time to eliminate any

extra neo us I/O cycles.

The exact sequence for the initiation ke y is listed below

in hexadecimal.

6A, B5, DA, ED, F6, FB, 7D, BE

DF, 6F, 37, 1B, 0D, 86, C3, 61

B0, 58, 2C, 16, 8B, 45, A2, D1

E8, 74, 3A, 9D, CE, E7, 73, 39

Isolation Protocol

A simple algorithm is used to isolate each Plug and

Play card. This algorithm uses the signals on the ISA

bus and requires lock-step operation between the Plug

and Play hardware and the isolation softw are.

The key element of this mechanism is that each card

contains a unique number, referred to as the serial

identifier for the rest of the discussion. The serial iden-

tifier is a 72-bit unique, non-zero , n umber composed of

two , 32-bit fields and an 8-bit checksum. The first 32-bit

field is a vendor identifier. The other 32 bits can be any

value, for example, a serial number, part of a LAN

address, or a static number, as long as there will never

be two cards in a single system with the same 64 bit

number. The s erial id enti fie r is ac ce ss ed bit- se rially by

the isolation logic and is used to diff erentiate the cards.

The shift order for all Plug and Play serial isolation and

resource data is defined as bit[0], bit[1], and so on

through bit[7].

Hardware Protocol

The is olation pr otocol can be invoked by the P lug and

Play software at any time. The init ia tion key, described

earlier, puts all cards into configuration mode. The

hardware on each card expects 72 pairs of I/O read

accesses to the READ_DATA port. The card’s

response to these reads depends on the v alue of each

bit of the ser ial identifi er which i s being examined on e

bit at a time in the sequence shown above.

If the current bit of the serial identifier is a “1", then the

card will drive the data bus to 0x55 to complete the first

I/O read cycle. If the bit is “0", then the card puts its data

bus driver into high impedance. All cards in high imped-

ance wil l check the data bus dur ing the I/O read cycle

to sense if another card is driving D[1:0] to “01". During

the second I/O read, the card(s) that drove the 0x55,

will now drive a 0xAA. All high impedance cards will

check the data bus to sense if another card is driving

D[1:0] to “10". Between pairs of Reads, the software

should wait at least 30 µs.

If a high impedance card sen sed another c ard driv ing

the data bus with the appropriate data during both

cycles, then that card ceases to par ticipate in the cur-

rent iteration of card isolation. Such cards, which lose

out, will participate in future iterations of the isolation

protocol.

Note: During each read cycle, the Plug and Play hard-

ware drives the entire 8-bit databus, but only checks

the lower 2 bits.

State

Isolation

Read all 72 bits

from serial

identifier

ID bit = “1H”

SD[1:0] = “01"

Wait for next read from serial isolation register

SD[1:0] = “10"

State

Sleep

One

Card

Isolated

Read from seria l

isol ation register Get one bit from

serial identifier

Yes No

Yes

Drive “55H”

on SD[7:0] Leave SD in

high-impedance

Leave SD in

high-impedance

Drive “AAH”

on SD[7:0]

Yes

After I/O read

completes, fetch

next ID bit from

serial identifier

ID = 0;

other card

ID = 1

19364B-12

Plug and Play ISA Card

Isolation Algorithm

Shifting of Serial Identifier

Byte

0 Byte

3 Byte

2 Byte

1Byte

0 Byte

3 Byte

2 Byte

1 Byte

Shift

Check-

sum Serial

Number Vendor

19364B-13

Am79C961A 51

If a card was dr iving the bus or if the car d was in high

impedanc e and did no t sense another car d driving th e

bus, then it should prepare for the next pair of I/O

reads. The card shifts the serial identifier by one bit and

uses the shi fted bit to decide its re sponse. The abov e

sequence is repeated for the entire 72-bit serial

identifier.

At the end of this process, one card remains. This card

is assigned a handle referred to as the Card Select

Number (CSN) that will be used later to select the card.

Cards which have been assigned a CSN will not partic-

ipate in s ubsequ ent iterati ons of the isolati on protoc ol.

Cards must be assigned a CSN before they will

respond to the other commands defined in the

specification.

It should be noted that the protocol permits the 8-bit

checksum to be stored in non-volatile memory on the

card or generated by the on-card logic in real-time. The

same LFSR algorithm described in the initiation key

sec tion of the Pl ug and Play spe cific ation is used in the

checksum generation.

Software Protocol

The Pl ug an d Play softwa re send s the ini tiation key to

all Plug and Play cards to place them into configuration

mode. The software is then ready to perform the isola-

tion protocol.

The Plug an d Play software generates 72 pairs of l/O

read cycles from the READ_DATA port. The software

checks the data returned from each pair of I/O reads for

the 0x55 and 0xAA driven by the hardware. If both 0x55

and 0xAA are read back, then the software assumes

that the hardware had a “1" bit in that position. All other

results are assumed to be a “0.”

During the first 64 bits, software generates a checksum

using the received data. The checksum is compared

with the checksum read back in the last 8 bits of the

sequence.

There are two other special considerations for the soft-

ware protocol. During an iteration, it is possible that the

0x55 and 0xAA combination is never detected. It is also

possible th at th e c hec ksum doe s n ot m atc h If e ithe r of

these cases occur on the first iteration, it must be

assumed that the READ_DATA port is in conflict. If a

conflict is detected, then the READ_DATA port is

reloca ted. The abov e process is re peated until a n on-

conflicting location for the READ_DATA port is found.

The entire range between 0x203 and 0x3FF is avail-

able, howev er in practic e it is ex pec ted that onl y a fe w

locatio ns will be tried before software determines that

no Plug and Play cards are present.

During subs equent ite rations, the o ccurrenc e of either

of these two special cases should be interpreted as the

absence of any further Plug and Play cards (i.e. the last

card was found in the previous iteration). This

terminates the isolation protocol.

Note: The software must delay 1 ms prior to starting

the first pair of isolation reads, and must wai t 250 µsec

between ea ch su bs equ ent p ai r of i so lat ion r ead s. Th is

delay gives the ISA card time to access information

from possibly very slow storage devices.

Plug and Play Card Control Registers

The state transitions and card control commands for

the PCnet-ISA II controller are shown in the following

figure.

52 Am79C961A

Plug and Play ISA Card State Transitions

Notes:

1. CSN = Card Select Number.

2. RESET_DRV causes a state transition from the current state to Wait for Key and sets all CSNs to

zero. All logical devices are set to their power-up configuration values.

3. The Wait for Key command causes a state transition from the current state to Wait for Key.

Po wer up

RESET_DRV

State Active Commands

Initiation Key

Set CSN = 0

Wait for Key no active commands

State Active Commands

Sleep

Reset

Wa it for Key

Wake[CSN]

State Active Commands

Isolation

Reset

Wait for Key

Set RD_DATA Port

Serial Isolation

Wake[CSN]

Stat e Active Commands

Config

Reset

Wa it for Key

Wake[CSN]

Resource Data

Status

Logi cal Device

I/O Range Check

Activate

Configuration Registers

Set CSN

Lose serial location OR

(WAKE <> CSN) WAKE <> CSN

19364B-13

Plug and Play Registers

The PCnet-ISA II controller supports all of the defined

Plug and P lay card contro l register s. Refer to th e tables

on the following pages for detailed information.

Am79C961A 53

Plug and Play Standard Registers

Name Address

Port Value Definition

Set RD_D ATA P ort 0x00 Writin g to this locat ion modifies the address of the port use d fo r reading from the

Plug and Play ISA cards. Bits[7:0] become I/O read port address bits [9:2].

Reads from this register are ignored. I/O Address bits 11:10 should = 00, and 1:0 = 11.

Serial Isolation 0x01 A read to this register causes a Plug and Play card in the Isolation state to

compare one bit of the board’s ID. This process is fully described above. This

Config Control 0x02 Bit[0] - Reset all log ic al devices and resto re con fig uration registers to their

power-up values.

Bit[1] - Return to the Wait for Key state

Bit[2] - Reset CSN to 0

A write to bit[0] of this register performs a reset function on all logical devices.

This rese ts the content s of configur ation registers to their default stat e. All card’s

logical devices enter their default state and the CSN is preserved.

A write to bit[1] of this register causes all cards to e nter the Wait for Key state but

all CSNs are preserved and logical devices are not affected.

A write to bit[2] of this register causes all cards to reset their CSN to zero.

This register is write-only. The values are not sticky, that is, hardware will

automatically clear them and there is no need for software to clear the bits.

Wake[CSN] 0x03 A wr ite to this port will cause all cards that have a CSN that matches the write

data[7:0 ] to go from the Sleep st ate to either the Isolation state if th e w rite da ta

for this command is zero or the Config state if the write data is not zero. This

beginning of the Plug and Play Data Structure.

Resource Data 0x04 A re ad from this address reads the ne xt b yte of reso urce inf ormation. Th e Status

Status 0x05 Bit[0] when set indicates it is okay to read the next data byte from the Resource

Data register. This register is read-only.

Card Select Number 0x06 A write to this port sets a card’s CSN. The CSN is a value uniquely assigned to

each ISA card after the serial identification process so that each card may be

individually selected during a Wake [CSN] command. This register is read/write.

Logical Device Number 0x07 Selects the current logical device. This register is read only. The PCnet-ISA II

controller has only 1 logical device, and this register contains a value of 0x00

54 Am79C961A

PLUG AND PLAY LOGICAL DEVICE CONFIGURATION REGISTERS

The PCnet-ISA II controller suppor ts a subset of the

defined Plug and Play logical device control registers.

The reason for only supporting a subset of the registers

is that the PCnet-ISA II controller does not require as

many system resources as Plug and Play allows. For

instance, Memory Descriptor 2 is not used, as the PC-

net-ISA II controller only requires two memory

descriptors, one for the Boot PROM/Flash, and one for

the SRAM in Shared Memor y Mode.

Plug and Play Logical Device Control Registers

Memory Space Configuration

I/O Space Configuration

Name Address

Port Value Definitio n

Activate 0x30 For each logical device there is one activate register that controls whether or

not the logical de vice is activ e on t he ISA b us. Bi t[0], if set, activ ates th e logica l

device. Bits[7:1] are reserved an d must be zero. This is a read/write register.

Before a logical device is activate d, I/O range check must be disable d.

I/O Range Check 0x31 This register is used to perfor m a conflict check on the I/O port range

programmed for use by a logical d evice.

Bit[7:2] Rese rved

Bit 1[1] Enable I/O Range check, if set then I/O Range Check is enabled. I/O

range check is only valid when the logical device is inactive.

Bit[0], if set, forces the logical device to respond to I/O reads of the logical

device’s assigned I/O ra nge with a 0x 55 whe n I/O ran ge chec k is in oper ation .

If clear, the logical device drives 0xAA. This register is read/write.

Name Register

Index Definition

Memory base address

bits[23:16] descriptor 0 0x40 Read/write value indicating the selected memory base address bits[23:16] for

memory descriptor 0. This is the Boot Prom Space.

Memory base address

bits [15:08] descriptor 0 0x41 Read/write value indicating the selected memor y base address bits[15:08] for

memory descriptor 0.

Memory control 0x42 Bit[1] specifies 8/16-bit control. The encoding relates to memory control

(bits[4:3]) of the information field in the memory descriptor.

Bit[0], =0, indicates the next field is used as a range length for decode

(implies range length and base alignment of memory descriptor are equal).

Bit[0] is read-only.

Memory upper limit

address;

bits [23:16] or range

length;

bits [15:08] for

descriptor 0

0x43 Read/write value indicating the selected memor y high address bits[23:16] for

memory descriptor 0.

If bit[0] of memory control is 0, this is the range length.

If bit[0] of memory control is 1, this is considered invalid.

Memory upper limit

bits [15:08] or range

length;

bits [15:08] for

descriptor 0

0x44 Read/write value indicating the selected memor y high address bits[15:08] for

memory desc riptor 0, ei ther a memory addres s or a ran ge len gth as desc ribed

above.

Memory descriptor 1 0x48-0x4C Memory descriptor 1. This is the SRAM Space for Shared Memory.

Name Register

Index Definition

I/O port base address

bits[15:08] descriptor 0 0x60 Read/write value indicating the selected I/O lower limit address bits[15:08] for

I/O descriptor 0. If a logical device indicates it only uses 10 bit encoding, then

bits[15:10] do not need to be supported.

I/O port base address

bits[07:00] descriptor 0 0x61 Read/write value indicating the selected I/O lower limit address bits[07:00] for

I/O des cripto r 0.

Am79C961A 55

I/O Interrupt Configuratio n

DMA Channel Configuration

DETAILED FUNCTIONS

EEPROM

Interface

The EEPROM supported by the PCnet-ISA II controller

is an indu stry standar d 93 C56 2-K bi t EE PROM device

which uses a 4-wire interface. This de vice directly inter-

faces to the PCnet-ISA II controller through a 4-wire

interface which uses 3 of the pr ivate data bus pins for

Data In, Data Out, and Serial Clock. The Chip Select

pin is a dedicated pin from the PCnet-ISA II controller.

Note: A ll data st ored in the EEPR OM is stor ed in bi t-re-

versal forma t. E ac h word ( 16 bits) m ust be wr itten int o

the EEPROM with bit 15 swapped with bit 0, bit 14

swapped with bit 1, etc.

This is a 2-Kbit device organized as 128 x 16 bit words.

A map of the device as used in the PCnet-ISA II con-

tro ller is below . The i nform atio n stor ed in th e EEPRO M

is as follows:

Impor tant Note About The EEPROM

Byte Map

The user is cautioned that while the Am79C961A (PC-

net-ISA II) and its associated EEPROM are pin com-

patible to their predecessors the Am79C961

(PCnet-ISA+) and its associated EEPROM, the byte

map structure in each of the EEPROMs are different

from each other.

The EEPROM byte map structure used for the

Am79C961A PCnet-ISA II has the addition of “MISC

Config 2, ISACSR9" at word location 10Hex. The

EEPROM byte map structure used for the Am79C961

PCnet-ISA+ does not have this.

Therefore, should the user intend to replace the PC-

net-ISA+ with the PCnet-ISA II, care MUST be taken to

reprogram the EEPROM to reflect the new byte map

structure needed and used by the PCnet-ISA II. For

additional information, refer to the Am79C961 PC-

net-ISA+ data sheet (PID #18183) under the sections

entitled EEPROM and Serial EEPROM Byte Map.

Name Register

Index Definition

Interrupt request level

select 0 0x70 Read/write value indicating selected interrupt level. Bits[3:0] select which interrupt

level used for Interrupt 0. One selects IRQL 1, fifteen selects IRQL fifteen. IRQL 0 is

not a valid interrupt selection and represents no interrupt selection.

Interrupt request type

select 0 0x71

Read/write value indicating which type of interrupt is used for the Request Level

sel ected above.

Bit[1] : Level, 1 = high, 0 = low

Bit[0] : Type, 1 = level, 0 = edge

The PCnet-ISA II controller only supports Edge High and Level Low Interrupts.

Name Register

Index Definition

DMA channel select 0 0x74

Read/write value indicating selected DMA channels. Bits[2:0] select which DMA

channel is in use for DMA 0. Zero selects DMA channel 0, seven selects DMA

channe l 7. DM A channe l 4, the cascade channel i s used t o indica te no D MA chann el

is active.

DMA channel select 1 0x75 Read only with a value of 0x04.

IEEE address 6 bytes

Reserved10 bytes

EISA ID4 bytes

ISACSRs14 bytes

Plug and Play Defa ults 19 b yt es

8-Bit Checksum1 byte

External Shift Chai n2 bytes

Plug and Play Config Info192 bytes

56 Am79C961A

Basic EEPROM Byte Map

The following is a byte map of the XXC56 series of

EEPROMs used by the PCnet-ISA II Ethernet

Controller. This byte map is for the case where a

non-PCnet Family compatible software driver is

implemented.

Note:

Checksum is calculated on words 0 through 0x1Bh (first 56 by tes).

Byte 1

Byte 3

Byte 5

Byte 7

Byte 9

Byte 11

Byte 13

Byte 15

EISA Byte 1

EISA Byte 3

Byte 0

Byte 2

Byte 4

Byte 6

Byte 8

Byte 10

Byte 12

Byte 14

EISA Byte 0

EISA Byte 2

MSRDA, ISACSR0

MSWRA, ISACSR1

MISC Config 1, ISACSR2

LED1 Config, ISACSR5

LED2 Config, ISACSR6

LED3 Config, ISACSR7

MISC Config 2, ISACSR9

PnP 0x61

Pnp 0x71

Unused

PnP 0x41

PnP 0x43

Unused

PnP 0x49

PnP 0x4B

Unused

8–Bit Checksum

PnP 0x60

PnP 0x70

PnP 0x74

PnP 0x40

PnP 0x42

PnP 0x44

PnP 0x48

PnP 0x4A

PnP 0x4C

PnP 0xF0

External Shif t Chain

Unused Locati ons

Plug and Play St arting Location

IEEE Address (0h)

(8h)

Internal Registers

(11h)

Plug and Play Reg.

(1Ah)

(20h)

EISA Config Reg.

(Ah)

(1Bh)

(1Ch)

Word

Location

I/O Ports

Interrupts

DMA Channels

ROM Memory

RAM Memory

Vendor Byte

(Bytes 0 – 5)

Am79C961A 57

AMD Device Driver Compatible

EEPROM Byte Map

The following is a byte map of the XXC56 series

of EEPROMs used by the PCnet-ISA II Ethernet

Controller. This byte map is for the case where a

PCnet Family compatible software driver is imple-

mented.

(This byte map is an application reference for use in

developing AMD software devices.)

Note:

Checksum 1 is calculated on words 0 through 5 plus word 7.

Checksum 2 is calculated on words 0 through 0x1Bh (first 56 bytes).

IEEE Address

Internal Registers

Plug and Play Reg.

See Appendix C

EISA Config Reg.

Word

Location

I/O Ports

Interrupts

DMA Channels

ROM Me mory

RAM Memory

Vendor Byte

See Appendix C

(Bytes 0–5)

Byte 1

Byte 3

Byte 5

ASCII W (0 x 57H)

EISA Byte 1

EISA Byte 3

Byte 0

Byte 2

Byte 4

ASCII W (0 x 57H)

EISA Byte 0

EISA Byte 2

MSRDA, ISACSR0

MSWRA, ISACSR1

MISC Config, ISACR2

LED1 Config, ISACSR5

LED2 Config, ISACSR6

LED3 Config, ISACSR7

MISC Config 2, ISACSR9

PnP 0x61

Pnp 0x71

Unused

PnP 0x41

PnP 0x43

Unused

PnP 0x49

PnP 0x4B

Unused

8-B it Checksum

PnP 0x60

PnP 0x70

PnP 0x74

PnP 0x40

PnP 0x42

PnP 0x44

PnP 0x48

PnP 0x4A

PnP 0x4C

PnP 0xF0

External Shift Chain

Unused Locations

Plug and Play Starting Location

User Space 1

16-Bit Checksum 1

Reserved

HWID (01H)

Reserved

58 Am79C961A

Plug and Play Register Map

The following char t and its bit descriptions show the

internal configuration registers associated with the

Plug and Play operation. These registers control the

configuration of the PCnet-ISA II controller.

Plug and

Play Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0x00 READ_DATA

0x01 SERIAL ISOLATION

0x02 0 0 0 0 0 RST WAIT RST

CSN KEY ALL

0x03 WAKE [CSN]

0x04 RESOURCE_DATA

0x05 0 0 0 0 0 0 0 READ

STATUS

0x06 CSN

0x07 LOGICAL DEVICE NUMBER

0x30 0 0 0 0 0 0 0 ACTIVATE

0x31 0 0 0 0 0 0 IORNG IORNG

READ_DATA Address of Plug and Play READ_DATA Port.

SERIAL_ISOLATION Used in the Serial Isolation process.

RST_CSN Resets CSN register to zero.

WAIT_KEY Rese ts Wait for Key State.

RST_ALL Res ets all logical devices.

WAKE [CSN] Will wake up if write data matches CSN Register.

READ_STATUS Read Status of RESOURCE DATA.

RESOURCE_DATA Next pending byte read from EEPROM.

CSN Plug and Play CSN Value.

ACTIVATE Indicates that the PCnet-ISA II device should be activated.

IORNG Bits used to enable the I/O Range Check Command.

Am79C961A 59

The following chart and its bit descriptions show the

internal command registers associated with the Plug and Play operation. These registers control the PC-

net-I SA I I co ntr ol le r Pl ug an d Pl ay oper a ti on .

PCnet–ISA II’s Legacy Bit Feature

Description

The current PCnet-ISA II chip is desig ned such that it

always responds to Plug and Play configuration soft-

ware. There ar e situatio ns wher e this re spons e to the

Plug and Play software is un desira ble. An exa mple o f

this is when a fixed configuration is required, or when

the only po ssi ble resource available for the P Cne t-ISA

II conflicts with a present but not used resource such as

IRQ, or when the chip is used in a system with a bugg y

PnP BIOS.

To function in the situations above, a new feature has

been added to the PCnet-ISA II chip . This new feature

makes the chi p ignor e the P nP so ftware’s s pecia l ini ti-

ation key sequence (6A). This will effect ively tur n the

chip into the “Legacy” mode operation, where it will be

visible in the I/O space, and only special setup pro-

grams will be able to reconfigure it. In case the

EEPROM is mis sin g, empty, or co rru pted, the chip will

still recognize AMD’s special initiation key sequence

(6B).

To en able this feature, a one has to be wr itten into th e

LGCY_EN bit, which is bit 6 of the Plug and Play regis-

ter 0xF0. A preferred method would be set this bit in

the Vendor Byte (PnP 0xF0) field of the EEPROM

located in word offset 0x1A.

Plug and

Play Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0x60 0 0 0 0 0 0 1 IOAM3

0x61 IOAM2 IOAM1 IOAM0 0 0 0 0 0

0x70 0 0 0 0 IRQ3 IRQ2 IRQ1 IRQ0

0x71 0 0 0 0 0 0 IRQ_LVL IRQ_TYPE

0x74 0 0 0 0 0 DMA2 DMA1 DMA0

0x40 0 0 0 0 1 1 0 BPAM3

0x41 BPAM2 BPAM1 BPAM0 0 0 0 0 0

0x42 0 0 0 0 0 0 BP_16B 0

0x43 1 1 1 1 1 1 1 BPSZ3

0x44 BPSZ2 BPSZ1 BPSZ0 0 0 0 0 0

0x48 0 0 0 0 1 1 SRAM4 SRAM3

0x49 SRAM2 SRAM1 SRAM0 0 0 0 0 0

0x4A 0 0 0 0 0 0 SR16B 0

0x4B 1 1 1 1 1 1 1 SRSZ3

0x4c SRSZ2 SRSZ1 SRSZ0 0 0 0 0 0

0xF0 0 LGCY_EN DXCVRP FL_SEL BP_CS APROM_EN AEN_CS IO_MODE

60 Am79C961A

Plug & Play Register Locations Detailed

Description (Refer to the Plug & Play

IOAM[3:0] I/O Address Match to bits [8:5] of SA

bus (PnP 0x60–0x61). Controls the

base address of PCnet-ISA II. The

IOAM will be written with a value

from the EEPROM.

IRQ[3:0] IRQ selection on the ISA bus (PnP

0x70). Controls which interrupt will

be asserted. ISA Edge sensitive or

EISA level mode is controlled by

IRQ_TYPE bit in PnP 0x71. Default

is ISA Edg e Sensitive. The IRQ sig-

nals will not be driven unless PnP

activate register bit is set.

IRQ Type IRQ Type(PnP 0x71). Indicates the

type of interrupt setting; Level is 1,

Edge is 0.

IRQ_LVL IRQ Le v el (PnP 0x71). A read-only regis-

ter bit that indicates the type of setting, ac-

tive high or low. Always complement of

IRQ_TYPE. See ISA CSR2 (EISA_LVL).

DMA[2:0] DMA Channel Select (PnP 0x74).

Controls the DRQ and DMA selec-

tion of PCnet-ISA II. The DMA[2:0]

from the EEPROM. {F or Bus Master

Mode Only} The DRQ signals will

not be driven unless Plug and Play

activate register bit is set.

BPAM[3:0] Boot PROM Address Match to bits

[16:13] of SA bus (PnP 0x40–0x41).

Selects the location where the Boot

PROM Address match decode is

started. The BPAM will be written

with a value from the EEPROM.

BP_16B Boot PROM 16-bit access (PnP

0x42). Is asserted if Boot PROM

cycles should respond as an 16-bit

device. In Bus Master mode, all boot

PROM cycles will only be 8 bits in

width.

BPSZ[3:0] Boot PROM Size (PnP 0x43–0x44).

Selects the size of the boot PROM

selected.

SRAM[4:0] Static RAM Address Match to bits

[17:13 ] of SA bus ( PnP 0x48 -0x49).

Selects the starting location of the

Shared Memory when using the

IOAM[3:0] Base Addr ess (Hex)

0000 200

0001 220

0010 240

0011 260

0100 280

0101 2A0

0110 2C0

0111 2E0

1000 300

1001 320

1010 340

1011 360

1100 380

1101 3A0

1110 3C0

1111 3E0

IRQ[3:0] ISA IRQ Pin

0 0 1 1 IRQ3 (Default)

0100IRQ4

0101IRQ5

1001IRQ9

1010IRQ10

1011IRQ11

1101IRQ12

1110IRQ15

DMA[2:0] DMA Channel (DRQ/DACK Pair)

0 1 1 Channel 3

1 0 1 Channel 5

1 1 0 Channel 6

1 1 1 Channel 7

1 0 0 No DMA Channel

BPAM[3:0] Address

Location (Hex) Size Supported

(K bytes)

0 0 0 0 C0000 8, 16, 32, 64

0001 C2000 8

0010 C4000 8, 16

0011 C6000 8

0100 C8000 8, 16, 32

0101 CA000 8

0 1 1 0 CC000 8, 16

0111 CE000 8

1 0 0 0 D0000 8, 16, 32, 64

1001 D2000 8

1010 D4000 8, 16

1011 D6000 8

1100 D8000 8, 16, 32

1101 DA000 8

1 1 1 0 DC000 8, 16

1111 DE000 8

BPSZ[3:0] Boot PROM Size

0 x x x No Boot PROM Selected

11118 K

111016 K

110032 K

100064 K

Am79C961A 61

Shared Memor y architecture mode.

The SRAM[2:0] bits are used for per-

forming address decoding on the

SA[15:13 ] address bits as shown in

the table below. SRAM[4] and

SRAM[3] must reflect the external

address match logic for SA[17] and

SA[16], respectively. The SRAM[4:0]

bits are ignored when in the Bus

Master m ode or in the Pro grammed

I/O Architecture mode.

SR_16B Static RAM 16-bit access (PnP

0x4A). If asserted, the PCnet-ISA II

will respond to SRAM cycles as a

16-bit device. This bit should be set

if external logic is designed to assert

the MEMCS16 signal when

accesses to the shared memory are

decoded. This bit is ignored when in

the Bus Master mo de or in the Pro-

grammed I/O Architecture mode.

SRSZ[3:0] Static RAM size (PnP 0x4B-0x4C).

Selects the size of the static RAM.

The SRSZ[3:0] bits are ignored

when in the Bus Master mode or in

the Programmed I/O Architecture

mode.

Vendor Defined Byte (PnP 0xF0)

LGCY_EN Legacy mode enable. When written

with a one, the PCnet-IS A II will no t

respond to the Plug and Play initia-

tion key sequence (6A) but will

respond to the AMD key sequence

(6B). Therefore, it cannot be recon-

figured by the Plug and Play soft-

ware . W hen set t o z ero (default), the

PCnet-ISA II will respond to the 6A

key sequence if the EEPROM read

was successful, otherwise it will re-

spond to the 6B key sequence.

DXCVRP DXCVR Polarity. The DXCVRP bit

sets the polarity of the DXCVR pin.

When DX CVRP is cle ared (default),

the DXCVR pin is driven HIGH when

the Twisted Pair port is active or

SLEEP mode has been entered and

driven LOW when the AUI port is

active. When DXCVRP is set, the

DXCVR pin is driven LOW when the

Twisted Pair port is active or SLEEP

mode has been entered and driven

HIGH when the AUI port is active.

The DXCVRP should generally be

left cleared when the PCnet-ISA II is

being used with an external DC-DC

converter that has an active low

enable pin. The DXCVRP should

generally be set when the PC-

net-ISA II is being used with an ex-

ter nal DC-DC conver ter that has a n

active high enable pin.

IO_MODE I/O Mode. When set to one, the

internal selection will respond as a

16-bit port, (i.e. drive IOCS16 pin).

When IO_MODE is set to zero,

(Default), the internal I/O selection

will respond as an 8-bit port.

AEN_CS External Decode Logic for I/O Reg-

isters. When written with a one, the

PCnet-ISA II will use the AEN pin as

I/O chip select bar , to allow f or exter-

nal decode logic for the upper ad-

dre ss bi t of SA [ 9: 5 ]. T he pu rpos e of

this pin is to allow I/O locati ons, not

supported with the IOAM[3:0],

selection, to be defined outside the

range 0x200–0x3F7. When set to a

zero , (Def ault), I/O Selection will use

IOAM[3:0].

APROM_EN External Parallel IEEE Address

PROM. When set, the IRQ15 pin is

reconfigu red to be an Addr ess Chip

Select low , similar to APCS pin in the

existing PCnet-ISA (Am79C960)

device. The purpose of this bit is to

allow for both a serial EEPROM and

parallel PROM to coexist. When

APROM_EN is set, the IEEE

address located in the serial EE-

PROM will be ignored and parallel

access will occur over the PRDB

SRAM[2:0] SA[15:13] SRAM Size

(K bytes)

0000008, 16, 32, 64

0010018

0100108, 16

0110118

1001008, 16, 32

1011018

1101108, 16

111 1118

SRSZ[3:0] Shared Memory Size

0 x x x No Static RAM Selected

1111 8 K

1110 16 K

1100 32 K

1000 64 K

62 Am79C961A

bus. When APROM_EN is cleared,

default state, the IEEE address will

be read in from the serial de vice and

written to an internal RAM. When

the I/O space of the IEEE PROM is

selected, PCnet-ISA II, will access

the conte nts o f thi s RAM for I/O r ead

cycles. I/O write cycles will be

ignored.

BP_CS Boot PROM Chip Select. When

BP_CS is set to one, BALE will act

as an external chip select (active

lo w) abo v e bit 15 of the a ddres s bus .

BALE = 0, will select the boot PROM

when MEMR is asserted low if the

BP_CS bit is set and BPAM[2:0]

match SA[15:13] and BPSZ[3:0]

matches the selected size. When

BP_CS i s set to zero. BALE will act

as the normal address latch strobe

to capture the upper address bits f or

memory access to the boot PROM.

BP_CS is by default low. The pri-

mary purpose of this bit is to allow

non-ISA bus appl icati ons to su pport

larger Boot PROMS or non-standard

Boot PROM/Flash locations.

FL_SEL Flash Memory Device Selected.

When set, the Boot PROM is

replaced with an external Flash

memory device. In Bus Master

Mode, BPCS is replaced with

Flash_OE. IRQ12 becomes

Flash_WE. The Flash’s CS pin is

grounded. In sh ar ed me mory mod e,

BPCS is replaced with Flash_CS.

IRQ12 becomes Static_RAM_CS

pin. The SROE and SRWE signals

are connected to both the SRAM

and Flash memory devices. FL_SEL

is cleared by a reset, which is the

default.

Checksum Fa ilure

After RESET, the PCnet-ISA II controller begins

reading the EEPROM and storing the information in

registers inside PCnet-ISA II controller. PCnet-ISA II

controller does a checksum on word locations 0-1Bh

inclusive and if the byte checksum = FFh, then the

data read from the EEPROM is considered good. If

the checksum is not equal to FFh, then the PC-

net-ISA II controller enters what is called software re-

locatable mode.

In software rel ocatable mode, the d ev ice func tions th e

same as in Plug and Play mode, e xcept that it does not

respond to the same initiation key as Plug and Play

suppor ts. Instea d, a different key is used to bring PC-

net-ISA II controller out of the Wait For Key state. This

key is as follows:

6B, 35, 9A, CD, E6, F3, 79, BC

5E, AF, 57, 2B, 15, 8A, C5, E2

F1, F8, 7C, 3E, 9F, 4F, 27, 13

09, 84, 42, A1, D0, 68, 34, 1A

Use Without EEPROM

In some designs, especially PC motherboard applica-

tions, it may be desirable to eliminate the

EEPROM altogether. This would save money, space,

and power consumption.

The ope ra tion of this mode is simi lar to when t he PC-

net-ISA II controller encou nters a checksum error, ex-

cept that to enter this mode the SHFBUSY pin is left

unconnected. The device will enter software relocat-

able mode, and the BIOS on the motherboard can

wak e up the device, configure it, load the IEEE address

(possibly stored in Flash ROM) into the PCnet-ISA II

controller, and activate the device.

External Scan Chain

The Exter nal Scan Chain is a set of bits stored in the

EEPROM whic h ar e not us ed in the PCn et-ISA I I con-

tro ll e r but wh ic h ca n be u se d w it h external h a rd w are to

allow jumperless configuration of external devices.

After RESET, the PCnet-ISA II controller

begins reading the EEPROM and storing the info rma-

tion in registers inside the PCnet-ISA II

controller . SHFBUSY is held high during the read of the

EEPROM. If external circuitry is added, such as a shift

DO fro m t he EEPROM, data r ead ou t o f th e EE PROM

will be shifted into the shift register. After reading the

EEPROM to the end of the Exte r nal Shift Chain, and if

there is a correct checksum, SHFBUSY will go low.

This will be used to latch the information from

the EEPROM into the shift reg ister. If the checksum is

invalid, SHFBUSY will not go low, indicating that the

EEPROM may be bad.

Flash PROM

Use

Instead of using a PROM or EPROM for the Boot

PR OM, it may be de sir ab l e to us e a Flas h o r EEPR OM

type of device for storing the Boot code. This would

allow for in-system updates and changes to the infor-

mation i n the B oot ROM with out ope ning u p the P C. It

may also be desirable to store statistics or drivers in the

Flash device.

Am79C961A 63

Interface

To use a Flash-type device with the PCnet-ISA

II cont roller, Flash S elect is set i n register 0F0h of the

Plug and Play registers. Flash Select is cleared

by RESET (default).

In bus master mode, BPCS becomes Flash_OE and

IRQ12 becomes Flash_WE. The Flash ROM devices

CS pin is connected to ground.

In shared memory mode, BPCS becomes Flash_CS

and IRQ12 becomes the static RAM Chip Select, and

the SROE and SRWE signals are connected to both

the SRAM and Flash devices.

Optional IEEE Address PROM

Nor mally, the Ether ne t physical addr ess will be store d

in the EEPROM with the other configuration data. This

reduces the parts count, board space requirements,

and power consumption. T he option to use a standa rd

parallel 8 bit PROM is provided to manufacturers who

are concerned about the non-volatile nature

of EEPROMs.

To use a 8 bit parallel PROM to store the IEEE address

data instead of storing it in the EEPROM, the

APROM_EN bit is set in the Plug and Play registers by

the EEP ROM up on RE SET. IR Q1 5 is red efi ned by th e

setting of this bit to be APCS, or ADDRESS PROM

CHIP SELE CT. This pi n is connected to an ex ternal 8

bit PROM, such as a 27LS 19 . The address pi ns of th e

PROM are conn ected to the lower addr ess pi ns of the

ISA bus, and the data lines are connected to the private

data bus.

In this mode, any accesses to the IEEE address will be

passed to the external PROM and the data will be

passed through the PCnet-ISA II controller to

the system data bus.

EISA Configuration Registers

The PCnet-ISA II controller has support for the 4-byte

EISA Configuration Registers. These are used in EISA

systems to identify the card and l oad the appropriate

configurati on file for that card. This feature is enabled

using bit 10 of ISACSR2. When set to 1, the EISA

Configuration registers will be enabled and will be

read at I/O location 0xC80–0xC83. The contents of

these 4 registers are stored in the EEPROM and are

automatically read in at RESET.

Bus Interface Unit (BIU)

The bus interface unit is a mixture of a 20 MHz state

machine and as yn ch ro nou s lo gi c. It ha ndl es two types

of accesses; accesses where the PCnet-ISA II control-

ler is a slave and accesses where the PCnet-ISA II con-

troller is the Current Master.

In slave mode, signals like IOCS16 are asserted and

deasserted as soon as the appropriate inputs

are received. IOCHRDY is asynchronously driven

LO W if the PCnet-ISA II controller needs a wait state. It

is releas ed s ynchr on ous ly w hen the PCnet-IS A I I c on-

troller is ready.

When the PCnet-ISA II controller is the Current Master ,

all the signals it generates are synchronous to the

on-chip 20 MHz clock.

DMA Transfers

The BIU will initiate DMA transfers according to the

type of operation being performed. There are three pri-

mary types of DMA transfers:

1. Initialization Block DMA Transfers

During initialization, the PCnet-ISA II transfers 12

words from the initialization block in memory to internal

registers. These 12 words are transferred through dif-

ferent bus mastership period sequences, depending on

whether the TIMER bit (CSR4, bit 13) is set and, if

TIMER is set, on the value in the Bus Activity Timer

If the TIMER bit is reset (default), the 12 words are

always transferred during three separate bus master-

ship per iods. During eac h bus ma stership per iod, four

words (8 bytes) will be read from contiguous memory

addresses.

If the TIMER bit is set, the 12 words ma y be transferred

using anywhere from 1 to 3 bus mastership periods,

depending on the v alue of the Bus Activity Timer regis-

ter (CSR82). During each bus mastership period, a

minimum of four words (8 bytes) will be read from con-

tiguous memory addresses. If the TIMER bit is set and

the value in the Bus Activi ty Timer reg ister all ows it, 8

or all 12 words of the initialization block are read during

a single bus mastership period.

2. Descriptor DMA Transfers

Descriptor DMA transfers are performed to read or

write to transmit or receive descriptors. All transmit and

receive descriptor READ accesses require 3 word

reads (TM D1, TMD0, then TMD2 for transmit descr ip-

tors and RMD1, RMD0, then RMD2 for receive descrip-

tors). Transmit and receive descriptor WRITE

access es to unc hained des cr i pto rs o r th e l as t des cr i p-

tor in a chain (ENP set) require 2 word writes (TMD1

then TMD3 for transmit and RMD1 then RMD3 for re-

ceive). Transmit and receive descriptor WRITE ac-

cesses to chained descriptors that do not hav e ENP set

require 1 word wr i te (TMD1 for transmit and RMD1 for

receive). During descriptor write accesses, only the

bytes which need to be written are written, as con-

trolled by the SA0 and SBHE pins.

If the TIMER bit is reset (default), all accesses during a

single bus mastership period will be either all read or all

write and will be to only one descriptor. Hence, when

the TIMER bit is r eset, the b us master ship period s for

64 Am79C961A

descriptor accesses are always either 3, 2, or 1 cycles

long, depending on which descriptor operation is being

performed.

If the T IME R b it is s et, the 3 , 2, or 1 c y cles requ ir ed i n

a descriptor access may be performed as a part of a

bus mastership period in which any combination of

descriptor reads and writes and buffer reads and writes

are performed. When the TIMER bit is set, the Bus

Activity Timer (CSR82) and the bus access require-

ments of the PCnet-ISA II gover n the operations per-

formed during a single bus mastership period.

3. FIFO DMA Transfers

FIFO DMA transfers occur when the PCnet-ISA II

microcode determines that transfers to and/or from the

FIFOs are required. Once the PCnet-ISA II BIU has

been granted bus mastership, it will perf orm a series of

consecutive transfer cycles before relinquishing the

bus.

When the Bus Activity Timer is disab led b y clearing the

TIMER (CSR4, bit 13) bit, all FIFO DMA transfers

within a bus mastership period will be either read or

write cycles, and all transfers will be to adjacent,

ascending addresses. When the Bus Activity Timer is

enabled by setting the TIMER bit, DMA transf ers within

a bus mastershi p per iod may consis t of any mixtur e of

read and write cycles, without restriction on the

address ordering. This mode of operation allows the

PCnet-ISA II to accomplish more during each bus

ownership period.

The number o f data transfer cycles contained wi thin a

single bus mastership period is in general dependent

on the programming of the DMAPLUS (CSR4, bit 14)

and the TIMER (CSR4, bit 13) options. Several other

fa ct or s will als o affect the lengt h of the bus masters hip

period. The possibilities are as follows:

If DMAPLUS = 0 and TIMER = 0, a maximum of 16

transfers to or from the FIFO will be performed by

default. This default value may be changed by writing

to the DMA Burst Register (CSR80, bits 7:0). Since

TIMER = 0, all FIFO DMA transfers within a bus mas-

tership period will be either read or write cycles, and all

transfers will be to adjacent, ascending addresses.

Not e that DM APLUS = 0 merely s ets a ma ximum v alue

f or the number of FIFO transfers that ma y occur during

one bus mastership period. The minimum number of

transfers in the bus mastership period will be deter-

mined by the setti ngs o f t he FI FO water m arks and th e

conditions of the FIFOs, and the value of the Bus Activ-

ity Timer (CSR82) if the TIMER bit is set.

If DMAPLUS = 1 and TIMER = 0, the bus mastership

period will continue until the transmit FIFO is filled to its

high threshold (read transfers) or the receive FIFO is

emptied to its low threshold (write transfers). Other

v ariables may also affect the end point of the bus mas-

tership period in this mode, including the particular con-

ditions existing within the FIFOs, and receive and

transmit status conditions. Since TIMER = 0, all FIFO

DMA transfers within a bus mastership period will be

either read or write cycles, and all transfers will be to

adjacent, ascending addresses.

If TIMER = 1, the bus mastership period will continue

until all “pending bus operations” are comple ted or unt il

the Bus Activity Timer value (CSR82) has expired.

These bus operations may consist of any mixture of

descriptor and buffer read and write accesses. If DMA-

PLUS = 1, “pending bus operations” includes any de-

scri ptor acces ses and buffe r access es that nee d to be

performed. If DMAPLUS = 0, “pending bus operations”

include any descriptor accesses that need to be per-

formed and any buffer accesses that need to be per-

formed up to the limit specified by the DMA Burst

Note that when TIMER=1, following a last bus transac-

tion during a bus mastership period, the PCnet-ISA II

may k eep ownership of the bus for up to approximately

1µs. The PCnet-ISA II determines whether there are

further pending bus operations by waiting approxi-

mately 1µs after the completion of ev ery bus operation

(e.g. a descriptor or FIFO access). If, during the 1 µs

peri od , no f urther bus operations ar e re ques te d by the

internal Buffer Management Unit, the PCnet-ISA II

determines that there are no further pending opera-

tions and gives up bus ownership. This 1 µs of unused

bus ownership time is more than made up for by the

efficien cy ga in ed by being able to perform any mi xt ure

of descriptor and buffer read and write accesses during

a single bus ownership period.

The FIFO thresholds are programmable (see descrip-

tion of CSR80), as are the DMA Burst Register and Bus

Activity Timer values. The exact number of transfer

cycles in the c ase o f DMAPLUS = 1 will b e d epe ndent

on the latency of the system bus to the PCnet-ISA II

controller’s DMA reque st and the speed of bus opera-

tion, but will be limite d by the value in the Bus Act ivity

Timer register (if the TIMER bit is set), the FIFO condi-

tion, and receive and transmit status. Barring a

time-ou t by either of thes e registers, or excepti onal re-

ceive and transmit events, or an end of packet signal

from the FIFO, the FIFO watermark settings and the

ex tent of Bus Grant latency will be the major factors de-

termining the number of accesses performed during

any given arbitration cycle when DMAPLUS = 1.

The IOCHRDY response of the memory device will

also affect the number of transfers when

DMAPLUS = 1, since the speed of the accesses will af-

fect the state of the FIFO. During accesses, the FIFO

may be filling or emptying on the network end. A slower

memory response will allow additional data to accumu-

late insi de of the FIFO (dur ing wr ite transfers from the

receive FIFO). If the accesses are slow enough, a com-

Am79C961A 65

plete word ma y become a vailab le before the end of the

arbitration cycle and thereby increase the number of

transfers in that cycle. The general rule is that the

longer the Bus Grant latency or the slower the bus

transfer operations (or clock speed) or the higher the

transmit watermark or the lower the receive watermark

or any combination thereof, the longer will be the aver-

age bus mastership period.

Buffer Management Un it (BMU)

The buffer management unit is a microcode d 20 MHz

state machine which implements the initialization block

and the descriptor architecture.

Initialization

PCnet-ISA II controller initialization includes the read-

ing of the initialization block in memory to obtain the

operating parameters. The initialization block is read

when the INIT bit in CSR0 is set. The INIT bit should be

set before or concurrent with the STRT bit to insure cor-

rect operation. See previous section “1. Initialization

Block DMA Transfer.” Once the initialization block has

been read in and processed, the BMU knows where the

receive and transmit descr iptor rings are. On comple-

tion of the read operation and after internal registers

have bee n u pda ted, IDON will be set i n C SR0 , an d a n

interrupt generated if IENA is set.

The Initialization Block is vectored by the contents of

CSR1 (least significant 16 bits of address) and CSR2

(most significant 8 bits of address). The block contains

the user defined conditions for PCnet-ISA II controller

operation, together with the address and length infor-

mation to allow linkage of the transmit and receive

descriptor ring s.

There is an alternative method to initialize the PC-

net-ISA II controller. Instead of initi alization v ia the ini-

tialization block in memory, data can be written directly

into the appropriate registers. Either method may be

used at the discretion of the programmer. If the regis-

ters are written to dire ctly, the INIT bit must not be se t,

or the initialization block will be read in, thus overwriting

the previously written information. Please refer to

Appendix D for details on this alternative method.

Reinitialization

The transm itter and receiver secti on of the PCnet-ISA

II controller can be turned on via the initialization bloc k

(MODE Register DTX, DRX bits; CSR15[1:0]). The

state of the transmitter and receiver are monitored

through CSR0 (RXON, TXON bits). The PCnet-ISA II

control ler should be reinitial ize d if the transm itter and/

or the receiver were not tur ned on during the or iginal

initialization and it was subsequently required to acti-

v ate them, or if either section shut off due to the detec-

tion of an error condition (MERR, UFLO, TX BUFF

error).

Reinitia lization may be done via the initial ization block

or by setting the STOP bit in CSR0, followed by writing

to CSR15, and then setting the START bit in CSR0.

Note that thi s form of restart will not perfor m t he s am e

in the PC net-ISA II contr oller as in the LA NCE. In par-

ticular, the PCn et-ISA II c ontroll er relo ads the transmit

and receive descriptor pointers (working registers) with

their respective base addresses. This means that the

software must clear the descriptor’s own bits and reset

its descriptor ring pointers before the restart of the PC-

net-ISA controller. The reload of descriptor base

addresses is performed in the LANCE only after initial-

ization , so a restart of the LA NCE witho ut ini tiali zatio n

leaves the LANCE pointing at the same descriptor

locations as before the restart.

Suspend

The PCnet-ISA II controller offers a suspend mode that

allows easy updating of the CSR registers without

going through a full reinitialization of the device. The

suspend mode also allows stopping the device with

orderly termination of all network activity.

The ho st requests the PCnet -I SA II contr oller to en ter

the suspend mode by setting SPND (CSR5, bit 0) to

ONE. The host must poll SPND until it reads back ONE

to determine that the PCnet-ISA II controller has en-

tered the suspend mode. When the host sets SPND to

ONE, the PCnet-ISA II controller first finishes all on-go-

ing transmit activity and updates the corresponding

transmit des c r iptor entr ie s. It then fini sh es all on- g oin g

receive activity and updates the corresponding receive

descriptor entries. It then sets the read-version of

SPND to ONE and enters the suspend mode. In sus-

pend mode, all of the CSR registers are accessible. As

long as th e PCn et- IS A II c on tro ll er is not rese t whil e i n

suspend mode (by asser ting the RESET pin, reading

the RESET register, or by setting the STOP bit), no

reinitialization of the device is required after the device

comes out of suspend mode. When SPND is set to

ZERO, the PCnet-ISA II controller will leave the sus-

pend mode and will continue at the transmit and re-

ceive descr ipto r r in g locati ons wher e it ha d left whe n it

entered the suspend mode.

Buffer Management

Buffer management is accomplished through message

descriptor entries organized as ring structures in mem-

or y. The re are two r ings, a recei ve ring an d a transmit

ring. The size of a message descriptor entry is 4 words

(8 bytes).

Descriptor Rings

Each descriptor ring must be organized in a contiguous

area of memory. At initialization time (setting the INIT

bit in CSR0), the PCnet-ISA II controller reads the

user-defined base address for the transmit and receive

descriptor rings, which must be on an 8-b yte boundary,

as well as the number of entries contained in the

66 Am79C961A

descriptor rings. By default, a maximum of 128 ring

entries is permitted when utilizing the initialization

bloc k, which uses values of TLEN and RLEN to specify

the transmit and receive descriptor ring lengths. How-

ever, the ring lengths can be manually defined (up to

65535) by wr iting the transmit and receive ring length

registers (CSR76,78) directly.

Each ring entry contains the following information:

■The address of the actual message data buffer in

user or host memory

■The length of the message buffer

■Status information indicating the condition of the

buffer

Receive descriptor entries are similar (but not identical)

to transmit descriptor entries. Both are composed of

four registers, each 16 bits wide for a total of 8 bytes.

To permit the queuing and de-queuing of message

buffers, ownership of each buffer is allocated to either

the PCnet-ISA II controller or the host. The OWN bit

within the descr iptor st atus infor mation, ei ther TMD or

RMD (see section on TMD or RMD), is used for this

purpose. “Deadly Embrace” condit ions are avoided by

the ownership mechanism. Only the owner is permitted

to relinquish ownership or to write to any field in the

descr iptor entry. A device that is n ot the cu rre nt ow ner

of a descriptor entry cannot assume ownership or

change any field in the entry.

Descriptor Rin g Access Mechan ism

At initialization, the PCnet-ISA II controller reads the

base address of both the transmit and receive descrip-

tor rings into CSRs for use b y the PCnet-ISA II control-

ler during subsequent operation.

When transmit and receive functions begin, the base

address of each ring is loaded into the current descrip-

tor address registers and the address of the next

descriptor entry in the transmit and receive rings is

computed and loa ded into the next descr iptor add ress

registers.

Am79C961A 67

Polling

When there is no channel ac tivity and there is no pre-

or post-receive or transmit activity being performed by

the PCnet-ISA II controller then the PCnet-ISA II con-

troller will periodically poll the current receive and

transmit descriptor entries in order to ascertain their

ownership. If the DPOLL bit in CSR4 is set, then the

transmit polling function is disabled.

A typical polling operation consists of the f ollowing: The

PCnet-ISA II controller will use the current receive

descriptor address stored internally to vector to the

appropr iate Receive Descr iptor Ta ble Entr y (RDT E). It

will then use the current transmit descriptor address

(stored internally) to vector to the appropriate Transmit

Descriptor Table Entry (TDTE). These accesses will be

made to RMD1 and RMD0 of the current RDTE and

TMD1 and TM D0 of the c urrent TDTE at per iodic poll-

Initialization

Block

24-Bit Base Address

Pointer to

Initialization Block

IADR[15:0]

IADR[23:16]

RES

CSR1

CSR2

TDRA[15:0]

MODE

PADR[15:0]

PADR[31:16]

PADRF[47:32]

LADRF[15:0]

LADRF[31:16]

LADRF[47:32]

LADRF[63:48]

RDRA[15:0]

RLEN RES RDRA[23:16]

TLEN RES TDRA[23:16]

RCV

Buffers

•

RX DESCRIPTOR RINGS

RMD0 RMD1 RMD2 RMD3

RCV Descriptor

Ring

NNNN•••

1st desc.

start 2nd desc.

start

RMD0

XMT

Buffers

•

RX DESCRIPTOR RINGS

TMD0 TMD1 TMD2 TMD3

RX DESCRIPTOR RINGS

XMT Descriptor

Ring

MMMM•••

1st desc.

start 2nd desc.

start

TMD0

Data

Buffer 1 Data

Buffer 2 Data

Buffer

Data

Buffer 1 Data

Buffer 2 Data

Buffer

19364B-15

Initialization Block and Descriptor Rings

68 Am79C961A

ing intervals. All information collected during polling

activity will be stored internally in the appropriate

CSRs. (i.e. CSR18–19, CSR40, CSR20–21, CSR42,

CSR50, CSR52). Unowned descriptor status will be

internally ignored.

A typical receive poll occurs under the following

conditions:

1. PCnet-ISA II controller does not possess ownership

of the current RDTE and

the poll time has elapsed and

RXON = 1,

2. PCnet-ISA II controller does not possess ownership

of the next RDTE and

the poll time has elapsed and

RXON = 1,

If RXON = 0, the PCn et-ISA II co ntroller will never poll

RDTE locations.

If RXON = 1, the system should always have at least

one RDTE available for the possibility of a receive

ev ent. When there is only one RDTE, there is no polling

for next RDTE.

A typical transmit poll occurs under the following

conditions:

1. PCnet-ISA II controller does not possess ownership

of the current TDTE and

DPOLL = 0 and

TXON = 1 and

the poll time has elapsed,

2. PCnet-ISA II controller does not possess ownership

of the current TDTE and

DPOLL = 0 and

TXON = 1 and

a packet has just been received,

3. PCnet-ISA II controller does not possess ownership

of the current TDTE and

DPOLL = 0 and

TXON = 1 and

a packet has just been transmitted.

The poll time interval is nominally defined as 32,768

crystal clock periods, or 1.6 ms. Ho wever, the poll time

other microcode controlled operation will interrupt the

incrementing of the poll count register. For example,

when a receive packet is accepted by the PCnet-ISA II

controller, the device suspends execution of the

poll-time-incrementing microcode so that a receive

microcode routine may instead be executed.

Poll-time-incrementing code is resumed when the

receive operation has completely finished. Note, how-

ever, that following the completion of any receive or

transmit ope ration, a poll operatio n will always be per-

formed. The poll time count register is never reset.

Note that if a non-default is desired, then a strict se-

quence of setting the INIT bit i n CSR0, waiting for the

IDON bit in CSR0, then writing to CSR47, and then set-

ting STRT in CSR0 must be observed, otherwise the

default value will not be overwritten. See the CSR47

section for details.

Setting the TDMD bit of CSR0 will cause the microcode

controller to exit the poll counting code and immedi-

ately perform a polling operation. If RDTE ownership

has not been previously established, then an RDTE

poll will be performed ahead of the TDTE poll.

Transmit Descriptor Table Entry (TDTE)

If, after a TDTE access, the PCnet-ISA II controller

finds that the O WN bit of that TDTE is not set, then the

PCnet-ISA II controller resumes the poll time count and

re-examines the same TDTE at the next expiration of

the poll time count.

If the OWN bit of the TDTE is set, b ut STP = 0, the PC-

net-ISA II controller will immediately request the bus in

order to r eset the OWN bit of this descripto r ; this con-

dition would normally be found following a LCOL or

RETRY err or that occurr ed in the middle of a transmit

packe t chain of buffers. After r esetting the OWN bit of

this descriptor, the PCnet-ISA II controller will again

immediately request the bus in order to access the next

TDTE location in the ring.

If the OWN bit is set and the buffer length is 0, the OWN

bit will be res et. In th e LANCE th e buffer length of 0 is

interpreted as a 4096-byte buffer. It is acceptable to

have a 0 length buffer on transmit with STP=1 or

STP=1 and ENP = 1. It is not acceptable to have 0

length buffer with STP = 0 and ENP = 1.

If the OWN bit is set and the start of pack et (STP) bit is

set, then m icrocode con trol pro ceeds to a routin e that

will enable transmit data transfers to the FIFO.

If the transmit buffers are data chained (ENP = 0 in the

first buffer), then the PCnet-ISA II controller will look

ahead to the next transmit descriptor after it has per-

formed at least one transmit data transfer from the first

buff er. More than one transmit data transfer ma y possi-

bly take place, depe nding upon the state o f the trans-

mitter . The transmit descriptor look ahead reads TMD0

first and TMD1 second. The contents of TMD0 and

TMD1 will be stored in Next TX Descriptor Address

(CSR32), Next TX Byte Count (CSR66) and Next TX

Status (CSR67) regardless of the state of the OWN bit.

This transmit descriptor lookahead operation is

performed only once.

If the PCnet-ISA II controller does not own the next

TDTE (i.e. the second TDTE for this pack et), then it will

complete transmission of the current buffer and then

Am79C961A 69

update the status of the current (first) TDTE with the

BUFF and UFLO bits being set. If DXSUFLO is 0 (bit 6

CSR3), then this will cause the transmitter to be dis-

abled (CSR0, TXON = 0). The PCnet-ISA II controller

will have to be restarted to restore the transmit function.

The situation that matches this description implies that

the system has not been able to stay ahead of the PC-

net-ISA II contro ller in the transmit descri ptor r ing an d

therefore, the condition is treated as a fatal error. To

avoid this situation, the system should always set the

transmit chain descriptor own bits in reverse order.

If the PCnet-ISA II controller does own the second

TDTE in a chain, it will gradually empty the contents of

the first b uffer (as the bytes are needed by the transmit

operation), perform a single-cycle DMA transfer to

update the status (reset the OWN bit in TMD1) of the

first descriptor, and then it may perform one data DMA

access on the second buffer in the chain before e xecut-

ing another lookahead operation. (i.e. a lookahead to

the third descriptor).

The PCnet-I SA II con tro ller can queu e up to two pack-

ets in the transmit FIFO. Call them packet “X” and

packet “Y”, where “Y” is after “X”. Assume that packet

“X” is currently being transmitted. Because the PC-

net-ISA II controller can perform lookahead data trans-

fer over an ENP, it is possible for the PCnet-ISA II

controller to update a TDTE in a buffer belonging to

packe t “Y” while packet “X” is being transmitted if

packet “Y” uses data chaining. This operation will result

in non-sequential TDTE accesses as packet “X” com-

pletes transmission and the PCnet-ISA II controller

writ es ou t i ts s tat us, sin ce pa cket “X”’s TDTE is before

the TDTE accessed as part of the lookahead data

transfer from packet “Y”.

This should not cause any problem for properly written

software which processes buffers in sequence, waiting

for ownership before proceeding.

If an error occurs in the transmission before all of the

bytes of the cu rren t buffer have been tra nsferred, then

TMD2 and TMD1 of the current buff er will be written; in

that case, data transfers from the next buffer will not

commence. Instead, following the TMD2/TMD1 up-

date, the PCnet-ISA II controller will go to the next

transmit packet, if any, skipping over the rest of the

packet which experienced an error, including chained

buffers.

This is done by returning to the polling microcode

where it will immediately access the next descriptor

and find the condition OWN = 1 and STP = 0 as

described earlier. In that case, the PCnet-ISA II control-

ler will reset the own bit f or this descriptor and continue

in like manner until a descriptor with OW N = 0 (no more

transmit packets in the ring) or OWN = 1 and STP = 1

(the first buffer of a new packet) is reached.

At the end of any transmit operation, whether success-

ful or with errors, and the com pletion of the desc riptor

updates, the PCnet-ISA II controller will al ways perf orm

another poll operation. As described earlier, this poll

operation will begi n with a check of the current RDTE,

unless the PCnet-ISA II controller already owns that

descriptor. Then the PCnet-ISA II controller will

proceed to polling the next TDTE. If the transmit

descriptor OWN bit has a zero value, then the PC-

net-ISA II controller will resume poll time count

increm entation. If th e transmit de scri ptor OWN bit has

a value of ONE, then the PCnet-ISA II controller will

begin filling the FIFO with transmit data and initiate a

transmission. This end-of-operation poll avoids inser t-

ing poll time counts between successive transmit

packets.

Whenever the PCnet-ISA II controller completes a

transmit pack et (either with or without error) and writes

the status inf ormation to the current descriptor, then the

TINT bit of CSR0 is set to in dicat e the comp letion of a

transmission. This causes an interrupt signal if the

IENA bit of CSR0 has been set and the TINTM bit of

CSR3 is reset.

Receive Descriptor Table Entry (RDT E)

If the PCnet-ISA II controller does not own both the cur-

rent and the next Receive Descripto r Table Entry, then

the PC net-IS A II c ontr olle r wil l continue to p ol l acc ord -

ing to the polling sequence described above. If the

receive descriptor ring length is 1, there is no next

descriptor, and no look ahead poll will take place.

If a poll operation has rev ealed that the current and the

next RDTE belongs to the PCnet-ISA II controller, then

additional poll accesses are not necessary. Future poll

operations wil l not inc lude RDTE acce sses as lon g as

the P Cnet-IS A II controller retains owne rship to the cur-

rent and the next RDTE.

When receive activity is present on the channel, the

PCnet-I SA II co ntroller waits for the complete address

of the message to arrive. It then decides whether to

accept or reject the packet based on all active address-

ing schemes. If the packet is accepted the PCnet-ISA II

control ler checks the current rec eive buffer status reg-

ister CRST (CSR40) to determine the ownership of the

current buffer.

If ownership is lacking, then the PCnet-ISA II controller

will immediately perf orm a (last ditch) poll of the current

RDTE. If ownershi p is stil l denie d, then the PCnet- ISA

II controller has no buff er in which to store the incoming

message. The MISS bit will be set in CSR0 and an

interrupt will be generated if IENA = 1 (CSR0) and

MISSM = 0 (CSR3 ). Another poll of the curren t RDTE

will not occur until the packet has finished.

If the PCnet-ISA II controller sees that the last poll

(either a normal poll or the last-ditch eff ort described in

70 Am79C961A

the above paragraph) of the current RDTE shows v alid

ownership, then it proceeds to a poll of the next RDTE.

Following this poll, and regardless of the outcome of

this poll, transfers of receive data from the FIFO may

begin.

Regardless of ownership of the second receive

descriptor, the PCnet-ISA II controller will continue to

perform receive data DMA transfers to the first buffer,

using burst-cycle DMA transfers. If the packet length

exceeds the length of the first buffer, and the PC-

net-ISA II controller does not own the second buffer,

ownership of the current descriptor will be passed back

to the system by writing a zero to the O WN bit of RMD1

and status will be wr itten indicating buffer (BUFF = 1)

and possibly overflow (OFLO = 1) errors.

If the packet length exceeds the length of the first (cur-

rent) buffer, and the PCnet-ISA II controller does own

the second (next) buffer, ownership will be passed

back to the system by writing a zero to the OWN bit of

RMD1 when the fi rst buffer is ful l. Receive data trans-

fers to the second buffer may occur before the PC-

net-ISA II controller proceeds to look ahead to the

ownership of the third buffer. Such action will depend

upon the state of the FIFO when the status has been

updated on the first descriptor. In any case, lookahead

will be performed to the third buff er and the inf ormation

gathered will be stored in the chip, regardless of the

state of the owner ship bit. As in the trans mit flow, loo-

kahead operations are performed only once.

This activity continues until the PCnet-ISA II controller

reco gniz es th e comple tion of the packet (t he last b yt e of

this receive message has been removed from the

FIFO). The PCnet-ISA II controller will subsequently up-

date the current RDTE status with the end of packet

(ENP) indication set, write the message byte count

(MCNT) of the complete packet into RMD2 and over-

write the “current” entri es in the CSRs with the “next” en-

tries.

Media Access Control

The Media Access Control engine incorporates the

essential protocol requirements for operation of a com-

pliant E ther net/802.3 node, and pr ovides the in terface

between the FIFO sub-system and the Manchester

Encoder/Decoder (MENDEC).

This section describes operation of the MAC engine

when operating in Half Duplex mode. When in Half

Duplex mode, the MAC engine is fully compliant to Sec-

tion 4 of ISO/IEC 8802-3 (ANSI/IEEE Standard 1990

Second Edition) and ANSI/IEEE 802.3 (1985). When

operating in Full Duple x mode, the MA C engine behavior

changes as described in the Full Duplex Operation sec-

tion.

The MAC engine provides programmable enhanced

features designed to minimize host supervision and pre

or post-message processing. These features include

the ability to disable retries after a collision, dynamic

FCS generation on a packet-by-packet basis, and au-

tomatic pad field insertion and deletion to enforce

minimum frame size attributes.

The two primary attributes of the MAC engine are:

■Transmit and receive message data encapsulation

—Framing (frame boundary delimitation, frame

synchronization)

—Addres si ng (sou rce and des tin ati on addres s

handling)

—Error detection (physical medium transmission

errors)

■Media access management

—Medium allocation (collision avoida nce)

—Contention resolution (collision handling)

Transmit and Receive Message Data

Encapsulation

The MAC engine provides minimum frame size

enforcement for transmit and receive packets. When

APAD_XMT = 1 (bit 11 in CSR4), transmit messages

will be pad ded wit h s uffi cien t bytes ( co ntaini ng 00h) t o

ensure that the receiv ing station will obser ve an infor-

mation field (destination address, source address,

length/type, data and FCS) of 64-bytes. When

ASTRP_RCV = 1 (bit 10 in CSR4), the receiver will

automatically strip pad bytes from the received mes-

sage by observing the value in the length field, and

stripping excess bytes if this value is below the mini-

mum data size (46 bytes). Both features can be inde-

pendently over-ridden to allow illegally short (less than

64 bytes of packet data) messages to be transmitted

and/or received. The use of these features reduce bus

bandwidth usage because the pad bytes are not trans-

ferred to or from host memory.

Framing (frame boundary delimitation, frame

synchronization)

The MAC engine will autonomously handle the con-

structi on of th e tran smit fr ame . Once th e Transmi t FIFO

has been fi lled to the predet ermi ned threshold (se t by

XMTSP in CSR80 ), and p rovidin g acce ss to the chan-

nel is currently permitted, the MAC engine will com-

mence the 7-byte preamble sequence (10101010b,

where firs t b it transmi tted is a 1). Th e M AC engine wi ll

subsequ ently appen d the Start Frame Delim iter (SFD)

byte (10101 011b) followed by the ser ialized data fro m

the Transmit FIFO. Once the data has been completed,

the MAC engin e w ill appe nd the FCS ( mos t signi fi can t

bit first) which was computed on the entire data portion

of the message.

Note tha t the user is responsible for the corr ect order-

ing and content in each of the fields in the frame,

Am79C961A 71

including the destination address, source address,

length/type and packet data.

The receive section of the MAC engine will detect an

inco min g pr ea mble seq uen ce and lock to the en code d

clock. The inter nal MENDE C will decode the se rial bit

stream an d present this to the MAC e ngine. The MAC

will discard the first 8 bits of information before search-

ing for the SFD seque nce. Once the SFD i s detected,

all subsequent bits are treated as part of the frame. The

MAC engine will inspect the length field to ensure min-

imum frame size, strip unnece ssar y pad characters (if

enabled), and pass the remaining bytes through the

Receive FIFO to the host. If pad stripping is performed,

the MAC engine will also strip the received FCS bytes,

although the normal FCS computation and checking

will occur. Note that apart from pad stripping, the frame

will be passed unmodified to the host. If the length field

has a value of 46 or greater, the MAC engine will not

attempt to validate the length against the number of

bytes contained in the mes sage.

If the frame terminates or suffers a collision before

64 bytes of information (after SFD) have been

received, the MAC engine wi ll aut oma tic al ly de let e th e

frame from the Receive FIFO, without host

intervention.

Addressing (source and destination addre ss

handling)

The firs t 6 bytes of info rm ation after SFD will be inter-

preted as the destination address field. The MAC

engine provides facilities for physical, logical, and

broadcast address reception. In addition, multiple

physical addresses can be constructed (perfect

address filtering) using external logic in conjunction

with the EADI interface.

Error detection (physical medium transmission

errors)

The MAC engine provides several facilities which

report and recover from errors on the medium. In addi-

tion, the ne twork is p rotected from gross error s due to

inabili ty of t he hos t to keep pac e with the MAC engin e

activity.

On completion of transmission, the following transmit

status is available in the appropriate TMD and CSR

areas:

■The exact number of transmission retry attempts

(ONE, MORE, or RTRY).

■Whether the MAC engine had to Defer (DEF) due to

chann el activ it y.

■Loss of Carrier, indicating that there was an inter-

ruption in the ability of the MAC engine to monitor its

own transmission. Repeated LCAR errors indicate

a potentially faulty transceiver or network

connection.

■Late Collision (LCOL) indicates that the transmis-

sion suffered a collision after the slot time. This is

indicat ive of a badly conf igured net work. Lat e colli-

sions should not occur in a normal operating net-

work.

■Collision Error (CERR) indicates that the trans-

ceiver did not respond with an SQE Test message

within the predeter mined time after a transmission

complete d. T hi s may be due to a failed transceiver,

disconnected or faulty transceiver drop cable, or the

fact the transceiver does not support this feature (or

the feature is disabled).

In additi on to the r ep orting of networ k e rror s, the M AC

engin e will also atte mpt to prevent the creatio n of any

network error due to th e inabi lity of the host to servic e

the MAC engine. During transmission, if the host fails

to keep the Transmit FIFO filled sufficiently, causing an

underflow , the MAC engine will guarantee the message

is either sent as a runt pack et (which will be deleted b y

the rec ei ving station) o r has a n invalid FCS ( whi c h wi ll

also cause the receiver to reject the message).

The statu s of eac h r ece ive message is available in the

appropriate RMD and CSR areas. FCS and Framing

errors (FRAM) are reported, although the received

frame is still passed to the host. The FRAM error will

only be reported if an FC S error is det ected and th ere

are a non-integral numbe r of bits in the messag e. T he

MAC engine will ignore up to seven additional bits at

the end of a message ( dribbling bits), whi ch c an o ccur

under normal network operating conditions. The recep-

tion of eigh t additional bi ts will ca use the MAC engine

to de-serialize the entire byte, and will result in the

received message and FCS being modified.

The PCnet-ISA II controller can handle up to 7 dribbling

bits when a received packet terminates. During the

reception, the CRC is generated on every serial bit

(including the dribbling bits) coming from the cable,

although the internally saved CRC value is only

updated on the eighth bit (on each byte boundary). The

framing error is reported to the user as follows:

1. If the number of the dribbling bits are 1 to 7 and

there is no CRC error, then there is no Framing error

(FRAM = 0).

2. If the number of the dribbling bits are less than 8

and there is a CRC error, then there is also a

Framin g error (FRAM = 1).

3. If the num ber of dribbling bits = 0, then there is no

Framing error. There may or may not be a CRC

(FCS) erro r.

Counters are provided to report the Receive Collision

Count and Ru nt Packet Coun t used for network stati s-

tics and utilization calculations.

Note that if the MAC engine detec ts a recei ved packet

which has a 00b pat tern in the prea mble (after the firs t

72 Am79C961A

8 bits, which are ignored), the entire packet will be

ignored. The MAC engine will wait f or the network to go

inactive before attempting to receive the next packet.

Media Access Management

The basic requirement for all stations on the network is

to provide fairness of channel allocation. The 802.3/

Ethernet protocol defines a media access mechanism

which permits all stations to access the channel with

equality. Any node can attempt t o contend f or t he chan-

nel by waiting for a predetermined time (Inter Packet

Gap inter val) after the last activity, before transmitting

on the medium. The channel is a multidrop

communications medium (with various topological con-

figurations permitted) which allows a single station to

transmit and all other stations to receive. If two nodes

simultaneously contend for the channel, their signals

will interact, causing loss of data (defined as a collision).

It is the responsibility of the MAC to attempt to avoid

and recov er from a collision, to guarantee data integrity

f or the end-to-end transmission to the receiving station.

Medium Allocation (collision avoidance)

The IEEE 802.3 Standard (ISO/IEC 8802-3 1990)

requires th at the CSMA/CD MAC mo nitor the medium

traffic by looking for carrier activity. When carrier is

detected the medium is considered b usy, and the MA C

should defer to the existing message.

The IEEE 802.3 Standard also allows optional two part

deferral after a receive message.

See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.1:

“Note: It is possib le for the P LS carri er sens e

indication to fail to be asserted during a colli-

sion on the media. If the deference process

simply times the interpacket gap based on this

indication it is possible for a short interFrame

gap to be ge nerated, le ading to a potenti al re-

ception failure of a subsequent frame. To en-

hance system robustness the following option-

al measures, as specified in 4.2.8, are recom-

mended when InterFrameSpacingPart1 is

other than zero:

(1) Upon completing a transmission, start timing

the interpacket gap, as soon as transmitting

and carrier Sense are both false.

(2) When timing an interpacket gap following re-

ception, reset the interpacket gap timing if car-

rier Sens e becom es tr ue d ur ing th e fi rst 2 / 3 o f

the inte rpacket gap timi ng inte rval. Duri ng the

final 1/3 of the interval the timer shall not be re-

set to ensure fair access to the medium. An ini-

tial period shorter than 2/3 of the interval is

permissible including zero.”

The MAC engine impleme nts th e optional receive two

part deferral algorithm, with a first part in-

ter-frame-spacing time of 6.0 µs. The second part of

the inter-frame-spacing interval is therefore 3.6 µs.

The PCnet-ISA II controller will perform the two-par t

deferral algorithm as specified in Section 4.2.8 (Pro-

cess Def erence). The Inter Pac k et Gap (IPG) timer will

start timing the 9.6 µs InterFrameSpacing after the

receive carrier is de-asserted. During the first part

deferral (InterFrameSpacingPart1 – IFS1) the PC-

net-ISA II controller will defer any pending transmit

frame and respond to the receive message. The IPG

counter will be r eset to zero co ntinuous ly unti l the car-

rier de-asserts, at which point the IPG counter will

resume the 9.6 µs count once again. Once the IFS1

period of 6.0 µs has elapsed, the PCnet-ISA II control-

ler will begin timing the second part deferral

(InterFrameSpacingPart2 – IFS2) of 3.6 µs. Once IFS1

has completed, and IFS2 has commenced, the PC-

net-ISA II c on tro ll er wil l not d efer to a r e cei ve packet if

a transmit packet is pending. This means that the PC-

net-ISA II controller will not attempt to receive the re-

ceive pack et, since it will start to transmit, and generate

a collision at 9.6 µs. The PCnet-ISA II controller will

guarantee to complete the preamble (64-bit) and jam

(32-bit) sequence before ceasing transmission and

invoking the random backoff algorithm.

In addition, transmit two part deferral is implemented

as an option which can be disabled using the

DXMT2PD bit (CSR3). Two-part deferral after trans-

mission is useful for ensuring that severe IPG shrink-

age canno t occ ur in speci fic cir cumsta nces, cau sing a

transmit message to follow a receive message so

closely as to make them indistinguishable.

During the time period immediately after a transmission

has been completed, the external transceiver (in the

case of a standard A UI connected de vice), should gen-

erate the SQ E Test me ss ag e (a nom ina l 10 MHz burst

of 5-15 bit times duration) on the CI± pair (within 0.6 µs

– 1.6 µs after the transmission ceases). During the time

period in which the SQE Test message is expected the

PCnet-IS A II control ler will not respon d to receive car-

rier sense.

See ANSI/IEEE Std 802.3-1990 Edition, 7.2.4.6 (1):

“At the conclusion of the output function, the

DTE opens a time window during which it ex-

pects to see the signal_quality_error signal as-

serted on the Control In circuit. The time win-

dow begins when the CARRIER_STATUS be-

comes CARRIER_OFF. If execution of the out-

put functi on does not c ause CARRIER_O N to

occur, no SQE test occurs in the DTE. The du-

ration of the window shall be at least 4.0 µs but

no more than 8. 0 µs. During the time window

the Carrier Sense Function is inhibited.”

The PCnet-ISA II controller implements a carrier sense

“blinding” period w ithi n 0 – 4.0 µs from de- a ss ert ion of

carrier sense after transmission. This eff ectiv ely means

that when transmit two part deferral is enabled

(DXMT2PD is cleared) the IFS1 time is from 4 µs to 6

Am79C961A 73

µs after a transm is si on . However, sinc e IPG shrinkage

below 4 µs will rarely be encountered on a correctly

configured network, and since the fragment size will be

larger than the 4 µs blinding window, then the IPG

counter will be reset by a worst case IPG shrinkage/

fragment scenario and the PCnet-ISA II controller will

defer its transmission. In addition, the PCnet-ISA II

control ler will not res tar t the “blinding” period if carrier

is detected with in the 4 .0 µs – 6.0 µs IFS1 per iod, but

will commence timing of the entire IFS1 period.

Contention resolution (collision handling)

Collision detection is performed and reported to the

MAC engine by the integrated Manchester Encoder/

Decoder (MENDEC).

If a collision is detected before the complete preamble/

SFD sequence has been transmitted, the MA C Engine

will comple te the pream bl e/SFD before appendi ng the

jam sequence. If a collision is detected after the pream-

ble/SFD has been completed, but prior to 512 bits

being transmitted, the MAC Engine will abort the trans-

mission, and append the jam sequence immediately.

The jam sequence is a 32-bit all zeroes pattern.

The MAC Engine will attempt to transmit a frame a total

of 16 times (initial attempt plus 15 retries) due to normal

collisions (those within the slot time). Detection of colli-

sion will cause the transmission to be re-scheduled,

dependent on the backoff time that the MAC Engine

computes. If a single retry was required, the ONE bit

will be set in the Transmit Frame Status (TMD1 in the

Transmit Descriptor Ring). If more than one retr y was

required, the MORE bit will be set. If all 16 attempts e x-

perienced collisions, the R TR Y bit (in TMD3) will be set

(ONE and M ORE wi ll be clea r), and t he transmit mes-

sage will be flushed from the FIFO. If retries have been

disabled by setting the DRTY bit in the MODE reg ister

(CSR15), the MAC Engine will abandon transmission

of the frame on detection of the first collision. In this

case, only the RTRY bit will be set and the transmit

message will be flushed from the FIFO.

If a collision is detected after 512 bit times have been

transmitted, the collision is termed a late collision. The

MAC Engine will abort the transmission, append the

jam se quence, and se t the LCOL bit. No r etr y attemp t

will be scheduled on detection of a late collision, and

the FIFO will be flushed.

The IEEE 80 2.3 S tan dar d re q uires us e of a “truncated

binary exponential backoff” algorithm which provid es a

controlled pseudo-random mechanism to enforce the

collision backoff interval, before re-transmission is

attempted.

See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.5:

“At the end of enforcing a col lision (jam ming),

the CSMA/CD sublayer delays before attempt-

ing to re-transmit the frame. The delay is an in-

teger multiple of slot Time. The number of slot

times to delay before the nth re-transmission

attempt is chosen as a uniformly distributed

random integer r in the range:

0 ≤ r < 2k, where k = min (n,10).”

The PCnet-ISA II controller provides an alternative

algorithm, which suspends the counting of the slot

time/IPG during the time that receive carrier sense is

detected. This algorithm aids in networks where large

numbers of nodes are present, and numerous nodes

can be in collision. The algorithm effectively acceler-

ates the increase in the backoff time in busy networks,

and allows nodes not inv olved in the collision to access

the channel while the colliding nodes aw ait a reduction

in channel activity. Once channel activity is reduced,

the nodes resolving the collision time out their slot time

counters as normal.

Manchester Encoder/Decoder (MENDEC)

The integrated Manchester Encoder/Decoder provides

the PLS (Physical Layer Signaling) functions required

for a fully compliant IEEE 802.3 station. The MENDEC

provides the en coding fu nction for data to be tran smit-

ted on the network using the high accuracy on-board

oscillator , driven by either the crystal oscillator or an ex-

ternal CMOS-level compatible clock. The MENDEC

also provides the decoding function from data receiv ed

from the ne twork. The M ENDEC c ontains a Power On

Reset (POR) circuit, which ensures that all analog por-

tions of the PCnet-ISA II controller are forced into their

correct state during pow er-up, and prevents erroneous

data transmission and/or reception during this time.

External Crystal Characteristics

When usin g a cr ys tal to dr ive the oscill ator, the crys tal

specification shown in the specification table may be

used to ensure less than ±0.5 ns jitter at DO±.

74 Am79C961A

External Crystal Characteristics

Requires trimming crystal spec; no trim is 50 ppm total

Parameter Min Nom Max Unit

1. Parallel Resonant Frequency 20 MHz

2. Resonant Frequency Error

(CL = 20 pF) –50 +50 PPM

3.Chan ge in Re so nan t

Frequency With Respect

To Temperature

(0° – 70° C; CL = 20 pF)*

–40 +40 PPM

4. Crystal C apacitance 20 pF

5. Mot ional Crystal C apacitanc e

(C1) 0.022 pF

6. Series Resistance 25 Ω

7. Shunt Capacitance 7 pF

8. Drive Level TBD mW

Am79C961A 75

External Clock Drive Characteristics

When driving the oscillator from an external clock

source, XTAL 2 must be left flo ating (unc onnec ted). An

ex ternal clock having the following characteristics must

be used to ensure less than ±0.5 ns jitter at DO±.

MENDEC Transmit Path

The transmit section encodes separate clock and NRZ

data input signals into a standard Manchester encoded

serial bit stream. The transmit outputs (DO±) are

designed to operate into terminated transmission lines.

When operating into a 78 Ω terminated transmission

line, the transmit signaling meets the required output

levels and skew for Cheapernet, Ethernet, and

IEEE-802.3.

Transmitter Timing and Operation

A 20 MHz fundamental-mode crystal oscillator pro-

vides t he bas ic ti ming reference for the MEN DEC por -

tion of the PCn et-ISA II controller. The crystal input is

divided by two to c reat e the inte r n al tran sm it cl ock ref-

erence. Both clocks are fed into the Manchester

Encoder to generate the transitions in the encoded

data strea m. T he i ntern al transmit clock is used by the

MENDEC to inter nally synchroni ze the Inter nal Trans-

mit Data (ITXDAT) from the controller and Internal

Transmit Enable (ITXEN). The internal transmit clock is

also used as a stable bit-rate clock by the receive sec-

tion of the MENDEC and controller.

The oscillator requires an external 0.005% crystal, or

an external 0.01% CMOS-level input as a reference.

The accuracy requirements, if an external crystal is

used, are tighter because allowance for the on-chip

oscillator must be made to deliver a final accuracy of

0.01%.

Transmission is enabled by the controller. As long as

the ITXE N request rem ains acti ve, the seria l output of

the contr oll er will be M anche ster en co ded an d appe ar

at DO±. When the internal request is dropped by the

control ler, t he d iffe renti al trans mi t ou tputs go to o ne o f

two idle states, dependent on TSEL in the Mode

Receive Path

The principal functions of the receiver are to signal the

PCnet-IS A II contro ller that ther e is informa tion on the

receive pair, and to separate the incoming Manchester

encoded data stream into clock and NRZ data.

The receiver section (see Receiver Block Diagram)

consis ts of two paralle l path s. The receive data path is

a zero threshold, wide bandwidth line receiver. The

carrier path is an offset threshold bandpass detecting

line receiver. Both receivers share common bias

networks to allow operation over a wide input common

mode range.

Input Signal Conditioning

Transient noise pulses at the input data stream are

rejected by the Noise Rejection Filter. Pulse width

rejection is proportional to transmit data rate which is

fixed at 10 MHz for Ethernet systems but which could

be different for proprietary networks. DC inputs more

negative than minus 100 mV are also suppressed.

The Carrier Detection circuitry detects the presence of

an incoming data packet by discerning and rejecting

noise from expected Manchester data, and controls the

stop and start of the phase-lock loop during clock

acquisition. Clock acquisition requires a valid

Manchester bit pattern of 1010b to lock onto the incom-

ing message.

When input amplitude and pulse width conditions are

met at DI±, a clock acquisition cycle is initiated.

Clock Acquisition

When there is no activity at DI± (receiver is idle), the

receive oscillator is phase-lock ed to STDCLK. The first

negative clock transition (bit cell center of first valid

Manchester “0") after clock acquisition begins inter-

rupts the receive oscillator. The oscillator is then

restarted at the second Manchester “0" (bit time 4) and

is phase-locked to it. As a result, the MENDEC

acquires the clock from the incoming Manchester bit

pattern in 4 bit time s wit h a “1010" Manchester bit pat-

tern.

The internal receiver clock, IRXCLK, and the internal

received data, IRXDAT, are enabled 1/4 bit time after

clock acquisition in bit cell 5. IRXDAT is at a HIGH state

when the receiver is idle (no IRXCLK). IRXDAT how-

ever, is undefined when clock is acquired and may

remain HIGH or change to LOW state whenever IRX-

CLK is enabled. At 1/4 bit time through bit cell 5, the

controller portion of the PCnet-ISA II controller sees the

first IRXCLK transition. This also strobes in the

incoming fifth bit to the MENDEC as Manchester “1".

IRXD AT may mak e a transition after the IRXCLK rising

edge in bit cell 5, but its state is still undefined. The

Manchester “1" at bit 5 is clocked to IRXDAT output at

1/4 bit time in bit cell 6.

Clock F re quency: 20 MHz ±0.01%

Rise/Fall Time (tR/tF): < 6 ns from 0.5 V to VDD–0.5

XTAL1 HIGH/LOW Time

(tHIGH/tLOW): 40 – 60% duty cycle

XTAL1 Falling Edge to

Falling Edge Jitte r: < ±0.2 ns at 2.5 V inp ut (VDD /2 )

TSEL LOW: The idle state of DO± yields “zero”

differential to operate transformer-coupled

loads

TSEL HIGH: In this idle state, DO+ is positive with respect

to DO– (logical HIGH).

76 Am79C961A

PLL Tracking

After c lock acquis ition , the phas e-locked clock is co m-

pared to the incoming transition at the bit cell center

(BCC) and the resulting phase error is applied to a cor-

rection circuit. This circuit ensures that the

phase-locked clock remains locked on the received

signal. Individual bit cell phase corrections of the

Voltage Controlled Oscillator (VCO) are limited to 10%

of the phase difference between BCC and phase-

locked clock.

Receiver Block Diagram

Carrier Tracking and End of Message

The carrier detection circuit monitors the DI± inputs

after IRXCRS is asserted for an end of message.

IRXCRS de- asserts 1 to 2 bit t imes after the la st posi-

tive transitio n on the inc oming mes sage. This ini tiates

the end of reception cycle. The time delay from the last

rising edge of the message to IRXCRS deassert allows

the last bit to be strobed by IRXCLK and transferred to

the controller section, but prevents any extra bit(s) at

the end of message. When IRXCRS de-asser ts an

IRXCRS hold off timer inhibits IRXCRS assertion for at

least 2 bit times.

Data Decoding

The data re ceiver i s a comparator with clocked output

to minimize noise sensitivity to the DI± inputs. Input

error is less than ±35 mV to minimize sensitivity to input

rise and fall time. IRXCLK strobes the data receiver

output at 1/4 bit time to determine the value of the

Manchester bit, and clocks the data out on IRXDAT on

the following IRXCLK. The data receiver also

generates th e si gn al u sed for phase detec tor co mpa ri-

son to the internal MENDEC voltage controlled

oscill ato r (VCO ).

Differential Input Terminations

The differential input for the Manchester data (DI±)

should be externally terminated by two 40.2 Ω ±1%

resistors and one optional common-mode bypass

capacitor, as shown in the Differential Input Termina-

tion diagram below. The differential input impedance,

ZIDF, and the common-mode input impedance, ZICM,

are specified so that the Ethernet specification for cable

termination impedance is met using standard 1%

resistor terminators. If SIP devices are used, 39 Ω is

the neare st usable equivalent value. The CI± differen-

tial inputs are ter minated in exactly the same way as

the DI± pair.

Collision Detection

A MAU detects the collision condition on the network

and generates a differential signal at the CI± inputs.

This collision signal passes through an input stage

which detects signal levels and pulse duration. When

the signal is detected by the MENDEC it sets the inter-

nal collision signal, ICLSN, HIGH. The condition contin-

Data

Receiver Manchester

Decoder

Noise

Reject

Filter

Carrier

Detect

Circuit

*Internal signal

DI±

IRXDAT*

IRXCLK*

IRXCRS*

19364B-16

PCnet-ISA II

DI+

40.2 Ω40.2 Ω

0.01 µF

to 0.1 µF

AUI Isolation

Transformer

Differential Input Termination

19364A-17

Am79C961A 77

ues for approximately 1.5 bit times after the last

LOW-to-HIGH transition on CI±.

Jitter Tolerance Definition

The MENDEC utilizes a clock capture circuit to align its

inter nal data strobe with an incoming bit stream. The

clock acquisition circuitry requires four valid bits with

the values 1010b. Clock is phase-locked to the nega-

tive transition at the bi t cell center of the seco nd “0" in

the pattern.

Since dat a is strobed at 1/4 bit tim e, Manchester tran-

sitions which shift from their nominal placement

through 1/4 bit time will result in improperly decoded

data. With this as the criteria for an error , a definition of

“Jitter Handling” is:

The peak deviation approaching or crossing

1/4 bit cell positio n from nomin al input transi-

tion, for which the MENDEC section will

properly decode data.

Attachment Unit Interface (AUI)

The AUI i s the PLS (P hysical Layer Signal ing) to PMA

(Physical Medium Attachment) interface which con-

nects the DTE to a MAU. The differential interface pro-

vided by the PCnet-ISA II controller is fully compliant

with Section 7 of ISO 8802-3 (ANSI/IEEE 802.3).

After the PCnet-ISA II controller initiates a transmis-

sion, it will expect to see data “looped-back” on the DI±

pair (when the AUI port is selected). This will internally

generate a “carrier sense”, indi cating that the in tegrity

of the data path to and from the MA U is intact, and that

the MA U is operating correctly. This “carrier sense” sig-

nal must be asserted within sometime before end of

transmission. If “carri er sense” does not become active

in response to the data transmission, or becomes inac-

tive before the end of transmission, th e loss of carrier

(LCAR) error bit will be set in the Transmit Descriptor

Ring (TMD3, bit 11) after the packet has been

transmitted.

Twisted Pair Transceiver (T-MAU)

This section describes operation of the T-MAU when

operating in the Half Duplex mode. When in Half

Duplex mode, the T-MAU implements the Medium

Attachment Unit (MAU) functions for the Twisted Pair

Medium as specified by the supplement to IEEE 802.3

standard (Type 10BASE-T). When operating in Full

Duplex mode, the MAC engine behavior changes as

described in the Full Duplex Operation section. The

T-MAU provides twisted pair driver and receiver cir-

cuits, including on-board transmit digital predistortion

and receiver squelch, and a number of additiona l fea-

tures including Link Status indication, Automatic

Twisted Pair Receive P olarity Detection/Correction and

Indication, Receive Carrier Sense, Transmit Active and

Collision Pr esent indication .

Twisted Pair Transmit Function

The differential driver circuitry in the TXD± and TXP±

pins provides the necessary electrical driving capability

and the pre-distor tion control for transmitting signals

over maximum length Twisted Pair cable, as specified

by the 10BASE-T sup pl eme nt to the IEE E 802 .3 St an-

dard. The transmit function for data output meets the

propagation delays and jitter specified by the standard.

Twisted Pair Receive Function

The receiver complies with the receiver specifications

of the IEEE 802.3 10BASE-T Standard, including noise

immunit y a nd received signal re jection cr iteria (‘Smart

Squelch’). Sign als meeting thes e criter ia appeari ng at

the RXD± differential input pair are routed to the

MENDEC. The receiver function meets the propagation

delays and jitter requirements specified by the stan-

dard. The receiver squelch le vel drops to half its thresh-

old value after unsquelch to allow reception of

minimum amplitude signals and to offset carrier f ade in

the event of worst case signal attenuation conditions.

Note that the 10 BASE-T Standar d d efines the rece ive

input amplitude at the e xternal Media Dependent Inter-

face (MDI). Filter and transformer loss are not speci-

fied. Th e T-MAU rece iver squelch level s are designe d

to account for a 1 dB inser tion loss at 10 MHz for the

type of receive filters and transformers usually used.

Normal 10BASE-T compatible receive thresholds are

inv oked when the LRT bit (CSR15, bit 9) is LO W. When

the LRT bit is set, the Low Receive Threshold option is

invoked, and the sensitivity of the T-MAU receiver is

increased. Increasing T-MA U sensitivity allows the use

of lines longer than the 100 m target distanc e of stan-

dard 10BASE-T (assuming typical 24 AWG cable).

Increased receiver sensitivity compensates for the

increased signal attenuation caused by the additional

cable distance.

However, making the receiver more sensitive means

that it is also more susceptible to ex traneous noise, pri-

marily caused by coupling from co-resident services

(crosstalk). For this reason, end users may wish to

invoke the Low Receive Threshold option on 4-pair

cable only. Multi-pair cables within the same outer

sheath hav e lower crosstalk attenuation, and may allow

noise emitted from adjacent pairs to couple into the

receive pair, and be of sufficient amplitude to falsely

unsquel ch the T-M AU.

Link Test Function

The link test function is implemented as specified by

10BASE-T standard. During periods of transmit pair

inactivity,’Link beat pulses’ will be periodically sent over

the twiste d p air m edi um to co nst antl y mo nito r med ium

integrity.

78 Am79C961A

When the link test function is enabled (DLNKTST bit in

CSR15 is cleared), the absence of link beat pulses and

receive data on the RX D± pair wil l cause the T MAU to

go into the Link Fail state. In the Link Fail state, data

transmission, data reception, data loopback and the

collision detection functions are disabled and remain

disabled until valid data or greater than 5 consecutive

link pul ses appea r on the R XD± pair. Dur ing Link Fail,

the Link Status (LNKST indicated by LED0) signal is

inactive. When the link is identified as functional, the

LNKST signal is asserted, and LED0 output will be

activated. Upon power up or assertion of the RESET

pin, the T-MAU will be forced into the Link Fail state.

Reading the RESET register of the PCnet-ISA+ (soft-

ware RESET) has no effect on the T-MAU

In order to inter-operate with systems which do not

implement Link Test, this function can be disabled by

setting the DLNKTST bit. With Link Test disabled, the

Data Driver, Re ceiver and Loopback functions as well

as Collision Detection remain enabled irrespective of

the pres ence or absence o f data or lin k pulses on th e

RXD± pair . Link Test pulses continue to be sent regard-

less of the state of the DLNKT ST bit.

Polarity Detection and Reversal

The T-MAU receive function includes the ability to

inv ert the polarity of the signals appearing at the RXD±

pair if the polarity of the received signal is reversed

(such as in the case of a wiring error). This feature

allows data packets received from a reverse wired

RXD± input pa ir to be corre cted in th e T-MAU pr ior to

transfer to the MENDEC. The polarity detection func-

tion is activated following reset or Link Fail, and will

reverse the r eceive polar ity based on bot h the polar ity

of any previous link beat pulses and the polarity of sub-

sequent packets with a valid End Transmit Delimiter

(ETD).

When in the Link Fail state, the T-MAU will recognize

link beat pulses of either positive or negative polarity.

Exit from the Link Fail state occurs at the reception of

5 – 6 consecutive link beat pulses of identical polarity.

On entry to the Link Pass state, the polarity of the last

5 link beat pulses is used to determine the initial

receive polarity configuration and the receiver is

reconfigured to subsequently recognize only link beat

pulses of the previously recognized polarity.

P ositive link beat pulses are defined as transmitted sig-

nal with a pos it ive amplitude greater than 585 mV wit h

a pulse width of 60 ns – 200 ns. This positive excursion

may be followed by a negative excursion. This defini-

tion is consistent with the expected received signal at a

corre ctly wired rece iver, when a link bea t pulse, which

fits the template of Figure 14-12 of the 10BASE-T Stan-

dard, is generated at a transmitter and passed through

100 m of twisted pair cable.

Negative link beat pulses are defined as transmitted

signals with a negative amplitude greater than 585 mV

with a pulse width of 60 ns – 200 ns. This negative

excursion may be followed by a positive excursion. This

definiti on is co nsistent wi th the expected rec eived sig-

nal at a reve rse wir ed rec eiver, when a link beat pulse

which fits the template of Figure 14-12 in the

10BASE -T Standa rd is gen erated at a transmitt er and

passed through 100 m of twisted pair cable.

The polarity detection/correction algorithm will remain

“armed” until two consecutive pac kets with valid ETD of

identical polarity are detected. When “armed,” the

receiver is capable of changing the initial or previous

polarity configuration according to the detected ETD

polarity.

On receipt of the first packet with valid ETD following

reset or link f ail, the T-MA U will use the inferred polarity

information to configure its RXD± input, regardless of

its previous state. On receipt of a second packet with a

v alid ETD with correct polarity, the detection/correction

algor ithm will “lock-in” th e recei ve d polar ity. If the sec-

ond (or subsequent) packet is not detected as confirm-

ing the previous polarity decision, the most recently

detected ETD polarity will be used as the default. Note

that packets with invalid ET D have no effect on updat-

ing the previous polarity decision . On ce two consecu-

tive packets with valid ETD have been received, the

T-MAU will lock the correction algorithm until either a

Link Fail condition occurs or RESET is asserted.

During polarity reversal, an internal POL signal will be

active. During normal polarity conditions, this internal

POL signal is inactive. The state of this signal can be

read by software and/or displayed by LED when

enabled by the LED control bits in the ISA Bus Config-

uration Registers (ISACSR5, 6, 7).

Twisted Pair Interface Status

Three internal signals (XMT, RCV and COL) indicate

whether the T-MAU is transmitting, receiving, or in a

collision state. These signals are internal signals and

the behavior of the LED outputs depends on how the

LED output circuitry is programmed.

The T-MAU will power up in the Link Fail st ate and the

nor mal algor ithm will appl y to al low it t o ente r the Link

Pass state. In the Link Pass state, transmit or rece ive

activity will be indicated by assertion of RCV signal

going active. If T-MAU is selected using the PORTSEL

bits in CSR15, when moving from AUI to T-MAU selec-

tion, the T-MAU will be forced into the Link Fail state.

In the Link Fail state, XMT, RCV and COL are inactive.

Collision Detect Function

Activity on both twisted pair signals RXD± and TXD±

constit utes a c ollis io n, the r eby causin g the COL si gnal

to be asserted. (COL is used by the LED control cir-

cuits) COL will remain asserted until one of the two col-

Am79C961A 79

liding signals changes from active to idle. COL stays

active for 2 bit times at the end of a collision.

Signal Quality Error (SQE) Test

(Heartbeat) Function

The SQE function is disabled when the 10BASE-T port

is selected and in Link Fail state.

Jabber Function

The Jabber function inhibits the twisted pair transmit

function of the T-MAU if the TXD± circuit is active f or an

excessive period (20 ms–150 ms). This prevents any

one node from disrupting the network due to a

‘stuck-on’ or faulty transmitter. If this maximum transmit

time is exceeded, the T-MA U transmitter circuitry is dis-

abled, the JAB bit is set (CSR4, bit 1), and the COL sig-

nal asserted. Once the transmit data stream to the

T-MA U is removed, an “unjab” time of 250 ms – 750 ms

will elapse before the T-MAU deasserts COL and

re-enables the transmit circuitry.

Power Down

The T-MAU circuitry can be made to go into low power

mode. This feature is use ful in batte ry powe red or low

duty cycle systems. The T-MAU will go into power

down mode when RESET is active, coma mode is ac-

tive, or the T-MAU i s not selecte d. Refer to the Power

Down Mode section for a description of the various

power down mod es.

Any of the three conditions listed above resets the

inter nal logic of the T -MAU and places the device into

power down mode. In this mode, the Twisted Pair

driver pins (TXD±,TXP±) are asserted LOW , and the in-

ternal T-MAU status signals (LNKST, RCVPOL, XMT,

RCV and COLLISION) are inactive.

Once the SLEEP pin is deasserted, the T-MAU will be

forced into the Link Fail state. The T-MAU will move to

the Link Pass state only after 5–6 link beat pulses and/

or a sin gle rec eived messag e is dete cted on the RX D±

pair.

In Snooze mode, the T-MAU receive circuitry will

remain enabled even while the SLEEP pin is driven

LOW.

The T-MAU circuitry will always go into power down

mode if RESET is asserted, coma is enabled, or the

T-MAU is not selected.

Full Duplex Operation

The PCnet-ISA II supports Full Duplex operation on the

10BASE-T, A UI, and GPSI ports. Full Duplex operation

allows simultaneous transmit and receive activity on

the TXD± and RXD± pairs of the 10BASE-T port, the

DO± and DI± pairs of the AUI port, and the TXD AT and

RXDAT pins of the GPSI port. It is enabled by the

FDEN and AU IFD bits located in ISACSR9. When o p-

erating in t he F ull Du pl ex mode, the following changes

to device operation are made:

Bus Interface/Buffer Management Unit changes:

1. The first 64 bytes of every transmit frame are not

preserved in the transmit FIFO during transmission

of the first 512 bits transmitted on the network, as

described in the Transmit Exception Conditions

section. Instead, when Full Duplex mode is active

and a frame is being transmitted, the XMTFW bits

(CSR80, bits 9, 8) always govern when transmit

DMA is requested.

2. Successful reception of the first 64 bytes of every

receive frame is not a requirement f or Receive DMA

to begin as described in the Receive Exception

Conditions section. Instead, receive DMA will be

request ed as soo n as ei ther the R CVFW thr eshold

(CSR80 bits 12, 13) is reached or a complete valid

receive frame is in t he Re ce ive FIFO, regardles s o f

length. This receive FIFO operation is identical to

when the RPA bit (C SR1 24, bit 3) is set during Half

Duplex mode operation.

MAC Engine changes :

1. Changes to the Transmit Deferral mechanism:

A. Transmission is not deferred while receive is

active.

B. The Inter Packet Gap (IPG) co unter which gov-

erns transmit deferral during the IPG between

back-to-back transmi ts is star ted w hen transmit

activi ty for the first packet ends instead of whe n

transmit and carrier activity ends.

2. When the AUI or GPSI port is active , Loss of Carrier

(LCAR) reporting is disabled (LCAR is still reported

when the 10BASE-T port is active if a packet is

transmitted while in the Link Fail state).

3. The 4.0 µs carrier sense blinding period after a

transmission during which the SQE test normally

occurs is disabled.

4. When the AUI or GP SI port is active, the SQE Test

error (Collision Error, CERR) reporting is disabled

(CERR is still repo r ted when the 10BASE-T por t is

active if a pack et is transmitted while in the Link F ail

state).

5. The co llision i ndication in put to the M AC Engi ne is

ignored.

T-MAU ch ange s:

1. The transmit to receive loopback path in the

T-MAU is disa bled.

2. The collision detect circuit is disabled.

3. The “heartbeat” generation (SQE Test function)

is disabled.

80 Am79C961A

EADI (E xterna l Addres s De te ct ion

Interface)

This in terface is provided to all ow exter nal address fi l-

tering. It is selected by setting the EADISEL bit in

ISACSR2. This feature is typically utilized for ter minal

ser vers, bridges and/or router type products. The use

of external logic is required to capture the serial bit

stream from the PCnet-ISA II controller, compare it with

a table of stor ed addr esses or identifie rs, and perform

the desired function.

The EADI interface operates directly from the NRZ

decoded dat a and clock recovered by t he Manchester

decoder or input to the GPSI, allowing the external

address detection to be performed in parallel with

frame reception and address comparison in the MAC

Station Address Detection (SAD) block.

SRDCLK is provided to allow clocking of the receive bit

stream into the external address detection logic.

SRDCLK runs only during frame reception activity.

Once a received frame commences and data and clock

are av ailable, the EADI logic will monitor the alternating

(“1,0") preamble pattern unti l the two ones of the Start

Frame Delimiter (“1,0,1,0,1,0,1,1") are detected, at

which point the SF/BD output will be driven HIGH.

After SF/BD is asserted the serial data from SRD

should be de-serialized and sent to a content address-

able memory (CAM) or other address detection de vice.

To al low si mple seri al to parallel c onversion , SF/BD is

provided as a strobe and/or marker to indicate the

delineati on of bytes, su bsequ ent to th e SFD. This pro-

vides a mechanism to allow not only capture and/or de-

coding of the physical or logical (group) address, it also

facilitates the capture of header information to

determine protocol and or inter-networking information.

The EAR pin is driven LOW by the external address

comparison logic to reject the frame.

If an internal address match is detected by comparison

with either the Physical or Logical Address field, the

frame will be accepted regardless of the condition of

EAR. Incoming frames which do not pass the internal

address comparison will continue to be received. This

allows approximately 58 byte times after the last des ti-

nation address bit is available to generate the EAR

signal, assuming the device is not configured to accept

runt packets. EAR will be ignored after 64 byte times

after the SFD, and the frame will be accepted if EAR

has not been asser ted before this time. If Runt Packet

Accept is configured, the EAR signal must be

generated prior to the receive message completion,

which could be as shor t as 12 byte times (assuming 6

bytes for source address, 2 bytes for length, no data, 4

bytes for FCS) after the last bit of the destination

address is av ailab le. EAR must ha v e a pulse w idth of at

least 200 ns.

Note that setting the PROM bit (CSR15, bit 15) will

cause al l receive frames to be re ceived, regardless o f

the state of the EAR input.

If the DRCUPA bit (CSR15.B) is set and the logical

address (LADRF) is set to zero, o nl y frames which ar e

not rejected by EAR will be received.

The EADI interf ace will operate as long as the STRT bit

in CSR0 is set, even if the receiver and/or transmitter

are disabled by software (DTX and DRX bits in CSR15

set). Th is si tuation is useful as a power down m ode i n

that the PCnet-ISA II controller will not perform any

DMA operations; this saves power by not utilizing the

ISA bus driver circuits. However, external circuitry

could still respond to specific frames on the network to

facilitate remote node control.

The table below summarizes the operation of the EADI

features.

Internal/External Address Recognition Capabilities

General Purpose Serial Interface (GPSI)

The PCnet-ISA II controller contains a General

Purpose Serial Interface (GPSI) designed for testing

the digital portions of the chip . The MENDEC, A UI, and

twisted pair interface are by-passed once the de vice is

set up in the special “test mode” for accessing the GPSI

functions. Although this access is intended only for

testing the device, some users may find the non-en-

coded data functions useful in some special

applications. Note, however, that the GPSI functions

can be accessed only when the PCnet-ISA II devices

operate as a bus master.

The PCnet -ISA II GPS I signals are co nsisten t with the

LANCE digital serial interface. Since the GPSI func-

tions can be accessed only through a special test

mode, expect some loss of functionality to the device

when the GPSI is invoked. The AUI and 10BASE-T

analog interfaces are disabled along with the internal

PROM EAR Required Timing Received Messages

1 X No timing requirements All Received Frames

0 1 No timing requirements All Received Frames

0 0 Low for 200 ns within 512 bits after SFD Physical/Logical Matches

Am79C961A 81

MENDEC logic. The LA (unlatched address) pins are

removed and become the GPSI signals, therefore, only

20 bits of address spac e is available. The table bel ow

shows the GPSI pin configuration:

To invoke the GPSI signals, f ollow the procedure below:

1. After r eset or I/O rea d of Reset A ddress, wr ite 10b

to PORTSEL bits in CSR15.

2. Set the ENTST bit in CSR4

3. Set the GPSIEN bit in CSR124 (see note below)

(The pins LA17–LA23 will change function after the

completion of the above three steps.)

4. Clear the ENTST bit in CSR4

5. Clear Media Select bits in ISACSR2

6. Define the PORTSEL bits in the MODE register

(CS R15 ) to be 10b t o def ine GPSI po rt. The MOD E

Note: LA pins will be tristated b ef ore writing to GPSIEN bit.

After writing t o GPSIEN, L A[17–21 ] will be in puts , LA[22–23]

will be outputs.

GPSI Pin Configurations

Note:

The GPSI Function is available only in the Bus Master Mode of operation.

GPSI Function GPSI

I/O Type LANCE

GPSI Pin PCnet-ISA II

Pin Number PCnet -ISA II Normal

Pin Function

Receive Da ta I RX RXDAT 5 LA17

Receive Clock I RCLK SRDCLK 6 LA18

Receive Carrier Sense I RENA RXCRS 7 LA19

Collision I CLSN CLSN 9 LA20

Transmit Clock I TCLK STDCLK 1 0 LA21

Transmit Enable O TENA TXEN 11 LA22

Transmit Data O TX TXDAT 12 LA23

82 Am79C961A

IEEE 1149.1 Test Access Port Interface

An IEEE 1 149.1 compati ble bou ndary scan Test Access

Port i s pr ovided for boar d-level continui ty tes t and di ag-

nostics. All digital input, output, and input/output pins are

tested. Analog pins, including the AUI differential driver

(DO±) and receivers (DI±, CI±), and the crystal input

(XTAL1/XTAL2) pins, are tested. The T-MAU drivers

TXD±, TXP±, an d rec eiver RXD ± are also tested.

The following is a brief summary of the IEEE 1149.1

compatible test functions implemented in the PC-

net-ISA II controller.

Boundary Scan Circuit

The boun dar y s can te st ci rcuit requ ires four extra pi ns

(TCK, TMS, TDI and TDO), defined as the Test Access

Port (TAP). It includes a finite state machine (FSM), an

instruction register, a data register array, and a

power-on reset circuit. Internal pull-up resistors are

pro vi ded f o r th e TDI , TC K, an d TMS pins . Th e TCK p in

must not be left un connected. T he boundar y scan cir-

cuit remains active during sleep.

TAP FSM

The TAP engine i s a 16-state FSM, dri ven by the Test

Clock (TCK) and the Test Mode Select (TMS) pins. This

FSM is in its reset state at power-up or RESET. An

independent power-on reset circuit is provided to

ensure th e FSM is in the TES T_LOGIC_RESE T state

at power-up.

Supported Instructions

In addition to the minimum IEEE 1149.1 requirements

(BYPASS, EXTEST and SAMPLE instructions), three

additional instructions (IDCODE, TRIBYP

and SETBYP) are pr ovided to f urt her e ase boar d-level

testing. All unused instruction codes are reser ved. See

the table below for a summary of supported instructions.

Instruction Register and Decoding Logic

After hardware or software RESET, the IDCODE

instruction is always invoked. The decoding logic gives

signals to control the data flow in the DATA registers

according to the current instruction.

Boundary Scan Register (BSR)

Each BSR ce ll has two stag es. A fl ip-flop and a lat ch are

used in the SERIAL SHIFT STAGE and the PARALLEL

OUTPUT STAGE, respectively.

There are four possible operational modes in the BSR cell:

Other Data Registers

(1) BYPASS REG (1 BIT)

(2) DEV ID REG (32 bits)

IEEE 1149.1 Supported Instruction Summary

Power Saving Modes

The PCnet-ISA II controller supports two hardware

power-savings modes. Both are entered by asserting

the SLEEP pin LOW.

In coma mode, the PCnet-ISA II controller will g o into

deep sleep with no support to automatically wake itself

up. Sleep mode is enabled when the AWAKE bit in

ISACSR2 is reset. This mode is the default powerdo wn

mode.

In Snooze mode, enabled by setting the AWAKE bit in

ISACSR2 and driving the SLEEP pin LOW, the T-MAU

receive circuitry will remain enabled even while the

SLEEP pin is driven LOW. The LED0 output will also

continue to function, indicating a good 10BASE-T link if

1Capture

2Shift

3 Update

4 System Function

Bits 31–28: Version

Bits 27–12: Part number (2261h)

Bits 11–1: Manufacturer ID. The 11 bit

manufacturer ID code for AMD is

00000000001 according to JEDEC

Publication 106-A.

Bit 0: Always a logic 1

Instruction

Name Description Selected

Data Reg Mode Instruction

Code

EXTEST External Test BSR Test 0000

IDCODE ID Code Inspection ID REG Normal 0001

SAMPLE Sample Boundary BSR Normal 0010

TRIBYP Force Tristate Bypass Normal 0011

SETBYP Control Boundary to 1/0 Bypass Test 0100

BYPASS Bypass Scan Bypass Normal 1111

Am79C961A 83

there are link beat pulses or valid frames present. This

LED0 pin can be used to drive a LED and/or external

hardware that directly controls the SLEEP pin of the

PCnet-ISA II controller. This configuration effectively

wakes the system when there is any activity on the

10BASE-T link.

Access Operations (Software)

We begin by describing how byte and word data are

addressed on the ISA bus, including conv ersion cycles

where 16-bit accesses are turned into 8-bit accesses

because the re sour ce acces sed d id not sup port 16-bi t

operations. The n we de scr ibe h ow registers and oth er

resour ces a re access ed. This section i s fo r the device

programmer, while the next section (bus cycles) is for

the hardware designer.

I/O Resources

The PCnet-ISA II controller has both I/O and memory

resources. In the I/O space the resources are orga-

nized as indicated in the following table:

The PCnet-ISA II controller does not respond to any

addresses outside of the offset range 0-17h. I/O offsets

18h and up ar e not used b y the P Cnet- I SA II contr oller.

I/O Register Access

The register address port (RAP) is shared by the regis-

ter data port (RDP) and the ISACSR data port (IDP) to

save registers. To access the Ethernet controller’s RDP

or IDP, the RAP should be wr itten fi rst, fo llowed by the

read or write access to the RDP or IDP. I/O register

access es sh ould be c oded a s 16-bi t acc esses, eve n if

the PCnet-ISA II controller is hardware configured for

8-bit I/O bus cy cles. It is acceptable ( and transparent)

for the motherboard to turn a 16-bit software access

into two separate 8-bit hardware bus cycles. The moth-

erboard accesses the low b yte bef ore the high byte and

the PCnet-ISA II controller has circuitr y to specifically

support this type of access.

The reset register causes a reset when read. Any value

will be accepted and the cycle may be 8 or 16 bits wide.

Writes are ignored.

All PCnet-ISA II controller register accesses should be

coded as 16-bit operations.

“Note that the RAP is cleared on Rese t.”

IEEE Address Access

The address PROM may be an external memory

device that contains the node’s unique p hy sic al Et her-

net address and any other data stored by the board

manufacturer. The software accesses must be 16-bit.

This information may be stored in the EEPROM.

Boot PROM Access

The boot PROM is an external memory resource

located by the address selected by the EEPROM or the

BPAM input in slave mode. It may be software

accessed as an 8-bit or 16-bit resource but the latter is

recommended for best performance.

Static RAM Access

The static RAM is only present in the Bus Slave mode.

In the Bus Slave mode, two SRAM access schemes

are available. When the Shared Memory architecture

mode is selected, the SRAM is accessed using ISA

memory cycles to the address range selected by the

SMAM input. It may be accessed as an 8 or 16-bit

resource but the latter is recommended f or best perf or-

mance. When the Programme d I/O archi tecture mod e

is selected, the SRAM is accessed through ISACSR0

and ISACSR1 using the RAP and IDP.

Bus Cycles (Hardware)

The PCnet-ISA II controller supports both 8-bit and

16-bit hardware bus cycles. The follo wing sections out-

line where any limitatio ns apply based up on the archi-

tecture mode and/or the resource that is being

accessed (PCnet-ISA II controller registers, address

PROM, boot PROM, or shared memory SRAM). For

completeness, the following sections are arranged by

architecture (Bus Master Mode or Bus Slave Mode).

SRAM resources apply only to Bus Slave Mode.

All resources (registers, PROMs, SRAM) are pre-

sented to the ISA bus by the PCnet-ISA II controller.

With few exceptions, these resources can be config-

ured for either 8-bit or 16-bit bus cycles. The I/O

resources (registers, address PROM) are width con-

figured using the EEPROM. The memory resources

(boot PROM, SRAM) are width configured by e xternal

hardware.

Fo r 1 6-bit memor y ac cess es, hard ware exter nal to th e

PCnet-ISA II controller asserts MEMCS16 when either

of the two memory resources is selected. The ISA bus

requires that all memory resources within a block of

128 Kb ytes be the same width, either 8- or 16-bits. The

reason for this is that the MEMCS16 signal is generally

a deco de of the LA 17-23 address lines. 16-bit memory

capability is desirable since two 8-bit accesses take the

same amount of time as four 16-bit accesses.

All accesses to 8-bit resources (which do not return

MEMCS16 or IOCS16) use SD0-7. If an odd byte is

accessed, the Current Master swap buffer turns on.

Offset #Bytes Register

0h 16 IEEE Address

10h 2 RDP

12h 2 RAP(shared by RDP and IDP)

14h 2 Reset

16h 2 IDP

84 Am79C961A

During an odd byte read the swap buffer copies the

data from SD0-7 to the high byte. During an odd byte

write the Current Master swap buffer copies the data

from the hig h byte to SD0-7. The P Cnet -IS A II cont rol-

ler can be confi gured to be an 8-b it I/O re source even

in a 16-bit system; this is set by the EEPROM. It is rec-

ommended that the PCnet-ISA II controller be config-

ured for 8-bit only I/O bus cycles for maximum

compatibility with PC/AT clone motherboards.

When the PCne t-ISA II c ontroller is in an 8-bit system

such as a PC/XT, SBHE and IOCS16 must be left

unconnected (these signals do not exist in the PC/XT).

This will f orce ALL resources (I/O and memory) to sup-

por t only 8-bit bus cycles. The PCnet-ISA II controller

will function in an 8-bit system only if configured for Bus

Slave Mode.

Accesses to 16-bit resources (which do return

MEMCS16 or IOCS16) use either or both SD0–7 and

SD8–15. A word access is indicated by A0=0 and

SBHE=0 and data is transferred on all 16 data lines. An

even byte access is indicated by A0=0 and SBHE=1

and data is transferred on SD0–7. An odd-byte access

is indicated by A0=1 and SBHE=0 and data is trans-

ferred on SD8-15. It is illegal to have A0=1 and

SBHE=1 in any bus cycle. The PCnet-ISA II controller

returns only IOCS16; MEMCS16 must be generated by

external hardware if desired. The use of MEMCS16

applies only to Shared Memory Mode.

The following table descr ibes all p ossible types of ISA

bus accesses, including Permanent Master as Current

Master and PCnet-ISA II controller as Current Master.

The PCnet-ISA II controller will not work with 8-bit

memory w h ile it is Curr en t Ma ster. Any descripti ons o f

8-bit memory accesses are for when the Permanent

Master is Current Master.

The two byte columns (D0–7 and D8–15) indicate

whether the bus master or slave is driving the byte.

CS16 is a shorthand for MEMCS16 and IOCS16.

Bus Master Mode

The PCnet-ISA II controller can be configured as a Bus

Maste r only in sys tems that support bus master ing. In

addition, the system is assumed to support 16-bit

memory (DMA) cycles (the PCnet-ISA II controller

does not use the MEMCS16 signal on the ISA bus).

This does not preclude the PCnet-ISA II controller from

doing 8-bit I/O transfers. The PCnet-ISA II controller

will not function as a b us master in 8-bit platf orms such

as the PC/XT.

Refresh Cycles

Although the PCnet-ISA II controller is neither an origi-

nator or a receiver of refresh cycles, it does need to

av oid unintentional activity during a refresh cycle in bus

master mode. A refresh cycle is performed as follows:

First, the REF signal goes active. Then a valid refresh

address is placed on the address b us. MEMR goes ac-

tive, the refresh is performed, and MEMR goes inac-

tive. The refresh address is held for a shor t time and

them go es invalid. F inally, REF g oes i nactive. During

a refresh cycle, as indicated by REF being active, the

PCnet-ISA II controller ignores DACK if it goes active

until it goes inactive. It is necessary to ignore DACK

during a refresh because some motherboards gener-

ate a false DACK at that time.

ISA Bus Accesses

Address PROM Cycles External PROM

The Add ress PROM is a sma ll (16 bytes) 8-bit PROM

connected to the PCnet-ISA II controller Private Data

Bus. The PCnet-ISA II controller will support only 8-bit

ISA I/O bus cycles for the address PROM; this limita-

tion is transparent to software and does not preclude

16-bit s oftware I/O acce sses. An ac cess cyc le begins

R/W A0 SBHE CS16 D0–7D8–15 Comments

RD 0 1 x Slave Flo a t Low byte RD

RD101SlaveFloat High byte RD with swap

RD 0 0 1 Slave Float 16-Bit RD converted to low byte RD

RD 1 0 0 Float Slav e High byte RD

RD 0 0 0 Slave Slave 16-Bit RD

WR 0 1 x Master Float Low byte WR

WR 1 0 1 Master Float High byte WR with swap

WR 0 0 1 Master Master 16-Bit WR converted to

low byte WR

WR 1 0 0 Float Master H i gh byte WR

WR 0 0 0 Master Master 16-Bit WR

Am79C961A 85

with the Permanent Master driving AEN LOW, driving

the addressess valid, and driving IOR active. The

PCnet-IS A II co ntr ol ler det ect s thi s co mb ina tio n of si g-

nals and arbitrates for the Private Data Bus (PRDB) i f

necessary. IOCHRDY is driven LOW duri ng accesses

to the address PROM.

When the Private Data Bus becomes available, the

PCnet-ISA II controller drives APCS active, releases

IOCHRDY, turns on the data path from PRD0-7, and

enables the SD0-7 drivers (but not SD8-15). During

this b us cy cle , I OCS16 is not driven active. This condi-

tion is maintained until IOR goes inactive, at which time

the bus cycle ends. Data is remov ed from SD0-7 within

30 ns.

Address PROM Cycl es Using EEPROM Data

Default mode. In this mode, the IEEE address inf orma-

tion is stored not in an external parallel PROM but in the

EEPROM along with other configuration information.

PCnet-ISA II will respond to I/O reads from the IEEE

address (the first 16 bytes of the I/O map) by supplying

data from an internal RAM inside PCnet-ISA II. This in-

ternal RAM is loaded with the IEEE address at RESET

and is write protected.

Ethernet Controller Register Cycles

Ethernet controller registers (RAP, RDP, IDP) are natu-

rally 16-bi t re so urces but can be confi gu re d to o perat e

with 8-bit b us cycles provided the proper protocol is fol-

lowed. This means on a read, the PCnet-ISA II control-

ler will onl y drive the l o w b yt e of t he sy stem data b us; if

an odd byte is accessed, it will be swapped down. The

high byte of the system data bus is never driven by the

PCnet-ISA II controller under these conditions. On a

write cycle, the even byte is placed in a holding register.

An odd byte write is internally swapped up and aug-

mented with the ev en byte in the holding register to pro-

vide an internal 16-bit write. This allows the use of 8-bit

I/O bus cycles which are more likely to be compatible

with all ISA-compatible clones, but requires that both

bytes be written in immediate succession. This is

accomplished simply b y treating the PCnet-ISA II con-

troller registers as 16-bit software resources. The

motherboard will convert the 16-bit accesses done by

software into two sequential 8-bit accesses, an even

byte access followed immediately by an odd byte

access.

An access cycle begins with the Permanent Master

driving AEN LOW, driving the address valid, and driving

IOR or IOW active. The PCnet-ISA II controller detects

this combination of signals and drives IOCHRDY LOW.

IOCS16 will also be driv en LO W if 16-bit I/O b us cycles

are enabled. When the register data is ready,

IOCHRDY will be released HIGH. This condition is

maintained until IOR or IOW goes inactive, at which

time the bus cycle ends.

RESET Cycles

A read to the reset address causes an PCnet-ISA II

control ler reset. Thi s has the sa me effect as asserting

the RESET pin on the PCnet-ISA+ controller (which

happens on system power up or on a hard boot) except

that the T-MAU is NOT reset. The T-MAU will retain its

link pass/fail state, disregarding the software RESET

command. The subsequent write cycle needed in the

NE2100 L ANCE based fa mily of E ther net cards is not

required but does not have any harmful effects.

IOCS16 is not asserted in this cycle.

ISA Configuration Register Cycles

The ISA configuration registers are accessed by plac-

ing the address of the desired register into the RAP and

reading the IDP. T he ISACS R bus cycl es are identic al

to all other PCnet-ISA II controller register bus cycles.

Boot PROM Cycles

The Boot PROM is an 8-bit PROM connected to the

PCnet-ISA II controller Private Data Bus (PRDB) and

can occup y up to 64K of address space. Since the PC-

net-ISA II controller does not generate MEMCS16, only

8-bit ISA memory bus cycles to the boot PROM are

supported in Bus Maste r Mode ; this lim itatio n is trans-

parent to software and does not preclude 16-bit soft-

ware memory accesses. A boot PROM access cycle

begins with the Permanent Master driving the

addresses valid, REF inactive, and MEMR active . (AEN

is not involved in memory cycles). The PCnet-ISA II

controller detects this combination of signals, drives

IOCHRDY LOW, and reads a byte out of the Boot

PROM. The data byte read is driven onto the lower sys-

tem data bus lines and IOCHRDY is released. This

condition is maintained until MEMR goes inactive, at

which time the access cycle ends.

The BPCS signal generated by the PCnet-ISA II con-

troller is three 20 MHz clock cycles wide (300 ns).

Including delays, the Boot PROM has 275 ns to

respond to the BPCS signal from the PCnet-ISA II con-

troller. This signal is intended to be connected to the

CS pin on the boot PROM, with the PROM OE pin tied

to ground.

Current Master Operation

Current Master operation only occurs in the Bus Master

mode. It does not occur in the Bus Slave mode.

There are three phases to the use of the bus by the PC-

net-ISA II controller as Current Master, the Obtain

Phase, the Access Phase, and the Release Phase.

Obtain Phase

A Master Mode Transfer Cycle begins by asserting

DRQ. When the Permanent Master asserts DACK, the

PCnet-ISA II controller asserts MASTER, signifying it

has taken control of the ISA bus. The Permanent Mas-

ter tristates the address, command, and data lines

86 Am79C961A

within 60 ns of DACK going active. The Permanent

Master drives AEN inactive within 71 ns of MASTER

going active.

Access Phas e

The ISA bus requires a wait of at least 125 ns after

MASTER is asserted bef ore the new master is allowed

to drive the address, command, and data lines. The

PCnet-IS A II controlle r will actuall y wait 3 clock cycles

or 150 ns.

The following signals ar e not driven by the Per manen t

Master and are simply pulled HIGH: BAL E, IOCHRDY,

IOCS16, ME MCS16, SRDY. Therefore, th e PCnet-ISA

II controller assumes the memory which it is accessing

is 16 bits wide and can complete an access in the time

programmed for the PCnet-ISA II controller MEMR and

MEMW signals. Refer to the ISA Bus Configuration

Release Phase

When the PCnet-ISA II controller is finished with the

bus, it drives the command lines inactive. 50 ns later,

the controller tri-states the command, address, and

data lines and drives DRQ inactive. 50 ns later , the con-

troller drives MASTER inactive.

The Perma nen t Ma ste r drives AEN act ive within 71 ns

of MASTER going inactive. The Permanent Master is

allowed to dri ve the command lines no soon er than 6 0

ns after DACK goes inactive.

Master Mode Memory Read Cycle

After th e PCnet-ISA II controll er has acq uired the ISA

bus, it can perform a m emory read cycle. All timing is

generated relative to the 20 MHz clock (network cloc k).

Since there is no way to tell if memory is 8-bit or 16-bit

or when it is ready, the PCnet-ISA II controller by

default assumes 16- bit, 1 wait sta te mem or y. The wait

state assumption is based on the default value in the

MSRDA register in ISACSR0.

The cycle begins with SA0-19, SBHE, and LA17-23

being presented. The ISA bus requires them to be v alid

fo r at l ea st 28 ns before a rea d com m an d an d t he P C-

net-ISA II controller provides one clock or 50 ns of

setup time before asserting MEMR.

The ISA bus requires MEMR to be active for at least

219 ns, and the PCnet-ISA II controller provides a

default of 5 clocks, or 250 ns, but this can be tun ed for

faster systems with the Master Mode Read Active

(MSRDA) register (see section 2.5.2). Also, if

IOCHRDY is driven LOW, the PCnet-ISA II controller

will wait. The wait state counter must expire and

IOCHRDY must be HIGH f or the PCnet-ISA II controller

to continue.

The PCnet-ISA II controller then accepts the memory

read data . The ISA bus req uires all c ommand lines to

remain inactive for at least 97 ns before starting

another bus cyc le and the PCne t-ISA II c ontroller pro-

vides at least two clocks or 100 ns of inactive time.

The ISA bus requires read data to be valid no more

than 173 ns after receiving MEMR active a nd the PC-

net-ISA II contro ller requ ires 10 ns of data se tup time.

The ISA bus requires read data to provide at least 0 ns

of hold time an d to be rem ove d from the bus within 30

ns after MEMR goes inactive. The PCnet-ISA II control-

ler requires 0 ns of data hold time.

Master Mode Memory Write Cycle

After the PCnet-ISA II controller has acquired the ISA

bus, it ca n perfor m a memo ry wr ite cycle. All timin g is

generated relative to a 20 MHz clock which happens to

be the same as the network clock. Since there is no

way to tel l if memor y is 8- or 16-bit or when it is ready,

the PCnet-ISA II controller by def ault assumes 16-bit, 1

wait state memory. The wait state assumption is based

on the default value in the MSWRA register in

ISACSR1.

The cycle begins with SA0-19, SBHE, and LA17-23

being presented. The ISA bus requires them to be valid

at least 28 ns before MEMW goes active and data to be

v alid at least 22 ns bef ore MEMW goes active. The PC-

net-ISA II controller provides one clock or 50 ns of

setup time for all these signals.

The ISA bus requires MEMW to be active for at least

219 ns, and the PCnet-ISA II controller provides a

default of 5 clocks, or 250 ns, but this can be tun ed for

faster systems with the Master Mode Write Active

(MSWRA) register (ISACSR1). Also, if IOCHRDY is

driven LOW, the PCnet-ISA II controller will wait.

IOCHRD Y must be HIGH for the PCnet-ISA II controller

to continue.

The ISA bus requires data to be valid for at least 25 ns

after ME MW goes inacti ve, and th e PCnet-ISA II con-

troller provides one clock or 50 ns.

The ISA bus requires all command lines to remain

inactive for at least 97 ns before star ting another bus

cycle. The PCnet-ISA II controller provides at least two

clocks or 100 ns of inactive time when bit 4 in ISACSR2

is set. The EISA bus requires all command lines to

remain inactive for at least 170 ns before starting

another bus cy cle. When bit 4 in IS ACSR4 i s cleared,

the PC net-ISA II c ontroller provides 200 ns of ina ctive

time.

Back-to-Back DMA Requests

The PCne t-I SA II pr ovide s for fair bus bandwid th shar -

ing between two bus mastering devices on the ISA bus

through an adaptive delay which is inser ted between

back-to-back DMA requests.

When the PCnet-ISA II requires bus access immedi-

ately following a bus ownership period, it first checks

the st atus of the three curr ent ly unus ed DR Q p ins. If a

Am79C961A 87

lower priority DRQ pin than the one currently being

used by the PCnet-IS A II i s ass erted , the P Cne t-I SA II

will wait 2.6 µs after the deassertion of DACK before

re-asserting its DRQ pin. If no lower priority DRQ pin is

asser ted, the PCnet-ISA II may re-asser t its DRQ pin

after as short as 1.1 µs following DACK deassertion.

The priorities assumed b y the PCnet-ISA II are ordered

DRQ3, DRQ5, DRQ6, DRQ7, with DRQ3 having high-

est priority and DRQ7 having the lowest priority. This

pri ority order ing match es that used by typica l ISA bus

DMA controllers.

This adaptive delay scheme allows for fair bus band-

width sharing when two bus mastering devices, e.g.

two PCnet-ISA II devices, are on an ISA bus. The con-

troller using the higher priority DMA channel cannot

lock out the controller using the lower priority DMA

channel because of the 2.6 µs delay that is inserted

before DRQ reassertion when a lower priority DRQ pin

is asserted. When there is no lower priority DMA

request asserted, the PCnet-ISA II re-requests the bus

immediately, providing optimal performance when

there is no competition for b us access.

Bus Slave Mode

The PCnet- ISA II can be confi gured to be a bus slave

for systems that do not support bus mastering or

require a local memory to tolerate high bus latencies.

In the Bus Sl ave mode, the I/O map of the PCne t-ISA

II is identical to the I/O map when in the Bus Master

mode (see I/O Resources section). Hence, the address

PROM, controller registers, and Reset port are

accessed through I/O cycles on the ISA bus. However,

the initialization block, descriptor rings, and buffers,

which are loc ated in sys tem memor y when in the Bus

Master mode, are located in a local SRAM when in the

Bus Slave mode. The local SRAM can be accessed b y

memory cycles on the ISA bus (Shared Memory archi-

tecture) or by I/O cycle s on th e ISA bus (Programme d

I/O mode).

Address PROM Cycles External PROM

The Add ress PROM is a sma ll (16 bytes) 8-bit PROM

connected to the PCnet-ISA II controller Private Data

Bus (PRDB). The PCnet-ISA II controller will support

only 8-bit ISA I/O bus cycles for the address PROM;

this limitation is transparent to software and does not

preclude 16-bit software I/O accesses. An access cycle

begins with the Permanent Master driving AEN LOW,

driving the addresses v alid, and driving IOR active. The

PCnet-IS A II co ntr ol ler det ect s thi s co mb ina tio n of si g-

nals and arbitrates for the Private Data Bus if neces-

sar y. IOCHRDY is always driven LOW dur ing address

PROM accesses.

When the Private Data Bus becomes available, the

PCnet-ISA II controller drives APCS active, releases

IOCHRDY, turns on the data path from PRD0-7, and

enables the SD0-7 drivers (but not SD8-15). During

this bus cycle, IOCS16 is not driven active. This condi-

tion is maintained until IOR goes inactiv e, at which time

the access cycle ends. Data is removed from SD0-7

within 30 ns.

The PCnet-ISA II controller will perform 8-bit ISA bus

cycle operation for all resources (registers, PROMs,

SRAM) if SBHE has been left unconnected, such as in

the case of an 8-bit system like the PC/XT.

Ethernet Controller Register Cycles

Ethernet controller registers (RAP, RDP, ISACSR) are

naturally 16-bit resources but can be configured to

operate with 8-bit bus cycles provided the proper pro-

tocol is followed. This is programmable by the

EEPROM. This means on a read, the PCnet-ISA II con-

troller will only drive the low byte of the system data

bus; if an odd byte is accessed, it will be swapped

down. The high byte of the system data bus is never

dri ve n by the PCnet-ISA II controll er under th ese con-

ditions. On a write, the even byte is placed in a holding

augmented with the e v en byte in the holding register to

provide an internal 16-bit wri te. This allows the use of

8-bit I/O bus cycles which are more likely to be compat-

ible with all clones, but requires that both bytes be writ-

ten in immediate succession. This is accomplished

simply by treating the PCnet-ISA II controller controller

registers as 16-bit software resources. The mother-

board will convert the 16-bit accesses done by soft-

ware into two sequential 8-bit accesses, an even-byte

access followed immediately by an odd-byte access.

An access cycle begins with the Permanent Master

driving AEN LOW, dr iving the address valid, and driv-

ing IOR or IOW active. The PC net-IS A II c ontrol le r de-

tects th is co mbin ation of signa ls a nd dr ives I OCHRDY

LOW. IOCS16 will also be driven LOW if 16-bit I/O bus

cycles are enabled. When the register data is ready,

IOCHRDY will be released HIGH. This condition is

maintained until IOR or IOW goes inactive, at which

time the bus cycle ends.

The PCnet-ISA II controller will perform 8-bit ISA bus

cycle operation for all resources (registers, PROMs,

SRAM) if SBHE has been left unconnected, such as in

the case of an 8-bit system like the PC/XT.

RESET Cycles

A read to the reset address causes an PCnet-ISA II

control ler reset. Thi s has the sa me effect as asserting

the RESET pin on the PCnet-ISA+ controller (which

happens on system power up or on a hard boot) except

that the T-MAU is NOT reset. The T-MAU will retain its

link pass/fail state, disregarding the software RESET

command. The subsequent write cycle needed in the

NE2100 LANCE- based family of Ethernet cards is not

required but does not have any harmful effects.

IOCS16 is not asserted in this cycle.

88 Am79C961A

ISA Configuration Register Cycles

The ISA configuration register is accessed by placing

the address of the desired register into the RAP and

reading the IDP. Th e ISACS R bu s cycles are i dentical

to all other PCnet-ISA II controller register bus cycles.

Boot PROM Cycles

The Boot PROM is an 8-bit PROM connected to the

PCnet-IS A II controller P rivate Data Bus ( PRDB), and

can occupy up to 64 Kbytes of address space. In

Shared Me mor y Mode, an exter nal addres s compara-

tor is responsible for asserting BPAM to the PCnet-ISA

II controller. BPAM is intended to be a perfect decode

of the boot PROM address space, i.e. LA17-23, SA16 .

The LA bus must be latched with BALE in order to pro-

vide stable signal for BPAM. REF inactive must be

used by the external logic to gate boot PROM address

decoding. This same logic must assert MEMCS16 to

the ISA bus if 16-bit Boot PROM bus cycles are

desired.

In the Bus Slave mode, boot PR OM cycles can be pro-

grammed to be 8 or 16-bit ISA memory cycles with the

BP_16B bit (PnP 0x42). If the BP_16B bit is set, the

PCnet-ISA II assumes 16-bit ISA memory cycles for

the boot PROM. In this case, the external hardware

responsible for generating BPAM must also generate

MEMCS16. A 16-bit boot PROM bus cycle begins with

the Perma nen t Mas te r d r iv in g the add re ss es valid and

MEMR active. (AEN is not involved in memory cycles).

External hardware would assert BPAM and MEMCS16.

The PCnet-ISA II controller detects this combination of

signals, drives IOCHRDY LOW, and reads two bytes

out of the boot PROM. The data bytes read from the

PROM are driven by the PCnet-ISA II controller onto

SD0-15 and IOCHRDY is released. This condition is

maintained until MEMR goes inactive , at which time the

access cycle ends.

The PCnet-ISA II controller will perform 8-bit ISA bus

cycle operation for all resource (registers, PROMs,

SRAM) if SBHE has been left unconnected, such as in

the case of an 8-bit system like the PC/XT.

The BPCS signal generated by the PCnet-ISA II con-

troller is three 20 MHz clock cycles wide (350 ns).

Including delays, the Boot PROM has 275 ns to

respond to the BPCS signal from the PCnet-ISA II con-

troller. This signal is intended to be connected to the

CS pin on the boot PROM, with the PROM OE pin tied

to ground.

Static RAM Cycles – Shared Memory Architecture

In the Shared Memory Architecture mode, the SRAM is

an 8-bit de vice connected to the PCnet-ISA II controller

Private Bus, and can occupy up to 64 Kbytes of

address space. The SRAM is memory mapped into the

ISA memory space at an address range determined b y

exter nal d ec ode l ogi c. The extern al ad dr es s compara-

tor is responsib le f or asserting SM AM to the PCnet-ISA

II contr oller. S MAM i s int ended to be a p erfect decode

of the SRAM address space, i.e. LA17-23, SA16 for 64

Kbytes of SRAM. The LA signals must be latched by

BALE in order to provide a stable decode for SMAM.

The PCn et-ISA II c ontroller assumes 16 -bit ISA mem-

or y bus cycles for the SRA M, so this same l ogic must

assert MEMCS16 to the ISA bus if 16-bit bus cycles are

to be supported.

A 16-bit SRAM bus cycle begins with the Permanent

Master driving the addresses valid, REF inactive, an d

either MEMR or MEMW active. (AEN is not involved in

memory cycles). External hardware would assert

SMAM and MEMCS16. The PCnet-ISA II controller

detects this combination of signals and initiates the

SRAM ac ce ss.

In a write cycle, the PCnet-ISA II controller stores the

data into an inter nal hol ding register, allowing the ISA

bus cycle to finish normally . The data in the holding reg-

ister will then be written to the SRAM without the need

for ISA bus control. In the event the holding register is

already filled with unwritten SRAM data, the PCnet-ISA

II controller will extend the ISA write cycle by driving

IOCHRDY LOW until the unwritten data is stored in the

SRAM. The current ISA bus cycle will then complete

normally.

In a read cycle, the PCnet-ISA II controller arbitrates for

the Private Bus. If it is unavailable, the PCnet-ISA II

controller drives IOCHRDY LOW. The PCnet-ISA II

controller compares the 16 bits of address on the Sys-

tem Address Bus with that of a data word held in an

internal pre-fetch register.

If the address does not match that of the prefetched

SRAM data, then the PCnet-ISA II controller drives

IOCHRDY LOW and reads two bytes from the SRAM .

The PCnet-ISA II controller then proceeds as though

the addressed data location had been prefetched.

If the internal pr efetch buffer co nta ins the co rrec t data ,

then the pre-fetch buffer data is driven on the System

Data bus. If IOCHRDY was pre viously driven LO W due

to either Private Data Bus arbitration or SRAM access,

then it is released HIGH. The PCnet-ISA II controller

remains in this state until MEMR is de-asserted, at

which ti me th e PCne t-ISA I I con troller perform s a new

prefetch of the SRAM. In this way memory read wait

states can be minimized.

The PCnet-IS A II contro ller perfor ms prefetches of the

SRAM between ISA bus cycles. The SRAM is

prefetched in an incrementing word address fashion.

Prefetched data are inv alidated by any other activity on

the Private Bus, including Shared Memory Writes by

either the ISA bus or the network interface, and also

address and boot PROM reads.

Am79C961A 89

The only way to configure the PCnet-ISA II controller

for 8-bit ISA bus cycles for SR AM accesses is to con-

figure the entire PCnet-ISA II controller to support only

8-bit ISA bus cycles. This is accomplished by leaving

the SBHE pi n di sco nnec te d. The P Cnet- IS A II control-

ler will perform 8-bit ISA bus cycle operation for all

resources (registers, PROMs, SRAM) if SBHE has

nev er been driven active since the last RESET, such as

in the case of an 8-bit system like the PC/XT. In this

case, the external address decode logic must not

assert MEMCS16 to the ISA bus, which will be the case

if MEMC S16 is left un co nnec te d. It is pos si ble to man-

ufacture a dual 8/16 bit PCnet-ISA II controller adapter

card, as the MEMCS16 and SBHE signals do not exist

in the PC/XT environment.

At the memory device level, each SRAM Private Bus

read cycle takes two 50 ns clock periods for a maxi-

mum read access time of 75 ns. The timing looks like

this:

The address and SROE go active within 20 ns of the

clock going HIGH. Data is required to be valid 5 ns

before the end of the second clock cycle. Addr es s an d

SROE have a 0 ns hold time after the end of the second

clock cycle. Note that the PCnet -ISA II cont roll er does

not normally provide a separate SRAM CS signal;

SRAM C S must always be asserted.

SRAM Private Bus write cycles require three 50 ns

clock periods to guarantee non-negative address setup

and hold times with regard to SRWE. The timing is

illustrated as follows:

Addres s and data a re valid 20 ns aft er the ri sing edge

of the fi rst c l ock per iod . S RWE goes ac ti ve 20 ns a fter

the falling edge of the first clock period. SRWE goes

inactive 20 ns after the falling edge of the third clock

peri od. Addr ess and data remain valid unti l the end o f

the third clock period. Rise and fall times are nominally

5 ns. Non-negative setup and hold times for address

and data with respect to SRWE are guaranteed. SRWE

has a pulse width of typically 100 ns, minimum 75 ns.

Static RAM Cycles – Programmed I/O Architecture

In the Programmed I/O Architecture mode, the SRAM

is an 8-bit device connected to the PCnet-ISA II con-

troller Pr ivate Bus, and ca n occupy up to 64 K bytes of

address space. The SRAM is accessed through the

ISACSR0 and ISACSR1 registers which serve as the

SRAM Data por t and SRAM Address pointer, respec-

tively. Since the ISACSRs are used to access the

SRAM, simple I/O accesses (to RAP and IDP) which

are decoded by the PCnet-ISA II are used to access

the SRAM without any external decoding logic.

The RAP and IDP por t s are nat urally 16-bit res ources

and can be accessed with 16-bit ISA I/O cycles if the

IO_MODE bit (PnP 0xF0) is set. As discussed in the

Ethernet Controller Register Cycles section, 8-bit I/O

cycles are also allowed, provided the proper protocol is

followed. This protocol requires that byte accesses

must be pe rformed i n pair s, with the eve n byte acce ss

alway s being followed by associate d odd byte acce ss.

In the Programmed I/O architecture mode, when

accessing the SRAM Data Port in particular

(ISACSR0), the restrictions on byte accesses are

slightly different. Ev en byte accesses (accesses where

A0 = 0, SBHE = 1) ma y be perf ormed to ISACSR0 with-

out any restriction. A corresponding odd byte access

need no t be performe d following the even byte ac cess

as is r equired when accessi ng all other control ler reg-

isters. In fact, odd byte access es (acces ses wher e A0

= 1, SBH E = 1) ma y not be performed to ISACSR0, ex-

cept when they are the result of a software 16-bit

access that are automatically converted to two byte ac-

cesses by motherboard logic.

Since the internal PCnet-ISA II registers are used to

access the S RAM in the Programmed I/O arc hitect ure

mode, the access cycle on the ISA bus is identical to

that described in the Ethernet Controller Register

Cycles section.

To minimize the number of I/O cycles required to

access the SRAM, the PCnet-ISA II auto-increments

the SRAM Address Pointer (ISACSR1) by one or two

following every read or write to the SRAM Data Port

(ISACSR0). If a single byte read or wri te to the SRAM

Data Por t occurs, the SRAM Address Pointer is auto-

matically incremented by 1. If a word read or write to

the SRAM Data Port occurs, the SRAM Address

Point er is autom atically i ncremented by 2. This allows

XTAL1

(20 MHz)

Address

SROE

19364B-18

Static RAM Read Cycle

Address/

Data

SRWE

XTAL1

(20 MHz)

Static 19364B-19

90 Am79C961A

reads and writes to adjacent ascending addresses in

the SRAM to be performed without intervening writes to

the SRAM Address Pointer. Since buffer accesses

comprise a high percentage of all accesses to the

SRAM, and buffer accesses are typ ically perform ed in

adjacent ascending order, the auto-increment of the

SRAM Address Pointer reduces the required ISA bus

cycles significantly.

In addition to the auto-incrementing of the SRAM

Addres s point er, the PC net-IS A II perform s wri te post-

ing on writes to the SRAM and read prefetching on

reads from the SRAM to ma ximize perfor mance i n the

Programmed I/O architecture mode.

Write Posting: When a write cycle to the SRAM Data

Port occurs, the PCnet-ISA II controller stores the data

into an internal holding register, allowing the ISA bus

cycle to finish normally. The data in the holding register

will then be written to the SRAM without the need for

ISA bus control. In the e vent that the holding register is

already filled with unwritten SRAM data, the PCnet-ISA

II controller will extend the ISA write cycle by driving

OCHRDY LOW until the unwri tte n dat a is stored i n th e

SRAM. Once the data is written into the SRAM, the

new write data is store d int o the i nte rnal h old in g re gis -

ter and IOCHRDY is released allowing the ISA bus

cycle to complete.

Read Prefetching: To gain performance on read

accesses to the SRAM, the PCnet-ISA II performs

prefetches of the SRAM after every read from the

SRAM Data Por t. T he prefetch is p erfo rm ed using the

speculated address that results from the auto-incre-

ment that occurs on the SRAM Address Pointer follow-

ing every access to the SRAM Data Port. Following

every read access, the 16-bit word following the

just-r ead SRA M byte or word is prefetched an d pla ce d

in a holding register. If a word read from the SRAM

Data Por t oc curs before a “prefetch invalid ation event ”

occurs, the prefetched word is driven onto the SD[15:0]

pins without a wait state (no IOCHRDY LOW asser-

tion). A “prefetch invalidation event” is defined as any

activity on the Private Bus other than SRAM reads.

This includes SRAM writes by either the ISA bus or the

network interface , address or boot PROM reads, or any

write to the SRAM Address Pointer.

The PCnet-ISA II interface to the SRAM in the Pro-

grammed I/O architecture mode is identical to that in

the Shared Memory Architecture mode. Hence, the

SRAM Read and Write cycle descriptions and dia-

grams shown in the “Static RAM Cycles – Shared

Memory Architecture” section apply.

Transmit Operation

The transmit operation and features of the PCnet-ISA

II controller are controlled by programmable options.

Transmit Function Programming

Automat ic tran sm it featur es, suc h as retry on co ll is ion ,

FCS generation/transmission, and pad field insertion,

can all be programmed to provide flexibility in the

(re-)transmission of messages.

Disable retry on collision (DRTY) is controlled by the

DRTY bit of the Mode register (CSR15) in the initializa-

tion block.

Automatic pad field insertion is controlled by the

APAD_XMT bit in CSR4. If APAD_XMT is set, auto-

matic pad field insertion is enabled, the DXMTFCS fea-

ture is ov er-ridden, and the 4-byte FCS will be added to

the trans mit ted fram e unc on ditionally. If APAD_X MT is

cleared, n o pad field i nser tion will take pla ce and run t

packet transmission is possible.

The disable FCS generation/transmission feature can

be programmed dynamically on a frame by frame

basis. See the ADD_FCS description of TMD 1.

Transmit FIFO Watermark (XMTFW in CSR80) sets

the point a t which th e BMU (Buffer Manageme nt Unit)

requests more data from the transmit buffers for the

FIFO. This point is based upon how many 16-bit bus

transfers (2 bytes) could be performed to the existing

empty space in the transmit FIFO.

Transmi t S tart Point (XMT SP i n CSR80) s ets the poin t

when the transmitter actually tries to go out on the

media. This point is based upon the number of bytes

written to the transmit FIFO for the current frame.

When the entire frame is in the FIFO , attempts at trans-

mission of preamble will commence regardless of the

value in XMTSP. The default value of XMTSP is 10b,

meaning 64 bytes full.

Automatic Pad Generation

Transmit frames can be automatically padded to ex-

tend them to 64 data bytes (excl uding preamble). This

allows the minimum frame size of 64 bytes (512 bits)

for 802.3/Ethernet to be guaranteed with no software

inter vention from the host/controlling process. Setting

the APAD_XMT bit in CSR4 enables the automatic

padding feature. The pad is placed between the LLC

data fie ld and FCS field in the 802.3 frame. FCS is al-

ways added if the frame is padded, regardless of the

state of DXMTFCS. The transmit frame will be padded

by bytes with the value of 00h. The default value of

APAD_XMT is 0, and this will disable auto pad genera-

tion after RESET.

It is the responsibility of upper layer software to cor-

rectly define the actual length field contained in the

message to correspond to the total number of LLC

Data bytes en capsula ted in th e packet (length fie ld as

define d in the IEEE 802.3 stan dard). The len gth value

contained in the message is not used by the PCnet-ISA

II controller to compute the actual number of pad b ytes

Am79C961A 91

to be ins erted. Th e P Cnet -ISA II c on tr oller wi ll ap pen d

pad bytes dependent on the actual number of bits

transmitted onto the network. Once the last data byte of

the frame has completed pr ior to appending the FCS,

the PCnet-ISA II controller will check to ensure that 544

bits have been transmitted. If not, pad bytes are added

to extend the frame size to this va lue, and the FCS is

then added.

The 544 bit count is derived from the following:

Minimum frame size (excluding preamble,

including FCS) 64 bytes 512 bits

Preamble/SFD size 8 bytes 64 bits

FCS size 4 bytes 32 bits

To be classed as a minimum-size frame at the receiver ,

the transmitted frame must contain:

Preamble + (Min Frame Size + FCS) bits

At the point that FCS is to be appended, the transmitted

frame should contain:

Preamble + (Min Frame Size - FCS) bits

64+ (512- 32) bits

A minimum-le ngth transmit frame from the PCnet-ISA

II control ler will, ther efore, be 576 bits after the FCS is

appended.

Transmit FCS Generation

Automatic generation and transmission of FCS for a

transmit frame dep ends on the value of DXMT FCS bit

in CSR15. When DXMTFCS = 0 the transmitter will

generate and append the FCS to the transmitted frame.

If the automatic padding feature is invoked

(APAD_XMT is SET in CSR4), the FCS will be

append ed by the PCn et-ISA II c ontroller regardle ss of

the st ate of DXM TFCS . No te that th e calcula ted FCS is

transmitted most-significant bit first. The default value

of DX MTFCS is 0 after RESET.

Transmit Exception Conditions

Exception conditions for frame transmission fall into

two distinct categories; those which are the result of

nor mal networ k opera tion, and tho se which o ccur due

to abnormal network and/or host related events.

Normal e vents which ma y occur and which are handled

autonomously by the PCnet-ISA II controlle r are basi-

cally co ll is ion s with in the slot time w ith automa tic retry.

The PCnet-ISA II controller will ensure that collisions

which occur within 512 bit times from the start of trans-

mission (including preamble) will be automatically

retried with no host interv ention. The transmit FIFO en-

sures this by guaranteeing that data contained within

the FIFO will not be overwr itten until at least 64 bytes

(512 bits) of data have been successfully transmitted

onto the network.

If 16 total attempts (initial attempt plus 15 retries) fail,

the PCnet-ISA II controller sets the R TR Y bit in the cur-

rent transmit TDTE in host memory (TMD2), gives up

ownership (sets the OWN bit to zero) for this packet,

and processes the next packet in the transmit ring for

transmission.

ISO 8802-3 (IEEE/ANSI 802.3) Data Frame

Preamble

1010....1010 SYNC

10101011 Dest.

ADDR SRCE.

ADDR. Length LLC

Data Pad FCS

Bits 8

Bits 6

Bytes 6

Bytes 2

Bytes

46-1500

Bytes

19364B-20

92 Am79C961A

Abnormal network conditions include:

■Loss of carrier

■Late collision

■SQE Test Error (Does not apply to 10BASE-T port.)

These should not occur on a correctly configured 802.3

network, and will be reported if they do.

When an error occurs in the middle of a multi-buffer

frame transmission, the error status will be written in

the current descriptor. The OWN bit(s) in the subse-

quent descriptor(s) will be reset until the STP (the next

frame) is found.

Loss of Carrier

A loss of carrier condition will be repor ted if the PC-

net-ISA II controller cannot observe receive activity

while it is transmitting on the AUI port. After the PC-

net-ISA II controller initiates a transmission, it will ex-

pect to see data “looped back” on the DI± pair . This will

internally generate a “carrier sens e ,” indicating that the

integrity of the data path to and from the MAU is intact,

and that the MAU is operating correctly. This “carrier

sense” signal must be asser ted before the end of the

transmission. If “carri er sense” does not become active

in response to the data transmission, or becomes inac-

tive before the end of transmission, th e loss of carrier

(LCAR) error bit will be set in TMD2 after the frame has

been transm itted. T he frame wi ll not be re-tr ied o n the

basis of an LC AR e rror. In 10BASE-T mo de LC AR wi ll

indicate that Jabber or Link Fail state has occurred.

Late Collision

A late collision will be reported if a collision condition

occurs after one slot time (512 bit times) after the trans-

mit process was initiated (first bit of preamble com-

menced) . The PCnet-ISA II c ont ro ller wil l aba ndo n th e

transmit pr oce ss for the particula r fram e, set Late Co l-

lision (LCOL) in the associated TMD3, and process the

next transmit frame in the r ing. Frame s experiencin g a

late collision will not be re-tried. Recovery from this

condition must be performed by upper-layer software.

SQE Test Error

Duri ng the inter packet gap time foll owing the comple -

tion of a transmitted message, the AUI CI± pair is

asserted by some transceivers as a self-test. The inte-

gral Manchester Encoder/Decoder will expect the SQE

Test Message (nominal 10 MHz sequence) to be

returned via the CI± pair within a 40 network bit time

period after DI± pair goes inactive. If the CI± inputs are

not asser ted within the 40 networ k bit time period fol-

lowing the completion of transmission, then the PC-

net-ISA II controller will set the CERR bit in CSR0.

CERR will be asserted in 10BASE-T mode after trans-

mit if T-MAU is in Link F ail state. CERR will nev er cause

INTR to be activated. It will, how ev er , set the ERR bit in

CSR0.

Host related transmit exception conditions include

BUFF and UFLO as described in the Transmit Descrip-

tor section.

Receive Opera tio n

The receive operation and features of the PCnet-ISA II

controller are controlled by programmable options.

Receive Function Programming

Automatic pad field stripping is enabled by setting the

ASTRP_RCV bit in CSR4; this can provide flexibility in

the reception of messages using the 802.3 frame format.

All receive frames can be accepted by setting the

PROM bit in CSR15. When PROM is set, the PC-

net-ISA II controller will attempt to receive all mes-

sages, subject to minimum frame enforcement.

Promis cuous mode overri des the effect of the Di sabl e

Receive Broadcast bit on receiving broadcast frames.

The point at which the BMU will start to transfer data

from the receive FIFO to buff er memory is controlled by

the RCVFW bits in CSR80. The default established

duri ng reset is 10b, which sets the thr es hold flag at 64

bytes empty.

Automatic Pad Stripping

During reception of an 802.3 frame the pad field can be

stripped automatically . ASTRP_RCV (bit 10 in CSR4) =

1 enables the automatic pad stripping f eature. The pad

field wi ll be str ipped befo re the frame is pas sed to th e

FIFO, thus preserving FIFO space for additional

frames. The FCS field will also be stripped, since it is

computed at the transmitting station based on the data

and pad field characters, and will be invalid for a

receive frame that has had the pad characters stripped.

The number of bytes to be s tripped is calculated f rom

the embedded length field (as defined in the IEEE

802.3 definition) contained in the frame. The length

indicates the actual number of LLC data bytes con-

tained in the message. Any received frame which con-

tains a length field less than 46 bytes will have the pad

field stripped (if ASTRP_RCV is set). Receive frames

which have a length fie ld of 4 6 bytes or gre ater w ill be

passed to the host unmodified.

Since any valid Ethernet Type field v alue will alwa ys be

greater than a normal 802.3 Length field (≥46), the PC-

net-ISA II controller will not attempt to strip valid Ether-

net frames.

Note that for some n etwork pro tocols the value passed

in the Ethernet Type and/or 802.3 Length field is not

compliant with either standard and may cause problems.

The diagram below shows the byte/bit ordering o f the

received length field for an 802.3 compatible frame

format.

Am79C961A 93

IEEE/ANSI 802.3 Frame and Length Field Transmission Order

Receive FCS Checking

Reception and checking of the received FCS is per-

formed automatically by the PCnet-ISA II controller.

Note that if the Automatic Pad Stripping feature is

enabled, the received FCS will be verified against the

value computed for the incoming bit stream including

pad characte rs, but it will not b e passed to the hos t. If

a FCS error is detected, this will be repor ted by the

CRC bit in RMD1.

Receive Exception Conditions

Exception conditions for frame reception fall into two

distinct categories; those which are the result of normal

network operation, and those which occur due to

abnormal network and/or host related events.

Normal e vents which ma y occur and which are handled

autonomously by the PCnet-ISA II controller are basi-

cally collisions within the slot time and automatic runt

packet rejection. The PCnet-ISA II controller will ensure

that collisions which occur within 512 bit times from the

start of reception (excluding preamb le) will be automat-

ically deleted from the rec ei ve FIFO with no ho st i nter -

ve ntion. Th e receive FIFO will del ete any frame whic h

is composed of fewer than 64 bytes provided that the

Runt Packet Accept (RPA bit in CSR124) feature has

not been enabled. This criteria will be met regardless of

whether th e r eceive frame was th e fi rst ( or o nly ) frame

in the FIF O or i f th e r ec eive frame was que ued beh ind

a previously received message.

Abnormal network conditions include:

■FCS er rors

■Late collision

These should not occur on a correctly configured 802.3

network and will be reported if they do.

Host related receive exception conditions include

MISS, BUFF, and OFLO. These are described in the

Receive Descriptor section.

Loopback Operation

Loopback is a mode of operation intended for system

diagnos tics. In this m ode, the transmitter an d receiver

are both operating at the same time so that the

control ler receives its own transmis sions. The con trol-

ler provides two types of internal loopback and three

types of extern al loop back. In inter nal loopback mode,

the transmitted data can be looped back to the receiver

at one of two places inside t he cont roll er withou t actu-

ally transm itting any data to the exter nal networ k. The

receiver will mov e the received data to the next receive

buffer, where it can be ex amin ed by software. Alterna-

tively, external loopback causes transmissions to go

off-chip. For the AUI port, frame transmission occurs

normally and assumes that an external MAU will loop

the frame back to the chip. F or the 10BASE-T port, two

exte rnal loopback options a re available, both of whi ch

requir e a valid link pass sta te an d both of whic h trans-

mit data frames at the RJ45 interface. Selection of

these modes is defined by the TMAU_LOOPE bit in

ISACSR2. One option loops the data frame back inside

the chip, and is compatible with a ‘live’ network. The

Preamble

1010....1010 SYNCH

10101011 Dest.

ADDR. Srce.

ADDR. Length LLC

DATA Pad FCS

Bits 8

Bits 6

Bytes 6

Bytes 2

Bytes

Bytes 4

Bytes

Most

Significant

Byte

Least

Significant

Byte

Bit

0Bit

Start of Packet

at T ime= 0

Increasing T ime

Bit

7Bit

45–0

Bytes

1–1500

Bytes

19364B-21

94 Am79C961A

other option requires an external device (such as a

‘loopback plug’) to loop the data back to the chip, a

function normally not available on a 10BASE-T

network.

The PCnet-ISA II chip has two dedicated FCS genera-

tors, eliminating the traditional LANCE limitations on

loopba ck FCS operation. The re ceive FCS genera tion

logic is always enabled. The transmit FCS generation

logic can be disabled (to emulate LANCE type loop-

back operation) by setting the DXMTFCS bit in the

Mode regis ter (CSR1 5). In this co nfiguration , software

must generate the FCS and append the four FCS bytes

to the transmit frame data.

The loopback facilities of the MAC Engine allow full

operation to b e verified witho ut dist urban ce to the n et-

work. Loopback opera tion i s al so af fe cte d by the stat e

of the Loopback Control bits (LOOP, MENDECL, and

INTL) in CSR15. This affects whether the internal

MENDEC is cons id er ed p art of the int ernal or external

loop- backpath.

The receive FCS generation logic in the PCnet-ISA II

chip is used for multicast address detection. Since this

FCS logic is always enabled, there are no restrictions

to the use of multicast addressing while in loopback

mode.

When performing an internal loopback, no frame will be

transmitted to the network. However, when the PC-

net-ISA II control ler is configur ed fo r inter nal loop back

the receiver will not be able to detect network traffic.

External loopback tests will transmit frames onto the

network if the AUI por t is s elec ted, and the PCne t-ISA

II controller will receive network traffic while configured

for external loopback when the AUI por t is selected.

Runt Pac k et Accept is automatically enabled when any

loopback mode is invoked.

Loopback mode can be performed with any frame size.

Runt Packet Accept is internally enabled (RPA bit in

CSR124 is not affected) when any loopback mode is

invoked. This is to be backwards compatible to the

LANCE (Am7990 ) sof tware.

LEDs

The PCnet-ISA II controller’s LED control logic allows

programming of the status signals, which are display ed

on 3 LED outputs. One LED (LED0) is dedicated to dis-

playing 10BASE-T Link Status. The status signals

av ailable are Collision, Jabber , Receive, Receive P olar-

ity, Trans mit, Receive Addres s Match, and Full Duplex

Link Stat us. If more than one status signa l is enabled,

they are ORed together. An opt ional puls e stretcher is

available for each programmable output. This allows

emulation of the TPEX (Am79C98) and TPEX+

(Am79C100) LED outputs.

Each status signal is ANDed with its corresponding

enable signal. The enabled status signals run to a com-

mon OR gate:

The output from the OR gate is run through a pulse

stretcher, which consists of a 3-bit shift register clock ed

at 38 Hz. The da ta input of the s hift register is at logic

0. The OR gate output asynchronously sets all three

bits of the shift register when its output goes active. The

output of the shift register controls the associated LEDx

pin. Th us, the pulse stretc her provides an LE D output

of 52 ms to 78 ms.

Signal Behavior

COL Active during collision activit y on the net work

FDLS Active when Fu ll Du plex ope ra tio n is en abled

and functioning on the selected network port

JAB Active when the PC net- ISA II is jabb ering on

the network

LNKST Active during Link OK Not active during Link

Down

RCV Active while receiving da ta

RVPOL Activ e during receiv e polarity is O K Not activ e

during reverse receive polarity

RCVADDM Active during Receive with Address Match

XMT Active while transmitting data

AND

FDLS

FDLSE

AND

RCVM

RCVM E

AND

XMT

XMT E

AND

RVPOL

RVPOL E

AND

RCV

RCV E

AND

JAB

JAB E

AND

COL

COL E

OR To

Pulse

Stretcher

AND

RCVADDM

RCVADDE

19364B-22

LED Control Logic

Am79C961A 95

Refer to the section “IS A B us Configuration Registers ”

for information on LED control via the ISACSRs.

MAGIC PACKET OPERATION

In the Magic P ack et mode, PCnet-ISA II completes any

transmit and re ce ive operations in pro gress, susp e nds

normal activity, and enters into a state where only a

Magic Pac ket could be detected. A Magic P ack et frame

is a frame that contains a data sequence which repeats

the Physical Address (PADR[47:00]) at least sixteen

times frame sequentially, with bit[00] received first. In

Magic Pac ket suspend mode, the PCnet-ISA II remains

powered up. Slave accesses to the PCnet-ISA II are

still possible, the same as any other mode. All of the

rec eiv ed pac ke ts are fl ushed from th e recei ve FI FO . An

LED and/or interr upt pin could b e activated, indica ting

the receive of a Magic Packet frame. This indication

could be used for a variety of management tasks.

Magic Packet Mode Activation

This m ode c an b e e nabled by either s oft ware or exter-

nal hardware means, but in either case, the MP_MODE

bit (CSR5, bit 1) must be set first.

Hardware Activation. This is done by driving the

SLEEP pin low. Deasserti ng the SLE EP pin wil l return

the PCnet-ISA II to normal operation.

Software Activation. This is done by setting the

MP_ENBL bit (CSR5, bit 2). Resetting this bit will return

the PCnet-ISA II to normal operation.

Magic Packet Receive Indicators

The reception of a Magic Packet can be indicated either

through one of the LEDs 1, 2 or 3, and/or the activation

of the i nterrupt p in. MP_INT bi t (CSR5, bit 4 ) will als o

be set upon the receive of the Magic Packet.

LED Indication. Either one of the LEDs 1, 2, or 3 could

be activated by the receive of the Magic Packet. The

“Magic Packet e nable” bi t (bi t 9 ) in th e IS ACSR 5, 6 or

7 should be set to enable this feature. Note that the

polarity of the LED2 could be controlled by the

LEDXOR bit (ISACSR6, bit 14). The LED could be

deactivated by setting the STOP bit or resetting the

MP_ENBL bit (CSR5, bit 2).

Interrupt Indication. Interrupt pin could be activated

by the receive of the Magic Pac ket. The MP_I_ENBL bit

(CSR5, bit 3) and IENA bit (CSR0, bit 6) should be set

to enable this feature.

Bit Name Description

1 MP_MODE Magic Packet Mode.

Setting this bit is a prerequisite

for entering the Magic Packet

mode. It also redefines the

SLEEP pin to be a Magic Packet

enable pin. Read/Write accessi-

ble always. It is cleared by as-

serting the RESET pin, or read-

ing the RESET register.

2 MP_ENBL Magic Packet Enable.

This bit when set, will force the

PCnet-ISA II into the Magic

Packet mode. Read/Write ac-

cessible always. It is cleared by

asserting the RESET pin or

reading the RESET register.

3 MP_I_ENBL Magic Packet Interrupt Enable.

Acts as an unmask bit for the

MP_INT (CSR5, bit 4). Read/

Write accessible always. It is

cleare d by as se rt ing the RE SE T

pin or readi ng the RES ET regis-

ter, or setting the STOP bit.

4 MP_INT Magic Packet Receive Interrupt.

Wil l be set when a Magic Pa cket

has been received. Writing a

“one” will clear this bit. It is

cleare d by as se rt ing the RE SE T

pin, or reading the RESET regis-

ter.

9 MP Magic Packet LED Enable.

When set, the LED output will be

asserted to indicate that a Magic

Packet has been received.

96 Am79C961A

PCNET-ISA II CONTRO LLER REGISTERS

The PCnet-ISA II controller implements all LANCE

(Am7990 ) regis ters, plus a number of ad dition al re gis-

ters. The PCnet-ISA II con tr oll er r eg is ters a re co mp at-

ible with the original LANCE, but there are some places

where previously reserved LANCE bits are now used

by the PCnet-ISA II controller. If the reserved LANCE

bits were used as recommended, there should be no

compatibility problems.

Regist er Ac ce ss

Internal registers are accessed in a two-step operation.

First, the address of the register to be accessed is writ-

ten into the register address port (RAP). Subsequent

read or write operations will access the register pointed

to by the contents of the RAP. The data will be read

from (or written to) the selected register through the

data port, either the register data port (RDP) for control

and status registers (CSR) or the ISACSR register data

port (IDP) for ISA control and status registers

(ISACSR).

RAP: Register Address Port

Bit Name Description

15-7 RES Reserved locations. Read and

written as zeroes.

6-0 RAP Register Address Port select.

Selects the CSR or ISACSR

loca tion to be accessed. RAP is

cleared by RESET.

Control and Status Registers

CSR0: PCnet-ISA II Controller Status Register

Bit Name Description

15 ERR Error is set by the ORing of

BABL, CERR, MISS, and

MERR. ERR remains set as long

as any of the error flags are true.

ERR is read only; write opera-

tions are ignored.

14 BABL Babble is a transmitter time-out

error. It indicates that the trans-

mitter has been on the channel

longer than the time required to

send the maximum length

frame. BABL will be set if 1519

bytes or greater are transmitted.

When BABL is set, IRQ is as-

serted if IE NA = 1 and the ma sk

bit BABLM (CSR3.14) is clear.

BABL ass er ti on wi ll se t the E RR

bit.

BABL is set by the MAC layer

and cleared by writing a “1".

Writing a “0" has no effect. BABL

is cleared by RESET or by set-

ting the STOP bit.

13 CERR Collision Error indicates that the

collision inputs to the AUI port

failed to activate within 20 net-

work b it times after the chip ter -

minated transmission (SQE

Test). This feature is a transceiv-

er test featu re. CERR will be set

in 10BASE-T mode during

transmit if in Link Fail state.

CERR assertion will not result in

an interrupt being generated.

CERR assertion will set the ERR

bit.

CERR is set by the MAC layer

and cleared by writing a “1".

Writing a “0" has no effect.

CERR is cleared by RESET or

by setting the STOP bit.

12 MISS Missed Frame is set when PC-

net-ISA II controller has lost an

incoming receive frame because

a Receive Descriptor was not

available. This bit is the only in-

dication that receive data has

been lost since there is no re-

ceive descriptor available for

status information.

When MISS is set, IRQ is

asserted if IENA = 1 and the

mask bit MISSM (CSR3.12) is

clear . MISS as sertion will set t he

ERR bit.

MISS is set by the Buffer Man-

agement Unit and cleared by writ-

ing a “1". Writing a “0" has no

effect. MISS is cleared by RESET

or by setting the STOP bit.

11 MERR Memory Error is set when PC-

net-ISA II controller is a bus

master and has not received

DACK assertion after 50 µs after

DRQ assertion. Memory Error

indicates that PCnet-ISA II con-

troller is not receiving bus mas-

tership in time to prevent over-

flow/underflow conditions in the

receive and transmit FIFOs.

(MERR indicates a slightly differ-

ent con dition fo r the LANCE; for

the LANCE MERR occurs when

READY has not been asserted

25.6 µs after the address has

been asserted.)

When MERR is set, IRQ is as-

serted if IE NA = 1 and the ma sk

bit MERRM (CSR3.11) is clear.

MERR assertion will set the

ERR bit.

Am79C961A 97

MERR is set by the Bus Inter-

face Unit and cleared by writing

a “1". Writing a “0" has no effect.

MERR is cleared by RESET or

by setting the STOP bit.

10 RINT Receive Interr upt is set aft er re-

ception of a receive frame and

toggling of the OWN bit in the

last buffer in the Receive

Descriptor Ring.

When RINT is set , IRQ is assert-

ed if IENA = 1 and the mask bit

RINTM (CSR3.10) is clear.

RINT is set by the Buffer Man-

agement Unit after the last

receive buffer has been updated

and cleared by writing a “1".

Writing a “0" has no effect. RINT

is cleared by RESET or by

setting the STOP bit.

9 TINT Transmit Interrupt is set after

transmiss i on of a trans mi t fr am e

and toggling of the OWN bit in

the last buffer in the Transmit

Descriptor Ring.

When TINT is set, IRQ is

asserted if IENA = 1 and the

mask bit TINTM (CSR3.9) is

clear.

TINT is set by the Buffer Man-

agement Unit after the last trans-

mit buffer has been updated and

cleared by writing a “1". Writing a

“0" has no effect. TINT is cleared

by RESET or by setting the

STOP bit.

8 IDON Initialization Done indicates that

the initialization sequence has

completed. When IDON is set,

PCnet-IS A II control ler has rea d

the Initialization block from

memory.

When IDON is set, IRQ is assert-

ed if IENA = 1 and the mask bit

IDONM (CSR3.8) is clear.

IDON is set by the Buffer Man-

agement Unit after the initializa-

tion block has been read from

memory and cleared by writing a

“1". Writing a “0" has no effect.

IDON is cleared by RESET or by

setting the STOP bit.

7 INTR Interrupt Flag ind icates that one

or more of the following interrupt

causing conditions has

occurred: BABL, MISS, MERR,

MPCO, RCVCCO, RINT, TINT,

IDON, JAB or TXSTRT; and its

associated mask bit is clear. If

IENA = 1 and INTR is set, IRQ

will be act iv e.

INTR is cleared automatically

when the condition that caused

interr upt is clea red.

INTR is read only. INTR is

cleared by RESET or by setting

the STOP bit.

6 IENA Interrupt Enable allows IRQ to

be active if the Interrupt Flag is

set. If IENA = “0" then IRQ will be

disabled regardless of the state

of INTR.

IENA is set by writing a “1" and

cleared by writi ng a “0". IENA is

cleared by RESET or by setting

the STOP bit.

5 RXON Receive On indicates that the

Receive function is enabled.

RXON is set if DRX (CSR15.0) =

“0" after the START bit is set. If

INIT and START ar e set togeth-

er, RXON will not be set until

after the initialization block has

been read in.

RXON is read only. RXON is

cleared by RESET or by setting

the STOP bit.

4 TXON Transmit On indicates that the

Transmit function is enabled.

TXON is set if DT X (CSR1 5.1 ) =

“0" after the START bit is set. If

INIT and START ar e set togeth-

er, TXON will not be set until

after the initialization block has

been read in.

TXON is read only. TXON is

cleared by RESET or by setting

the STOP bit.

3 TDMD Transmit Demand, when set,

causes the Buffer Management

Unit to access the Transmit

Descriptor Ring without waiting

for the poll-time counter to

elapse. If TXON is not enabled,

TDMD bit will be reset and no

Transmit Descriptor Ring access

will occur. TDMD is required to

be set if the DPOLL bi t in CSR4

is set; setting TDMD while

DPOLL = 0 merely hastens the

PCnet-ISA II controller’s re-

sponse to a Tran smit D escr iptor

Ring Entry.

TDMD is set by writing a “1".

Writing a “0" has no effect.

TDMD will be cleared by the

Buffer Management Unit when it

fetches a Transmit Descriptor.

98 Am79C961A

TDMD is cleared by RESET or

by setting the STOP bit.

2 STOP STOP assertion disables the

chip from all external activity.

The chip remains inactive until

either STRT or INIT are set. If

STOP, STRT and INIT are all set

together, STOP will override

STRT and INIT.

STOP is set by writing a “1" or by

RESET. Writi ng a “0" has no ef-

fect. STOP is cleared by setting

either STRT or INIT.

1 STRT STRT assertion enables PCnet-

ISA II controller to send and

receive frames, and perform

buffer management operations.

Setting STRT clears the STOP

bit. If STRT a nd INIT are set to-

gether, PCnet-ISA II controller

initialization will be performed

first.

STRT is set by writing a “1". Writ-

ing a “0" has no effect. STRT is

cleared by RESET or by settin g

the STOP bit.

0 INIT INIT assertion enables PC-

net-ISA II c ontroller to begin the

initialization procedure which

reads in the initialization block

from memory. Setting INIT

clears the STOP bit. If STRT and

INIT are set together, PCnet-ISA

II controller initialization will be

performed first. INIT is not

cleared when the initialization

sequence has completed.

INIT is set by w riting a “1". W rit-

ing a “0" has no effect. INIT is

cleared by RESET or by settin g

the STOP bit.

CSR1: IADR[15:0]

Bit Name Description

15-0 IADR [15:0] Lower address of the Initializa-

tion address register. Bit location

0 must be zero. Whenever this

updated with CSR1’s conten ts.

Read/Write accessible only

when the STOP or SPND bits

are set. Unaffected by RESET.

CSR2: IADR[23:16]

Bit Name Description

15-8 RES Reserved locations. Read and

written as zero.

7-0 IADR [23:16] Upper 8 bits of the address of

the Initialization Block. Bit loca-

tions 15-8 must be written with

zeros. Whenever this register is

written, CSR17 is updated with

CSR2’s contents.

Read/Write accessible only

when the STOP or SPND bits

are set. Unaffected by RESET.

CSR3: Interrupt Masks and Deferral Control

Bit Name Description

15 RES Reserved location. Written as

zero and read as undefined.

14 BABLM Babble Mask. If BABLM is set,

the BABL bit in CSR0 will be

masked and will not set INTR

flag in CSR0.

BABLM is cleared by RESET

and is not affected by STOP.

13 RES Reserved location. Written as

zero and read as undefined.

12 MISSM Missed Frame Mask. If MISSM

is set, the MISS bit in CSR0 will

be masked and will not set INTR

flag in CSR0.

MISSM is cleared by RESET

and is not affected by STOP.

11 MERRM Memory Error Mask. If MERRM

is set, the MERR bit in CSR0 will

be masked and will not set INTR

flag in CSR0.

MERRM is cleared by RESET

and is not affected by STOP.

10 RINTM Receive Interrupt Mask. If

RINTM is set, the RINT bit in

CSR0 will be masked and will

not set INTR flag in CSR0.

RINTM is cleared by RESET

and is not affected by STOP.

9 TINTM Transmit Interrupt Mask. If

TINTM is set, the TINT bit in

CSR0 will be masked and will

not set INTR flag in CSR0.

TINTM is cleared by RESET and

is not affected by STOP.

8 IDONM Initialization Done Mask. If

IDONM is set, the IDON bit in

CSR0 will be masked and will

not set INTR flag in CSR0.

IDONM is cleared by RESET

and is not affected by STOP.

7 RES Reserved locations. Written as

zero and read as undefined.

6 DXSUFLO Disable Transmit Stop on

Underflow error.

Am79C961A 99

When DXSU FLO is set to ZERO,

the transmitter is turned off when

an UFLO error occurs (CSR0,

TXON = 0).

When DXSUFLO is set to ONE,

the PCnet-ISA II controller

gracefully recovers from an

UFLO error. It scans the transmit

descriptor ring until it finds the

start of a new frame and starts a

new transmission.

Read/Write accessible always.

DXSUFLO is cleared by asserting

the RESET pin or reading the

Reset register and is not affected

by STOP.

5 LAPPEN Look Ahead Packet Processing

(LAPPEN). When set to a one,

the LAPPEN bit will cause the

PCnet-IS A II c on troll er to ge ner-

ate an interrupt following the

descriptor write operation to the

first buffer of a receive packet.

This interrupt will be generated

in additio n to the i nter rupt that is

generate d following the des crip-

tor write operation to the last

buffer of a receive packet. The

interrupt will be signaled through

the RINT bit of CSR0.

Setting LAPPEN to a one also

enables the PCnet-ISA II con-

troller to read the STP bit of the

receive descriptors. PCnet-ISA

II controller will use STP infor-

mation to determine where it

should begin writing a receive

packet’s da ta. Note that while in

this mode, the PCnet-ISA II con-

troller can write intermediate

packet data to buffers whose

descriptors do not contain STP

bits set to one. Following the

write to the last descriptor used

by a packet, the PCnet-ISA II

controller will scan through the

next descriptor entries to locate

the next STP bit that is set to a

one. The P Cnet- ISA II con troller

will begin writing the next pack-

et’s data to the b uffer poin ted to

by that descriptor.

Note that because several

descripto rs may be allocated by

the host for each packet, and not

all messages may need all of the

descriptors that are allocated

between descriptors that contain

STP = one, then some descrip-

tors/buffers may be skipped in

the ring. While performing the

search for the next STP bit that

is set to one, the PCnet-ISA II

controller will advance through

the receive descriptor ring

regardless of the state of owner-

ship bits. If any of the entries that

are exam in ed du ring t his s ear ch

indicate OWN = one, PCnet-ISA

II will RESET the OWN bit to

zero in these entries. If a

scanned entry indicates host

ownership with STP=“0", then

the PCnet-ISA II controller will

not alter the entry, but will

advance to the next entry.

When the S TP bit is found to b e

true, but the de scrip tor that con-

tains this setting is not owned by

the PC net-ISA II contr oller, the n

the PCnet-ISA II controller will

stop advancing through the ring

entries and begin periodic poll-

ing of this entry. When the STP

bit is found to be true, and the

descr iptor that c ontains th is set-

ting is owned by the PCnet-ISA II

controller, then the PCnet-ISA II

controller will stop advancing

through the ring entries, store

the descri ptor i nformation tha t is

has just read, and wait for the

next receive to arrive.

This behavior allows the host

software to pre-assign buffer

space in such a man ner that the

“header” portion of a receive

packet will always be written to a

particula r mem ory are a, and th e

“data” portion of a receive pack-

et will always be written to a sep-

arate memory area. The inter-

rupt is generated when the

“header” bytes have been writ-

ten to the “header” memory

area.

Read/Write accessible always.

The LAPPEN bit will be reset

zero by RESET and will

unaffected by the STOP. See

Appendix E for more information

on LAPP.

4 DXMT2PD Disable Transmit Two Part

Deferral. (Described in the

Media Access Management

section). If DXMT2PD is set,

Transmit Two Part Deferral will

be disabled.

DXMT2PD is cleared by RESET

and is not affected by STOP.

3 EMBA Enable Modified Back-off Algo-

rithm. If EMBA is set, a modified

100 Am79C961A

back-off algorithm is

implemented as described in the

Media Access Management

section.

Read/Write accessible. EMBA is

cleared by RESET and is not

affected by STOP.

2-0 RES Reserved locations. Written as

zero and read as undefined.

CSR4: Test and Features Control

Bit Name Description

15 ENTST Enable Test Mode operation.

When ENTST is set, writing to

test mode registers CSR124 and

CSR126 is allowed, and other

enabled. In order to set ENTST, it

must be written with a “1" during

the first write access to CSR4

after RESET. Once a “0" is writ-

ten to this bit location, ENTST

cannot be set until after the PC-

net-ISA II controller is reset.

ENTST is cleared by RESET.

14 DMAPLUS When DMAPLUS = “1", the burst

transaction counter in CSR80 is

disabled. If DMAPLUS = “0", the

burst transaction counter is

enabled.

Caution: When u sing DMAP LUS

AND/OR TIMER bits in a PC

environment, care must be taken

not to ho ld the b us fo r mo re than

the r eq ui r ed ref resh time.

DMAPLUS i s clear ed by RESE T.

13 TIMER Timer Enable Register. If TIMER

is set, the Bus Activity Timer reg-

ister (CSR82) is enabled and the

PCnet-ISA II may perform any

combina tion of ac cesses (buf fer

reads, buffer writes, descriptor

reads, and descriptor writes)

during a single bus mastership

period. The bus is held until

either the Bus Activity Timer

expires or there are no further

pending operations to be per-

formed. Th e PCnet-ISA II d eter-

mines whether there are further

pending b us operatio ns by wait -

ing approximately 1 µs after th e

completion of every bus opera-

tion (e.g. a descriptor or FIFO

access). If, during the 1 µs

period, no further bus operations

are requested by the internal

Buffer Management Unit, the

PCnet-ISA II determines that

there are no further pending

operations and gives up bus

ownership.

If TIMER is cleared, the Bus

Activity Timer register is dis-

abled and the PCnet- ISA II per-

forms only one type of access

(descriptor read, descriptor

write, buffer read, or buffer

write) and buffer accesses are

performed to adjacent

ascending addresses during

each bus maste rship per iod .

TIMER is cleared by RESET.

12 DPOLL Disable Transmit Polling. If

DPOLL is set, the Buffer Man-

agement Unit will disable trans-

mit polling. Likewise, if DPOLL is

cleared, au tomatic trans mit poll-

ing is enabled. If DPOLL is set,

TDMD bit in CSR0 must be peri-

odically set in order to initiate a

manual poll of a transmit

descriptor. Transmit descriptor

polling will not take place if

TXON is reset.

DPOLL is cleared by RESET.

11 APAD_XMT Auto Pad Transmit. When set,

APAD_XMT enables the auto-

matic padding feature. Transmit

frames will be padded to exten d

them to 64 bytes, including FCS.

The FCS is calculated for the en-

tire frame (including pad) and

appended after the pad field.

APAD_XMT will override the

programming of the DXMTFCS

bit (CSR15.3).

APAD_ XMT is reset by activa-

tion of the RESET pin.

10 ASTRP_RCV ASTRP_RCV enables the auto-

matic pad stripping feature. The

pad and FCS fields will be

stripped from receive frames

and not placed in the FIFO.

ASTRP_ RCV is reset by activa-

tion of the RESET pin.

9 MFCO Missed Frame Counter Overflow

Interrupt.

This bit indicates the MFC

(CSR112) has overflowed. Can

be cleared by writing a “1" to this

bit. Also cleared by RESET or

setting the STOP bit. Writing a

“0" has no effect.

8 MFCOM Missed Frame Counter Overflow

Mask.

If MFCOM is set, MFCO will not

set INTR in CSR0.

Am79C961A 101

MFCOM is set by Reset and is

not affected by STOP.

7-6 RES Reserved locations. Read and

written as zero.

5 RCVCCO Receive Collision Counter Over-

flow.

This bit indicates the Receive

Collision Coun ter (CSR114 ) has

overflo wed. It can be cle ared by

writing a 1 to this bit. Also

cleared by RESET or setting the

STOP bit. Writing a 0 has no

effect.

4 RCVCCOM Receive Collision Counter Over-

flow Mask.

If RCVCCOM is set, RCVCCO

will not set INTR in CSR0.

RCVCCOM is set by RESET

and is not affected by STOP.

3 TXSTRT Transmit Start status is set when-

ever PCnet-ISA II controller

begins transmission of a frame.

When TXSTRT is set, IRQ is

asserted if IENA = 1 and the

mask bit T XSTRTM ( CSR4. 2) is

clear.

TXSTRT is set by the MAC Unit

and cleared by writing a “1", set-

ting RESET or setting the STOP

bit. Writing a “0" has no effect.

2 TXSTRTM Transmit Start Mask. If

TXSTRTM is set, the TXSTRT bit

in CSR4 will be masked and will

not set INTR flag in CSR0.

TXSTRTM is set by RESET and

is not affected by STOP.

1 JAB Jabber Error is set when the

PCnet-ISA II controller Twist-

ed-pair MAU function exceeds

an allowed transmission limit.

Jabber is set by the TMAU cir-

cuit and can only be asserted in

10BASE-T mode.

When JAB is set, IRQ is a ssert-

ed if IENA = 1 and the mask bit

JABM (CSR4.4) is clear.

The JA B bit ca n be r es et e ve n i f

the jabber condition is still

present.

JAB is set by the TMAU circuit

and cleared by writing a “1".

Writing a “0" has no effect. JAB

is also cleared by RESET or set-

ting the STOP bit.

0 JABM Jabber Error Mask. If JABM is

set, the JAB bit in CSR4 will be

masked and will not set INTR

flag in CSR0.

JABM is set by RESET and is

not affected by STOP.

CSR5: Control 1

Bit Name Description

0 SPND Suspend . Se ttin g SP ND to ONE

will cause the PCnet-ISA II con-

troller to start entering the sus-

pend mode. The host must poll

SPND until it reads a ONE back,

to determ ine that the PCne t-ISA

II controller has entered the sus-

pend mode. Setting SPND to

ZERO will get the PCnet-ISA II

controller out of suspend mode

and back into its active state.

SPND can o nly be set to O NE if

STOP (CSR0, bit 2) is set to

ZERO. Asserting the RESET

pin, reading the RESET register,

or setting the STOP bit forces

the PCnet-ISA II controller out of

suspend mode.

When the host requests the PC-

net-ISA II controller to enter the

suspend mode, the device first

finishes all on-going transmit

activity and updates the

corresponding transmit descrip-

tor entries. It then completes

any frame reception occurring

at the time the SPND bit was

set, and updates the corre-

sponding receiv e des criptor en-

tries. Any subsequent frames

incident upon the PCnet-ISA II

during suspend mode will not

be received, nor will any notifi-

cation be given as to the missed

frames (the MISS bit in CSR0

will not be updated while in sus-

pend mode). It then sets the

read-version of SPND to ONE

and enters the suspend mode.

In suspend mode, all of the

CSR registers are accessible.

As long as the PCnet-ISA II

controller is not reset while in

suspend mode (by asserting the

RESET pin, reading the RESET

bit), no reinitialization of the

device is required after the

device comes out of suspend

mode. The PCnet-ISA II control-

ler will continue at the transmit

and receive descriptor ring

locations, where it had left,

when it entered the suspend

mode.

102 Am79C961A

Read/Write accessible always.

SPND is cleared by asserting

the RESET pin, reading the

RESET register, or setting the

STOP bit

1 MP_MODE Magic Packet M ode.

Setting this bit is a prerequisite

for entering the Magic Packet

mode. It also redefines the

SLEEP pin to be a Magic Packet

enable pi n. Read/Write a ccessi-

ble always. It is cleared by as-

serting the RESET pin, or read-

ing the RESET register.

2 MP_ENBL Magic Packet Enable.

This bit when set, will force the

PCnet-ISA II into the Magic

Packet mode. Read/Write ac-

cessible always. It is cleared by

asserting the RESET pin or

reading the RESET register.

3 MP_I_ENBL Magic Packet Interrupt Enable.

Acts as an unmask bit for the

MP_INT (CSR5, bit 4). Read/

Write accessible always. It is

cleare d by as se rting the RESE T

pin or readin g the RESET regis -

ter, or setting the STOP bit.

4 MP_INT Magic Packet Receive Interrupt.

Wil l be set when a Magic Pa cket

has been received. Writing a

“one” will clear this bit. It is

cleare d by as se rting the RESE T

pin, or reading the RESET regis-

ter.

CSR6: RCV/XMT Descriptor Table Length

Bit Name Description

15-12 TLEN Contains a copy of the transmit

encod ed ring length (TLE N) field

read from the initialization block

during PCnet-ISA II controller ini-

tialization. This field is written

during the PCnet-ISA II controller

initia li zatio n ro utin e.

Read accessible only when STOP

or SPND bit s are set . Wr ite o per -

ations have no effect and should

not be performed. TLEN is only

defined a fter i nit ializa ti on.

11-8 RLEN Contains a copy of the receive

encoded ring length (RLEN)

read from the initialization

block during PCnet-ISA II con-

troller initialization. This field is

written during the PCnet-ISA II

controller initialization routine.

Read accessible only when

STOP or SPND bits are set. Write

operations have no effect and

should not be performed. RLEN is

only defined after initialization.

7-0 RES Reserved locations. Read as

zero. Write operations should

not be performed.

CSR8: Logical Address Filter, LADRF[15:0]

Bit Name Description

15-0 LADRF[15:0] Logical Address Filter, LADRF

[15:0]. Undefined unti l initialize d

either automatically by loading

the init ialization block or di rectly

by an I/O write to this register.

Read/write accessible only

when STOP or SPND bits are

set.

CSR9: Logical Address Filter, LADRF[31:16]

Bit Name Description

15-0 LADRF[31:16] Logical Address Filter,

LADRF[31:16]. Undefined until

initialized either automatically by

loading the ini tializatio n block or

directly by an I/O write to this

Read/write accessible only

when STOP or SPND bits are

set.

CSR10: Logical Address Filter, LADRF[47:32]

Bit Name Description

15-0 LADRF[47:32] Logical Address Filter,

LADRF[47:32]. Undefined until

initialized either automatically by

loading the ini tializatio n block or

directly by an I/O write to this

Read/write accessible only

when STOP or SPND bits are

set.

CSR11: Logical Address Filter, LADRF[63:48]

Bit Name Description

15-0 LADRF[63:48] Logical Address Filter,

LADRF[63:48]. Undefined until

initialized either automatically by

loading the ini tializatio n block or

directly by an I/O write to this

Am79C961A 103

Read/write accessible only

when STOP or SPND bits are

set.

CSR12: Ph ysical Address Register, PADR[15:0]

Bit Name Description

15-0 PADR[15:0] Physical Address Register,

PADR[15:0]. Undefined until

initialized either automatically by

loading the ini tializatio n block or

directly by an I/O write to this

transmitted PADR[0] first and

PADR[47] last.

Read/write accessible only

when STOP or SPND bits are

set.

CSR13: Ph ysical Address Register, PADR[31:16]

Bit Name Description

15-0PADR[31:16] Physical Address Register,

PADR[31:16]. Undefined until

initialized either automatically by

loading the ini tializatio n block or

directly by an I/O write to this

transmitted PADR[0] first and

PADR[47] last.

Read/write accessible only

when STOP or SPND bits are

set.

CSR14: Ph ysical Address Register, PADR[47:32]

Bit Name Description

15-0 PADR[47:32] Physical Address Register,

PADR[47:32]. Undefined until

initialized either automatically by

loading the ini tializatio n block or

directly by an I/O write to this

transmitted PADR[0] first and

PADR[47] last.

Read/write accessible only

when STOP or SPND bits are

set.

CSR15: Mode Register

Bit Name Description

This register’s fields are loaded

during the PCnet-ISA II controller

initialization routine with the cor-

responding Initialization Block

values. The register can also be

loaded directly by an I/O write.

Activating the RESET pin clears

all bits of CSR15 to zero.

15 PROM Promiscuous Mode.

When PR OM = “1", all inc oming

receive frames are accepted.

Read/write accessible only

when STOP or SPND bits are

set.

14 DRCVBC DisableReceiveBroadcast.

When set, disables the PCnet-ISA

II controller from receiving broad-

cast messages. Used for proto-

cols t hat do not support broadca st

addressing, except as a function

of multicast. DRCVBC is cleared

by activation of the RESET pin

(broadcast messages will be

received).

Read/write accessible only

when STOP or SPND bits are

set.

13 DRCVPA Disable Receive Physical Ad-

dress. When set, the physical

address detection (Station or

node ID) of the PCnet-ISA II con-

troller will be disabled. Frames

addressed to the nodes

individual physical address will

not be r ecognized (a lthough the

frame may be accepted by the

EADI mechanism).

Read/write accessible only

when STOP or SPND bits are

set.

12 DLNKTST Disable Link Status. When

DLNKTST = “1", monitoring of

Link Pulses is disabled. When

DLNKTST = “0", monitoring of

Link Pulses is enabled. This bit

only has meaning when the

10BASE-T network interface is

selected.

Read/write accessible only

when STOP or SPND bits are

set.

11 DAPC Disable Automatic Polarity

Correction. When DAPC = “1",

the 10BASE-T receive polarity

reversal algorithm is disabled.

Likewise, when DA PC = “0", the

polarity reversal algorithm is

enabled.

This bit only has meaning whe n

the 10 B ASE -T ne tw or k i nt erf a ce

is selected.

Read/write accessible only

when STOP or SPND bits are

set.

104 Am79C961A

10 MENDECL MENDEC Loopback Mode. See

the description of the LOOP bit

in CSR15.

Read/write accessible only

when STOP or SPND bits are

set.

9 LRT/TSE L Low Recei ve Thr eshol d ( T- MAU

Mode only)

Transmit Mode Select (AUI

Mode only)

LRT Low Receive Threshold. When

LRT = “1", the internal twisted

pair receive thresholds are

reduced by 4.5 dB below the

standard 10BASE-T value

(approximately 3/5) and the

unsquelch threshold for the RXD

circuit will be 180-312 mV peak.

When LRT = “0", the unsquelch

threshold fo r the RXD cir cuit will

be the standard 10BASE-T

value, 300-520 mV peak.

In either case, the RXD circuit

post squelch threshold will be

one half of the unsquelch thresh-

old.

This bit only has meaning when

the 10BASE-T network interface

is selected.

Read/write accessible only

when STOP or SPND bits are

set. Cleared by RESET.

TSEL Transmit Mode Select. TSEL

controls the levels at which the

AUI drivers rest when the AUI

transmit port is idle. When TSEL

= 0, DO+ and DO- yield “zero” dif-

ferential to operate transformer

coupled loads (Ethernet 2 and

802.3). When TSEL = 1, the DO+

idles at a higher value with

respect to DO-, yielding a logical

HIGH st at e (Eth ern et 1).

This bit only has meaning when

the AUI network interface is

selected. Not available under

Aut o-Select Mode.

Read/write accessible only

when STOP or SPND bits are

set. Cleared by RESET.

8-7 PORTSEL Port Select bits allow for software

[1:0] controlled selection of the net-

work medium. PORTSEL active

only when Media-Select Bit set

to 0 in ISACSR2.

Read/write accessible only

when STOP or SPND bits are

set. Cleared by RESET.

The network port configuration

are as follows:

6 INTL Internal Loopback. See the

description of LOOP, CSR15.2.

Read/write accessible only

when STOP bit is set.

5 DRTY Disable Retry. When DRTY =

“1", PCnet-ISA II controller will

attempt only one transmission. If

DRTY = “0", PCnet-ISA II con-

troller wil l attempt to trans mit 16

times before signaling a retry

error.

Read/write accessible only

when STOP or SPND bits are

set.

4 FCOLL Force Collision. This bit allows

the collision logic to be tested.

PCnet-ISA II controller must be

in internal loopback for FCOLL

to be valid. If FCOLL = “1", a col-

lision will be fo rced during loop-

back transmission attempts; a

Retry Error will ultimately result.

If FCOLL = “0", the Force Colli-

sion logic will be disabled.

Read/write accessible only

when STOP or SPND bits are

set.

3 DXMTFCS Disable Transmit CRC (FCS).

When DXMTFCS = “0", the

transmitter will generate and

append a FCS to the transmitted

frame. When DXMTFCS = “1",

the FCS logi c is allocated to the

receiv er and n o FCS is gen erat-

ed or sent with the transmitted

frame.

See also the ADD_FCS bit in

TMD1. If DXMTFCS is set, no

FCS will be generated. If both

DXMTFCS is set and ADD_FCS

is clear for a particular frame, no

FCS will be generated. If

ADD_FCS is set for a particular

frame, the s tate of DXM TFC S is

ignored and a FCS will be ap-

pended on that frame by the

transmit circuitry.

PORTSEL[1:0] Network Port

0 0 AUI

0 1 10BASE-T

1 0 GPSI*

1 1 Reserved

*Refer to the section on General Purpose Serial Interface for

detailed information on accessing GPSI.

Am79C961A 105

In loopb ack mo de, this bit deter -

mines if t he tr an sm itte r a ppe nds

FCS or if the receiver checks the

FCS.

This bit was called DTCR in the

LANCE (Am7990 ).

Read/write accessible only

when STOP or SPND bits are

set.

2 LOOP Loopback Enable allows PC-

net-ISA II controller to operate in

full duplex mode for test purpos-

es. When LOOP = “1", loopback

is enabled. In combination with

INTL and MENDECL, various

loopback modes are defined as

follows.

Read/write accessible only

when STOP or SPND bits are

set. LOOP is cleared by RESET.

1 DTX Disable Transmit. If this bit is set,

the PCnet-ISA II controller will

not access the Transmit

Descriptor Ring and, therefore,

no transmissions will occur. DTX

= “0" wil l s et TXON bit ( CSR0 .4)

after STRT (CSR0.1) is assert-

ed. DTX is defined after the ini-

tialization block is read.

Read/write accessible only

when STOP or SPND bits are

set.

0 DRX Disable Receiver. If this bit is

set, the PCnet-ISA II controller

will not access the Receive

Descriptor Ring and, therefore,

all receive frame data are

ignored. DRX = “0" will set

RXON bit (CSR0.5) after STRT

(CSR0.1) is asserted. DRX is

defined after the initialization

block is read.

Read/write accessible only

when STOP or SPND bits are

set.

CSR16: Initialization Block Address Lower

Bit Name Description

15-0 IADR Lower 16 bits of the address of

the Initialization Block. Bit loca-

tion 0 must be zero. This register

is an alias of CSR1. Whenever

this register is written, CSR1 is

updated with CSR16’s contents.

Read/Write accessible only

when the STOP or SPND bits

are set. Unaffected by RESET.

CSR17: Initialization Block Address Upper

Bit Name Description

15-8 RES Reserved locations. Written as

zero and read as undefined.

7-0 IADR Upper 8 bits of the address of

the Initialization Block. Bit loca-

tions 15-8 must be written with

zeros. Th is re gi st e r is an a li as of

CSR2. When ev er thi s reg is ter is

written, CSR2 is updated with

CSR17’s contents.

Read/Write accessible only

when the STOP or SPND bits

are set. Unaffected by RESET.

CSR18-19 : Current Receive Buffer Address

Bit Name Description

31-24 RES Reserved locations. Written as

zero and read as undefined.

23-0 CRBA Contains the current receive

buffer a ddress to whic h the PC-

net-ISA II controller will store in-

coming frame data.

Read/wr i te acc es si bl e on ly w hen

STOP or SPND bits are set.

CSR20-21: Current Transmit Buffer Address

Bit Name Description

31-24 RES Reserved locations. Written as

zero and read as undefined.

23-0 CXBA Contains the current transmit

buffer address from which the

PCnet-ISA II controller is trans-

mitting.

Read/wr i te acc es si bl e on ly w hen

STOP or SPND bits are set.

LOOP INTL MENDECL Loopback Mode

0 X X Non-loopback

1 0 X External Loopback

11 0

Internal Loopback

Include MEND EC

11 1

Internal Loopback

Exclude MEND EC

106 Am79C961A

CSR22-23: Next Receive Buffer Address

Bit Name Description

31-24 RES Reserved locations. Written as

zero and read as undefined.

23-0 NRB A Con tains the next receive buffer

address to which the PCne t-ISA

II controller will store incoming

frame data.

Read/write accessible only

when STOP or SPND bits are

set.

CSR24-25: Base Address of Receive Ring

Bit Name Description

31-24 RES Reserved locations. Written as

zero and read as undefined.

23-0 BADR Contains the base address of

the Receive Ring.

Read/write accessible only

when STOP or SPND bits are

set.

CSR26-27: Next Receive Descriptor Address

Bit Name Description

31-24 RES Reserved locations. Written as

zero and read as undefined.

23-0 NRDA Contains the next RDRE

address pointer.

Read/write accessible only

when STOP or SPND bits are

set.

CSR28-29 : Current Rece ive Desc ript or Address

Bit Name Description

31-24 RES Reserved locations. Written as

zero and read as undefined.

23-0 CRDA Contains the current RDRE

address pointer.

Read/write accessible only

when STOP or SPND bits are

set.

CSR30-31: Base Address of Transmit Ring

Bit Name Description

31-24 RES Reserved locations. Written as

zero and read as undefined.

23-0 BADX Contains the base address of

the Transmit Ring.

Read/write accessible only

when STOP or SPND bits are

set.

CSR32-33: Next Transmit Descriptor Address

Bit Name Description

31-24 RES Reserved locations. Written as

zero and read as undefined.

23-0 NXDA Contains the next TDRE address

pointer.

Read/write accessible only

when STOP or SPND bits are

set.

CSR34-35: Current Transmit Descriptor Address

Bit Name Description

31-24 RES Reserved locations. Written as

zero and read as undefined.

23-0 CXDA Contains the current TDRE

address pointer.

Read/write accessible only

when STOP or SPND bits are

set.

CSR36-37: Next Next Receive Descriptor Address

Bit Name Description

31-0 NNRDA Contains the next next RDRE

address pointer.

Read/write accessible only

when STOP or SPND bits are

set.

CSR38-39: Next Next Transmit Descri ptor Address

Bit Name Description

31-0 NNXDA Contains the next next TDRE

address pointer.

Read/write accessible only

when STOP or SPND bits are

set.

CSR40-41: Current Receive Status and Byte Count

Bit Name Description

31-24 CRST Current Receive Status. This

field is a copy of bits 15:8 of

RMD1 of the current receive

descriptor.

Read/write accessible only

when STOP or SPND bits are

set.

23-12 RES Reserved locations. Written as

zero and read as undefined.

Am79C961A 107

11-0 CRBC Current Receive Byte Count.

This f ield is a cop y of the BCNT

field of RMD2 of the current

receive descriptor.

Read/write accessible only

when STOP or SPND bits are

set.

CSR42-43: Current Transmit Status and Byte

Count

Bit Name Description

31-24 CXST Current Transmit Status. This

field is a copy of bits 15:8 of

TMD1 of the current transmit

descriptor.

Read/wr ite ac c ess ibl e o nl y wh en

STOP or SPND bits are set.

23-12 RES Reserved locations. Written as

zero and read as undefined.

11-0 CXBC Current Transmit Byte Count.

This f ield is a cop y of the BCNT

field of TMD2 of the current

transmit descriptor.

Read/wr ite ac c ess ibl e o nl y wh en

STOP or SPND bits are set.

CSR44-45: Next Receive Status and Byte Count

Bit Name Description

31-24 NRST Next Receive Status. This field

is a copy of bits 15:8 of RMD1 of

the next receive descriptor.

Read/wr ite ac c ess ibl e o nl y wh en

STOP or SPND bits are set.

23-12 RES Reserved locations. Written as

zero and read as undefined.

11-0 NRBC Next Receive Byte Count. This

field is a copy of the BCNT field

of RMD2 of the next receive

descriptor.

Read/wr ite ac c ess ibl e o nl y wh en

STOP or SPND bits are set.

CSR46: Poll Time Counter

Bit Name Description

15-0 POLL Poll Time Counter. This counter

is incriminated by the PCnet-ISA

II controller microcode and is

used to trigger the descriptor

ring po lling o peration of the P C-

net-ISA II controller.

Read/wr ite ac c ess ibl e o nl y wh en

STOP or SPND bits are set.

CSR47: Po lling Interval

Bit Name Description

31-16 RES Reserved locations. Written as

zero and read as undefined.

15-0 POLLINT Polling Interval. This register

contains the time that the PC-

net-ISA II controller will wait be-

tween successive polling

operations. The POLLINT value

is expressed as the two’s com-

plement of the desired interval,

where each bit of POLLINT rep-

resents one-half of an XTAL1

period of time. POLLINT[3:0] are

ignored. (POLINT[16] is implied

to be a one, so POLLINT[15] is

significant, and does not repre-

sent the sign of the two’s

complem ent PO LL INT value.)

The default value of this register

is 0000. This corresponds to a

polling interval of 32,768 XTAL1

periods. The POLINT value of

0000 is created during the micro-

code initialization routine, and

therefore might not be seen when

reading CSR47 after RESET.

If the use r desires to program a

value for POLLINT other than

the default, then the correct

procedure is to first set INIT only

in CS R0. The n, when the ini tial-

ization sequence is complete,

the user must set STOP in

CSR0. Then the user may write

to CSR47 and then set ST RT in

CSR0. In this way, the default

value of 0000 in CSR47 will be

overwritten with the desired user

value.

Read/write accessible only

when STOP or SPND bits are

set.

CSR48-49: Temporary Storage

Bit Name Description

31-0 TMP0 Temporary Storage location.

Read/write accessible only

when STOP or SPND bits are

set.

CSR50-51: Temporary Storage

Bit Name Description

31-0 TMP1 Temporary Storage location.

108 Am79C961A

Read/wr ite ac c ess ibl e o nl y wh en

STOP or SPND bits are set.

CSR52-53: Temporary Storage

Bit Name Description

31-0 T MP 2 Temporary Sto rage loc ation.

Read/write accessible only

when STOP or SPND bits are

set.

CSR54-55: Temporary Storage

Bit Name Description

31-0 T MP 3 Temporary Sto rage loc ation.

Read/write accessible only

when STOP or SPND bits are

set.

CSR56-57: Temporary Storage

Bit Name Description

31-0 T MP 4 Temporary Sto rage loc ation.

Read/write accessible only

when STOP or SPND bits are

set.

CSR58-59: Temporary Storage

Bit Name Description

31-0 T MP 5 Temporary Sto rage loc ation.

Read/write accessible only

when STOP or SPND bits are

set.

CSR60-61: Previous Transmit Descriptor Address

Bit Name Description

31-24 RES Reserved locations. Written as

zero and read as undefined.

23-0 PXDA Contains the previous TDRE

address poi nter. T he P Cnet- ISA

II control ler has the capabil ity to

stack multiple transmit frames.

Read/write accessible only

when STOP or SPND bits are

set.

CSR62-63: Previous Transmit Status and Byte

Count

Bit Name Description

31-24 PXST Previous Transmit Status. This

field is a copy of bits 15:8 of

TMD1 of the previous transmit

descriptor.

Read/write accessible only

when STOP or SPND bits are

set.

23-12 RES Reserved locations. Written as

zero and read as undefined.

Accessible only when STOP bit

is set.

11-0 PXBC Previous Transmit Byte Count.

This field i s a copy of the BCNT

field of TMD2 of the previous

transmit descriptor.

Read/write accessible only

when STOP or SPND bits are

set.

CSR64-65: Next Transmit Buffer Address

Bit Name Description

31-24 RES Reserved locations. Written as

zero and read as undefined.

23-0 NXBA Contains the next transmit buffer

address from which the PC-

net-ISA II controller will transmit

an outgoing frame.

Read/write accessible only

when STOP or SPND bits are

set.

CSR66-67: Next Transmit Status and Byte Count

Bit Name Description

31-24 NXST Next Transmit Status. This field

is a copy of bits 15:8 of TMD1 of

the next transmit descriptor.

Read/write accessible only

when STOP or SPND bits are

set.

23-12 RES Reserved locations. Written as

zero and read as undefined.

Accessible only when STOP bit

is set.

11-0 NXBC Next Transmit Byte Count. This

field is a copy of the BCNT fi eld

of TMD2 of the next transmit

descriptor.

Read/write accessible only

when STOP or SPND bits are

set.CSR68 -69: Trans mit Status

Temporary Storage

Bit Name Description

31-0 XSTMP Transmit Status Temporary

Storage location.

Read/write accessible only

when STOP or SPND bits are

set.

Am79C961A 109

CSR70-71: Temporary Storage

Bit Name Description

31-0 T MP 8 Temporary Sto rage loc ation.

Read/write accessible only

when STOP or SPND bits are

set.

CSR72: Receive Ring Counter

Bit Name Description

15-0 RCVRC Receive Ring Counter location.

Contains a Two’s complement

binary number used to number

the current receive descriptor.

This counter interprets the value

in CSR76 as pointing to the first

descriptor; a two’s complement

value of -1 (FFFFh) cor responds

to the last descriptor in the ring.

Read/write accessible only

when STOP or SPND bits are

set.

CSR74: Transmit Ring Counter

Bit Name Description

15-0 XMTRC Transmit Ring Counter location.

Contains a Two’s complement

binary number used to number

the current transmit descriptor.

This counter interprets the value

in CSR78 as pointing to the first

descriptor; a two’s complement

value of -1 (FFFFh) cor responds

to the last descriptor in the ring.

Read/write accessible only

when STOP or SPND bits are

set.

CSR76: Receive Ring Length

Bit Name Description

15-0 RCVRL Receive Ring Length. Contains

the Two’s complement of the

receive descriptor ring length.

This register is initialized during

the PCnet-ISA II controller initial-

ization routine based on the

value in the RLEN field of the ini-

tialization block. This register

can be manually altered; the

actual receive ring length is

defined by the current value in

this registe r.

Read/write accessible only

when STOP or SPND bits are

set.

CSR78: Transmit Ring Length

Bit Name Description

15-0 XMTRL Transmit Ring Length. Contains

the two’s complement of the

transmit descriptor ring length.

This register is initialized during

the PCnet-ISA II controller initial-

ization routine based on the

value in the TLEN field of the ini-

tialization block. This register

can be manually altered; the

actual transmit ring length is

defined by the current value in

this registe r.

Read/write accessible only

when STOP or SPND bits are

set.

CSR80: Burst and FIFO Threshold Control

Bit Name Description

15-14 RES Reserved locations. Read as

ones. Written as zero.

13-12RCVFW[1:0] Receive FIFO Watermark.

RCVFW controls the point at

which ISA bus receive DMA is

requested in relation to the num-

ber of received bytes in the

receive FIFO. RCVFW specifies

the number of bytes which must

be present (once the frame has

been verified as a non-runt)

before receive DMA is request-

ed. Note however that, if the net-

work interface is operating in

half-duplex mode, in order for

receive DMA to be performed for

a new frame, at least 64 bytes

must have been received. This

effe ctive ly avoi ds havin g to reac t

to receive frames which are

runts or suffer a collision during

the slot time (512 bit times). If

the Runt Packet Accept feature

is enabled, receive DMA will be

reques ted as soon as either the

RCVFW threshold is reached, or

a complete valid receive frame is

detected (regardless of length).

RCVFW is set to a value of 10b

(64 bytes) after RESET.

Read/write accessible only

when STOP or SPND bits are

set.

110 Am79C961A

11-10XM TSP[1:0 ]Transmi t Start

Point . XMT SP co ntrol s the p oint

at which preamble transmission

attempts commence in relation

to the number of bytes written to

the transmit FIFO for the current

transmit frame. When the entire

frame is in the FIFO, transmis-

sion will start regardless of the

value in XMTSP. XMTSP is

given a value of 10b (64 bytes)

after RESET. Regardless of

XMTSP, the FIFO will not inter-

nally over-write its data until at

least 64 bytes (or the entire

frame if <64 bytes) have been

transmitted onto the network.

This ensures that for collisions

within the slot time window,

transmit data need not be

re-written to the transmit FIFO,

and retries will be handled

autono mously b y the M AC. This

bit is read/write accessible only

when the STOP or SPND bits

are set.

9-8 XMTFW[1:0] Transmit FIFO Watermark.

XMTFW specifies the point at

which transmit DMA stops,

based upon the number of write

cycles that could be performed

to the transmit FIFO without

FIFO overflow. Transmit DMA is

allowed at any time when the

number of write cycles specified

by XMTFW could be executed

without causing transmit FIFO

overflow. XMTFW is set to a

value of 00b (8 cycles) after

hardware RESET. Read/write

accessible only when STOP or

SPND bits are set.

7-0 DMABR DMA Burst Register. This reg-

ister contains the maximum

allowable number of transfers

to system memory that the Bus

Interface will perform during a

single DMA cycle. The Burst

number of transfers during

Descriptor transfers. A value of

zero will be interpreted as one

transfer. During RESET a

value of 16 is loaded in the

BURST register. If DMAPLUS

(CSR4.14) is set, the DMA

Burst Register is disabled.

When the Bus Activity Timer

enabled, the PCnet-ISA II con-

troller will relinquish the bus

when either the time specified

in DMABAT has elapsed or the

number of transfers specified

in DMABR have occurred or no

more pending operation left to

be performed.

Read/write accessible only

when STOP or SPND bits are

set.

CSR82: Bus Activity Timer

Bit Name Description

15-0 DM ABAT Bu s Activ ity Timer. If the TIMER

bit in CSR4 is set, this register

contains the maximum allowable

time that the PCnet-ISA II con-

troller wil l ta ke up on the s yste m

bus during FIFO data transfers

in each bus mastership period.

The DMABAT starts counting

upon receipt of DACK from the

host system. The DMABAT Reg-

ister does not limit the number of

transfers during Descriptor

transfers.

A valu e of zero will limit th e PC-

net-ISA II controller to one bus

cycle per mastership period. A

non-zero value is interpreted as

an unsi gned number with a res-

olution of 100 ns. For instance, a

value of 51µs would be pro-

grammed with a value of 510.

When the T IMER bit in CSR4 is

set, DMABAT is enabled and

must be initialized by the user.

RCVFW[1 :0] Bytes Received

00 16

01 32

10 64

11 Reserved

XMTSP[1:0] Bytes Written

00 4

01 16

10 64

11 112

XMTFW[1:0] Write Cyc les

00 8

01 16

10 32

11 Reserved

XMTFW[1:0] Write Cycles

Am79C961A 111

The DMABAT register is unde-

fined until written .

When the Bus Activity Timer

enabled, the PCnet-ISA II con-

troller will relinquish the bus

when either the time specified in

DMABAT has elapsed or the

number of transfers specified in

DMABR have occurred or no

more pending operation left to

be performed. When ENTST

(CSR4.15) is asserted, all writes

to this registe r will automatically

perform a decrement cycle.

Read/write accessible only

when STOP or SPND bits are

set.

CSR84-85: DMA Address

Bit Name Description

31-0 DMABA DMA Address Register.

This regist er contains th e address

of system memory for the current

DMA cycle. The Bus Interface

Unit controls the Address Register

by issuing increment commands

to incre ment the mem ory add ress

for sequential operations. The

DMABA register is u ndefin ed until

the first PCnet-ISA II controller

DMA oper ation.

This register has meaning only if

the PCnet-ISA II controller is in

Bus Master Mode.

Read/write accessible only

when STOP or SPND bits are

set.

CSR86: Buffer Byte Counter

Bit Name Description

15-12 RES Reserved, Read and written with

ones.

11-0 DMABC DMA Byte Count Register.

Contains the Two’s comple-

ment of the current size of the

remaining transmit or receive

buffer in bytes. This register is

incriminated by the Bus Inter-

face Unit. The DMABC register

is undefined until written.

Read/write accessible only

when STOP or SPND bits are

set.

CSR88-89: Chip ID

Bit Name Description

31-28 Version. This 4-bit pattern is

silicon revision dependent.

27-12 Part Number. The 16-bit code

for the PCnet- ISA II controlle r is

0010001001100001b (2261h).

11-1 Manufacturer ID. The 11-bit

manufacturer code for AMD is

00000000001b. This code is per

the JEDEC Publication 106-A.

0 Always a logic 1.

This register is exactly the same

as the Chip ID register in the

JTAG description.

This register is readable only

when STOP or SPND bits are

set.

CSR92: Ring Length Conversion

Bit Name Description

15-0 RCON Ring Length Conversion Regis-

ter. This register performs a

ring length conversion from an

encoded value as found in the

initialization block to a Two’s

complement value used for

internal counting. By writing

bits 15–12 with an encoded

ring length, a Two’s comple-

mented value is read. The

RCON register is undefined

until written.

Read/write accessible only

when STOP or SPND bits are

set.

CSR94: Transmit Time Domain Reflectometry

Count

Bit Name Description

15-10 RES Reserved locations. Read and

written as zero.

9-0 XMTTDR Time Domain Reflectometry

reflects the state of an internal

counter that counts from the

start of transmission to the

occurrence of loss of carrier.

TDR is incriminated at a rate of

10 MHz.

Read accessible only when

STOP or SPND bits are set.

Write operations are ignored.

XMTTDR is cleared by RESET.

112 Am79C961A

CSR96-97: Bus Interface Scratch Register 0

Bit Name Description

31-0 SCR0 This register is shared between

the Buffer Management Unit and

the Bus Interface Unit. All

Descriptor Data communica-

tions between the BIU and BMU

are written and read through

SCR0 and SCR1 registers. The

SCR0 reg ister is un defined until

written.

Read/wr ite ac c ess ibl e o nl y wh en

STOP or SPND bits are set.

CSR98-99: Bus Interface Scratch Register 1

Bit Name Description

31-0 SCR1 This register is shared between

the Buffer Management Unit and

the Bus Interface Unit. All

Descriptor Data communica-

tions between the BIU and BMU

are written and read through

SCR0 and SCR1 registers.

Read/write accessible only

when STOP or SPND bits are

set.

CSR104-105: SWAP

Bit Name Description

31-0 SWA P This register p erforms wo rd and

byte swapping depending upon

if 32-bit or 16-bit internal write

operations are performed. This

registe r is used internally by the

BIU/BMU as a word or byte

swapp er. The s wap r egiste r can

perform 32-bit operations that

the PC can not; the register is

externally accessible for test

reasons only. CSR104 holds the

lower 16 bits and CSR105 holds

the upper 16 bits.

The swap function is defined as

follows:

Read/write accessible only

when STOP or SPND bits are

set.

CSR108-109: Buffer Management Scratch

Bit Name Description

31-0 BMSCR The Buffer Management Scratch

Receive and Transmit Status.

This reg ister is al so used a s the

primary scan register for Buffer

Management Test Modes.

BMSCR register is undefined

until written.

Read/write accessible only

when STOP bit is set.

CSR112: Missed Frame Count

Bit Name Description

15-0 MFC Counts the number of missed

frames.

This register is always readable

and is cleared by STOP.

A write to this register performs

an increment when the ENTST

bit in CSR4 is set.

When MFC is all 1’s (65535) and

a missed frame occurs, MFC

increments to 0 and sets MFC0

bit (CSR4.9).

CSR114: Receive Collisio n Count

Bit Name Description

15-0 RCVCC Counts the number of Receive

collisions seen, regular and late.

This register is always readable

and is cleared by STOP.

A write to this register performs

an increment when the ENTST

bit in CSR4 is set.

When RCVCC is all 1’s (65535)

and a receive collision occurs,

RCVCC increments to 0 and

sets RCVCC0 bit (CSR4.5)

CSR124: Buffer Management Unit Test

Bit Name Description

This register is used to place the

BMU/BIU into various test

modes to support Test/Debug.

This register is writeable when

the ENTST bit in CSR4 is set.

15-5 RES Reserved locations. Written as

zero and read as undefined.

4 GPSIEN This mode places the PCnet-ISA

II controller in the GPSI Mode.

Internal Write Operation SWAP Register Result

32-Bit wo rd SRC[31:16]→SWAP[15:0]

SRC[15:0]→SWAP[31:16]

Lower 16-Bit

(CSR104) SRC[15:8]→SWAP[7: 0]

SRC[7:0]→SWAP[15:8]

Am79C961A 113

This mode will reconfigure the

External Address Pins so that

the GPSI port is exposed. This

allows by passin g the MENDEC-

TMAU logic. This bit should only

be set if the external logic sup-

ports GPSI operation. Damage

to the device may occur in a

non-GPSI configuration. Refer

to the GPSI section.

3 RPA Runt Packet Accept. This bit

forces the CORE receive logic to

accept Runt Packets. This bit

allows for faster testing.

2-0 RES For test purposes only. Reserved

locations. Written as zero and

read as und efined .

114 Am79C961A

ISA Bus Configuration Registers

The ISA Bus Data P ort (IDP) allows access to registers

which are associated with the ISA bus. These registers

are called ISA Bus Configuration Registers (ISACSRs),

and are indexed by the value in the Register Address

Port (RAP). The table below defines the ISACSRs

which can be accessed. All registers are 16 bits. The

“Default” value is the value in the register after reset

and is hexadecimal.Refer to the section “LEDs” fo r i n -

formation on LED control logic.

ISACSR0: Master Mode Read Active/SRAM Data

Port

When in the Bus Master mode:

Bit Name Description

15-4 RES Reserved locations. Written as

zero and read as undefined.

3-0 MSRDA Master Mode Read Active time.

This register is used to tune the

MEMR command signal active

time when the PCnet-ISA II is in

the B us Mas ter m ode. T he val ue

stored in MSRDA defines the

numb er of 50 n s per iod s th at the

command signal is active. The

default value of 5h indicates

250ns pulse widths. A value of 0

should not be used and may

result in no com mand assertio n.

When in the Bus Slave, Programmed I/O architecture

mode:

15-0 SRAMDP SRAM Data Port. This register

serves as a da ta po rt for acc es s -

ing the SRAM when the PC-

net-ISA II is in the Bus Slave,

Programmed I/O architecture

mode. Accesses to this port are

directed to the SRAM location

that is addressed by the

SRAMAP register (ISACSR1).

Word accesses and byte

accesses to the even byte (least

significant bits) are allowed. B yte

access e s to the od d b y te are not

allowed except when they are

performed automatically by

motherboard logic as discussed

in the Bus Cycles (Hardware)

section. Read and write

acces ses to thi s registe r will hav e

the si de effe ct that the SRA MAP

ment by 1 or 2 depending on

whether a byte or word access,

respectively, is performed.

ISACSR1: Master Mode Write Active/SRAM

Address Pointer

When in the Bus Master mode:

Bit Name Description

15-4 RES Reserved locations. Written as

zero and read as undefined.

3-0 MSWRA Master Mode Write Active time.

This register is used to tune the

MEMW command signal active

time when the PCn et-IS A II is in

the Bus Master mode. The value

stored in MSWRA defines the

number of 50 ns periods that the

command signal is active. The

default value of 5h indicates

250ns pulse widths. A value of 0

should not be used and may

result in no command assertion.

When in the Bus Slave, Programmed I/O architecture

mode:

15-0 SRAMAP SRAM Address Pointer. This

regist er functi ons as an add ress

pointer for accessing the SRAM

when the PCnet-ISA II is in the

Bus Slave, Programmed I/O

architecture mode. Accesses to

the SRAMDP (ISACSR0) regis-

ter are directed to the SRAM

location that is addressed by this

ISACSR MNEMONIC Default Name

0 MSRDA 0005H M as t er Mo de

Read Acti ve

1 MSWRA 0005H Master Mode

Write Active

2 MC 0002H Miscellaneous

Configuration

3 EC 8000H* EEPROM

Configuration

4 LED0 0000H Link Integrity

5 LED1 0084H Def au lt: RC V

6 LED2 0008H Default:

RCVPOL

7 LED3 0 090 H Default: XMT

8 SC 0000H

Software

Configuration

(Read-Only

9 DUP 0000H Default: Half

Duplex

This value can be 0000H for systems that do not support

EEPROM option .

Am79C961A 115

matically incriminated by 1 or 2

when byte or word accesses,

respectively, are performed to

the SRAMDP register

(ISACSR0).

ISACSR2: Miscellaneous Configuration 1

Bit Name Description

15MODE_STATUS Mode Status. This is a read-only

registe r which indic ates wheth er

the PCne t-ISA II is con fig ured i n

slave mode. A set condition indi-

cates slave mode while a clear

condition indicates bus-master

condition.

14 TMAU_LOOPE 10BASE-T External Loop back

Enable. This bit is usable only

when 10BASE-T is selected

AND PCnet-ISA II is in external

loop bac k. Ex ternal loop back is

set during initialization via the

MODE register. When

TMAU_LOOPE is set, a board

level test is enabled via a loop

back clip which ties the

10BASE-T RJ 45 trans mit pai r t o

the receiver pair. This will test all

external components (i.e. trans-

formers, resistors, etc.) of the

10BASE-T path. TMAU_

LOOPE asse rtion is no t suita ble

for live network tests. When

TMAU_LOOPE is deasserted,

default condition, external loop

back in 10BASE-T is allowed.

13 PIOSEL Programmed I/O Select. When

oper ati ng in th e Bus Sl ave m ode

with this bit reset to ZERO, a

shared memory implementation

is selected and the local SRAM

is accessible through memory

cycles on the ISA bus interface.

When operating in the Bus Slave

mode with this bit set to ONE, a

Programmed I/O implementa-

tion is selected and the local

SRAM is accessibl e through I/O

cycles on the ISA bus interface.

Refer to the Shared Memory and

Programmed I/O sections for

details on these two architecture

schemes.

When operating in the Bus Master

mode, this bit has no effect.

PIOSEL is reset to ZERO.

12 SLOT_ID Slot Identification. This is a

read-o nly regis ter bit w hich ind i-

cates if PCnet-ISA II is either in

an 16 or 8 bit slot. Reading a one

indicates an 8 bit slot. Zero indi-

cates a 16-bi t sl ot. (SLO T_ID bi t

is not valid after the INIT bit is set

in CSR0.)

11 ISA_PROTECT ISA Protect. When set, the

ISACSR’s 0–2 and 4–9 are

protected from being written

over by software drivers. When

ISA_ PROTECT is cleared,

ISACSR’s 0–2 and 4–9 are

allowed to be written over by

software and reset by reading

the Software reset I/O location.

(Default is zer o)

10 EISA_DECODE EISA Decode. This control bit

allows EISA p roduct i dentifier re g-

isters 12-bit decode xC80 - xC83

(4 Bytes). Default is zero.

9 P&P_ACT Plug and Play Active. When

this bit is set, PCnet-ISA II will

become active after serially

reading the EEPROM. If check

sum failure exist, PCnet-ISA II

will not become active and

alternate access method to

Plug and Play registers will

occur. Default is zero.

8 A PWEN Address PROM Write Enable. It

is reset to zero by RESET. When

asserted, this pin allows write

access to the internal Address

PROM RAM. APWEN is used

also to protect the Flash device

from write cycles. When pro-

grammin g of the Flash dev ice is

required, the APWEN bit needs

to be set. When reset, this pin

protects the internal Address

PROM RAM, and external Flash

device from being overwritten.

7 EISA_LVL EISA Level. This bit is a

read-only register. It indicates if

the lev el or edg e se nsitive inter-

rupts h ave been s elected. A set

condition indicates level sensi-

tive interrupts. A clear condition

indicates ISA edge.

6 DSDBUS Disable Staggered Data Bus.

When thi s bit is a zero, the data

bus driver timing is staggered

from the address bus driver

timing in Bus Master mode.

When this bit is a one, the data

bus is not staggered. It is similar

to the PCnet-ISA (Am79C960)

timing. This bit is reset to zero.

For most applications, this bit

should not have to be set.

5 10BASE5_SEL 10BASE5 Select. When set, this

bit inverts the pol ari ty of th e DX-

CVR pin o nly when t he AUI p ort

116 Am79C961A

is active. When the

10BASE5_SEL bit is set and the

AUI port is active, the DXCVR is

driven such that an external

DC-DC converter will be

disabled. The ac tual po larity of

the DXCVR pin is determined by

the DXCVRP bit in PnP Register

0xF0.

When the 10BASE-T port is

active, this bit has no effect.

10BASE5 _SEL is reset t o ZERO.

4 ISAINACT ISAINACT allows for reduced

inactive timing appropriate for

modern ISA machines. ISAINACT

is cleared when RESET is assert-

ed. When ISAINACT is a zero,

tMMR3 and tMMW3 parameters

are nominally 200 ns, which is

compatible with EISA system.

When ISAIN ACT is set by writing

a one, tMMR3 and tMMW3 are

nominally set to 100 ns.

3 EADISEL EADI Select. Enables EADI

match mode.

When EADI mode is selected,

the pins named LED1, LED2,

and LED3 change in function

while LED0 continues to indicate

10BASE-T Link Status.

2 AWAKE Auto-Wake. If AWAKE = “1", the

10BASE-T receive circuitry is

active during sleep and listens

for Link Pulses. LED0 indicates

Link Status and goes active if the

10BASE-T port comes out of

“link fail” state. This LED0 pin

can be used by external circuitry

to re-enable the PCnet-ISA II

controller and/or other devices.

When AWAKE = “0", the Au-

to-Wake circuity is disabled.

This bit only has meaning when

the 10BASE-T network interface

is selected.

1,0 MEDSEL Media Select. It was previously

defined as ASEL (Auto Select)

and XMAUSEL (External MAU

Select) in the PCnet-ISA. They

are now combined together and

defi ned to be softwa re compa tible

with ASEL and XMAUSEL in the

PCnet- IS A (Am7 9C 960 ).

ISACSR3: EEPROM Configuration

Bit Name Description

15 EE_VALID EEPROM Valid. This bit is a

read-only register. When a one

is read, EE_PROM has a valid

checksum. The sum of the total

bytes reads should equals FF

hex. When a zero is read, check-

sum failed, or SHFTBUSY pin

was sampled with a zero which

indicates no EEPROM present.

14 EE_LOAD EEPROM Load. When written

with a one, the device will load

the EEPROM into the PC-

net-ISA II, performing self con-

figuration. This command must

be las t write to IS ACSR3 Re gis-

ter. PCnet-ISA II will not respond

to any slave commands while

loading the EEPROM register.

EE_LOAD will be reset with a

zero after EEPROM is read. It

takes approximately, 1.4 ms for

serial EEPROM load process to

complete.

13–5 N/A Reserved. Read and written as

zeros.

4 EE_EN EEPROM Enable. When EE_EN

is written with a one, the lower

three bits of PRDB becomes SK,

DI and DO, respectively. EECS

and SHFBUSY are controlled by

the software select bits. This bit

must be written with a one to

write to or read from the EE-

PROM. PCnet-ISA II should be

in the STO P state when EE_E N

is written. When EE_EN is

cleared, DI/DO, SK, EECS and

SHFBUSY have no control.

3 SHFBUSY Shift Busy. SHFBUSY allows for

the co ntrol of the SHFB USY pin .

When a one is written, SHFBUSY

goes high provided EE_EN is a 1.

When a zero is written, SHF-

BUSY is held to a zero. When

EE_EN is cleared, SHFBUSY will

maintain the last value pro-

grammed. (Refer to Bit 4 above,

LED EADI Function

1SF/BD

2SRD

3 SRDCLK

MEDSEL (1:0) Function

0 0 Software Select (Mode Reg, CSR15)

0 1 10BASE-T Port

1 0 Auto Selection (Default)

1 1 AUI Port

Am79C961A 117

EE_EN, for detailed use of this

bit).

2 EECS EEPROM Chip Select. EECS

asserts the chip select to the

Serial EEPROM. (Refer to Bit 4

above, EE_EN, for detailed use

of this bit).

1 SK Serial Shift Clock. SK controls

the SK input to the Serial EE-

PROM and the optional External

Shift Logic. (Refer to Bit 4 above,

EE_EN, for detailed use of this

bit).

0 DI/DO Serial Shift Data In and Serial

Shift Data Out. When written,

this bit controls the DI input of

the serial EEPROM. When read,

this bi t represents th e DO value

of the seri al EEPRO M. (R ef er to

Bit 4 above, EE_EN, for detailed

use of this bit).

ISACSR4: LED0 Status (Link Integrity)

Bit Name Description

ISACSR4 is a non-programm-

able registe r that us es one bi t to

reflect the status of the LED0

pin. This pin defaults to twisted

pair MAU Link Status (LNKST)

and is not programmable.

15 LNKST 10BASE-T Link Status. LNKST

is a read-only bit that indicates

whether the Link Status LED is

asserted. When LNKST is read

as zero, the Link Status LED is

not asserted. When LNKST is

read as one, the Link Status LED

is asserted, indicating good

10BASE-T link integrity.

Note that the LNKST LED is

masked if the 10BASE-T port is

operating in Full Duplex mode,

AUIFD (ISACSR9, bit 1) is

cleared, and any one of the

FDLSE bits is set in ISACSR5,

6, or 7. Hence, an adapter card

with a 10BASE2 port (through

the AUI port) and a 10BASE-T

port that can be software

enabled for Half or Full Duplex

operation can have a Half

Duplex Link Status LED and a

Full Duplex Link Status LED in

which only one will be allowed

ON, depending on if FDEN

(ISACSR9, bit 0) is set. 14-0

RESReserved locations. Written

as zero, read as undefined.

14-0 RES Reserved locations. Written as

zero, read as undefined.

ISACSR5 : LED1 Status

Bit Name Description

ISACSR5 controls the function(s)

that the LED1 pin d isp lays. Mu lti-

ple functions can be simulta-

neously enabled on this LED pin.

The LE D display will indi cate the

logical OR of the enabled func-

tions. ISACSR5 defaults to

Receiv e S ta tus ( RC V) with pul se

stret cher enabl ed (PSE = 1) and

is fully programmable.

15 LEDOUT Indicates the current (non-

stre tche d) stat e o f t he function(s)

generated. Read only.

14-10 RES Reserved locations. Read and

written as zero.

9 MP Magic Packet LED Enable.

When set, the LED output will be

asserted to indicate that a Magic

Packet has been received.

8 FDLSE Full Duplex Link Status Enable.

Indicates the Full Duplex Link

Test Status. When this bit is set,

a va lue o f ONE is passed to the

LEDOUT signal when the PC-

net-ISA II is functioning in a link

pass state with Full Duplex ca-

pability. When the PCnet-ISA II

is not functioning in a link pass

state w ith Fu ll Dupl ex ca pab ili ty,

a value of ZERO is passed to the

LEDOUT signal.

When the 10BASE-T port is

active, a value of ONE is passed

to the LEDOUT signal whenever

the Link Test F unction (described

in the T-MAU section) detects a

Link Pass state and the FDEN

(ISACSR9, bit 0) bit is set. When

the AUI port is active, a value of

ONE is passed to the LEDOUT

signal whenever Full Duplex oper-

ation on the AUI port is enabled

(both FDEN and AUIFD bits in

ISACSR9 are set to ONE). When

the GPSI port is active, a value of

ONE is passed to the LEDOUT

signal whenever Full Duplex oper-

ation on the GPSI port is enabled

(FDEN bit in ISACSR9 is set to

ONE).

7 PSE Pulse Stretcher Enable. Extends

the LED illumination for each

enabled function occurrence.

118 Am79C961A

0 is disabled, 1 is enabled.

6 RES Reserved locations. Read and

written as zero.

5 RCVADDM Receive Address Match. This bit

when set allows for LED control

of only receive packets which

match internal address match.

4 XMT E Enable Transmit Status Signal.

Indicates P C ne t-ISA II c on troll er

transmit activity.

0 disables the signal, 1 enables

the signal.

3 RVPOL E Enable Receive Polarity Signal.

Enables LED pin assertion when

receiv e polarit y is correct on th e

10BASE-T port. Clearing the bit

indicates this function is to be

ignored.

2 RCV E Enable Receive Status Signal.

Indicates receive activity on the

network.

0 disables the signal, 1 enables

the signal.

1 JAB E Enable Jabber Signal. Indicates

the PCnet-ISA II controller is jab-

bering on the network.

0 disables the signal, 1 enables

the signal.

0 COL E Enable Collision Signal. Indi-

cates collision activity on the

network.

0 disables the signal, 1 enables

the signal.

ISACSR6: LED2 Status

Bit Name Description

ISACSR6 controls the func-

tion(s) that the LED2 pin dis-

plays. Multipl e functions can be

simultaneously enabled on this

LED pin. The LED display will

indicate the logical OR of the

enabled functions. ISACSR6

defaults to twisted pair MAU

Receive Polarity (RCVPOL)

with pulse stretcher enabled

(PSE = 1) and is fully program-

mable.

15 LEDOUT Indicates the current (non-

stretched) state of the func-

tion(s) generated. Read only.

14 LEDXOR This bit when set causes LED2

to be an activ e hig h si gna l whe n

asserted. When this bit is

cleare d, LED2 will be activ e low

when asserted.

Note: This bit when used in conjunction with the

RVPOLE bi t (Bit 3) of IS ACSR6 can be u se d t o cr eat e

a “Polarity Bad” LED.)

13-10 RES Reserved locations. Read and

written as zero.

9 MP Magic Packet LED Enable.

When set, the LED output will be

asserted to indicate that a Magic

Packet has been received.

8 FDLSE Full Duplex Link Status Enable.

Indicates the Full Duplex Link

Test Status. When this bit is set,

a va lue o f ONE is passed to the

LEDOUT signal when the PC-

net-ISA II is functioning in a link

pass state with Full Duplex ca-

pability. When the PCnet-ISA II

is not functioning in a link pass

state w ith Fu ll Dupl ex ca pab ili ty,

a value of ZERO is passed to the

LEDOUT signal.

When the 10BASE-T port is

active, a value of ONE is passed

to the LEDOUT signal whenever

the Link Test F unction (described

in the T-MAU section) detects a

Link Pass state and the FDEN

(ISACSR9, bit 0) bit is set. When

the AUI port is active, a value of

ONE is passed to the LEDOUT

signal whenever Full Duplex oper-

ation on the AUI port is enabled

(both FDEN and AUIFD bits in

ISACSR9 are set to ONE). When

the GPSI port is active, a value of

ONE is passed to the LEDOUT

signal whenever Full Duplex oper-

ation on the GPSI port is enabled

(FDEN bit in ISACSR9 is set to

ONE).

7 PSE Pulse Stretcher Enable. Extends

the LED illumination for each

enabled function occurrence.

0 is disabled, 1 is enabled.

6 RES Reserved locations. Read and

written as zero.

5 RCVAD DM Rece ive Ad dres s Mat ch. This bit

when set allows for LED control

RVPOLE LEDXOR Result

10BASE-T polarity function

ignored

LED2 pin low with “Good”

10BASE-T polarity (LED on)

LED 2 pin high wi th “Good”

10BASE-T polarity (LED off)

Am79C961A 119

of only receive packets that

match internal address match.

4 XMT E Enable Transmit Status Signal.

Indicates P C ne t-ISA II c on troll er

transmit activity.

0 disables the signal, 1 enables

the signal.

3 RVPOL E Enable Receive Polarity Signal.

Enables LED pin assertion when

receiv e polarit y is correct on th e

10BASE-T port. Clearing the bit

indicates this function is to be

ignored.

2 RCV E Enable Receive Status Signal.

Indicates receive activity on the

network.

0 disables the signal, 1 enables

the signal.

1 JAB E Enable Jabber Signal. Indicates

the PCnet-ISA II controller is jab-

bering on the network.

0 disables the signal, 1 enables

the signal.

0 COL E Enable Collision Signal. Indi-

cates collision activity on the

network.

0 disables the signal, 1 enables

the signal.

ISACSR7: LED3 Status

Bit Name Description

ISACSR7 controls the function(s)

that the LED3 pin disp la ys. Mult i-

ple functions can be simulta-

neously enabled on this LED pin.

The LED display will indicate the

logical OR of the enabled func-

tions. ISACSR7 defaults to

Transmit Status (XMT) with pulse

stret cher enabl ed (PSE = 1) and

is fully programmable.

15 LEDOUT Indicates the current (non-

stretched) state of the func-

tion(s) generated. Read only.

14-10 RES Reserved locations. Read and

written as zero.

9 MP Magic Packet LED Enable.

When set, the LED output will be

asserted to indicate that a Magic

Packet has been received.

8 FDLSE Full Duplex Link Status Enable.

Indicates the Full Duplex Link

Test Status. When this bit is set,

a value of ONE is passed to the

LEDOUT signal when the PC-

net-ISA II is functioning in a link

pass sta te wit h Full D upl ex capa-

bility. When the PCnet-ISA II is

not functioning in a link pass state

with Ful l Du pl ex cap ab i li ty, a v al-

ue of ZERO is passed to the

LEDOUT signal.

When the 10BASE-T port is

active, a value of ONE is passed

to the LEDOUT signal whenever

the Link Test F unction (described

in the T-MAU section) detects a

Link Pass state and the FDEN

(ISACSR9, bit 0) bit is set. When

the AUI port is active, a value of

ONE is passed to the LEDOUT

signal whenever Full Duplex oper-

ation on the AUI port is enabled

(both FDEN and AUIFD bits in

ISACSR9 are set to ONE). When

the GPSI port is active, a value of

ONE is passed to the LEDOUT

signal whenever Full Duplex oper-

ation on the GPSI port is enabled

(FDEN bit in ISACSR9 is set to

ONE).

7 PSE Pulse Stretcher Enable. Extends

the LED illumination for each

enabled function occurrence.

0 is disabled, 1 is enabled.

6 RES Reserved locations. Read and

written as zero.

5 RCVAD DM Rece ive Ad dres s Mat ch. This bit

when set allows for LED control

of only receive packets that

match internal address match.

4 XMT E Enable Transmit Status Signal.

Indicate s PC ne t-ISA II c on tr oller

transmit activity.

0 disables the signal, 1 enables

the signal.

Enable Receive Polarity Signal.

3 RVPOL E Enables LED pin assertion when

receiv e polarity i s correct on the

10BASE-T port. Clearing the bit

indicates this function is to be

ignored.

2 RCV E Enable Receive Status Signal.

Indicates receive activity on the

network.

0 disables the signal, 1 enables

the signal.

1 JAB E Enable Jabber Signal. Indicates

the PCnet-ISA II controller is jab-

bering on the network.

0 disables the signal, 1 enables

the signal.

120 Am79C961A

0 COL E Enable Collision Signal. Indi-

cates collision activity on the

network.

0 disables the signal, 1 enables

the signal.

ISACSR8: Software Configuration Register

(Read-Only Register)

ISACSR9: Miscellaneous Configuration 2

Bit Name Description

1 AUIFD AUI Full Duplex. AUIFD controls

whether Full Duplex operation

on the AUI port is enabled.

AUIFD is only meaningful if

FDEN (ISA CSR9, b it 0) is set t o

ONE. If the FDEN bit is ZERO,

the AUI port will always operate

in Half Duplex mode. In addition,

if FDEN is set to ONE but the

AUIFD bit is reset to ZER O, the

AUI port will always operate in

Half Duplex mode. If FDEN is set

to ONE and AUIFD is set to

ONE, Full Duplex operation on

the AUI port is enabled.

AUIFD is read/write accessible

always. It is reset to ZERO by

the RESE T pin, and i s unaffect-

ed by read ing the Reset r eg ister

or setting the STOP bit.

0 FDEN Full Duplex Ena ble. FDEN con-

trols whether Full Duplex opera-

tion is enabled. When FDEN is

cleared, Full Duplex operation

is not enabled and the PC-

net-ISA II will al ways o perate i n

the Half Duplex mode. When

FDEN is set, the PCnet-ISA II

will operate in Full Duplex mode

when the 10BASE-T or GPSI

port is enabled or when the AUI

port is enabled and the AUIFD

(ISACSR9, bit 1) bit is set. Note

that Full Duplex operation will

not be enabled on the

10BASE-T port if DLNKST

(CSR15, bit 12) is set.

FDEN is read/write accessible

always. It is reset to ZERO by

the RESE T pin, and i s unaffect-

ed by reading the Reset register

or setting the STOP bit.

Initialization Block

The figure below shows the Initialization Block memory

configuration. Note that the Initialization Block must be

based on a word (16-bit) boundary.

RLEN and TLEN

The TLEN and RLEN fields in the initialization block are

3 bits wide, occup ying bits 15,14, and 13, and the value

in these fields determines the number of Transmit and

Receive Descriptor Ring Entries (DRE) which are used

in the descriptor rings. Their meaning is as follows:

If a value other than those listed in the above table is

desired, CSR76 and CSR78 can be written after initializa-

tion is complete. See the description of the appropriate

CSRs.

Bit Description

15-12 Read-only image of SRAM(3:0) of PnP register

0x48-0x49.

11-8 Read-only image of BPAM(3:0) of Pn P register

0x40-0x41.

7-4 Read-only image of IRQSEL(3:0) of PnP

Read only bit indicating w hether the SRAM is

activated as a memory resource. Set when the

Shared Memory is not activated as an ISA

memory resou rce.

2-0 Read-only image of DMASEL(2:0) of PnP

Address Bits

15–12 Bits

11–8Bits

7–4Bits

3–0

IADR+00 MODE 15–00

IADR+02 PADR 15–00

IADR+04 PADR 31–16

IADR+06 PADR 47–32

IADR+08 LADRF 15–00

IADR+10 LADRF 31–16

IADR+12 LADRF 47–32

IADR+14 LADRF 63–48

IADR+16 RDRA 15–00

IADR+18 RLEN RES RDRA 23–16

IADR+20 TDRA 15–00

IADR+22 TLEN RES TDRA 23–16

R/TLEN # of DREs

000 1

001 2

010 4

011 8

100 16

101 32

110 64

111 128

Am79C961A 121

RDRA and TDRA

TDRA and RDRA indicate where the transmit and

receive descriptor rings, respectively, begin. Each DRE

must be located on an 8-byte boundary.

LADRF

The Logical Address Filter (LADRF) is a 64-bit mask

that is used to accept incoming Logical Addresses. If

the fir st bit in the incom ing a ddress (as t ransmitted on

the wire) is a “1", the addre ss is dee med log ical. If th e

first bit is a “0", it is a physical address and is compared

against the physical address that was loaded through

the initialization block.

A logic al address is passed throu gh the CRC genera-

tor, producing a 32-bit result. The high order 6 bits of

the CRC are used to select on e of the 64 bit positions

in the Log ical Address Filte r. If the s elected filte r bi t is

set, the address is accepted and the frame is placed

into memory.

The Logical Address Filter is used in multicast addressing

sche mes. The a cceptan ce of th e inco ming fram e based

on the filter value indicates that the message may be

intended for the node. It is the node’s responsibility to

determine if the message is actually intended for the node

by comparing the destination address of the stored mes-

sage with a list of acceptab le logi cal a ddresses .

If the Logical Address Filter is loaded with all zeroes

and promiscuous mode is disabled, all incoming logical

addresses except broadcast will be rejected.

The Broadc as t add ress, whi ch is all on es, does not g o

through the Logical Address Filter and is handled as

follows:

7. If the Disable Broadcast Bit is cleared, the

broadcast address is accepted.

8. If the Disable Broadcast Bit is set and promiscuous

mode is enabled, the broadcas t addr ess is

accepted.

9. If the Disable Broadcast Bit is set and promiscous

mode is disabled, the broadcast address is

rejected.

If external loopback is used, the FCS logic must be

allocated to the receiver (by setting the DXMTFCS bit

in CSR15, and clearing the ADD_FCS bit in TMD1)

when using multicast addressing.

PADR

This 48-bit value represents the unique node address

assigned by the IEEE and used for internal address

comparison. PADR[0] is the first address bit transmit-

ted on the wire, and must be zero . The six-hex-byte no-

menclature used by the IEEE maps to the PCnet-ISA II

controlle r PADR registe r as follows: the first byte com-

pri ses PADR[7: 0], w ith PADR[0 ] be ing th e leas t s ig nifi-

cant bit of the byte. The second IEEE byte maps to

PADR[15:8], again from LSbit to MSbit, and so on. The

sixth byte maps to PADR[47:40], the LSbit being

PADR[40].

MODE

The mode register in the initialization block is copied

into CSR15 and inter preted according to the descrip-

tion of CSR15.

CRC

GEN

SEL

47 1 0 31 26 0

63 0

MUX

MATCH = 1: Packet Accepted

MATCH = 0: Packet Rejected

MATCH

Logical

Address

Filter

(LADRF)

Received Message

Destination Address 32-Bit Resultant CRC

Address Match Logic 19364B-23

122 Am79C961A

Recei ve De sc riptors

The Receive Descriptor Ring Entries (RDREs) are

composed of four receive message fields (RMD0-3).

Together they contain the following information:

■The address of the actual message data buffer in

user (host) memory

■The length of that message buffer

■Status information indicating the condition of the

buffer. The eight most significant bits of RMD1

(RMD1[15:0]) are collectively termed the STATUS

of the receive descriptor.

RMD0

Holds LADRF [15:0]. This is combined with HADR [7:0]

in RMD1 to form the 24-bit address of the buffer

pointed to by this descriptor table entry. There are no

restrictions on buffer byte alignment or length.

RMD1

Bit Name Description

15 OWN This bit indicates that the descrip-

tor entry is owned by the host

(OWN =0) or b y the PC net-ISA I I

controller (OWN=1). The PCnet-

ISA II controller clears the OWN

bit after filling the buffer pointed

to by the descriptor entry. The

host sets the OWN bit after emp-

tying the buffer. Once the PC-

net-ISA II controller or host has

relin qui shed owne rs hip o f a b uff-

er, it must not change any field in

the descriptor entry.

14 ERR ERR is the OR of FRAM, OFLO,

CRC, or BUFF. ERR is written

by the PCnet-ISA II controller.

13 FRAM FRAMING ERROR indicates

that the incoming frame con-

tained a non-integer multiple of

eight bits and there was an FCS

error. If there was no FCS error

on the incoming frame, then

FRAM will not be set even if

there was a no n intege r multi ple

of eight bi ts in the frame . FRAM

is not valid in internal loopback

mode. FRAM is valid only whe n

ENP is set and OFLO is not.

FRAM is written by the PC-

net-ISA II controller.

12 OFLO OVERFLOW error indicates that

the re ceiv er has l ost all or part of

the incoming frame, due to an

inability to store the frame in a

memory buffer before the inter-

nal FIFO overflowed. OFLO is

valid only when ENP is not set.

OFLO is written by the PC-

net-ISA II controller.

11 CRC CRC indicates that the receiver

has detected a CRC (FCS) error

on the incoming frame. CRC is

valid only when ENP is set and

OFLO is not. CRC is written by

the PCnet-ISA II controller.

10 BUFF BUFFER ERROR is set any time

the PCnet-ISA II controller does

not own the next buffer while

data chaining a received frame.

This can occur in either of two

ways:

1) The OWN bit of the next

buffer is zero

2) FIFO overflow occurred

before the PCnet-ISA II

controller polled the next

descriptor

If a Buffer Error occurs, an Over-

flow Error may also occur inter-

nally i n the FIFO, but w ill not be

reported in the descriptor status

entry unless both BUFF and

OFLO errors occur at the same

time. BUFF is written by the PC-

net-ISA II controller.

9 STP START OF PACKET indicates

that this is the first buffer used by

the PCnet-ISA II controller for

this frame. It is used for data

chaining buffers. STP is written

by the PCnet-ISA II controller in

normal operation. In SRPINT

Mode (CSR3.5 set to 1) this bit is

written by the driver.

8 ENP END OF PACKE T indic ates tha t

this is the last buffer used by the

PCnet-ISA II controller for this

frame. It is used for data chain-

ing buffers. If both STP and ENP

are set, the frame fits into one

buffer and there is no data chain-

ing. ENP is written by the PC-

net-ISA II controller.

7-0 HADR The HIGH ORDER 8 address

bits of the buffer pointed to by

this descriptor. This field is writ-

ten by the host and is not

changed by the PCnet-ISA II

controller.

RMD2

Bit Name Description

15-12 ONES MUST BE ONES. This field is

written by the host and

Am79C961A 123

unchanged by the PCnet-ISA II

controller.

11-0 BCNT BUFFER BYTE COUNT is the

length of the buffer pointed to by

this descriptor, expressed as the

two’s complement of the length

of the buffe r. This fiel d is writte n

by the host and is not changed

by the PCnet-ISA II controller.

RMD3

Bit Name Description

15-12 RES RESERVED and read as zeros.

11-0 MCNT MESSAGE BYTE COUNT is the

length in bytes of the received

message, expressed as an un-

signed binary integer. MCNT is

valid only when ERR is clear and

ENP is set. MCNT is written by

the PCnet-ISA II controller and

cleared by the host.

MCNT Includes: DEST + SRC +

Length + Data + CRC unless the

auto strip on receive bit is set. In

this case, t he Pad and CRC are

thrown away by the controller.

Transmit Descriptors

The Transmit Descriptor Ring Entries (TDREs) are

composed of four transmit message fields (TMD0-3).

Together they contain the following information:

■The address of the actual message data buffer in

user or host memory

■The length of the message buffer

■Status information indicating the condition of the

buffer. The eight most significant bits of TMD1

(TMD1[15:8]) are collectively termed the STATUS

of the transmit descriptor .

Note that bit 13 of TMD1, which was formerly a

reserved bit in the LANCE (Am7990), is assigned a

new meaning, ADD_FCS.

TMD0

Holds LAD R [15:0]. This is comb ined with HADR [7:0 ]

in TMD1 to fo rm a 24-bit address of the buffe r pointed

to by this descriptor table entry. There are no restric-

tions on b uffer byte alignment or length.

TMD1

Bit Name Description

15 OWN This bit indicates that the

descripto r entry is owne d by the

host (OWN=0) or by the PC-

net-ISA II controller (OWN=1).

The host s ets the OWN bit after

filling the buffer pointed to by the

descriptor entry. The PCnet-ISA

II controller clears the OWN bit

after transmitting the contents of

the buffer. Both the PCnet-ISA II

controlle r and the hos t must not

alter a descriptor entry after it

has relinquished ownership.

14 ERR ERR is the OR of UFLO, LCOL ,

LCAR, or RTRY. ERR is written

by the PCnet-ISA II controller.

This bit is set in the current de-

scriptor when the error occurs,

and the refore may b e set in any

descriptor of a chained buffer

transmission.

13 ADD_FCS ADD_FCS dynamically controls

the generation of FCS on a

frame by frame basis. It is valid

only if the STP bit is set. When

ADD_FCS is set, the state of

DXMTFCS i s ign ored and trans-

mitter FCS generation is activat-

ed. When ADD_FCS = 0, FCS

generation is controlled by

DXMTFCS. ADD_FCS is written

by the host, and unchanged by

the PC net-ISA II co ntroller. This

was a reserved bit in the LANCE

(Am7990).

12 MORE MORE indicates that more than

one re-try was needed to trans-

mit a fr ame. MORE is wri tten by

the PC net-ISA II co ntroller. This

bit has meaning on ly if the ENP

or the ERR bit is set.

11 ONE ONE indicates that exactly one

re-try was needed to transmit a

frame. ONE flag is not valid

when LCOL is set. ONE is writ-

ten by the PCnet-ISA II control-

ler. This bit has meaning only if

the ENP or the ERR bit is set.

10 DEF DEFERRED indicates that the

PCnet-ISA II controller had to

defer while trying to transmit a

frame. This condition occurs if

the channel is busy when the

PCnet-ISA II controller is ready

to transmit. DEF is written by the

PCnet-ISA II controller. This bit

has meaning only if the ENP or

ERR bits are set.

124 Am79C961A

9 STP START OF PACKET indicates

that this is the first buffer to be

used by the PCnet-ISA II con-

troller for this frame. It is used for

data chaining buffers. The STP

bit must be s et in the first buf fer

of the frame, or the PCnet-ISA II

controller will skip over the

descriptor and poll the next

descriptor(s) until the OWN and

STP bits are set.

STP is written by the host and is

not changed by the PCnet-ISA II

controller.

8 ENP END OF PACKET indicates that

this is the last buffer to be used

by the PCnet-ISA II cont r ol le r f or

this frame. It is used for data

chaining buffers. If both STP and

ENP are set, the frame fits into

one buffer and there is no data

chaining. ENP is written by the

host and is not changed by the

PCnet-ISA II controller.

7-0 HADR The HIGH ORDER 8 address

bits of the buffer pointed to by

this descriptor. This field is writ-

ten by the host and is not

changed by the PCnet-ISA II

controller.

TMD2

Bit Name Description

15-12 ONES MUST BE ONES. This field is

written by the host and

unchanged by the PCnet-ISA II

controller.

11-0 BCNT BUFFER BYTE COUNT is the

length of the buffer pointed to by

this descriptor, expressed as the

two’s complement of the length

of the b uffer. T his is the numb er

of bytes from this buffer th at will

be transmitted by the PCnet-ISA

II controller. This field is written

by the host and is not changed

by the PCnet-ISA II controller.

There are no minimum buffer

size restrictions. Zero length

buffers a re all owe d for pr oto co ls

which require it.

TMD3

Bit Name Description

15 BUFF BUFFER ERROR is set by the

PCnet-ISA II controller during

transmission when the PC-

net-ISA II controller does not find

the ENP flag in the current buffer

and does not own the ne xt buff-

er. This can occur in either of two

ways:

1) The OWN bit of the next

buffer is zero.

2) FIFO underflow occurred

before the PCnet-ISA II

controlle r obtaine d the

next STATUS byte

(TMD1[15:8]).

BUFF error will turn off the

transmitter (CSR0, TXON = 0),

if DXSUFLO = 0 (bit 6 CSR3). If

a Buffer Error occurs, an

Underflow Error will also occur.

BUFF is not valid when LCOL

or RTRY error is set during

transmit data chaining. BUFF

is written by the PCnet-ISA II

controller.

14 UFLO UNDERFLOW ERROR indi-

cates that the transmitter has

truncated a message due to

data late from memory. UFLO

indicates that the FIFO has emp-

tied before the end of the frame

was reache d. Upo n UFLO err or,

the transmitter is turned off

(CSR0, TXON = 0), if DXSUFLO

= 0 (bit 6 CSR3). UFLO is written

by the PCnet-ISA II controller.

13 RES R ESERVED bit. The PCnet-ISA

II controlle r will write thi s bit wit h

a “0".

12 LCOL LATE COLLISION indicates that

a collision has occurred after the

slot time of the channel has

elapsed. The PCnet-ISA II con-

troller does not re-try on late col-

lisions. LCOL is written by the

PCnet-IS A II control le r.

11 LCAR LOSS OF CARRIER is set in

AUI mode when the carrier is

lost duri ng an PCnet-ISA II con-

troller- initiated transmission.

The PCnet-ISA II controller does

not stop transmission upon loss

of carrier. It will continue to

transmit the whole frame until

done. LCAR is written by the

PCnet-IS A II control le r.

In 10BASE-T mode, LCAR will

be set when the T-MAU is in link

fail state.

10 RTRY RETRY ERROR indicates that

the transmitter has failed after

16 attempts to successfully

transmit a message, due to

repeated collisions on the

Am79C961A 125

medium. If DRTY = 1 in the

MODE register, RTRY will set

after one failed transmission at-

tempt. RTRY is written by the

PCnet-ISA II controller.

09-00 TDR TIME DOMAIN REFLECTOME-

TRY reflects the state of an inter-

nal PCnet-ISA II controller

count er tha t c ou nts at a 10 MHz

rate from the start of a transmis-

sion to t he o ccurr ence of a co lli-

sion or loss of carrier. This value

is useful in determining the

approx imate dis tance to a cable

fault. The TDR value is written

by the PCnet-ISA II controller

and is valid only if RTRY is set.

Note that 10 MHz gives very low

resolution and in general has not

been found to be particularly

useful. This feature is here

primarily to maintain full compat-

ibility with the LANCE.

126 Am79C961A

Ethernet Controller Registers (Accessed via RDP Port)

RAP Addr Symbol Width User Register Comments

00 CSR0 16-bit Y PCnet-ISA II controller status

01 CSR1 16-bit Y Lower IADR: maps to location 16

02 CSR2 16-bit Y Upper IADR: maps to location 17

03 CSR3 16-bit Y Mask Register

04 CSR4 16-bit Y Miscellaneous Register

05 CSR5 16-bit Reserved

06 CSR6 16-bit RXTX: RX/TX Encoded Ring Lengths

07 CSR7 16-bit Reserved

08 CSR8 16-bit Y LADR0: LADRF[15:0]

09 CSR9 16-bit Y LADR1: LADRF[31:16]

10 CSR10 16-bit Y LADR2: LADRF[47:32]

11 CSR11 16-bit Y LADR3: LADRF[63:48]

12 CSR12 16-bit Y PADR0 : PADR[15:0]

13 CSR13 16-bit Y PADR1: PADR[31:16]

14 CSR14 16-bit Y PADR2: PADR[47:32]

15 CSR15 16-bit Y MODE: Mode Register

16-17 CSR16 32-bit IADR: Base Address of INIT Block

18-19 CSR18 32-bit CRBA: Current RCV Buffer Address

20-21 CSR20 32-bit CXBA: Current XMT Buffer Address

22-23 CSR22 32-bit NRBA: Next RCV Buffer Address

24-25 CSR24 32-bit Y BADR: Base Address of RCV Ring

26-27 CSR26 32-bit NRDA: Next RCV Descriptor Address

28-29 CSR28 32-bit CRDA: Current RCV Desc riptor Address

30-31 CSR30 32-bit Y BADX: Base Address of XMT Ring

32-33 CSR32 32-bit NXDA: Next XMT Descriptor Address

34-35 CSR34 32-bit CXDA: Current XMT Descriptor Address

36-37 CSR36 32-bit Ne xt Next Receiv e De sc riptor Addre ss

38-39 CSR38 32-bit Ne xt Next Transm it Desc riptor Addre ss

40-41 CSR40 32-bit CRBC: Current RCV Stat and Byte Count

42-43 CSR42 32-bit CXBC: Current XMT Status and Byte Count

44-45 CSR44 32-bit NRBC: Next RCV Stat and Byte Count

46 CSR46 16-bit POLL: Poll Time Counter

47 CSR47 32-bit Y Polling Interval

48-49 CSR48 32-bit TMP0: Temporary Storage

50-51 CSR50 32-bit TMP1: Temporary Storage

52-53 CSR52 32-bit TMP2: Temporary Storage

54-55 CSR54 32-bit TMP3: Temporary Storage

56-57 CSR56 32-bit TMP4: Temporary Storage

58-59 CSR58 32-bit TMP5: Temporary Storage

60-61 CSR60 32-bit PXDA: Previous XMT Des criptor Address

62-63 CSR62 32-bit PXBC: Previous XMT Status and Byte Count

Am79C961A 127

Ethernet Controller Registers (Accessed via RDP Port)

Note:

Although the PCnet-ISA II co ntrolle r has man y registers that can be ac cess ed b y softw are , most of thes e registe rs are inten ded

for debugging and production testing purposes only. The registers with a "Y" are the only registers that should be accessed by

network software.

RAP Addr Symbol Width User Register Comments

64-65 CSR64 32-bit NXBA: Next XMT Buffer Address

66-67 CSR66 32-bit NXBC: Next XMT Status and Byte Count

68-69 CSR68 32-bit XSTMP: XMT Status Temporary

70-71 CSR70 32-bit RSTMP: RCV Status Temporary

72 CSR72 16-bit RCVRC: RCV Ring Counter

74 CSR74 16-bit XMTRC: XMT Ring Counter

76 CSR76 16-bit Y RCVRL: RCV Ring Length

78 CSR78 16-bit Y XMTRL: XMT Ring Length

80 CSR80 16-bit Y DMABR: Burst Register

82 CSR82 16-bit Y DMABAT: Bus Activity Timer

84-85 CSR84 32-bit DMABA: Address Register

86 CSR86 16-bit DMABC: Byte Counter/Register

88-89 CSR88 32-bit Y Chip ID Register

92 CSR92 16-bit RCON: Ring Length Conver sion Register

94 CSR94 16-bit XMTTDR: Transmit Time Domain Reflectometry

96-97 CSR96 32-bit SCR0: BIU Scratch Register 0

98-99 CSR98 32-bit SCR1: BIU Scratch Register 1

104-105 CSR104 32-bit SWAP:16-bit Word/Byte Swap Register

108-109 CSR108 32-bit BMSCR: BMU Scratch Register

112 CSR112 16-bit Y Missed Frame Count

114 CSR114 16-bit Y Receive C oll is ion Coun t

124 CSR124 16-bit Y BMU Test Register

126 CSR126 16-bit Reserved

128 Am79C961A

ISACSR—ISA Bus Configuration Registers (Accessed via IDP Port)

* This value can be 0000H for systems that do not support EEPROM option

I/O Address Offset

RAP Addr M n emonic Default Name

0 MSRDA 0005H Master Mode Read Active

1 M SWRA 0005H Master Mode Write Active

2 MC 0002H Miscellaneous Configuration

3 EC 8000* H EEPROM Configura tio n

4 LED0 0000H LED0 Status (Link Integrity)

5 LED1 0084H LED1Status (Default: RCV)

6 LED2 0008H LED2 Status (Default: RCVPOL)

7 LED3 0090H LED3 Status (Default: XMT)

8 SC 0000H Software Configuration (Read-Only Re gister)

9 DUP 0000H Full/Half Duplex Conditions (Default: Half

Duplex)

Offset #Bytes Register

0h 16 Address PR O M

10h 2 RDP

12h 2 RAP(shared by RDP and IDP)

14h 2 Reset

16h 2 IDP

Am79C961A 129

SYSTEM APPLICATION

ISA Bus Interfac e

Compatibility Considerations

Although 8 MHz is now widely accepted as the standard

speed at which to run the ISA bus, many machines hav e

been built which operate at higher speeds with non-stan-

dard timing. Some machines do not correctly suppor t

16-bit I/O operations with wait states. Although the PC-

net-ISA II controller is quite fast, some operations still re-

quire an occasional wait state. The PCnet-ISA II

contr oller m ov es da ta thr ough memo ry accesses , ther e-

fore, I/O operations do not affect performance. By con-

figuring the PCnet-ISA II controller as an 8-bit I/O device,

compatibility with PC/AT-class machines is obtained at

virt ua ll y no co st in perfor ma nc e. To trea t th e P C ne t-IS A

II controller as an 8-bit software resource (for non-ISA

applications), the even-byte must be accessed first,

followed by an odd-byte access.

Memor y cy cle timing is an area where so me tradeoffs

may be necessar y. Any slow down in a memor y cycle

translates directly into lower bandwidth. The PC-

net-ISA II cont roller starts ou t with muc h higher band-

width than most slave type controllers and should

continue to be superior even if an extra 50 or 100 ns

are added to memory cycles.

The memory cycle active time is tunable in 50 ns incre-

ments with a default of 250 ns. The memory cycle idle

time defaults to 200 ns and can be reprogrammed to

100 ns. See register description for ISACS42. Most

machines should not need tuning.

The PCnet-ISA II controller is compatible with NE2100

and NE1 500T softwa re dr ivers. All the reso urce s suc h

as addr ess P ROM, boot PROM, RAP, and RDP are in

the same location with the same semantics. An addi-

tional se t of registers (IS A CSR) is availa ble to config-

ure on board resources such as ISA bus timing and

LED operatio n. However, l oopback frames for the PC-

net-ISA II controller must contain more than 64 bytes of

data if the Runt Packet Accept feature is not enabled;

this size limitation does not apply to LANCE (Am7990)

based boards such as the NE2100 and NE1500T.

Bus Master

Bus Master mode is the preferred mode for client appli-

cations on PC/AT or similar machines supporting 16-bit

DMA with i ts unsu rpas sed co mbination of h igh perfor-

mance and low cost.

Shared Memory

The shared memory mode is recommended for file

ser vers or other appl ication s where there is ve r y high,

average or peak latency.

The address compare circuit has the following func-

tions. It receives the 7 LA signals, generates

MEMCS16, and c omp ares the m to the desire d s ha red

memory and boot PROM addresses. The logic latches

the addres s compare result when BALE goes inact ive

and uses the appropriate SA signals to generate

SMAM and BPAM.

All these functions can be performed in one PAL

device. To o perate in an 8-bit PC/XT environment, th e

LA sign als should h ave weak pull-d own resist ors con-

nected to them to present a logic 0 level when not

driven.

130 Am79C961A

D[0–7]

A[0–15]

ORG

SD[0–15]

ISA

Bus

16-Bit System Data

24-Bit System

Address

PCnet-ISA II

Controller

Boot

PROM

EEPROM

VCC

PRDB[2]/EEDO

PRDB[1]/EEDI

PRDB[0]/EESK

PRDB[0-7]

SA[0–19]

LA[17–23]

BPCS

SHFBUSY

CE OE

EECS

Bus Master Block Diagram Plug and Play Compatible 19364B-24

SD[0–15]

SA[0]

LA[17–23]

D[0–7]

A[0–4]

EECS

ORG

D[0–7]

A[0–15] WE

ISA

Bus

24-Bit

System

Address

PCnet-ISA II

Controller

IEEE

Address

PROM

EEPROM

Flash

PRDB[0]/EESK

PRDB[1]/EEDI

PRDB[2]/EEDO

16-Bit

System

Data

VCC

IRQ15/ IRQ12/FlashWE

OE CS

BPCS

PRDB[0]

SHFBUSY

Bus Master Block Diagram Plug and Play Compatible with Flash Support 19364B-25

Am79C961A 131

A[0–15]

0VCC

ISA

Bus

PCnet-ISA II

Controller

Boot

PROM

SRAM

EEPROM

PRDB[2]/EEDO

PRDB[1]/EEDI

PRDB[0]/EESK

D[0-7]

A[0-15]

D[0-7]

WE CS

BPAM

SMAM

SA[16]

MEMCS16

External

Glue

Logic

SHFBUSY

CLK

SIN

16-Bit

System Data

24-Bit System

Address

SRWE

PRAB(0:15)

LA[17-23]

VCC

SROE

BPCS

PRDB[0–7]

EECS

SD[0–15]

SA[0–15]

SMAM

SHFBUSY

BPAM

ORG

Shared Memory Block Diagram Plug and Play Compatible 19364B-26

132 Am79C961A

Optional Address PROM Interface

The suggested address PROM is the Am27LS19, a

32x8 device. APCS should be connected directly to the

device’s G input.

Boot PROM Interface

The boot PROM is a 8K –64K EPROM. Its OE pin

should be tied to ground, and chip enab le CE to BP CS

to minimize power consumption at the expense of

speed. Shown below is a 27C128.

Higher d ensity EP ROMs place an ad dress line o n the

pin that is defined for lower density EPROMs as the

VPP (programming voltage) pin. For READ only opera-

tion on an E PROM, the VPP pin ca n assume any logic

level, as long as the voltage on the VPP pin does not

exceed the programming voltage threshold (typically

7 V to 12 V). Therefore, a socket with a 27512 pinout

will also support 2764 and 27128 EPROM devices.

BPCS

PRDB[0–7]

ORG

FLASH

EEPROM

SRAM

External

Glue

Logic

EECS

ISA

Bus

24-Bit System

Address

PCnet-ISA II

Controller PRDB[2]/EEDO

PRDB[1]/EEDI

PRDB[0]/EESK

16-Bit

System Data

PRAB[0-15]

IRQ12/SRCS

VCC

D[0-7]

A[0-15]

MEMCS16

SA[16] LA[17-23]

VCC

SRWE

SROE

BPAMSRAMSHFBUSY

SIN

CLK

BPAM

SRAM

SHFBUSY

SA[0–19]

SD[0–15]

Shared Memory Block Diagram Plug and Pla y Compatible with Flash Memory Support

19364B-27

27LS19

32 x 8 PROM

A4–A0

Q7–Q0

Address PROM Example

19364B-28

Am79C961A 133

Static RAM Interface (for Shared Memory

Only)

The SRAM is an 8Kx8 or 32Kx8 device. The PCnet-ISA

II controller can support 64 Kbytes of SRAM address

spac e. T he PCne t-ISA II con troll er pro vid es SR OE and

SRWE outputs which can go directly to the OE and

pins of the SRA M, respectively. The add ress lines ar e

connected as described in the shared memory section

and the data lines go to the Private Data Bus.

AUI

The PCnet-ISA II controller drives the AUI through a set

of transformers. The DI and CI inputs should each be

terminated with a pair of matched 39 Ω or 40.2 Ω resis-

tors connected in series with the middle node bypassed

to grou nd w it h a. 01 µF to 0.1 µF capacito r. Refe r to the

PCnet-ISA Technical Manual (PID #16850B) for network

interface design and refer to Appendix A for a list of

compatible A UI isolation transf ormers.

EEPROM Interface

The suggested EEPROM is the industry standard

93C56 2 Kbit serial EEPROM. This is used in the 16-bit

mode to provide 128 x 16-bit EEPROM locations to

store configuration information as well as the Plug and

Play informa tion.

10BASE-T Interface

The diag ram b elow sho ws the proper 10BASE-T n etwork

interface design. Refer to the PCnet Family Technical

Manual (PID #1 821 6A) for mor e design det ai ls, and refer

to Appendix A for a list of compatible 10BASE-T filter/

transf ormer modules.

27C128

16K x 8 EPROM

A13–A0

DQ7–DQ0

19364B-29

93C56

VCC

EECS

PRDB2/EEDO

PRDB1/EEDI

PRDB0/EESK

CLK

ORG

Boot PROM Example

19364B-30

XMT

Filter

RCV

Filter

RJ45

Connector

Filter &

Transformer

Module

TXP+

TXD-

TXP-

TXD+

RXD+

RXD-

PCnet-ISA II TD+

TD-

RD+

RD-

61.9

422.0

61.9

422.0

100

1.21 K

1:1

Controller

10BASE-T External Components and Hookup 19364B-31

134 Am79C961A

ABSOLUTE MAXIMUM RATINGS

Storage Temperature . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . .

Under Bias . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

Supply Voltage to AVss

or DVSS (AVDD, DVDD). . . . . . . . . . . –0.3 V to +6.0 V

Stresses above those listed under Absolute Maximum Rat-

ings may cause permanent device failure. Functionality at or

above these limits is not implied. Exposure to Absolute Max-

imum Ratings f or e xtend ed periods ma y aff ec t dev ice reliabi l-

ity. Programming conditions may differ.

OPERATING RANGES

Commercial (C) Devices

Ambient Tempe rature (TA) . . . . . . . . . . . 0°C to+70°C

Industrial (I) Devices

Ambient Tempe rature (TA) . . . . . . . . . –40°C to+85°C

VCC Supply Voltages. . . . . . (AVDD, DVDD) 5 V ±5%

All inputs within the range: . . AVSS – 0.5 V ≤ VIN ≤

AVDD + 0.5 V, or

DVSS – 0.5 V ≤ VIN ≤

DVDD + 0.5 V

Opera ting range s define those li mits between w hich the func-

tionality of the device is guaranteed.

DC CHARACTERISTICS (Unless otherwise noted, parametric values are the same

between Commer cial devices and Industrial devices)

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

Digital Input Voltage

VIL Input LOW Voltage 0.8 V

VIH Input HIGH Voltage 2.0 DVDD + 0.5 V

Digital Output Voltage

VOL O utp ut LOW Voltage 0.5 V

VOH Output HIGH Voltage (Note 1) 2.4 V

Digital Input Leaka ge Current

IIX Input Leakage Current VDD = 5 V, VIN = 0 V

(Note 2) –10 10 µA

Digital Output Leakage Current

IOZL Output Low Leakage Current

(Not e 3) VOUT = 0 V –10 µA

IOZH Outp ut High Leakage Current

(Not e 3) VOUT = VDD 10 µA

Crystal Input Current

VILX XTAL1 Input LOW Threshold

Voltage VIN = Exter nal Clock –0.5 0.8 V

VILHX XTAL1 Input HIGH Threshold

Voltage VIN = Exter nal Clock 3.5 VDD + 0.5 V

IILX XTAL1 Input LOW Current VIN = DVSS Active –120 0 µA

Sleep –10 +10 µA

IIHX XTAL1 Input HIGH Current VIN = VDD Active 0 120 µA

Sleep 400 µA

Attachment Unit Interface

IIAXD Input Current at DI+ and DI–AVSS < VIN < AVDD –500 +500 µA

IIAXC Input current at CI+ and CI–AVSS < VIN < AVDD –500 +500 µA

VAOD Diff er ential Output Voltage |( DO+)–

(DO–)| RL = 78 Ω630 1200 mV

Am79C961A 135

DC CHARACTERISTICS (continued)

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

Attachment Unit Interface (continued)

VAODOFF Transmit Differential Output Idle

Voltage RL = 78 Ω–40 +40 mV

IAODOFF Transmit Differential Output Idle

Current RL = 78 Ω (Note 4) –1+1mA

VCMT Transmit Output Common Mode

Voltage RL = 78 Ω2.5 AVDD V

VODI DO± Transmit Differential Output

Voltage Im balance RL = 78 Ω (Note 5) 25 mV

VATH Receive Data Differential Input

Threshold (Note 5) –35 35 mV

VASQ DI± and CI± Differential Input

Threshold (Squelch) –275 –160 mV

VIRDVD DI± and CI± Differential Mode Input

Voltage Range –1.5 +1.5 V

VICM DI± and CI± Input Bias Vo ltage IIN = 0 mA AVDD–3.0 AVDD–1.0 V

VOPD

DO± Undershoot Voltage at Zero

Differential on Transmit Return to

Zero (ETD) (Note 5) –100 mV

Twisted Pair Interface

IIRXD Input Current at RXD±AVSS < VIN < AVDD –500 500 µA

RRXD RXD± Diff eren tia l Input Resi stanc e (N ote 5) 10 KΩ

VTIVB RXD+, RXD– Open Circuit Input

Voltage (Bias) IIN = 0 mA AVDD – 3.0 AVDD – 1.5 V

VTIDV Differential Mode Input Voltage

Range (RXD ±)AVDD = +5 V –3.1 +3.1 V

VTSQ+RXD Positive Squelch Threshold

(Peak) Sinusoid

5 MHz ≤ f ≤10 MHz 300 520 mV

VTSQ–RXD Negative Squelch Threshold

(Peak) Sinusoid

5 MHz ≤ f ≤10 MHz –520 –300 mV

VTHS+ RXD Post-Squelch

Positive Threshold (Peak) Sinusoid

5 MHz ≤ f ≤10 MHz 150 293 mV

VTHS–RXD Post-Squelch

Negative Threshold (Peak) Sinusoid

5 MHz ≤ f ≤10 MHz –293 –150 mV

VLTSQ+ RXD Positive Squelch Threshold

(Peak) LRT = 1 (Note 6) 180 312 mV

VLTSQ–RXD Negative Squelch Threshold

(Peak) LRT = 1 (Note 6) –312 –180 mV

VLTHS+ RXD Post-Squelch Positive

Threshold (Peak) LRT = 1 (Note 6) 90 156 mV

VLTHS–RXD Post-Squelch Negative

Threshold (Peak) LRT = 1 (Note 6) –156 –90 mV

136 Am79C961A

DC CHARACTERISTICS (continued)

1. VOH does not apply to open-drain output pins.

2. IIX applies to all input only pins except DI+, CI+, XTAL1 and PRDB[7:0].

3. OZL applies to all three-state output pins and bi-directional pins, except PRDB[7:0]. IOZH applies to pins PRDB[7:0].

4. Correlated to other tested parameters—not tested di rectly.

5. Parame ter not tes ted .

6. LRT is bit 9 o f Mode register (CSR15)

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

Twisted Pair Interface (continued)

VRXDTH RXD Switching Threshold (Note 5) –35 35 mV

VTXH TXD± and T XP± Output HIGH

Voltage DVSS = 0 V DVDD – 0.6 DVDD V

VTXL TXD± and TXP± Output LOW

Voltage DVDD = +5 V DVSS DVSS + 0.6 V

VTXI TXD± and TXP± Differential Output

Voltage Im balance –40 +40 mV

VTXOFF TXD± an d TXP± Idle Output

Voltage DVDD = +5 V –40 +40 mV

RTX TXD± Differential Driver Output

Impedance (Note 5) 40 Ω

TXP± Differential Driver Output

Impedance (Note 5) 80 Ω

IEEE 1149.1 (JTAG) Test Port

VIL TCK, TMS, TDI 0.8 V

VIH TCK, TMS, TDI 2.0 V

VOL TDO IOL = 2.0 mA 0.4 V

VOH TDO IOH = –0.4 mA 2.4 V

IIL TCK, TMS, TDI VDD = 5.5 V, VI = 0.5 V –200 µA

IIH TCK, TMS, TDI VDD =5 .5 V, VI = 2.7 V –100 µA

IOZ TDO 0.4 V < VOUT < VDD –10 +10 µA

Power Supply Current

IDD Active Power Supply Current XTAL1 = 20 MHz 75 mA

IDDCOMA Coma Mode P ower

Supply Current SLEEP active 200 µA

IDDSNOOZE Snooze Mode Mall Power

Supply Current Awake bit set active 10 mA

Am79C961A 137

SWITCHING CHARACTERISTICS: BUS MASTER MODE (Unless otherwise noted,

parametric values are the same between Commerc ial devices and Industrial devices)

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

Input/Output Write Timing

tIOW1 AEN, SBHE, SA0–9 Setup to

↓ IOW 10 ns

tIOW2 AEN, SBHE,SA0–9 Hold After

↑ IOW 5ns

tIOW3 IOW Assertion 100 ns

tIOW4 IOW Inactive 55 ns

tIOW5 SD Setup to ↑ IOW 10 ns

tIOW6 SD Hold After ↑ IOW 10 ns

tIOW7 ↓ IOCHRDY Delay fro m ↓ IOW 0 35 ns

tIOW8 IOCHRDY Inactive 125 ns

tIOW9 ↑IOCHRDY to ↑ IOW 0ns

Input/Output Read Timing

tIOR1 AEN, SBHE, SA0–9 Setup to

↓ IOR 15 ns

tIOR2 AEN, SBHE, SA0–9 Hold After

↑ IOR 5ns

tIOR3 IOR Inactive 55 ns

tIOR4 SD Hold After ↑ IOR 020ns

tIOR5 SD Valid from ↓ IO R 0110ns

tIOR6 ↓ IOCHRDY Delay from ↓ IOR 0 35 ns

tIOR7 IOCHRDY Inactive 125 ns

tIOR8 SD Valid from ↑ IOCHRDY –130 10 ns

I/O to Memory Command Inactive

tIOM1 ↑ IO W/MEMW to ↓ (S)MEMR/IOR 55 ns

tIOM2 ↑ (S)MEMR/IOR to ↓ IOW/MEMW 55 ns

IOCS16 Timing

tIOCS1 AEN, SBHE, SA0–9 to ↓ IOCS16 035ns

tIOCS2 AEN, SBHE, SA0–9 to IOCS16

Tristated 025ns

Master Mode Bus Acquisition

tMMA1 REF Inacti ve to ↓ DACK 5ns

tMMA2 ↑ DRQ to ↓ DACK 0ns

tMMA3 DACK Inactiv e 55 ns

tMMA4 ↓ DACK to ↓ MASTER 35 ns

tMMA5 ↓ MASTER to Active Command,

SBHE, SA0–19, LA17–23 125 185 ns

138 Am79C961A

SWITCHING CHARACTERISTICS: BUS MASTER MODE (continued)

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

Master Mode Bus Release

tMMBR1 Command Deassert to ↓ DRQ 45 65 ns

tMMBR2 ↓ DRQ to ↑ DACK 0ns

tMMBR3 ↓ DRQ to ↑ MA STER 40 60 ns

tMMBR4 ↓ DRQ to Command, SBHE,

SA0–19, LA17–23 Tristated –15 0 ns

Master Write Cycles

tMMW1 SBHE, SA0–19, LA17–23, Active

to ↓ MEMW (Note 1) EXTIME + 45 EXTIME + 65 ns

tMMW2 MEMW Active (Note 2) MSWRA – 10 MSWRA + 5 ns

tMMW3 MEMW Inactive (Note 1) EXTIME + 97 EXTIME + 105 ns

tMMW4 ↑ MEMW to SBHE, SA0–19,

LA17–23,SD Inactive 45 55 ns

tMMW5 SBHE, SA0–19, LA17–23, SD

Hold After ↑ MEMW 45 60 ns

tMMW6 SBHE, SA0–19, LA17–23, SD

Setup to ↓ MEMW (Note 1) EXTIME + 45 EXTIME + 55 ns

tMMW7 ↓ IOCHRDY Delay from

↓ MEMW tMMW2 – 175 ns

tMMW8 IOCHRDY Inactive 55 ns

tMMW9 ↑ IOCHRDY to ↑ MEMW 130 ns

tMMW10 SD Active to ↓ MEMW (Note 1) EXTIME + 20 EXTIME + 60 ns

tMMW11 SD Setup to ↓ MEMW (Note 1) EXTIME + 20 EXTIME + 60 ns

Master Read Cycles

tMMR1 SBHE, SA0–19, LA17 –23, Active

to ↓ MEMR (Note 1) EXTIME + 45 EXTIME + 60 ns

tMMR2 MEMR Active (Note 2) MS RDA – 10 MSRDA + 5 ns

tMMR3 MEMR Inactive (Note 1) EXTIME + 97 EXTIME + 105 ns

tMMR4 ↑ MEMR to SBHE, SA0–19,

LA17–23 Inacti ve 45 55 ns

tMMR5 SBHE, SA0–19, LA17–23 H old

After ↑ MEMW 45 55 ns

tMMR6 SBHE, SA0–19, LA17–23 Setup to

↓ MEMR (Note 1) EXTIME + 45 EXTIME + 55 ns

tMMR7 ↓ IOCHRDY De lay from ↓ MEMR tMMR2 – 175 ns

tMMR8 IOCHRDY Inactive 55 ns

tMMR9 ↑ IOCHRDY to ↑ MEMR 130 ns

tMMR10 SD Setup to ↑ MEMR 30 ns

tMMR11 SD Hold After ↑ ME M R 0ns

Am79C961A 139

SWITCHING CHARACTERISTICS: BUS MASTER MODE (continued)

Notes:

1. EXTIME is 100 ns when ISACSR2, bit 4, is cleared (default). EXTIME is 0 ns when ISACSR2, bit 4, is set.

2. MSRDA and MSWDA are parameters which are defined in registers ISACSR0 and ISACSR1, respectively.

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

Master Mode Address PROM Read

tMA1 ↓ IOR to ↓ APCS 125 260 ns

tMA2 APCS Active 140 155 ns

tMA3 PRDB Setup to ↑ APCS 20 ns

tMA4 PRDB Hold After ↑ APCS 0ns

tMA5 ↑ APCS to ↑ IOCHRDY 45 65 ns

tMA6 SD Valid from ↑ IOCHRDY 0 10 ns

Master Mode Boot PROM Read

tMB1 REF, SBHE,SA0–19 Setup to ↓

SMEMR 10 ns

tMB2 REF, SBHE,SA0–19 Hold ↑

SMEMR 5ns

tMB3 ↓ IOCHRDY Delay from ↓ SMEMR 035ns

tMB4 SMEMR Inacti ve 55 ns

tMB5 ↓ SMEMR to ↓ BPCS 125 260 ns

tMB6 BPCS Active 290 305 ns

tMB7 ↑ BPCS to ↑ IOCHRDY 45 65 ns

tMB8 PRDB Setup to ↑ BPCS 20 ns

tMB9 PRDB Hold After ↑ BPCS 0ns

tMB10 SD Valid from ↑ IOCHRDY 0 10 ns

tMB11 SD Hold After ↑ SMEMR 020ns

tMB12 LA20–23 Hold from ↓ BALE 10 ns

tMB13 LA20–23 Setu p to ↓ MEMR 10 ns

tMB14 ↑ BALE Setup to ↓ MEMR 10 ns

140 Am79C961A

SWITCHING CHARA CTERISTICS: BUS MASTER MODE—FLASH READ CYCLE

SWITCHING CHARA CTERISTICS: BUS MASTER MODE—FLASH WRITE CYCLE

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

tMFR1 REF, SBHE,SA0–19 Setup to

↓ MEMR 10 ns

tMFR2 REF, SBHE,SA0–19 Hold from

↑ MEMR 5ns

tMFR3 ↓ IOCHRDY to MEMR 035ns

tMFR4 ↓ MEMR Inactiv e 55 ns

tMFR5 ↓ MEMR to ↓ BPCS 125 260 ns

tMFR6 BPCS Active 190 205 ns

tMFR7 ↑ BPCS to ↑ IOCHRDY 45 65 ns

tMFR8 PRDB Setup to ↑ of BPCS 20 ns

tMFR9 PRDB Hold to ↑ of BPCS 0ns

tMFR10 SD Valid from ↑ IOCHRDY 0 10 ns

tMFR11 SD Tristate to ↑ MEMR 020ns

tMFR12 LA20–23 Hold from ↓ BALE 10 ns

tMFR13 LA20–23 Setu p to ↓ MEMR 10 ns

tMFR14 ↑ BALE Setup to ↓ MEMR 15 ns

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

tMFW1 SBHE, SA0–19 Setup to ↓ MEMW 10 ns

tMFW2 SBHE, SA0–19 Hold from ↑

MEMW 5ns

tMFW3 ↓ IOCHRDY to ↓ MEMW 035ns

tMFW4 MEMW Inactive 50 ns

tMFW5 ↑ FL_WE to ↑ IOCHRDY 20 90 ns

tMFW6 ↑ MEMW Hold from

↑ IOCHRDY 0ns

tMFW7 SD Valid from ↓ MEMW 175 ns

tMFW8 SD Hold from ↑ MEMW 0ns

tMFW9 PRDB Valid from ↓ MEMW 175 ns

tMFW10 PRDB Setup to ↓ FL_W E 15 ns

tMFW11 FL_WE Active 140 155 ns

tMFW12 PRDB Hold from ↑ FL_WE 15

tMFW13 LA20–23 Hold from ↓ BALE 10 ns

tMFW14 LA20–23 Setup to ↓ MEMW 10 ns

tMFW15 ↑ BALE Setup to ↓ ME MW 15 ns

Am79C961A 141

SWITCHING CHARACTERISTICS: SHARED MEMORY MODE (Unless otherwise noted,

parametric values are the same between Commerc ial devices and Industrial devices)

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

Input/Output Write Timing

tIOW1 AEN, SBHE, SA0–9 Setup to

↓ IOW 10 ns

tIOW2 AEN, SBHE,SA0–9 Hold from

↑ IOW 5ns

tIOW3 IOW Assertion 150 ns

tIOW4 IOW Inactive 55 ns

tIOW5 SD Setup to ↑ IOW 10 ns

tIOW6 SD Hold After ↑ IOW 10 ns

tIOW7 ↓ IOCHRDY Delay fro m

↓ IOW 035ns

tIOW8 IOCHRDY Inactive 125 ns

tIOW9 ↑IOCHRDY to ↑ IOW 0ns

Input/Output Read Timing

tIOR1 AEN, SBHE, SA0–9 Setup to

↓ IOR 15 ns

tIOR2 AEN, SBHE,SA0–9 Hold After

↑ IOR 5ns

tIOR3 IOR Inactive 55 ns

tIOR4 SD Hold from ↑ IOR 020ns

tIOR5 SD Valid from ↓ IO R 0110ns

tIOR6 ↓ IOCHRDY Delay from ↓ IOR 035ns

tIOR7 IOCHRDY Inactive 125 ns

tIOR8 SD Valid from ↑ IOCHRDY –130 10 ns

Memory Wr ite Timing

tMW1 SA0–15, SBHE , ↓ SMAM Setup to

↓ MEMW 10 ns

tMW2 SA0–15, SBHE, ↑ SMAM Hold

from ↑ MEMW 5ns

tMW3 MEMW Asser tion 150 ns

tMW4 MEMW Inactive 55 ns

tMW5 SD Setup to ↑ MEMW 10 ns

tMW6 SD Hold from ↑ MEMW 10 ns

tMW7 ↓ IOCHRDY Delay from ↓ MEMW 035ns

tMW8 IOCHRDY Inactive 1 25 ns

tMW9 ↑ MEMW to ↑ IOCHRDY 0ns

142 Am79C961A

SWITCHING CHARACTERISTICS: SHARED MEM ORY MODE (continued)

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

Memory Read Timing

tMR1 SA0–15, SBHE, ↓ SMAM/BPAM

Setup to ↓ MEMR 10 ns

tMR2 SA0–15, SBHE, ↑ SMAM/BPAM

Hold from ↑ MEM R 5ns

tMR3 MEMR Inactive 55 ns

tMR4 SD Hold from ↑ MEMR 020ns

tMR5 SD Valid from ↓ MEMR 0110ns

tMR6 ↓ IOCHRDY Delay from ↓ MEMR 035ns

tMR7 IOCHRDY Inactive 125 ns

tMR8 SD Valid from ↑ IOCHRDY –130 10 ns

I/O to Memory Command Inactive

tIOM1 ↓ IOW/MEMW to ↓ (S)MEMR/IOR 55 ns

tIOM2 ↓ (S)MEMR/IOR to ↓ IOW/MEMW 55 ns

IOCS16 Timing

tIOCS1 AEN, SBHE, SA0–9 to ↓ IOCS16 035ns

tIOCS2 AEN, SBHE, SA0–9 to IOCS16

Tristated 025ns

SRAM Read/Write, Boot PROM Read, Address PROM Read on Private Bus

tPR4 PRAB Change to PRAB Change,

SRAM Access 95 105 ns

tPR5 PRDB Setup to PR AB Change,

SRAM Access 20 ns

tPR6 PRDB Hold from PRAB Change,

SRAM Access 0ns

tPR7 PRAB Change to PRAB Change,

APROM Access 145 155 ns

Am79C961A 143

SWITCHING CHARACTERISTICS: SHARED MEM ORY MODE (continued)

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

SRAM Read/Write, Boot PROM Read, Address PROM Read on Priva te Bus (continued)

tPR8 PRDB Setup to PR AB Change,

APROM Access 20 ns

tPR9 PRDB Hold After PR AB Change,

APROM Access 0ns

tPR10 PRAB Change to PRAB Change,

BPROM Access 290 305 ns

tPR11 PRDB Setup to PR AB Change,

BPROM Access 20 ns

tPR12 PRDB Hold After PRAB Change,

BPROM Access 0ns

tPR13 PRAB Change to PRAB Change,

SRAM Write 145 155 ns

tPR14 PRAB Change to ↓ SRWE 20 30 ns

tPR15 PRAB Change to ↑ SRWE 120 130 ns

tPR16 PRAB Change to PRAB Change,

Flash Access 190 205 ns

tPR17 PRAB Change to PRAB Change,

Flash Write 190 205 ns

tPR18 PRAB Change to ↑ SRWE 170 180 ns

144 Am79C961A

SWITCHING CHARA CTERISTICS: SHARED MEMORY MODE—FLASH READ CYC L E

SWITCHING CHARA CTERISTICS: SHARED MEMORY MODE—FLASH WRITE CYCLE

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

tMFR1 BPAM, REF, SBHE, SA0–19 Setup

to ↓ MEMR 10 ns

tMFR2 BPAM, REF, SBHE, SA0–19 Hold

from ↑ MEMR 5ns

tMFR3 ↓ IOCHRDY to ↓ MEMR 035ns

tMFR4 MEMR Inactiv e 55 ns

tMFR5 ↓ MEMR to ↓ BPCS/SROE 125 260 ns

tMFR6 BPCS/SROE Active 190 205 ns

tMFR7 ↑ BPCS/SROE to ↑ IOCHRDY 45 65 ns

tMFR8 PRDB Setup to ↑ of BPCS/SROE 20 ns

tMFR9 PRDB Hold to ↑ of BPCS/SROE 0ns

tMFR10 SD Valid from ↑ IOCHRDY 0 10 ns

tMFR11 SD Tristate to ↑ MEMR 020ns

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

tMFW1 BPAM, SBHE, SA0–19 Setup to

↓ MEMW 10 ns

tMFW2 BPAM, SBHE, SA0–19 Hold After

↑ MEMW 5ns

tMFW3 ↓ IOCHRDY to ↓ MEMW 035ns

tMFW4 MEMW Inactive 50 ns

tMFW5 ↑ SRWE to ↑ IOCHRDY 20 90 ns

tMFW6 ↑ MEMW Hold from

↑ IOCHRDY 0ns

tMFW7 SD Valid from ↓ MEMW 175 ns

tMFW8 SD Hold from ↑ MEMW 0ns

tMFW9 BPCS/PRDB Valid from

↓ MEMW 175 ns

tMFW10 BPCS/PRDB Setup to

↓ SRWE 15 ns

tMFW11 SRWE Active 140 155 ns

tMFW12 BPCS/PRDB Hold from

↑ SRWE 15 ns

Am79C961A 145

SWITCHING CHARACTERISTICS: EADI (Unless otherwise noted, parametric values are

the same between Commercial devices and Industrial devices)

Note:

External Address Detection i nterf ace is in v oke d by s etting bit 3 in ISACSR2 and resetting bit 0 in ISA CSR2. Ex ternal MA U se lect

is not available when EADISEL bit is set.

SWITCHING CHARACT ERISTICS: JTAG (IEEE 1149.1) INTERFACE (U nless otherwise

noted, parametric values are the same between Commercial devices and Industrial

devices)

Note:

JTAG logic is reset with an internal Power-On Reset circuit independent of Sleep Modes.

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

tEAD1 SRD Setup to ↑ SRDCLK 40 ns

tEAD2 SRD Hold to ↑ SRDCLK 40 ns

tEAD3 SF/BD Change to ↓ SRDCLK –15 +15 ns

tEAD4 EAR Deassertion to ↑ SRDCLK

(First Risi ng Edge) 50 ns

tEAD5 EAR Assertion from SFD Event

(Packet Rejection) 051,090ns

tEAD6 EAR Assertion 110 ns

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

tJTG1 TCK HIGH Assertion 20 ns

tJTG2 TCK Period 100 ns

tJTG3 TDI Setup to ↑ TCK 5 ns

tJTG4 TDI, TMS Hold from ↑ TCK 5 ns

tJTG5 TMS Setup to ↑ TCK 8 ns

tJTG6 TDO Active from ↓ TCK 0 30 ns

tJTG7 TDO Change from ↓ TCK 0 30 ns

tJTG8 TDO Tristate from ↓ TCK 0 25 ns

146 Am79C961A

SWITCHING CHARACTERISTICS: GPSI (Unless otherwise noted, parame tric values are

the same between Commercial devices and Industrial devices)

Notes:

1. CLSN must be asserted for a continuous period of 1 10 ns or more. Asserti on for less than 110 ns period may or may

not result in CLSN recognition.

2. RCLK should meet jitter requirements of IEEE 802.3 specification.

3. CLSN assertion before 51.2 µs will be indicated as a normal collision. CLSN assertion after 51.2 µs will be

considered as a Late Receive Collision.

Param ete r

Symbol Parameter Descri ption Test Conditions Min Max Unit

Transmit Timing

tGPT1 STDCLK Period (802.3 Compliant) 99.99 100.01 ns

tGPT2 STDCLK HIGH Time 40 60 ns

tGPT3 TXDAT and TXEN Delay from ↑ TCLK 0 70 ns

tGPT4 RXCRS Setup to ↑ S TDCLK (Las t Bit) 210 n s

tGPT5 RXCRS Hold from ↓ TENA 0 ns

tGPT6 CLSN Active Time to Trigger Collision (Note 1) 110 ns

tGPT7 CLSN Active to ↓ RXCRS to Prevent

LCAR Assertion 0ns

tGPT8 CLSN Active to ↓ RXCRS for SQE

Hearbeat Window 04.0µs

tGPT9 CLSN Activ e to ↑ RXCRS f or Normal Collision 0 51.2 µs

Receive Timing

tGPR1 SRDCLK Period (Note 2) 80 120 ns

tGPR2 SRDCLK High Time (Note 2) 30 80 n s

tGPR3 SRDCLK Low Time (Note 2) 30 80 ns

tGPR4 RXDAT and RXCRS Setup to

↑ SRDCLK 15 ns

tGPR5 RXDAT Hold from ↑ RCLK 15 ns

tGPR6 RXCRS Hold from ↓ SRDCLK 0 ns

tGPR7 CLSN Active to First ↑ SRDCLK

(Collision Recognition) 0ns

tGPR8 CLSN Activ e to ↑ SRDCLK for Address Type

Designation Bit (Note 3) 51.2 µs

tGPR9 CLSN Setup to last ↑ SRDCLK for

Collision Recognition 210 ns

tGPR10 CLSN Active 110 ns

tGPR11 CLSN Inactive Setup to First ↑ RCLK 300 ns

tGPR12 CLSN Inactive Hold to Last ↑ RCLK 300 ns

Am79C961A 147

SWITCHING CHARA CTERISTICS: A UI (Unless otherwise noted, parametric values are the

same between Commercial devices and Industrial devices)

Notes:

1. DI pulses narrower than tPWODI (min) will be rejected; pulses wider than tPWODI (max) will turn internal DI carrier sense on.

2. DI pulses narrower than tPWKDI (min) will maintain internal DI carrier sense on; pulses wider than tPWKDI (max) will turn

internal DI carrier sense off.

3. CI pulses narrower than tPWOCI (min) will be rejected; pulses wider than tPWOCI (max) will turn internal CI carrier sense on.

4. CI pulses narrower than tPWKCI (min) will maintain internal CI carrier sense on; pulses wider than tPWKCI (max) will turn

internal CI carrier sense off.

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

A UI Port

tDOTR DO+,DO- Rise Time (10% to 90%) 2.5 5.0 ns

tDOTF DO+,DO- Fall Time (90% to 10%) 2.5 5.0 ns

tDORM DO+,DO- Rise and fall Time Mismatch 1.0 ns

tDOETD DO+/- End of Transmission 200 375 ns

tPWODI DI Pulse Width Accept/Reject Threshold |VIN| > |VASQ| (Note 1) 15 45 ns

tPWKDI DI Pulse Width Maintain/Turn-Off

Threshold |VIN| > |VASQ| (Note 2) 136 200 ns

tPWOCI CI Pulse Width Accept/Reject Threshold |VIN| > |VASQ| (Note 3) 10 26 ns

tPWKCI CI Pulse Width Maintain/Turn-Off

Threshold |VIN| > |VASQ| (Note 4) 90 160 ns

Internal MENDEC Clock Timing

tX1 XTAL1 Period VIN = External Clock 49.995 50.005 ns

tX1H XTAL1 HIGH Pulse Width VIN = External Clock 20 ns

tX1L XTAL1 LOW Pulse width VIN = External Clock 20 ns

tX1R XTAL1 Rise Time VIN = External Clock 5 ns

tX1F XTAL1 Fall Time VIN = External Clock 5 ns

148 Am79C961A

SWITCHING CHARACTERISTICS: 10BASE-T INTERFACE (Unless otherwise noted,

parametric values are the same between Commerc ial devices and Industrial devices)

Note:

1. Not tested; parameter guaranteed by characterization.

SWITCHING CHARACTERISTICS: SERIAL EEPROM INTERF ACE (Unless otherwise noted,

parametric values are the same between Commerc ial devices and Industrial devices)

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

Transmit Timing

tTETD Transmit Start of Idle 250 350 ns

tTR Transmitter Rise Time (10% to 90%) 5 .5 ns

tTF Transmitter Fall Time (90% to 10%) 5.5 ns

tTM Tra nsmitter Rise and F all Time

Mismatch 2ns

tPERLP Idle Sign al Period 8 24 ms

tPWLP Idle Link Pulse Width (Note 1) 75 120 ns

tPWPLP Predistortion Idle Link Pulse

Width (Note 1) 45 55 ns

tJA Transmit Jabber Acti vation

Time 20 150 ms

tJR Transmit Jabber Reset Time 250 750 ms

Receive Timi ng

tPWNRD RXD Pulse Width Not to Turn

Off Internal Carrier Sense VIN > VTHS (min) 136 ns

tPWROFF RXD Pulse Width to Turn Off VIN > VTHS (min) 200 ns

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

tSR1 EESK High Time 790 ns

tSR2 EESK Low Time 790 ns

tSR3 ↑ EECS EEDI from ↓ EESK – 15 15 ns

tSR4 ↓ EECS, EEDI and SHFBUSY

from ↓ EESK – 15 15 ns

tSR5 EECS Low Time 1590 ns

tSR6 EEDO Setup to ↑ EESK 35 ns

tSR7 EEDO Hold from ↑ EESK 0 ns

tSL1 EEDO Setup to ↓ IOR 95 ns

tSL2 EEDO Setup to ↑ IOCHRDY 140 ns

tSL3 EESK, EEDI, EECS and

SHFBUSY Delay from↑ IOW 160 235 ns

Am79C961A 149

SWITCHING TEST CIRCUITS

KS000010

Must b e

Steady

May

Change

from H to L

May

Change

from L to H

Does Not

Apply

Don’t Care,

Any Change

Permitted

Will be

Steady

Will be

Changing

from H to L

Will be

Changing

from L to H

Changing,

State

Unknown

Center

Line is High-

Impedance

“Off” State

WAVEFORM INPUTS OUTPUTS

150 Am79C961A

SWITCHING TEST CIRCUITS

19364B-32

VTHRESHOLD

IOL

IOH

Normal and Three-State Outputs

Sense Point

19364B-33

AVDD

DO+

154 Ω

100 pF

DO–

AVSS

52.3 Ω

Test Point

AUI DO Switching Test Circuit

Am79C961A 151

SWITCHING TEST CIRCUITS

TXD Switching Test Circuit

DVDD

TXD+

294 Ω

100 pF

TXD–

DVSS

294 Ω

Test Point

19364B-34

Includes Test

Jig Capa cit anc e

TXD Outputs Test Circuit

DVDD

TXP+

715 Ω

100 pF

TXP–

DVSS

715 Ω

Test Point

Includes Test

Jig Capacitance

19364B-35

152 Am79C961A

SWITCHING WAVEFORMS: BUS MASTER MODE

I/O Write without Wait States

19364B-36

AEN, SBHE,

SA0–9

IOW

tIOW5 tIOW6

tIOW4

tIOW1 tIOW3 tIOW2

Stable

AEN, SBHE,

SA0–9

IOW

tIOW5 tIOW6

tIOW4

tIOW1 tIOW2

Stable

IOCHRDY

tIOW7 tIOW8 tIOW9

19364B-37

I/O Write with Wait States

Am79C961A 153

SWITCHING WAVEFORMS: BUS MASTER MODE

Serial Shift EEPROM Interface Read Timing 19364B-38

EESK

(PRDB0)

EECS

EEDI

(PRDB1)

EEDO

(PRDB2)

SHFBUSY

011 A7 A6 A5 A4 A3 A2 A1 A0

D0 D1 D2 D14 D15

Falling transition at 26th Word, if checksum is 0xFF.

19364B-39

Serial EEPROM Control Timing

EESK

(PRDB0)

EECS

EEDI

(PRDB1)

SHFBSY

EED0

(PRDB2)

tSR1 tSR2

tSR3 tSR4 tSR5

Stable

tSR6 tSR7

154 Am79C961A

SWITCHING WAVEFORMS: BUS MASTER MODE

Slave Serial EEPROM Latency Timing 19364B-40

tSL1

tSL2

tSL3

EED0

(PRDB2)

IOR

IOCHRDY

IOW

EESK, EEDI,

EECS,

SHFBUSY

19364B-41

I/O Read without Wait States

AEN, SBHE,

SA0–9

IOR

tIOR5 tIOR4

tIOR3

tIOR1 tIOR2

Stable

Am79C961A 155

SWITCHING WAVEFORMS: BUS MASTER MODE

I/O Read with Wait States 19364B-42

AEN, SBHE,

SA0–9

IOR

tIOR8 tIOR4

tIOR3

tIOR1 tIOR2

Stable

IOCHRDY

tIOR6 tIOR7

Stable

19364B-43

I/O to Memory Command Inactive Time

IOW, MEMW

MEMR, IOR

tIOM1 tIOM2

156 Am79C961A

SWITCHING WAVEFORMS: BUS MASTER MODE

IOCS16 Timings

19364B-44

AEN, SBHE,

SA0–9

IOCS16

tIOCS tIOCS2

19364B-45

Bus Acquisition

tMMA1

tMMA2

tMMA3

tMMA4

tMMA5

REF

DRQ

DACK

MASTER

MEMR/MEMW

SBHE,

SA0–19,

LA17–23

Am79C961A 157

SWITCHING WAVEFORMS: BUS MASTER MODE

Bus Release 19364B-46

tMMBR1

tMMBR4

DRQ

DACK

MASTER

MEMR/MEMW

tMMBR2

tMMBR3

SBHE, SA0–19,

LA17–23

19364B-47

Write Cycles

tMMW1 tMMW2 tMMW3 tMMW4

tMMW7 tMMW8 tMMW9

tMMW5 tMMW6

SBHE, SA0–19,

LA17–23

MEMW

IOCHRDY

SD0–15

(Non Wait) (Wait States Added)

tMMW11

tMMW10

158 Am79C961A

SWITCHING WAVEFORMS: BUS MASTER MODE

tMMR1 tMMR2 tMMR3 tMMR4

tMMR7 tMMR8 tMMR9

tMMR10 tMMR11

Stable Stable

tMMR5 tMMR6

SBHE, SA0–19,

LA17–23

MEMR

IOCHRDY

SD0–15

19364B-48

(Non Wait) (Wait States Ad ded )

Read Cyc les

Stable

tIOR1 tIOR2

tIOR3

tMA5

tIOR6

tMA1 tMA2

tMA3 tMA4

tMA6 tIOR4

AEN, SBHE,

SA0–9

IOR

IOCHRDY

APCS

(IRQ15)

PRDB0–7

SD0–7

19364B-49

External Address PROM Re ad Cycle

Am79C961A 159

SWITCHING WAVEFORMS: BUS MASTER MODE

Stable

tMB1 tMB2

tMB4

tMB7

tMB3

tMB5 tMB6

tMB8 tMB9

tMB10 tMB11

REF, SBHE,

SA0–19

MEMR

IOCHRDY

BPCS

PRDB0–7

SD0–7

19634B-50

BALE

Stable

LA20–23

tMB12

tMB13

tMB14

Boot PROM Read Cycle

160 Am79C961A

SWITCHING WAVEFORMS: BUS MASTER MODE

Stable

tMFR1 tMFR2

tMFR4

tMFR7

tMFR3

tMFR5 tMFR6

tMFR8 tMFR9

tMFR10 tMFR11

REF, SBHE,

SA0–19

MEMR

IOCHRDY

BPCS

PRDB0–7

SD0–7

19364B-51

BALE

Stable

LA20–23

tMFR12

tMFR13

tMFR14

Flash Read Cycle

Am79C961A 161

SWITCHING WAVEFORMS: BUS MASTER MODE

tMFW5

Stable

tMFW1 tMFW2

tMFR4

tMFW3

tMFW7

SBHE,

SA0–19

MEMW

IOCHRDY

SD0-7

BALE

Stable

LA20–23

tMFW13

tMFW14

tMFW15 tMFW6

tMFW8

FL_WE (IR Q12)

tMFW11

tMFW10

tMFW12

Stable

PRDB0-7

19364B-52

tMFW9

Flash Write Cycle

162 Am79C961A

SWITCHING WAVEFORMS: SHARED MEMORY MODE

Stable

AEN, SBHE,

SA0–9

IOW

tIOW6

tIOW5

19364B-53

tIOW

tIOW1 tIOW

tIOW4

I/O Write without Wait States

Stable

AEN, SBHE,

SA0–9

IOW

tIOW

tIOW5

19664B-54

IOCHRDY

tIOW1 tIOW2

tIOW tIOW8 tIOW9

tIOW4

I/O Write with Wait States

Am79C961A 163

SWITCHING WAVEFORMS: SHARED MEMORY MODE

tIOR1

Stable

AEN, SBHE,

SA0–9

IOR

tIOR4

tIOR5

Stable

tIOR2

tIOR3

19364B-55

I/O Write without Wait States

Stable

AEN, SBHE,

SA0–9

IOR

tIOR2

IOCHRDY

tIOR4

Stabl

tIOR3

tIOR6 tIOR7

tIOR1

tIOR8

19364B-56

I/O Read with Wait States

164 Am79C961A

SWITCHING WAVEFORMS: SHARED MEMORY MODE

Stable

SA0–15,

SBHE

SMAM

tMW2

tMW6

tMW5

MEMW tMW4

tMW1 tMW3

19364B-57

Memory Write without Wait States

Stable

SA0–15,

SBHE

SMAM

tMW4

tMW6

tMW5

MEMW

tMW7 tMW8 tMW9

IOCHRDY

tMW2

tMW1

19364B-58

Memory Write with Wait States

Am79C961A 165

SWITCHING WAVEFORMS: SHARED MEMORY MODE

Stable

tMR1 tMR2

tMR5 tMR4 tMR3

SA0–15,

SBHE

SMAM

MEMR

19364B-59

Memory Read without Wait States

Stable

tMR1 tMR2

tMR6 tMR3

SA0–15,

SBHE

SMAM/BPAM

MEMR

tMR7

tMR8 tMR4

IOCHRDY

19364B-60

Memory Write with Wait States

166 Am79C961A

SWITCHING WAVEFORMS: SHARED MEMORY MODE

tIOM2

IOW, MEMW

MEMR, IOR

tIOM1

I/O to Memory Command Inactive Time 19364B-61

AEN, SBHE,

SA0–9

IOCS16

tIOCS1 tIOCS2

IOCS16 Timings 19364B-62

Am79C961A 167

SWITCHING WAVEFORMS: SHARED MEMORY MODE

tSFW5

Stable

tSFW1 tSFW2

tSFR4

tSFW3

tSFW7

SBHE,

SA0–15,

BPAM

MEMW

IOCHRDY

SD0-7

tSFW6

tSFW8

SRWE tSFW11

tSFW10

tSFW12

Stable

PRDB0-7

tSFW9

BPCS

Flash Write Cycle 19364B-63

168 Am79C961A

SWITCHING WAVEFORMS: SHARED MEMORY MODE

tSFR7

Stable

tSFR1 tSFR2

tSFR4

tSFR3

REF,

SBHE

SA0-15

MEMR

IOCHRDY

SROE

BPCS

Stable

tSFR8 tSFR9

tSFR10 tSFR11

PRDB0–7

SD0–7

tSFR5 tSFR6

Flash Read Cycle 19364B-64

Am79C961A 169

SWITCHING WAVEFORMS: SHARED MEMORY MODE

tPR13 tPR13

tPR15 tPR15

tPR14 tPR14

PRAB

SRWE

PRDB

SRCS

(IRQ12)

SRAM Write on Private Bus (When FL_Sel is Enabled) 19364B-65

tPR4 tPR4

PRAB

SROE

PRDB

tPR6

tPR5 tPR6 tPR5

SRCS

(IRQ12)

SRAM Read on Private Bus (When FL_Sel is Enabled) 19364B-66

170 Am79C961A

SWITCHING WAVEFORMS: SHARED MEMORY MODE

tPR10 tPR10

PRAB

BPCS

PRDB

tPR12

tPR11 tPR12 tPR11

Boot PROM Read on Private Bus 19364B-67

PRAB0–9

APCS

(IRQ15)

PRDB

tPR9

Add ress PROM Read on Private Bus 19364B-68

tPR8

tPR7

Am79C961A 171

SWITCHING WAVEFORMS: SHARED MEMORY MODE

tPR17 tPR17

tPR14 tPR14

tPR18 tPR18

PRAB0

SRWE

PRDB

FLCS

Flash Write on Private Bus 19364B-69

tPR16 tPR16

PRAB0

PRDB

FLOE

FLCS

tPR12

tPR11 tPR12

tPR11

19364B-70

Flash Re ad on Private Bus

172 Am79C961A

SWITCHING WAVEFORMS: GPSI

Notes:

1. RXCRS is not present during transmission, LCAR bit in TMD3 will be set.

2. CLSN is not present during or shortly after transmission, CERR in CSR0 will be set.

Transmit

Clock

(

STDCLK)

Transmit

Data

(TXDAT)

Transmit

Enable

(TXEN)

Carrier

Present

(RXCRS)

(Note 1)

Collision

(CLSN)

(Note 2)

(First Bit Prea mble )

tGPT2

tGPT3

tGPT3 tGPT3

tGPT5

(Last Bit)

19364B-71

Transmit Timing

tGPT1

tGPT9 tGPT6

tGPT7 tGPT8

tGPT4

Receive

Clock

(SRDCLK)

(First Bit Preamb le) (Address Type Designation Bit) (Last Bit)

tGPR2 tGPR3

tGPR4 tGPR5 tGPR5

tGPR6

tGPR8 tGPR9

tGPR11 tGPR12

Receive

Data

(RXDAT)

Carrier

Present

(RXCRS)

Collision

(CLSN),

Active

Collision

(CLSN),

Inactive

tGPR4

Receive Timing 19364B-72

tGPR1

tGPR7 tGPR10

(No Collis ion)

Am79C961A 173

SWITCHING WAVEFORMS: EADI

SWITCHING WAVEFORMS: JTAG (IEEE 1149.1) INTERFACE

EAR (MAUSEL)

SRDCLK (LED3)

SRD (LED2)

SF/BD (LED1) tEAD4

tEAD1 tEAD2

One Zero One SFD Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 8 Bit 0 Bit 7 Bit 8

tEAD3 tEAD3

tEAD5 tEAD6

Preamble Data Field

Reject

EADI Reject Timing 19364B-73

TCK

tJTG3 tJTG4 tJTG2

tJTG5

TDI

TMS

TDO

tJTG6 tJTG7 tJTG8

Test Access Port Timing

tJTG1

19364B-74

174 Am79C961A

SWITCHING WAVEFORMS: AUI

Note:

1. I nternal signal and is shown for clarificati on only.

tXI

tDOTR tDOTF

tX1HtX1L tX1F tX1R

1 1

XTAL1

ISTDCLK

(Note 1)

ITXDAT+

(Note 1)

DO+

DO–

DO±

ITXEN

(Note 1)

19364B-75

Transmit Timing—Start of Packet

Am79C961A 175

SWITCHI NG WAVE FORMS: AUI

Note:

1. I nternal signal and is shown for clarificati on only.

Typical > 200 ns

tDOETD

XTAL1

ISTDCLK

(Note 1)

ITXEN

(Note 1)

ITXDAT+

(Note 1)

DO+

DO–

DO±

010

Bit (n–2) Bit (n–1) Bit (n)

19364B-76

Transmit Timing—End of Packet (Last Bit = 0)

176 Am79C961A

SWITCHING WAVEFORMS: AUI

Note:

1. I nternal signal and is shown for clarificati on only.

Typical > 250 ns

XTAL1

ITXEN

(Not e 1)

ITXDAT+

(Not e 1)

DO+

DO–

DO±

Bit (n–2) Bit (n–1) Bit (n)

ISTDCLK

(Not e 1)

Transmit Timing—End of Packet (Last Bit = 1)

tDOETD

19364B-77

Am79C961A 177

SWITCHING WAVEFORMS: AUI

DI+/–

VASQ

tPWODI

tPWKDI

Receive Timing Diagram 19364B-78

CI+/–

VASQ

tPWOCI tPWKCI

tPWKCI

Collision Timing Diagram 19364B-79

tDOETD

DO+/–40 mV

100 mV ma x. 0 V

Port DO ETD Waveform 19364B-80

80 Bit Times

178 Am79C961A

SWITCHING WAVEFORMS: 10BASE-T INTERFACE

Note:

1. I nternal signal and is shown for clarificati on only.

tTR tTF tTETD

TXD+

TXP+

TXD–

TXP–

XMT

(Note 1)

Transmit Timing 19364B-81

TXD+

tPERLP

tPWLP

tPWPLP

TXP+

TXD–

TXP–

Idle Link Test Pulse 19364B-82

Am79C961A 179

SWITCHING WAVEFORMS: 10BA SE-T INTERFACE

RXD±

VTSQ+

VTSQ–

VTHS–

VTHS+

Receive Thresholds (LRT = 0 in CSR15 bit 9) 19364B-83

RXD±

VLTSQ+

VLTSQ–

VLTHS–

VLTHS+

Receive Thresholds (LRT = 1 in CSR15 bit 9) 19364B-84

180 Am79C961A

PHYSICAL DIMENSIONS*

PQB132

Plastic Quad Flat Pack Trimmed and Formed (measured in inches)

Pin 132

Pin 99

Pin 66

Pin 1 I.D.

16-038-PQB

PQB132

DB87

7-26-94 ae

TOP VIEW

1.097

1.103

0.947

0.953

1.075

1.085

1.097

1.103

0.008

0.012

Pin 33

1.075

1.085 0.947

0.953

0.025 BASIC

0.160

0.180

0.80 REF

BOTTOM VIEW

0.130

0.150

0.020

0.040

SEATING

PLANE

Pin 132

Pin 99

Pin 66

Pin 1 I.D.

TOP VIEW

1.097

1.103

0.947

0.953

1.075

1.085

1.097

1.103

0.008

0.012

Pin 33

1.075

1.085 0.947

0.953

0.025 BASIC

0.160

0.180

0.80 REF

BOTTOM VIEW

0.130

0.150

0.020

0.040

SEATING

PLANE

Am79C961A 181

PHYSICAL DIMENSIONS*

PQB132

Molded Carrier Ring Plastic Quad Flat Pack

(measured in inches, Ring measured in millimeters)

45.87

46.13

45.50

45.90

41.37

41.63

37.87

38.13

35.15

35.25 32.15

32.25

1.097

1.103

.944

.952

.944

.952

1.097

1.103

32.15

32.25

35.15

35.25

37.87

38.13

41.37

41.63

45.50

45.90

45.87

46.13

.750

NOM. Pin 132

Pin 1

4.80

2.00

256 NOM.

SIDE VIEW

1.50 DIA.

1.80

Pin 99

Pin 66

1.50 DIA.

Pin 33

1.50 DIA.

182 Am79C961A

APPENDIX A

Am79C961A 183

PCnet-ISA II Compatible Media

Interface Modules

PCnet-ISA II COMPATIBLE 10BASE-T

FILTERS AND TRANSFORMERS

The table below provides a sample list of PCnet-IS A II

compatible 10BASE-T filter and transformer modules

availa ble from variou s vendors. Conta ct the r e spe ct ive

manufacturer for a complete and updated listing of

components.

PCnet-ISA II Compatible AUI Isolation

Transformers

The table below provides a sample list of PCnet-IS A II

compatible AUI isolation transformers available from

various vendors. Contact the respective manufacturer

for a complete and updated listing of components.

Manufacturer Part No. Package Filters and

Transformers

Filters

Transformers

and Choke

Filters

Transformers

Dual Choke

Filters

Transformers

Dual Chokes

Bel Fuse A556-2006-DE 16-pin 0.3" DIL √

Bel Fuse 0556-2006-00 14-pin SIP √

Bel Fuse 0556-2006-01 14-pin SIP √

Bel Fuse 0556-6392-00 16-pin 0.5" DIL √

Halo Electronics FD02-101G 16-pin 0.3 " DIL √

Halo Electronics FD12-101G 16-pin 0.3" DIL √

Halo Electronics FD22-101G 16-pin 0.3" DIL √

PCA Electronics EPA1990A 16-pin 0.3" DIL √

PCA Electronics EPA2013D 16-pin 0.3" DIL √

PCA Electronics EPA2162 16-pin 0.3" SIP √

Pulse Engineer in g PE-65421 16-pin 0.3" DIL √

Pulse Engineering PE-65434 16-pin 0.3" SIL √

Pulse Engineering PE-65445 16-pin 0.3" DIL √

Pulse Engineering PE-65467 12-pin 0.5" SMT √

Valor Electronics PT3877 16-pin 0.3" DIL √

Valor Electronics FL1043 16-pin 0.3" DIL √

Manufacturer Part No. Package Description

Bel Fuse A553-0506-AB 16-pin 0.3" DIL 50 µH

Bel Fuse S553-0756-AE 16-pin 0.3" SMD 75 µH

Halo Electronics TD01 -0756K 16-pin 0.3" DIL 75 µH

Halo Electronics TG01-0756W 16-pin 0.3" SMD 75 µH

PCA Electronics EP9531-4 16-pin 0.3" DIL 50 µH

Pulse Engineer in g PE64106 16-pin 0.3" DIL 50 µH

Pulse Engineering PE65723 16-pin 0.3" SMT 75 µH

Valor Electronics LT6032 16-pin 0.3" DIL 75 µH

Valor Electronics ST7032 16-pin 0.3" SMD 75 µH

184 Am79C961A

PCnet-ISA II Compatible DC/DC

Converters

The table below provides a sample list of PCnet-IS A II

compatible DC/DC conver ters available from various

vendors. Contact the respective manufacturer for a

complete and updated listing of components.

MANUFACTURER CONTACT

INFORMATION

Contact the follo wing companies for further inf ormation

on their products :

Manufacturer Part No. Package Voltage Remote On/Off

Halo Electronics DCU0-0509D 24-pin DIP 5/-9 No

Halo Electronics DCU0-0509E 24-pin DIP 5/-9 Yes

PCA Electronics EPC1007P 24-pin DIP 5/-9 No

PCA Electronics EPC1054P 24-pin DIP 5/-9 Yes

PCA Electronics EPC1078 24-pin DIP 5/-9 Yes

Valor Electronics PM7202 24-pin DIP 5/-9 No

Valor Electronics PM7222 24-pin DIP 5/-9 Yes

Compan y U .S. and Dome stic Asia Europe

Bel Fuse Phone:

FAX: (201) 432-0463

(201) 432-954 2 852-328-5515

852-352-3706 33-1-69410402

33-1-69413320

Halo Electronics Phone:

FAX: (415) 969-7313

(415) 367-715 8 65-285-1566

65-284-9466

PCA Electronics

(HPC in Hong Kong) Phone:

FAX: 818-892-0761

818-894-5791 852-553-0165

852-873-1550 33-1-44894800

33-1-42051579

Pulse Engineering Phone:

FAX: (619) 674-8100

(619) 675-826 2 852-425-1651

852-480-5974 353-093-24107

353-093-24459

Valor Electronics Phone:

FAX: (619) 537-2500

(619) 537-252 5 852-513-8210

852-513-8214 49-89-6923122

49-89-6926542

APPENDIX B

Am79C961A 185

Layout Recommendations

for Reducing Noise

DECOUPLING LOW-PASS R/C

FILTER DESIGN

The PCnet-ISA II controller is an integrated, single-chip

Ethernet controller, which contains both digital and

analog circuitry. The analog circuitry contains a high

speed Phase-Locked Loop (PLL) and Voltage Con-

trolled Oscillator (VCO). Because of the mixed signal

chara cteristics of th is chip , som e ex tra preca utions must

be taken into acco un t when desi gnin g w it h this device .

Described in this section is a simple decoupling

low-pass R/C filter that can significantly increase noise

immunity of the PLL circuit, thus, prevent noise from

disrupting the VCO . Bit error rate, a common measure-

ment of network performance, as a result can be dras-

tically reduced. In certain cases the bit error rate can be

reduced by orders of magnitude.

Impl emen tation of thi s filt er is no t necess ary to achi e ve

a functional product that meets the IEEE 802.3 specifi-

cation and provides adequate performance. However,

this filt er will help des igners meet thos e specifications

with more margin.

Digital Decoupling

The DVSS pins that are sinki ng the most current are

those that provide the ground for the ISA bus output

signals since these outputs require 24 mA drivers.

The DVSS10 and DVSS12 pins provide the ground

for the internal digital logic. In addition, DVSS11

provides ground for the internal digital and for the

Input and I/O pins.

The CMOS technology used in fabricating the PC-

net-ISA II controller employs an n-type substrate. In this

technology, all VDD pins are electrically connected to

each other internally. Hence, in a four-lay er board, when

decoup lin g between VDD an d criti cal V SS pi ns, the s pe -

cific VDD pin that y ou c onnect to is not critic al. In f act, the

VDD connection of the decoupling capacitor can be

made di rectly to the power pl ane, near the closes t VDD

pin to the VSS pin of interest. However, we recommend

that the VSS connection of the decoupling capacitor be

made directly to the VSS pin of interest as shown.

AMD recommends that at least one low-frequency

bulk decoupling capacitor be used in the area of the

PCnet-ISA II controller . 22 µF capacitors ha v e worked

well for this. In addition, a total of four or five 0.1 µF

capacitors have proven sufficient around the DVSS

and DV DD pins that supply the dr iver s of the ISA bus

output pins.

Analog Decoupling

The most critical pins are the analog supply and ground

pins . All of the analo g supply an d groun d pins are located

in one corner of the device. Specific requirements of the

analog supp ly pins are listed belo w.

AVSS1 and AVDD3

These pins provide the power and ground for the

Twisted Pair and AUI drivers. Hence, they are very

noisy. A dedicated 0.1 µF capacitor between these pins

is recommended.

AVSS2 and AVDD2

These pins are the most critical pins on the PCnet-ISA

II controller because they provide the power and

ground for the PLL portion of the chip. The VCO portion

of the PLL is sens itive to noise in the 60 kHz -200 kHz

range. To prevent noise in this frequency range from

disrupting the VCO, AMD strongly recommends that

the low-pass filter shown below be implemented on

these pins. Tests using this filter have shown signifi-

cantly inc re ased noise immun ity and red uc ed Bit Er ror

Rat e (BER) stat ist ics in design s usi ng t he PCn et- ISA II

controller.

VDD Pin

VSS Pin

PCnet-ISA II

via to VDD

via to VSS plane

19364B-85

186 Am79C961A

To determine the value for the resistor and capacitor,

the formula is:

R * C ≥ 88

Where R is in ohms and C is in microf arads. Some pos-

sible combinations are given below. To minimize the

v oltage drop across the resistor, the R v alue should not

be more than 20 Ω.

AVSS2 and AVDD2/AVDD4

These pins provide power and ground for the AUI and

twisted pair receive circuitry. No specific decoupling

has been necessary on these pins.

PCnet-ISA II

AVDD2

Pin 108

AVSS2

Pin 98

VDD Plane 33 µF to 6.8 µF

1 Ω to 20 Ω

19364B-86

2.7 Ω33 µF

4.3 Ω22 µF

6.8 Ω15 µF

10 Ω10 µF

20 Ω6.8 µF

APPENDIX C

187

Sample Plug and Play Configuration Record

SAMPLE CONFIGURATION FILE

The following is a sample configuration record for the

PCnet-ISA II device used in an AMD Ethernet card.

This card requires one DMA channel, one interrupt,

one I/O port in the 0x200-0x3FF range (0x20 bytes

aligned). The vendor ID of AMD is ADV. The vendor

assigne d part number fo r this c ard is 21 00 and the se-

rial number is 0x12345678. The card has only one log-

ical device, that is an ethernet controller. There are no

compatible devices with this logical device. The follow-

ing record should be returned by the card during the

identification process.

Note:

All data stored in the EEPR OM is stored in bit-rev ersal for-

mat. Each word (16 bits) must be written into the EEPROM

with bit 15 swapped with bit 0, bit 14 swapped with bit 1, etc.

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

; Plug and Play Header

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

DB 0x04 ; Vendor EISA ID Byte 0

DB 0x96 ; Vendor EISA ID Byte 1

DB 0x00 ; Vendor Assigned ID Byte 0

DB 0x21 ; Vendor Assigned ID Byte 1

DB 0x78 ; Serial Number byte 0

DB 0x56 ; Serial Number byte 1

DB 0x34 ; Serial Number byte 2

DB 0x12 ; Serial Number byte 3

DB Checksum ; Checksum calculated on above bits

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

; Plug and Play Version

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

DB 0x0A ; Small Item, Plug and Play version

DB 0x10 ; BCD major version [7:4] = 1

; BCD minor version [3:0] = 0

DB 0x00 ; Vendor specific version number

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

; Identifier String

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

DB 0x82 ; Large Item, Type Identifier string (ANSI)

DB 0x1C ; Length Byte 0 (28 bytes)

DB 0x00 ; Length Byte 1

DB “AMD PCnet-ISA II Ethernet

Network Adapter“ ; Identifier String

188

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

; Logical Device ID

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

DB 0x15 ; Small Item, Type Logical Device ID

DB 0x04 ; Logical Device ID byte 0

DB 0x96 ; Logical Device ID byte 1

DB 0x55 ; Logical Device ID byte 2

DB 0xAA ; Logical Device ID byte 3

DB 0x02 ; Logical Device Flags [0] – required for boot

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

; Compatible Device ID

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

DB 0x1C ; Small Item, Type Compatible Device ID

DB 0x41 ; Compatible Device ID byte 0

DB 0xD0 ; Compatible Device ID byte 1

DB 0x82 ; Compatible Device ID byte 2

DB 0x8C ; Compatible Device ID byte 3

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

; I/O Port Descriptor

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

DB 0x47 ; Small Item, type I/O Port

DB 0x00 ; Information, [0] = 0, 10 bit Decode

DB 0x00 ; Minimum Base Address [07:00]

DB 0x02 ; Minimum Base Address [15:08]

DB 0xE0 ; Maximum Base Add re ss [07:00 ]

DB 0x03 ; Maximum Base Address [15:08 ]

DB 0x20 ; Base Address Increment (32 ports)

DB 0x18 ; Number of ports required

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

; DMA Descriptor

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

DB 0x2A ; Small Item, type DMA Format

DB 0xE8 ; DMA channel mask ch 3, 5, 6, 7

DB 0x05 ; 16-Bit only, Bus Master

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

;IRQ Format

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

DB 0x23 ; Small Item, type IRQ Format

DB 0x38 ; IRQs support ed [7:0] 3, 4, 5

DB 0x9E ; IRQs supported [15:8] 9, 10, 11, 12, 15

DB 0x09 ; Information: High true, edge

Low true, level

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

; End Tag

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

DB 0x79 ; Small item, type END TAG

DB Checksum ; Checksum

APPENDIX D

Am79C961A 189

Alternative Method

for Initializati on

The PCnet-ISA II controller may be initialized by

performing I/O wr i tes on ly. Tha t i s, data ca n b e wr i tte n

directly to the appropriate control a nd status registers

(CSR) instead of reading from the Initialization Block in

memor y. The r egister s that must be wr itten are s hown

in the table below. These are followed by writing the

START b it in CSR0.

Note:

The INIT bit must not be set or the initialization block will be

accessed instead.

Control and Status

CSR8 LADRF[15:0]

CSR9 LADRF[31:16]

CSR10 LADRF[47:32]

CSR11 LADRF[63:48]

CSR12 PADR[15:0]

CSR13 PADR[31:16]

CSR14 PADR[47:32]

CSR15 Mode

CSR24–25 BADR

CSR30–31 BADX

CSR47 POLLINT

CSR76 RCVRL

CSR78 XMTRL

190 Am79C961A

APPENDIX E

Am79C961A 191

Introduction of the Look-

Ahead Packet Proces sing (LAPP) Concept

A driv er f or the PCnet-ISA II controller would normally

require that the CPU copy receiv e frame data from the

controller’s buffer space to the application’s buffer

space after the entire frame has been received by the

controller. For applications that use a ping-pong

windowing style, the traffic on the network will be

halted until the current frame has been completely

processed by the entire application stac k. This means

that the time between last byte of a receive frame

arriving at the client’s Ethernet controller and the

client’s transmission of the first byte of the next

outgoing frame will be separated by:

1. the time that it takes the client’s CPU’s interrupt

procedure to pass software control from the current

task to the driver

2. plus the time that it takes the client driver to pass the

header data to the application and request an

application buffer

3. plus the time that it takes the application to generate

the buffer poin ter and t hen return the buffe r poin ter

to the driver

4. plus the time that it takes the client driver to transfer

all of the frame data from the controller’s buffer

space into the application’s buffer space and then

call the application again to process the complete

frame

5. plus the time that it takes the application to process

the frame and generate the next outgoing frame

6. plus the tim e that it takes the cl ient dr ive r to set up

the descriptor for the controller and then write a

TDMD bit to CSR0

The sum of these times can often be about the same

as the time taken to actually transmit the frames on the

wire, thereby yielding a network utilization rate of less

than 50%.

An impo r tant th ing to n ote is tha t the PCnet -ISA II con-

troller’s data transfers to its buffer space are such that

the syst em b u s is ne eded by the PCnet- IS A II con tro ll er

for approximately 4% of the time. This leav es 96% of the

system bus bandwidth for the CPU to perform some of

the inte r -f rame ope rat io ns in advance of the completion

of network receive activity, if possib le. The qu estion then

becomes: how much of the tasks that need to be per-

formed bet wee n recept ion of a frame a nd transmiss ion

of th e next f ram e can be p erformed before the reception

of the frame actually ends at the network, and how can

the CPU be instructed to perform these tasks during the

network reception time?

The answer depends upon exactly what is happening

in the driver and application code, but the steps that

can be performed a t the sa me t ime as t he re ceive da ta

are arriving include as much as the first three steps and

par t of the four th step shown in the sequence above.

By performi ng these steps before the entire frame has

arrived, the frame throughput can be substantially

increased.

A good increase in performance can be expected

when the first three steps are performed before the

end of the network receive operation. A much more

significant perfo rmance increase could be r ealized if

the PCnet-ISA II controller could place the frame

data directly into the application’s buffer space; (i.e.

eliminate the need for step four). In order to make

this work, it is necessary that the application buffer

pointer be determined before the frame has com-

pletely arrived, then the buffer pointer in the next

desriptor for the receive frame would need to be

modified in order to direct the PCnet-ISA II contr oller

to write directly to the application b uff er. More details

on this operation will be given later.

An alternative modification to the existing system can

gain a s malle r, bu t stil l si gnifican t impr ovem ent in per-

formance. This alternative leaves step four unchanged

in that the CPU is still required to perform the copy

operation, but it allows a large portion of the copy oper-

ation to be done before the frame has been completely

received by the controller, (i.e. the CPU can perform

the copy operation of the receive data from the PC-

net-ISA II controller ’s buffer spac e into the appli cation

buffer s pace befo re the frame data h as comp letely ar-

rived from the network). This allows the copy operation

of step four to be performed concurrently with the ar-

rival of network data, rather than sequentially, following

the end of network receive activity.

Outline of the LAPP Flow:

This se ction gives a suggested ou tline for a driver that

utilizes the LAPP feature of the PCnet-ISA II controller.

192 Am79C961A

Note:

The labe ls in the fo llowing text are used as re ferences in the

timeline diagram that follows.

SETUP:

The driver should set up descriptors in groups of 3, with

the OWN and STP bits of each set of three descriptors

to read as follows: 11b, 10b, 00b.

An option bit (LAPPEN) exists in CSR3, bit position 5.

The sof tw are sh ould se t t his bi t. Wh en set , th e LA PPEN

bit directs the PCnet-ISA II to generate an INTERRUPT

when STP has been written to a receive descriptor by

the PCnet-ISA II controller.

FLOW:

The PCnet-ISA II controller polls the current receive

descriptor at some point in time before a message

arrives. The PCnet-ISA II c ontroller deter mines that

this receive buffer is OWNed by the PCnet-ISA II

controller and it stores the descriptor information to

be used when a message does arrive.

N0: Frame preamble appears on the wire, followed by

SFD and destinati on address.

N1: The 64th byte of frame data arrives from the wire.

This causes the PCnet-ISA II controller to begin

frame data DMA operations to the first buffer.

C0: When the 64th byte of the message arrives, the

PCnet -ISA II co ntrolle r perfor ms a look ahead o per-

ation to the next receive descriptor. This descriptor

should be owned by the PCnet-ISA II controller.

C1: The PCnet-ISA II controller intermittently requests

the bus to transfer frame data to the first buffer as

it arrives on t he wire.

S0: The driver remains idle.

C2: When the PCnet-ISA II controller has completely

filled the first buffer, it writes status to the first

descriptor.

C3: When the first descriptor for the frame has been

written, changing ownership from the PCnet-ISA II

controlle r to the CPU, the PCnet- ISA II contr oller

will generate an SRP INTERRUPT. (This inter-

rupt appears as a RINT interrupt in CSR0.)

S1: T he SRP INTERRUPT causes t he C PU to s witc h

tasks to allow the PCne t-ISA II controller’s driver

to run.

C4: During the CPU interrupt-generated task switch-

ing, the PCnet-ISA II controller is performing a

lookahead operation to the third descriptor. At this

point in time , t he third descri ptor is owned by the

CPU. [Note: Even though the third buffer is not

owned by the PCnet-ISA II controller, existing

AMD Ethe rnet contr olle rs will co ntinue to pe rform

data DMA i nto the buffer space that the con tr oll er

already owns (i.e. buffer number 2). The controller

does not k now if buff er space in bu ffer number 2

will be sufficient or not, for this frame, but it has no

way to tell except by trying to move the entire mes-

sage into that space. Only when the message

does no t f it will it s ignal a b uffer er ror c ondit ion—

there is no need to panic at the point that it discov-

ers that it does not yet own descriptor number 3.]

S2: The first task of the driver’s interrupt service

routine is to collect the header information from

the PCnet-ISA II controller’s first buffer and pass it

to the application.

S3: The application will return an application buffer

pointer to the driver. T he driver will a dd an offset

to the application data buffer pointer, since the

PCnet-ISA II controller will be placing the first

portion of the message into the first and second

buffers. (The modified application data buffer

pointer will only be directly used by the PCnet-ISA

II contro ller when it r eaches the thi rd buffer .) The

driver will place the modified data buffer pointer

into the final descriptor of the group (#3) and will

grant ownership of this descriptor to the PC-

net-ISA II controller.

C5: Interleaved with S2, S3 and S4 driver activity, the

PCnet-ISA II controller will write frame data to

buffer number 2.

S4: The dri ver will next proc eed to copy th e contents

of the PCnet-ISA II controller’s first buffer to the

beginning of the appl ication sp ace. This copy will

be to the exact (unmodified) buffer pointer that

was passed by the application.

S5: After copying all of the data from the first buffer

into the beginning of the application data buffer,

the dr iver wil l be gin to pol l th e o wne rshi p bit of t he

second descriptor. The driver is waiting for the

PCnet-IS A II controller to finish filling the second

buffer.

C6: At this point, knowing that it had not previously

owned the third descriptor, and knowing that the

current message has not ended (there is more

data in the fifo), the PCnet-ISA II controller will

make a “last ditch lookahead” to the final (third)

descr ipt or; This time, the ow ners hip will be TR UE

(i.e. the descriptor belongs to the controller),

because the driver wrote the application pointer

into this descriptor and then changed the owner-

ship to give the descriptor to the PCnet-ISA II con-

troller back at S3. Note that if steps S1, S2 and S3

have not completed at this time, a BUFF error will

result.

C7: After filling the second buffer and performing the

last cha nce lookahe ad to the next de scriptor, the

PCnet-ISA II controller will write the status and

change the ownership bit of descriptor number 2.

Am79C961A 193

S6: After the ownership of descriptor number 2 has

been chan ged by the PCnet- ISA II controll er, the

next driver poll of the 2nd descriptor will show

ownership granted to the CPU. The driver now

copies the data from buffer number 2 into the

“middle section” of the application buffer space.

This operation is interleaved with the C7 and C8

operations.

C8: The PCnet-ISA II controller will perform data DMA

to the last buffer, whose pointer is pointing to

application space. Data entering the last buffer

will not need the infamous “double copy” that is

required by existing drivers, since it is being

placed directly into the application buffer space.

N2: The message on the wire ends.

S7: When the driver completes the copy of buffer

number 2 data to the application buffer space, it

begins polling descriptor number 3.

C9: When the PCnet-ISA II controller has finish ed all

data DMA operations, it writes status and changes

ownership of descriptor number 3.

S8: The driver sees that the ownership of descriptor

number 3 has changed, and it calls the application

to tell the application that a frame has arrived.

S9: The application processes the received frame and

generate s the n ext TX fr ame, plac ing it into a T X

buffer.

S10:The driver sets up the TX descriptor for the PC-

net-ISA II controller.

19364B-87

Figure 1. Look Ahead Packet Processing (LAPP) Timeline

Buffer

Ethernet

Wire

activity:

Ethernet

Controller

activity:

Software

activity:

S10: Driver sets up TX descriptor.

S9: Application processes packet, generates TX packet.

S8: Driver calls application

to tell application that

packethas arrived.

S7: Driver polls descriptor of buffer #3.

S6: Driver copies data from buffer #2 to the application

buffer.

S5: Driver polls descriptor #2.

S4: Driver copies data from buffer #1 to the application

buffer.

S3: Driver writes modified application

pointer to descriptor #3.

S2: Driver call to application to

get application buffer pointer.

S1: Interrupt latency.

S0: Driver is idle.

}

N2:EOM

N0: Packet preamble, SFD

and destination address

are arriving.

{

Packet data arriving

}

C9: Controller writes descriptor #3.

C8: Controller is performing intermittent

bursts of DMA to fill data buffer #3.

C7: Controller writes descriptor #2.

C6: "Last chance" lookahead to

descriptor #3 (OWN).

C5: Controller is performing intermittent

bursts of DMA to fill data buffer #2

C3: SRP interrupt is

generated.

C2: Controller writes descriptor #1.

C1: Controller is performing intermittent

bursts of DMA to fill data buffer #1.

C0: Lookahead to descriptor #2.

N1: 64th byte of packet

data arrives.

C4: Lookahead to descriptor #3 (OWN).

194 Am79C961A

LAPP Enable Software Requirements

Software needs to set up a receive ring with descriptors

formed into groups of 3. The first descriptor of each

group should h ave OWN = 1 a nd S TP = 1, the s ec on d

descripto r of each group should have OWN = 1 and

STP = 0. The third descriptor of each group should

have OWN = 0 and STP = 0. The size of the first buff er

(as indi cated in th e fir s t desc riptor ), sho ul d be at least

equal to the largest expected header size; However,

for maximum efficiency of CPU utilization, the first

buffer size should be larger than the header size. It

should be equal to the expected number of message

bytes, minus the ti me n eed ed for Interr up t l ate nc y an d

minus the application call latency, minus the time

needed for the driver to write to the third descriptor,

minus the time needed fo r the dr iver to copy data from

buff er #1 to the application buffer space, and minus the

time n eeded for the driver to copy data f rom buffer # 2

to the application buffer space. Note that the time

needed for the copies performed by the driver depends

upon the sizes of the 2nd and 3rd buffers, and that the

sizes of the second and third buff ers need to be set ac-

cording to the time needed for the data copy opera-

tions! This means that an iterative self-adjusting

mech anism n eeds to be plac ed int o the so ftw are to de-

ter mine the correct buffer sizing for optim al operation .

Fixed values for buffer sizes may be used; In such a

case, the LAPP method will still provide a significant

performance increase, but the performance increase

will not be maximized.

The following diagram illustrates this setup for a re-

ceive ring size of 9:

LAPP Enable Rules for Parsing of

Descriptors

When using the LAPP method, software must use a

modified form of descriptor parsing as follows:

Software will examine OWN and STP to determine

where a RCV frame begins. RCV frames will only

begin in buffers that have OWN = 0 and STP = 1.

Software shall assume that a frame continues until it

finds either ENP = 1 or ERR= 1.

Software must discard all descriptors with OWN = 0

and STP = 0 and move to the next descriptor when

searchin g for the begi nning of a new frame; E NP an d

ERR should be ignored by software during this search.

Software cannot change an STP value in the receive

descriptor ring after the initial setup of the ring is

complete, even if software has ownership of the STP

descriptor unless the previous STP descriptor in the

ring is also OWNED by the software.

When L APPE N = 1 , then hardware wil l use a modifie d

form of descriptor parsing as follows:

The controller will examine OWN and STP to deter-

mine where to begin placing a RCV frame. A new RCV

frame will only beg in i n a buffer that has OWN = 1 and

STP = 1.

The controller will always obey the OWN bit for deter-

mining whether or not it may use the next buffer for a

chain.

The controller will always mark the end of a frame with

either ENP = 1 or ERR= 1.

Descriptor

OWN = 1 STP = 1

SIZE = A-(S1+S2+S3+S4+S6)

OWN = 1 STP = 0

SIZE = S1+S2+S3+S4

OWN = 0 STP = 0

SIZE = S6

OWN = 1 STP = 1

SIZE = A-(S1+S2+S3+S4+S6)

OWN = 1 STP = 0

SIZE = S1+S2+S3+S4

OWN = 0 STP = 0

SIZE = S6

OWN = 1 STP = 1

SIZE = A-(S1+S2+S3+S4+S6)

OWN = 1 STP = 0

SIZE = S1+S2+S3+S4

OWN = 0 STP = 0

SIZE = S6

A = Expected message size in bytes

S1 = Interrupt latency

S2 = Application call latency

S3 = Time needed for driver to write

to third descriptor

S4 = Time needed for driver to copy

data from buffer #1 to

application buffer space

S6 = Time needed for driver to copy

data from buffer #2 to

application buffer space

Note that the times needed for tasks S1,

S2, S3, S4, and S6 should be divided by

0.8 microseconds to yield an equivalent

number of network byte times before

subtracting these quantities from the

expected message size A.

19364B-88

Figure 2. LAPP 3 Buffer Grouping

Am79C961A 195

The controller will discard all descriptors with OWN = 1

and STP = 0 and move to the next descriptor when

searching for a place to begin a new frame. It dis-

cards t hese desc iptors by simply changin g the owner-

ship bit from OWN=1 to OWN = 0. Such a descriptor is

unused for receive pur pos es by the con troller, and the

driver must recognize this. (The driver will recognize

this if it follows the software rules.)

The control ler will ignore all descriptors with OW N = 0

and STP = 0 and move to the next descriptor when

sear ching for a place to begin a new frame . In other

words, the controller is allowed to skip entries in the

ring that it does not own, but only when it is looking for

a place to begin a new frame.

Some Examples of LAPP Descriptor

Interaction

Choose an expected frame size of 1060 bytes.

Choose buffer sizes of 800, 200 and 200 bytes.

1. Assume that a 1060 byte frame arrives correctly,

and that the timing of the early interrupt and the soft-

ware is s mooth. The descr ip tors wi ll have change d

from:

*ENP or ERR

2. Assume that instead of the expected 1060 byte

frame, a 900 byte frame arrives, either because

there was an error in the network, or because this is

the last frame in a file transmission sequence.

*ENP or ERR

** Note that the PCnet-ISA II controller might write a ZERO to ENP lo cation in the 3rd descriptor. Here are the two possibilities:

1. If the c ontrol ler fini shes the da ta tr ansfers into b uffer nu mber 2 a fter the driv er writes the app licati on’s modified b uffer pointer

into the third descriptor, then the controller wi ll write a ZERO to ENP for this buffer and will write a ZERO to OWN and STP.

2. If the controller finishes the data transf ers into buff er number 2 before th e driver writes the application’s modified b uffer pointer

into the third descriptor , then the co ntroller will comp lete the fram e in buff er number two and then skip the then uno wned third

buf f er. In this c ase, the PCne t-ISA II control ler wil l not ha ve had the o pportunity to RESET the ENP bit in this descriptor, and

it is possible that the software left this bit as ENP=1 from the last time through the ring. Therefore, the software must treat

the location as a don’t care; The rule is, after finding ENP=1 (or ERR=1) in descriptor number 2, the software must ignore

ENP bits until it finds the next STP=1.

Descriptor

Number Before the Frame Arrived After the Frame Has Arrived Comments

(After Frame Arrival)

OWN STP ENP* OWN STP ENP*

111X010Bytes 1–800

2 1 0 X 0 0 0 Bytes 801–1000

3 0 0 X 0 0 1 Bytes 1001–1060

4 1 1 X 1 1 X Controller’s current loca tion

5 1 0 X 1 0 X Not yet used

6 0 0 X 0 0 X Not yet used

etc. 1 1 X 1 1 X Not yet used

Descriptor

Number

Before the Frame Arrived After the Frame Has Arrive d Comments

(After Frame Arrival)

OWN STP ENP* OWN STP ENP*

111X010Bytes 1–800

2 1 0 X 0 0 1 Bytes 801–900

3 0 0 X 0 0 ?** Discarded buffer

4 1 1 X 1 1 X Controller’s current loca tion

5 1 0 X 1 0 X Not yet used

6 0 0 X 0 0 X Not yet used

etc. 1 1 X 1 1 X Not yet used

196 Am79C961A

3. Assume that instead of the expected 1060 byte

frame, a 100 byte frame arrives, because there was

an error in the network, or because this is the last

frame in a file transmission sequence, or perhaps

because it is an acknowledge frame.

*ENP or ERR

** Same as note in case 2 abo v e, except that in this c ase, it is v ery unlik ely that the driver c an respond to the interrupt and get the

pointer from the application bef ore the PCnet-ISA II controller has completed its poll of the ne xt descriptors. Thi s means that for

almost all occurrences of this case , the PCnet-ISA II controller will not find the OWN bit set f or this descriptor and therefore, the

ENP bit will almost always contain the old value , sinc e the PCnet-ISA II controller will not have had an opportunity to modi fy it.

*** Note that ev en though the PCnet-ISA II co ntroller will write a ZERO to this ENP location, the software should treat the location

as a d on’t care, since after finding the ENP=1 in descriptor number 2, the software should ignore ENP bits until it finds the

next STP=1.

Buffer Size Tuning

For maximum performance, buffer sizes should be

adjusted depending upon the expected frame size and

the values of the interrupt latency and application call

latency. The best driver code will minimize the CPU

utilization while also minimizing the latency from frame

end on the network to frame sent to application from

driver (frame latency). These objectives are aimed at

increasing throughput on the network while decreasing

CPU utilization.

Note that the buffer sizes in the r ing may be altere d at

any time that the CPU has ownership of the corre-

sponding descriptor. The best choice for buffer sizes

will maximize the time that the dr iver is swapped out,

while minimi zing the time from the l ast byte wr itten by

the PCnet-ISA II controller to the time that the data is

passed from the driver to the application. In the

diagram, this corresponds to maximizing S0, while min-

imizing the time between C9 and S8. (The timeline

happens to show a minimal time from C9 to S8.)

Note that b y increasing the size of buffer number 1, we

increa se the value o f S0. However, when we inc reas e

the s ize of buffer n um ber 1, we al so increase the value

of S4. If the size of bu ffer number 1 is too large, then

the driver will not have enough time to perform tasks

S2, S3, S 4, S 5 an d S 6. T he re su lt i s that there wil l b e

delay from the exec uti on of t as k C 9 u nti l th e exe cu tio n

of task S8. A perfectly timed system will have the

values for S5 and S7 at a minimum.

An average incr ea s e in performanc e ca n be ac hi eved if

the general guidelines of buffer sizes in Figure 2 is fol-

lowed. Howev er , as was noted earlier , the correct sizing

f or b uff er s will d epend u pon th e e xpect ed mess age siz e.

There are two problems with relating expected message

size with the correct buffer sizing:

1. Message sizes cannot always be accurately

predicted, since a single application may expect

different mess age sizes at di ffe rent tim es, therefore,

the buffer sizes chosen will not always maximize

throughput.

2. Within a single application, message sizes might be

somewhat predicta ble, but when th e same dr iver is

to be shared with multiple applications, there may

not be a common predictable message size.

Additional problems occur when trying to define the

correct sizing because the correct size also depends

upon the interrupt latency, which may v ary from system

to system, depe ndi ng up on bo th the ha rd ware and the

software installed in each system.

In order to deal with the unpredictable nature of the

message size, the driver can implement a self tuning

Descriptor

Number

Before the Frame Arrived After the Frame Has Arrive d Comments

(After Frame Arrival)

OWN STP ENP* OWN STP ENP*

111X011Bytes 1–100

2 1 0 X 0 0 0*** Discarded buffer

3 0 0 X 0 0 ?** Discarded buffer

4 1 1 X 1 1 X Controller’s current loca tion

5 1 0 X 1 0 X Not yet used

6 0 0 X 0 0 X Not yet used

etc. 1 1 X 1 1 X Not yet used

Am79C961A 197

mechanism that examines the amount of time spent in

tasks S5 and S7 as such: While the driver is polling for

each descriptor, it could count the number of poll oper-

ations performed and then adjust the number 1 buffer

size to a larger value, by adding “t” bytes to the buffer

count, if the number of poll operations was greater than

“x”. If fewer than “x” poll operations were needed for

each of S5 and S7, then the software should adjust the

buffer size to a smaller value by, subtracting “y” byte s

from the buffer count . E x periments with suc h a tun in g

mechanism must be performed to determine the best

val ues for “X” and “y.”

Note whenev er the size of buff er number 1 is adjusted,

buffer sizes for buffer number 2 and buffer 3 should

also be adjusted.

In some systems the typical mix of receive frames on a

network f or a client application consists mostly of large

data frames, with very few small frames. In this case,

for maximum efficiency of buffer sizing, wh en a frame

arr ives under a cert ain size limit, th e driver shoul d not

adjust the buffer sizes in response to the short frame.

An Alternative LAPP Flow - the TWO Interrupt

Method

An alternative to the above suggested flow is to use

two interrupts, one at the start of the Receive frame

and the other at the end of the receive frame, instead

of just looking for the SRP interrupt as was descr ib ed

above. This alternative attempts to reduce the

amount of time that the software “wastes” while poll-

ing for descriptor own bits. This time would then be

available for other CPU tasks. It also minimizes the

amount of time the CPU needs for data copying. This

savings can be applie d to other CPU tasks.

The time from the end of frame arrival on the wire to

delivery of the frame to the application is labeled as

frame latency. For the one-interrupt method, frame

latency is minimized, while CPU utilization increases.

For the two-interrupt method, frame latency becomes

greater, while CPU utilization decreases.

Note that some of the CPU tim e that c an be applied to

non-Ethernet tasks is used for task switching in the

CPU . One task switch is required to swap a non-Ether-

net task into the CPU (after S7A) and a second task

switch is needed to swap the Ethernet driver back in

again (at S8A). If the time needed to perform these

task switches exceeds the time saved by not polling

descriptors, then there is a net loss in performance with

this method. Therefore, the NEW WORD method im-

plemented should be carefully chosen.

Figure 3 shows the event flow for the two-interrupt

method.

Figure 4 shows the buffer sizing for the two-interrupt

method. Note tha t the se cond buffer size will be about

the same for each method.

There is another alter native which is a marriage of the

two previous meth ods. This thi rd possi bility would use

the buffer sizes set by the two-interrupt method, but

would use the polling method of determining frame

end. T hi s wi ll gi ve good fra me la tenc y but at the p ri c e

of very high CPU utilization.

And still, there are even more compromise positions

that use various fixed buffer sizes and effectively, the

flow of the o ne- i nterrupt m eth od. A ll o f these com pr o-

mises will reduce the complexity of the one-interrupt

method by removing the heuristic buffer sizing code,

but they all become less efficient than heuristic code

would allow.

198 Am79C961A

Buffer

Ethernet

Wire

activity:

Ethernet

Controller

activity:

Software

activity:

S10: Driver sets up TX descriptor.

S9: Application processes packet, generates TX packet.

S8: Driver calls application

to tell application that

packethas arrived.

S7: Driver is swapped out, allowing a non-Ethernet

application to run.

S6: Driver copies data from buffer #2 to the application

buffer.

S5: Driver polls descriptor #2.

S4: Driver copies data from buffer #1 to the application

buffer. S3: Driver writes modified application

pointer to descriptor #3.

S2: Driver call to application to

get application buffer pointer.

S1: Interrupt latency.

S0: Driver is idle.

}

N2:EOM

N0: Packet preamble, SFD

and destination address

are arriving.

{

Packet data arriving

}

C9: Controller writes descriptor #3.

C8: Controller is performing intermittent

bursts of DMA to fill data buffer #3.

C7: Controller writes descriptor #2.

C6: "Last chance" lookahead to

descriptor #3 (OWN).

C5: Controller is performing intermittent

bursts of DMA to fill data buffer #2

C3: SRP interrupt is

generated.

C2: Controller writes descriptor #1.

C1: Controller is performing intermittent

bursts of DMA to fill data buffer #1.

C0: Lookahead to descriptor #2.

N1: 64th byte of packet

data arrives.

C10: ERP interrupt

is generated. }S8A: Interrupt latency.

}

S7A: Driver Interrupt Service

Routine executes

RETURN.

C4: Lookahead to descriptor #3 (OWN).

19364B-89

Figure 3. LAPP TImeline for TWO-INTERR UPT Method

Am79C961A 199

Descriptor

OWN = 1 STP = 1

SIZE = HEADER_SIZE (minimum 64 bytes)

OWN = 1 STP = 0

SIZE = S1+S2+S3+S4

OWN = 0 STP = 0

SIZE = 1518 - (S1+S2+S3+S4+HEADER_SIZE)

OWN = 1 STP = 1

SIZE = HEADER_SIZE (minimum 64 bytes)

OWN = 1 STP = 0

SIZE = S1+S2+S3+S4

OWN = 0 STP = 0

SIZE = 1518 - (S1+S2+S3+S4+HEADER_SIZE)

OWN = 1 STP = 1

SIZE = HEADER_SIZE (minimum 64 bytes)

OWN = 1 STP = 0

SIZE = S1+S2+S3+S4

OWN = 0 STP = 0

SIZE = 1518 - (S1+S2+S3+S4+HEADER_SIZE)

A = Expected message size in bytes

S1 = Interrupt latency

S2 = Application call latency

S3 = Time needed for driver to write

to third descriptor

S4 = Time needed for driver to copy

data from buffer #1 to

application buffer space

S6 = Time needed for driver to copy

data from buffer #2 to

application buffer space

Note that the times needed for tasks S1,

S2, S3, S4, and S6 should be divided by

0.8 microseconds to yield an equivalent

number of network byte times before

subtracting these quantities from the

expected message size A.

19364B-90

Figure 4. LAPP 3 Buffer Grouping for TWO-INTERRUPT Method

200 Am79C961A

APPENDIX F

Am79C961A 201

Some Characteristics of the

XXC56 Serial EEPROMs

SWITCHING CHARACTERISTICS of a TYPICAL XXC56 SERIAL EEPROM INTERFACE

Applicable over recommended operating rang e from TA = –40×C to +85×C, VCC = +1.8 V

to +5.5 V, CL = 1 TTL Gate and 100 pF (unless otherwise noted)

Notes:

1. The SK frequency specifies a minimum SK clock period of 2 µs, therefore in an SK clock cycle tSKH + tSKL must be gr eat er

than or equal to 2 µs. For example, if the tSKL = 500 ns then the minimum tSKH = 1.5 µs in order to meet the SK frequency

specification.

2. CS must be brought low for a minimum of 500 ns (tCS) between consecutive instruction cycles.

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

fSK SK Clock Frequen cy 0 0.5 MHz

tSKH SK High Time (Note 1) 500 ns

tSKL SK Low Time (Note 1) 500 ns

tCS Minimum CS Low Time (Note 2) 500 ns

tCSS CS Setup Time Relative to SK 100 ns

tDIS DI Setup Time Relative to SK 200 ns

tCSH CS Hold Time Relative to SK 0 ns

tDIH DI Hold Time Relative to SK 200 ns

tPD1 Output Delay to ‘1’AC Test 1000 ns

tPD0 Output Delay to ‘0’AC Test 1000 ns

tSV CS to Status Valid AC Test 1000 ns

tDF CS to DO in High Impedance AC Test; CS = VIL 200 ns

tWP Write Cycle Time 10 ms

Endura nc e Num ber of Data

Changes per Bit Typical 100,000 Cycles

202 Am79C961A

INSTRUCTION SET FOR THE XXC56 SERIES OF EEPROMS

Note:

1. This is the minimum SK period.

Address Data

Instruction SB Op

Code x8 x16 x8 x16 Comments

READ 1 10 A8–A0 A7–A0 Reads data stored in memory, at

specified address

EWEN 1 00 11XXXXXXX 11XXXXXX Write enable must precede all

programming modes

ERASE 1 11 A8–A0 A7–A0 Erases memory location An–A0

WRITE 1 01 A0–A0 A7–A0 D7–D0 D15–D0 Writes memory location An–A0

ERAL 1 00 10XXXXXXX 10XXXXXX Erases all memory locations.

Valid only at VCC = 4.5 V to 5.5 V

WRAL 1 00 01XXXXXXX 01XXXXXX D7–D0 D15–D0 Writes all memory locations. Valid

when VCC = 5.0 V ± 10% and

Disable Register clear ed

EWDS 1 00 00XXXXXXX 00XXXXXX Disables all programming

instructions

DO (PROGRAM)

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VOH

VOL

DO (READ)

Status Valid

1 µs (1)

tCSS tSKH tSKL

tCSH

tDIS tDIH

tPDO tPDI tDF

tDF

tSV

19364B-91

Typical XXC56 Series

Serial EEPROM Control Timing

APPENDIX G

Am79C961A 203

Am79C961A PCnet-ISA II

Silicon Errata Report

AM79C961A REV FD SILICON STATUS

The items below are the known errata for Rev FD silicon. Rev FD silicon is the production silicon.

Note: A signal followed by "*" indicates active low; i.e., MASTER*.

The Description section of this document gives an external description of the problem. The Implication section

gives an explanati on of how the PCnet-ISA II c ontroller behave s and its impact on the system. The Work-around

section describes a work around for the problem.

The Status section indicates when and how the problem will be fixed.

Current package marking for this revision: Line 1: <Logo>

Line 2: PCnet(tm)-ISA II

Line 3: Am79C961AKC (Assuming package is PQFP)

Line 4: <Date Code> FD

Value of chip identification registers, CSR89+CSR88 [31:0] for this revision = 32261003h.

1) False BABL err ors generated

Description: The PCnet-ISA II FD device will intermittenly give BABL error indications when the network traffic has

frames equal to or greater than 1518 bytes.

Implication: False BABL errors on the receiving station can be passed up to the upper lay er software if PCnet-ISA

II FD device is just coming out of deferral and the multi-purpose counter used to count the number of bytes re-ce vied

reaches 15 18 at t he s ame tim e. If the network is heavily lo aded with ful l-si ze frames, then the proba bil ity of a false

BABL error is high.

Work-around: There are two possible work-arounds.

1. If the user has no intention to transmit frames larger than 1518 bytes, then the BABL bit may be mask ed to ignore

babble errors. In this ca se the false babble error wi ll not cau se an i nter r up t, nor will it be pa ss ed to th e hi ghe r level

software.

2. Check to see if the device is transmitti ng in ISR (Inter r u pt Service Routine) , whi ch is induced by the BABL error.

The BCRs which control the LED settings can be programmed to indicate a transmit activity, assuming the interrupt

latency is not longer than one mininum IFG (inter-frame gap) time.

If (ISR_LATENCY < 9.6 us)

True_bable_err = BABL * ( TINT + XMT_LED)

{ i.e. False_bable_err = ~ (BABL * ( TINT + XMT_LED))}

else

Cannot tell if the BABL error is true or false just by reading BABL, TINT, XMT_LED

bits in ISR.

Status: No current plan to fix this item.

204 Am79C961A

2) DRQ inactive to MASTER* inactive time

Description: T he data sheet lists a minimum limit of 40ns for the time that DRQ goes inactiv e until MASTER* goes

inactive. During the course of device characterization a minimum value of less than 40ns has been observed.

The lower limit for this parameter therefore has been changed to 30ns. (DRQ inactive to MASTER* inactive time).

Implication: There is no jeopardy because of this change. The device tristates its active command, SBHE, SA, and

LA lines before MASTER* goes inactive.

Work-around: None required.

Status: Data sheet limit will be changed. There will be no change to the silicon.

3) DRQ inactive to Command, SBHE*, SA0-9 and LA17-23 tristated.

Description: The data sheet lists a maximum limit of 0ns for the time that DRQ goes inactive until Command,

SBHE*, SA0-9 and LA17-23 signals tristate. During the course of de vice characterization a maximum value of more

than 0ns has been observed. The upper limit for this parameter theref ore has been changed to 10ns. (DRQ inactiv e

to Command, SBHE*, SA0-9 and LA17-23 tristated)

Implication: T here is no jeopardy because of this ch ange. The MASTER * which control s the IO on the bus goes

inactive after this time.

Work-around: None required.

Status: Data sheet limit will be changed. There will be no change to the silicon.

Am79C961A 205

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