128MB / 256MB (x72) 168-PIN REGISTERED SDRAM DIMMs SYNCHRONOUS DRAM MODULE MT9LSDT1672 - 128MB MT9LSDT3272 - 256MB For the latest data sheet, please refer to the Micron Web site: www.micron.com/datasheets FEATURES PIN ASSIGNMENT (FRONT VIEW) 168-PIN DIMMS * JEDEC-standard 168-pin, dual in-line memory module (DIMM) * PC133- and PC100-compliant * Registered inputs with one-clock delay * Phase-lock loop (PLL) clock driver to reduce loading * ECC-optimized pinout * 128MB (16 Meg x 72), 256MB (32 Meg x 72) * Single +3.3V 0.3V power supply * Fully synchronous; all signals registered on positive edge of PLL clock * Internal pipelined operation; column address can be changed every clock cycle * Internal SDRAM banks for hiding row access/ precharge * Programmable burst lengths: 1, 2, 4, 8, or full page * Auto Precharge and Auto Refresh Modes * Self Refresh Mode * 64ms refresh (128MB - 4,096 cycles; 256MB - 8,192 cycles) * LVTTL-compatible inputs and outputs * Serial Presence-Detect (SPD) OPTIONS Standard Low Profile PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 MARKING * Package 168-pin DIMM (gold) G * Frequency/CAS Latency* 133 MHz/CL = 3 -13E 133 MHz/CL = 4 -133 100 MHz/CL = 3 -10E * Standard or Low Profile PCB Contact Factory * Module latency; extra clock cycle due to input register when in registered mode. DEVICE TIMING Module Markings PC100 CL - tRCD - tRP PC133 CL - tRCD - tRP -13E -133 -10E 2-2-2 2-2-2 2-2-2 2-2-2 3-3-3 NA ADDRESS TABLE Refresh Count Device Banks Row Addressing Column Addressing Module Banks 128MB Module 256MB Module 4K 4 (BA0, BA1) 4K (A0-A11) 1K (A0-A9) 1 (S0,S2) 8K 4 (BA0, BA1) 8K (A0-A12) 1K (A0-A9) 1 (S0,S2) SYMBOL VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 CB0 CB1 VSS NC NC VDD WE# DQMB0 DQMB1 S0# DNU VSS A0 A2 A4 A6 A8 A10 BA1 VDD VDD CK0 PIN SYMBOL 43 VSS 44 DNU 45 S2# 46 DQMB2 47 DQMB3 48 DNU 49 VDD 50 NC 51 NC 52 CB2 53 CB3 54 VSS 55 DQ16 56 DQ17 57 DQ18 58 DQ19 59 VDD 60 DQ20 61 NC 62 NC 63 RFU 64 VSS 65 DQ21 66 DQ22 67 DQ23 68 VSS 69 DQ24 70 DQ25 71 DQ26 72 DQ27 73 VDD 74 DQ28 75 DQ29 76 DQ30 77 DQ31 78 VSS 79 CK2 80 NC 81 WP 82 SDA 83 SCL 84 VDD PIN SYMBOL PIN 85 VSS 127 86 DQ32 128 87 DQ33 129 88 DQ34 130 89 DQ35 131 90 VDD 132 91 DQ36 133 92 DQ37 134 93 DQ38 135 94 DQ39 136 95 DQ40 137 96 VSS 138 97 DQ41 139 98 DQ42 140 99 DQ43 141 100 DQ44 142 101 DQ45 143 102 VDD 144 103 DQ46 145 104 DQ47 146 105 CB4 147 106 CB5 148 107 VSS 149 108 NC 150 109 NC 151 110 VDD 152 111 CAS# 153 112 DQMB4 154 113 DQMB5 155 114 RFU 156 115 RAS# 157 116 VSS 158 117 A1 159 118 A3 160 119 A5 161 120 A7 162 121 A9 163 122 BA0 164 123 A11 165 124 VDD 166 125 CK1 167 126 RFU/A12* 168 SYMBOL VSS CKE0 RFU DQMB6 DQMB7 NC VDD NC NC CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 VDD DQ52 NC NC REGE VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS CK3 NC SA0 SA1 SA2 VDD NOTE: Symbols in parentheses are not used on these modules but may be used for other modules in this product family. They are for reference only. *RFU on 128MB, A12 on 256MB 16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs SD9C16_32X72G_A.p65 - Rev. 4/02 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. 128MB / 256MB (x72) 168-PIN REGISTERED SDRAM DIMMs PART NUMBERS PART NUM BER MT9LSDT1672G-13E__ MT9LSDT1672G-133__ MT9LSDT1672G-10E__ MT9LSDT3272G-13E__ MT9LSDT3272G-133__ MT9LSDT3272G-10E__ CONFIGURATION 16 Meg x 72 16 Meg x 72 16 Meg x 72 32 Meg x 72 32 Meg x 72 32 Meg x 72 clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the PRECHARGE cycles and provide seamless, high-speed, random-access operation. These modules are designed to operate in 3.3V, lowpower memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAM modules offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks in order to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access. For more information regarding SDRAM operation, refer to the 128Mb and 256Mb SDRAM data sheets. SYSTEM BUS SPEED 133 MHz 133 MHz 100 MHz 133 MHz 133 MHz 100 MHz NOTE: The designators for component and PCB revision are the last two characters of each part number. Consult factory for current revision codes. Example: MT9LSDT1672G-133B1 GENERAL DESCRIPTION PLL AND REGISTER OPERATION The MT9LSDT1672 and MT9LSDT3272 are highspeed CMOS, dynamic random-access, 128MB and 256MB memory modules organized in x72 configurations. These modules use internally configured quadbank SDRAMs with a synchronous interface (all signals are registered on the positive edge of clock signals CK0). Read and write accesses to the SDRAM modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the device bank and row to be accessed (BA0, BA1 select the device bank; A0-A11 for 128MB/A0-A12 for 256MB, select the device row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. These modules provide for programmable READ or WRITE burst lengths of 1, 2, 4, or 8 locations, or full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. These modules use an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every 16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs SD9C16_32X72G_A.p65 - Rev. 4/02 These modules can be operated in either registered mode (REGE pin HIGH), where the control/address input signals are latched in the register on one rising clock edge and sent to the SDRAM devices on the following rising clock edge (data access is delayed by one clock), or in buffered mode (REGE pin LOW) where the input signals pass through the register/buffer to the SDRAM devices on the same clock. A phase-lock loop (PLL) on the modules is used to redrive the clock signals to the SDRAM devices to minimize system clock loading (CK0 is connected to the PLL, and CK1, CK2, and CK3 are terminated). SERIAL PRESENCE-DETECT OPERATION These modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 2,048bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard IIC bus using the DIMM's SCL (clock) and SDA (data) signals, together with SA(2:0), which provide eight unique DIMM/EEPROM addresses. 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. 128MB / 256MB (x72) 168-PIN REGISTERED SDRAM DIMMs FUNCTIONAL BLOCK DIAGRAM STANDARD PCB LAYOUT RS0# RDQMB0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 RDQMB4 DQM CS# DQ0 DQ1 U1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 RDQMB1 DQM CS# DQ0 DQ1 U14 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 RDQMB5 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM CS# DQ0 DQ1 U2 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DQM CS# DQ0 DQ1 U12 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQM CS# DQ0 DQ1 U13 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 RS2# RDQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 RDQMB6 DQM CS# DQ0 DQ1 U3 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 RDQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQM CS# DQ0 DQ1 U11 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 RDQMB7 DQM CS# DQ0 DQ1 U4 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQM CS# DQ0 DQ1 U10 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U5, U7 RAS# R E G I S T E R CAS# CKE0 WE# A0-A12* BA0 BA1 S0#, S2# DQMB0-DQMB7 RRAS#: SDRAMs U1-4, U10-14 U6 RCAS#: SDRAMs U1-4, U10-14 CK0 RCKE0: SDRAMs U1-4, U10-14 RWE#: SDRAMs U1-4, U10-14 PLL 12pF SDRAM x 3 SDRAM x 3 SDRAM x 3 REGISTER x 2 RA0-RA11: SDRAMs U1-4, U10-14 RBA0: SDRAMs U1-4, U10-14 CK1-CK3 RBA1: SDRAMs U1-4, U10-14 12pF RS0#, RS2# RDQMB0-RDQMB7 PLL CLK 10K VDD REGE NOTE: U8 SCL WP 47K SPD U9 A0 A1 A2 SDA SA0 SA1 SA2 VDD SDRAMs U1-4, U10-14 VSS SDRAMs U1-4, U10-14 U1-4, U10-14 = MT48LC16M8A2TG SDRAMs for 128MB U1-4, U10-14 = MT48LC32M8A2TG SDRAMs for 256MB 1. All resistor values are 10 ohms unless otherwise specified. *A12 for 256MB module, A11 for 128MB Module 16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs SD9C16_32X72G_A.p65 - Rev. 4/02 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. 128MB / 256MB (x72) 168-PIN REGISTERED SDRAM DIMMs FUNCTIONAL BLOCK DIAGRAM LOW PROFILE PCB LAYOUT RS0# RDQMB0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 RDQMB4 DQM CS# DQ0 DQ1 U1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 RDQMB1 DQM CS# DQ0 DQ1 U14 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 RDQMB5 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM CS# DQ0 DQ1 U2 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DQM CS# DQ0 DQ1 U3 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQM CS# DQ0 DQ1 U13 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 RS2# RDQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 RDQMB6 DQM CS# DQ0 DQ1 U5 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 RDQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQM CS# DQ0 DQ1 U10 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 RDQMB7 DQM CS# DQ0 DQ1 U6 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQM CS# DQ0 DQ1 U9 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U12, U11 RAS# R E G I S T E R CAS# CKE0 WE# A0-A12* BA0 BA1 S0#, S2# DQMB0-DQMB7 RRAS#: SDRAMs U1-3, 5-6, 9-10, 13-14 U4 RCAS#: SDRAMs U1-3, 5-6, 9-10, 13-14 CK0 RCKE0: SDRAMs U1-3, 5-6, 9-10, 13-14 RWE#: SDRAMs U1-3, 5-6, 9-10, 13-14 PLL 12pF SDRAM x 3 SDRAM x 3 SDRAM x 3 REGISTER x 2 RA0-RA11: SDRAMs U1-3, 5-6, 9-10, 13-14 RBA0: SDRAMs U1-3, 5-6, 9-10, 13-14 CK1-CK3 RBA1: SDRAMs U1-3, 5-6, 9-10, 13-14 12pF RS0#, RS2# RDQMB0-RDQMB7 PLL CLK 10K VDD REGE NOTE: U8 SCL WP 47K SPD U7 A0 A1 A2 SDA SA0 SA1 SA2 VDD SDRAMs U1-3, 5-6, 9-10, 13-14 VSS SDRAMs U1-3, 5-6, 9-10, 13-14 U1-3, 5-6, 9-10, 13-14 = MT48LC16M8A2TG SDRAMs for 128MB U1-3, 5-6, 9-10, 13-14 = MT48LC32M8A2TG SDRAMs for 256MB 1. All resistor values are 10 ohms unless otherwise specified. *A12 for 256MB module, A11 for 128MB module. 16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs SD9C16_32X72G_A.p65 - Rev. 4/02 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. 128MB / 256MB (x72) 168-PIN REGISTERED SDRAM DIMMs PIN DESCRIPTIONS PIN NUMBERS SYMBOL TYPE 27, 111, 115 WE#, CAS#, RAS# Input Command Inputs: WE#, RAS#, and CAS# (along with S0#, S2#) define the command being entered. 42, 79, 125, 163 CK0-CK3 Input Clock: CK0 is distributed through an on-board PLL to all devices. CK1-CK3 are terminated. 128 CKE0 Input Clock Enable: CKE0 activates (HIGH) and deactivates (LOW) the CK0 signal. Deactivating the clock provides POWERDOWN and SELF REFRESH operation (all device banks idle) or CLOCK SUSPEND operation (burst access in progress). CKE0 is synchronous except after the device enters powerdown and self refresh modes, where CKE0 becomes asynchronous until after exiting the same mode. The input buffers, including CK0, are disabled during power-down and self refresh modes, providing low standby power. 30, 45 S0#, S2# Input Chip Select: S0#, S2# enable (registered LOW) and disable (registered HIGH) the command decoder. All commands are masked when S0#, S2# are registered HIGH. S0#, S2# are considered part of the command code. 28-29, 46-47, 112-113, 130-131 DQMB0DQMB7 Input Input/Output Mask: DQMB is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked when DQMB is sampled HIGH during a WRITE cycle. The output buffers are placed in a High-Z state (twoclock latency) when DQMB is sampled HIGH during a READ cycle. 39, 122 BA0, BA1 Input Bank Address: BA0 and BA1 define to which device bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. 33, 34, 35, 36, 37, 38, 117, 118, 119, 120, 121, 123 A0-A11, 128MB; A0-A12, 256MB Input Address Inputs: A0-A11 are sampled during the ACTIVE command (row-address A0-A11) and READ/WRITE command (column-address A0-A9, with A10 defining auto precharge) to select one location out of the memory array in the respective devicebank. A10 is sampled during a PRECHARGE command to determine if both device banks are to be precharged (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE REGISTER command. 126 RFU/A12 Input Reserved for future use on 128MB module; Address input A12 on 256MB module. 81 WP Input Write Protect: Serial presence-detect hardware write protect. 83 SCL Input Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. 165-167 SA0-SA2 Input Presence-Detect Address Inputs: These pins are used to configure the presence-detect device. 147 REGE Input Register Enable. 16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs SD9C16_32X72G_A.p65 - Rev. 4/02 DESCRIPTION 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. 128MB / 256MB (x72) 168-PIN REGISTERED SDRAM DIMMs PIN DESCRIPTIONS (continued) PIN NUMBERS SYMBOL TYPE 2-5, 7-11, 13-17, 19-20, 55-58, 60, 65-67, 69-72, 74-77, 86-89, 91-95, 97-101, 103-104, 139-142, 144, 149-151, 153-156, 158-161 DQ0-DQ63 Input/ Output Data I/Os: Data bus. 21-22, 52-53, 105-106, 136-137 82 CB0-CB7 Input/ Output Input/ Output Check Bits. 6, 18, 26, 40-41, 49, 59, 73, 84, 90, 102, 110, 124, 133, 143, 157, 168 VDD Supply Power Supply: +3.3V 0.3V. 1, 12, 23, 32, 43, 54, 64, 68, 78, 85, 96, 107, 116, 127, 138, 148, 152, 162 VSS Supply Ground. 24, 25, 31, 44, 48, 50, 51, 61,62, 80, 108, 109, 132, 134, 135,145, 146 NC - Not Connected: These pins are not connected on this module but are assigned pins on the compatible DRAM version. 63 RFU - Reserved for Future Use: CKE1 114 RFU - Reserved for Future Use: S1# 129 RFU - Reserved for Future Use: S3# 16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs SD9C16_32X72G_A.p65 - Rev. 4/02 SDA DESCRIPTION Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer addresses and data into and data out of the presence-detect portion of the module. 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. 128MB / 256MB (x72) 168-PIN REGISTERED SDRAM DIMMs SDRAM FUNCTIONAL DESCRIPTION Mode Register Definition In general, the 128Mb and 256Mb SDRAM memory devices used for these modules are quad-bank DRAMs, that operate at 3.3V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). The four banks of a x8, 128Mb device are each configured as 4,096 bit-rows, by 1,024 bitcolumns, by 8 input/output bits. The four banks of a x8, 256Mb device are configured as 8,192 bit-rows by 1,024 bit columns, by 8 input/output bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the device bank and row to be accessed BA0 and BA1 select the device bank, A0-A11 (for 128Mb), or A0-A12 (for 256Mb), select the device row. The address bits A0-A9, registered coincident with the READ or WRITE command are used to select the starting device column location for the burst access. Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. MODE REGISTER The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in the Mode Register Definition Diagram (p. 9). The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. Mode register bits M0-M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4-M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M10 and M11 are reserved for future use. The mode register must be loaded when all device banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Burst Length Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in the Mode Register Definition Diagram (p. 9). The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached, as shown in the Burst Definition Table (p. 9). The block is uniquely selected by A1A9 when the burst length is set to two; A2-A9 when the burst length is set to four; and by A3-A9 when the burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached. Initialization SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Once power is applied to VDD and VDDQ (simultaneously) and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the SDRAM requires a 100s delay prior to issuing any command other than a COMMAND INHIBIT or NOP. Starting at some point during this 100s period and continuing at least through the end of this period, COMMAND INHIBIT or NOP commands should be applied. Once the 100s delay has been satisfied with at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command should be applied. All device banks must then be precharged, thereby placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for mode register programming. Because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command. 16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs SD9C16_32X72G_A.p65 - Rev. 4/02 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. 128MB / 256MB (x72) 168-PIN REGISTERED SDRAM DIMMs CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in the CAS Latency Diagram. The CAS Latency Table indicate the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Operating Mode The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Write Burst Mode When M9 = 0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses. CAS Latency Table ALLOWABLE OPERATING FREQUENCY (MHz) T0 T1 T2 T3 CLK COMMAND READ NOP SPEED -13E -133 -10E NOP tLZ tOH DOUT DQ CAS LATENCY = 2* 133 100 100 CAS LATENCY = 3* 143 133 125 tAC * When in registered mode, input register will add one extra clock. CAS Latency = 2 T0 T1 T2 T3 NOP NOP NOP T4 CLK COMMAND READ tLZ tOH DOUT DQ tAC CAS Latency = 3 DON'T CARE UNDEFINED CAS Latency Diagram 16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs SD9C16_32X72G_A.p65 - Rev. 4/02 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. 128MB / 256MB (x72) 168-PIN REGISTERED SDRAM DIMMs Burst Definition Table Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in the Burst Definition Table. A12 A11 A10 A9 A8 A6 A7 A5 A4 A3 A1 A2 Burst Length 2 Address Bus A0 4 12 11 10 9 8 6 7 Reserved* Reserved* WB Op Mode 5 4 CAS Latency 3 1 2 BT 0 Mode Register (Mx) Burst Length *Should program M12, M11, M10 = 0, 0, 0 to ensure compatibility with future devices. Burst Length M2 M1 M0 M3 = 0 M3 = 1 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Full Page Reserved 8 Full Page (y) 0 Sequential 1 Interleaved M6 M5 M4 CAS Latency 0 0 0 Reserved 0 1 0 2 0 1 1 3 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved M8 M7 M6-M0 Operating Mode 0 0 Defined Standard Operation - - - M9 Write Burst Mode 0 Programmed Burst Length 1 Single Location Access A0 0 1 A1 A0 0 0 0 1 1 0 1 1 A2 A1 A0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 n = A0-9 (location 0-y) 0-1 1-0 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn+1, Cn+2 Cn+3, Cn+4... ...Cn-1, Cn... 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Not supported NOTE: 1. For full-page accesses: y = 1,024 2. For a burst length of two, A1-A9 select the block of two burst; A0 selects the starting column within the block. 3. For a burst length of four, A2-A9 select the block of four burst; A0-A1 select the starting column within the block. 4. For a burst length of eight, A3-A9 select the block of eight burst; A0-A2 select the starting column within the block. 5. For a full-page burst, the full row is selected and A0-A9 select the starting column. 6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. For a burst length of one, A0-A9 select the unique column to be accessed, and Mode Register bit M3 is ignored. Burst Type M3 Starting Column Order of Accesses Within a Burst Address Type = Sequential Type = Interleaved All other states reserved Mode Register Definition Diagram 16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs SD9C16_32X72G_A.p65 - Rev. 4/02 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. 128MB / 256MB (x72) 168-PIN REGISTERED SDRAM DIMMs Commands The Truth Table provides a quick reference of available commands. This is followed by a written description of each command. For a more detailed description of commands and operations refer to the 128Mb or 256Mb SDRAM datasheets. TRUTH TABLE - SDRAM COMMANDS AND DQMB OPERATION (Note: 1; notes appear below table) NAME (FUNCTION) CS# RAS# CAS# WE# DQMB COMMAND INHIBIT (NOP) X NO OPERATION (NOP) L H H H X X X ACTIVE (Select bank and activate row) L L H H X Bank/Row X 3 H L/H8 Bank/Col X 4 Bank/Col Valid L H L X X X DQs NOTES H READ (Select bank and column, and start READ burst) X ADDR X WRITE (Select bank and column, and start WRITE burst) L H L L L/H8 BURST TERMINATE L H H L X X Active PRECHARGE (Deactivate row in bank or banks) L L H L X Code X 5 AUTO REFRESH or SELF REFRESH (Enter self refresh mode) L L L H X X X 6, 7 LOAD MODE REGISTER L L L L X Op-Code X 2 Write Enable/Output Enable - - - - L - Active 8 Write Inhibit/Output High-Z - - - - H - High-Z 8 NOTE: 1. 2. 3. 4. 5. 6. 7. 8. 4 CKE is HIGH for all commands shown except SELF REFRESH. A0-A11, 128MB; and A0-A12, 256MB define the op-code written to the Mode Register. A0-A11, 128MB; and A0-A12, 256MB provide row address, and BA0, BA1 determine which device bank is made active. A0-A8/A9 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which device bank is being read from or written to. A10 LOW: BA0, BA1 determine which device bank is being precharged. A10 HIGH: all device banks are precharged and BA0, BA1 are "Don't Care." This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). 16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs SD9C16_32X72G_A.p65 - Rev. 4/02 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. 128MB / 256MB (x72) 168-PIN REGISTERED SDRAM DIMMs ABSOLUTE MAXIMUM RATINGS* *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage on VDD, VDDQ Supply Relative to VSS ................................. -1V to +4.6V Voltage on Inputs, NC or I/O Pins Relative to VSS ................................. -1V to +4.6V Operating Temperature, TA ............................ 0C to +70C Storage Temperature (plastic) ........... -55C to +150C Power Dissipation ................................................... 9W DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 5, 6; notes appear following parameter tables); (VDD, VDDQ = +3.3V 0.3V) PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES SUPPLY VOLTAGE VDD, VDDQ 3 3.6 V INPUT HIGH VOLTAGE: Logic 1; All inputs VIH 2 VDD + 0.3 V 22 INPUT LOW VOLTAGE: Logic 0; All inputs VIL -0.3 0.8 V 22 II -5 5 A OUTPUT LEAKAGE CURRENT: DQs are disabled; 0V VOUT VDDQ IOZ -5 5 A OUTPUT LEVELS: Output High Voltage (IOUT = -4mA) Output Low Voltage (IOUT = 4mA) VOH 2.4 - V VOL - 0.4 V INPUT LEAKAGE CURRENT: Any input 0V VIN VDD (All other pins not under test = 0V) 16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs SD9C16_32X72G_A.p65 - Rev. 4/02 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. 128MB / 256MB (x72) 168-PIN REGISTERED SDRAM DIMMs IDD SPECIFICATIONS AND CONDITIONS*: 128MB MODULE (Notes: 1, 5, 6, 11, 13; notes appear following the parameter tables); (VDD, VDDQ = +3.3V 0.3V) PARAMETER/CONDITION MAX SYMBOL -13E -133 -10E UNITS NOTES OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE; tRC = tRC (MIN) IDD1 1,215 1,125 1,125 mA 3, 18, 19, 30 STANDBY CURRENT: Power-Down Mode; All device banks idle; CKE = LOW IDD2 18 18 18 mA 30 STANDBY CURRENT: Active Mode; CKE = HIGH; CS# = HIGH; All device banks active after tRCD met; No accesses in progress IDD3 360 360 360 mA 3, 12, 19, 30 OPERATING CURRENT: Burst Mode; Continuous burst; READ or WRITE; All device banks active IDD4 1,215 1,215 1,215 mA 3, 18, 19, 30 AUTO REFRESH CURRENT tRFC = tRFC (MIN) IDD5 2,565 2,430 2,430 mA CKE = HIGH; CS# = HIGH tRFC = 15.625s IDD6 31.5 31.5 31.5 mA 3, 12, 18, 19, 30, 31 SELF REFRESH CURRENT: CKE 0.2V Standard IDD7 22.5 22.5 22.5 mA 4 *DRAM Components only. EEPROM, registers, and PLL not included in these calculations. 16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs SD9C16_32X72G_A.p65 - Rev. 4/02 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. 128MB / 256MB (x72) 168-PIN REGISTERED SDRAM DIMMs IDD SPECIFICATIONS AND CONDITIONS*: 256MB MODULE (Notes: 1, 6, 11, 13; notes appear following parameter tables) (VDD, VDDQ = +3.3V 0.3V) PARAMETER/CONDITION MAX SYMBOL -13E -133 -10E UNITS NOTES OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE; tRC = tRC (MIN) IDD1 1530 1440 1350 mA 3, 18, 19, 30 STANDBY CURRENT: Power-Down Mode; All device banks idle; CKE = LOW IDD2 18 18 18 mA 30 STANDBY CURRENT: Active Mode; CKE = HIGH; CS# = HIGH; All device banks active after tRCD met; No accesses in progress IDD3 540 540 495 mA 3, 12, 19, 30 OPERATING CURRENT: Burst Mode; Continuous burst; READ or WRITE; All device banks active IDD4 1440 1440 1350 mA 3, 18, 19, 30 2700 2700 2700 mA AUTO REFRESH CURRENT tRFC = tRFC (MIN) IDD5 CS# = HIGH; CKE = HIGH tRFC = 7.81 s IDD6 36 36 36 mA 3, 12, 18, 19, 30, 31 SELF REFRESH CURRENT: CKE 0.2V Standard IDD7 36 36 36 mA 4 *DRAM components only. EEPROM, registers, and PLL not included in thes calculations. 16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs SD9C16_32X72G_A.p65 - Rev. 4/02 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. 128MB / 256MB (x72) 168-PIN REGISTERED SDRAM DIMMs CAPACITANCE (Note: 2; notes appear following parameter tables) 128MB SYMBOL MIN MAX PARAMETER 256MB MIN MAX UNITS Input Capacitance: A0-A12, BA0, BA1, RAS#, CAS#, WE# CI1 4 6 4 6 pF Input Capacitance: CK0 CI2 - 4 - 4 pF Input Capacitance: S0#-S2# CI3 4 6 4 6 pF Input Capacitance: CKE0 CI4 4 6 4 6 pF Input Capacitance: DQMB0-DQMB7 CI5 4 6 4 6 pF Input/Output Capacitance: SCL, SA0-SA2 CI6 - 6 - 6 pF Input/Output Capacitance: DQ0-DQ63, SDA CIO 4 6 4 6 pF 16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs SD9C16_32X72G_A.p65 - Rev. 4/02 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. 128MB / 256MB (x72) 168-PIN REGISTERED SDRAM DIMMs ELECTRICAL CHARACTERISTICS AND RECOMMENDED SDRAM DEVICE AC TIMING PARAMETERS* (Notes: 5, 6, 8, 9, 11; notes appear following parameter tables) AC CHARACTERISTICS PARAMETER Access time from CLK (pos. edge) Address hold time Address setup time CLK high-level width CLK low-level width Clock cycle time CKE hold time CKE setup time CS#, RAS#, CAS#, WE#, DQM hold time CS#, RAS#, CAS#, WE#, DQM setup time Data-in hold time Data-in setup time Data-out high-impedance time Data-out low-impedance time Data-out hold time (load) Data-out hold time (no load) ACTIVE to PRECHARGE command ACTIVE to ACTIVE command period ACTIVE to READ or WRITE delay Refresh period (4,096 rows) AUTO REFRESH period PRECHARGE command period ACTIVE bank a to ACTIVE bank b command Transition time WRITE recovery time Exit SELF REFRESH to ACTIVE command CL = 3 CL = 2 CL = 3 CL = 2 CL = 3 CL = 2 -13E -133 -10E SYMBOL MIN MAX MIN MAX MIN MAX tAC (3) 5.4 5.4 6 tAC (2) 5.4 6 6 tAH 0.8 0.8 1 tAS 1.5 1.5 2 tCH 2.5 2.5 3 tCL 2.5 2.5 3 tCK (3) 7 7.5 8 tCK (2) 7.5 10 10 tCKH 0.8 0.8 1 tCKS 1.5 1.5 2 tCMH 0.8 0.8 1 tCMS 1.5 1.5 2 tDH 0.8 0.8 1 tDS 1.5 1.5 2 tHZ (3) 5.4 5.4 6 tHZ (2) 5.4 6 7 tLZ 1 1 1 tOH 3 3 3 tOH 1.8 1.8 1.8 N tRAS 37 120,000 44 120,000 50 120,000 tRC 60 66 70 tRCD 15 20 20 tREF 64 64 64 tRFC 66 66 70 tRP 15 20 20 tRRD 14 15 20 tT 0.3 1.2 0.3 1.2 0.3 1.2 tWR 1 CLK + 1 CLK + 1 CLK + 7ns 7.5ns 7ns 14 67 tXSR 15 75 15 80 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns - NOTES 27 ns ns 25 20 23 23 10 10 28 29 7 24 * Module AC timing parameters comply with PC133 SDRAM Registered DIMM Design Specs, based on component parameters. 16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs SD9C16_32X72G_A.p65 - Rev. 4/02 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. 128MB / 256MB (x72) 168-PIN REGISTERED SDRAM DIMMs AC FUNCTIONAL CHARACTERISTICS* (Notes: 5, 6, 7, 8, 9, 11; notes appear following parameter tables) PARAMETER READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode DQM to input data delay DQM to data mask during WRITEs DQM to data high-impedance during READs WRITE command to input data delay Data-in to ACTIVE command SYMBOL -13E tCCD 1 tCKED 1 tPED 1 tDQD 0 tDQM 0 tDQZ 2 tDWD 0 tDAL 4 -133 1 1 1 0 0 2 0 5 Data-in to PRECHARGE command tDPL 2 2 Last data-in to burst STOP command Last data-in to new READ/WRITE command Last data-in to PRECHARGE command tBDL 1 1 2 1 1 2 2 3 2 2 3 2 tCDL tRDL LOAD MODE REGISTER command to ACTIVE or REFRESH command Data-out to high-impedance from PRECHARGE command tMRD CL = 3 CL = 2 tROH(3) tROH(2) -10E UNITS NOTES tCK 1 17 tCK 1 14, 32 tCK 1 14, 32 tCK 0 17, 32 tCK 0 17, 32 tCK 2 17, 32 tCK 0 17, 32 tCK 4 15, 21, 32 tCK 2 16, 21, 32 tCK 1 17, 32 tCK 1 17, 32 tCK 2 16, 21, 32 tCK 2 26 tCK 3 17, 32 tCK 2 17, 32 * Module AC timing parameters comply with PC133 SDRAM Registered DIMM Design Specs, based on component parameters. 16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs SD9C16_32X72G_A.p65 - Rev. 4/02 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. 128MB / 256MB (x72) 168-PIN REGISTERED SDRAM DIMMs NOTES 1. 2. 3. 4. 5. 6. 7. 8. 9. 14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate. 15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate. 16. Timing actually specified by tWR. 17. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 18. The IDD current will increase or decrease proportionally according to the amount of frequency alteration for the test condition. 19. Address transitions average one transition every two clocks. 20. CLK must be toggled a minimum of two times during this period. 21. Based on tCK = 10ns for -10E, and tCK = 7.5ns for -133 and -13E. 22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width 3ns. 23. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate. 24. Auto precharge mode only. The precharge timing budget (tRP) begins 7ns for -13E; 7.5ns for -133 and 7ns for -10E after the first clock delay, after the last WRITE is executed. May not exceed limit set for precharge mode. 25. Precharge mode only. 26. JEDEC and PC100 specify three clocks. 27. tAC for -133/-13E at CL = 3 with no load is 4.6ns and is guaranteed by design. 28. Parameter guaranteed by design. 29. The value of tRAS. use in -13E speed grade module SPDs is calculated from tRC - tRP = 45ns. 30. For -10E, CL= 2 and tCK = 10ns; for -133, CL = 3 and tCK = 7.5ns; for -13E, CL = 2 and tCK = 7.5ns. 31. CKE is HIGH during refresh command period tRFC (MIN) else CKE is LOW. The IDD6 limit is actually a nominal value and does not result in a fail value. 32. This timing function will incur one extra clock cycle due to the input register when in registered mode. All voltages referenced to VSS. This parameter is sampled. VDD, VDDQ = +3.3V; f = 1 MHz, TA = 25C; pin under test biased at 1.4V. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. Enables on-chip refresh and address counters. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured; (0C TA +70C). An initial pause of 100s is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VDD and VDDQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. AC characteristics assume tT = 1ns. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. Outputs measured at 1.5V with equivalent load: Q 50pF 10. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going High-Z. 11. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced to 1.5V crossover point. If the input transition time is longer than 1 ns, then the timing is referenced at VIL (MAX) and VIH (MIN) and no longer at the 1.5V crossover point. 12. Other input signals are allowed to transition no more than once every two clocks and are otherwise at valid VIH or VIL levels. 13. IDD specifications are tested after the device is properly initialized. 16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs SD9C16_32X72G_A.p65 - Rev. 4/02 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. 128MB / 256MB (x72) 168-PIN REGISTERED SDRAM DIMMs SPD CLOCK AND DATA CONVENTIONS SPD ACKNOWLEDGE Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (Figures 1 and 2). Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data (Figure 3). The SPD device will always respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a WRITE operation have been selected, the SPD device will respond with an acknowledge after the receipt of each subsequent eightbit word. In the read mode the SPD device will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode. SPD START CONDITION All commands are preceded by the start condition, which is a HIGH-to-LOW transition of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. SPD STOP CONDITION All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device into standby power mode. SCL SCL SDA SDA DATA STABLE DATA CHANGE DATA STABLE START BIT Figure 1 Data Validity STOP BIT Figure 2 Definition of Start and Stop SCL from Master 8 9 Data Output from Transmitter Data Output from Receiver Acknowledge Figure 3 Acknowledge Response from Receiver 16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs SD9C16_32X72G_A.p65 - Rev. 4/02 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. 128MB / 256MB (x72) 168-PIN REGISTERED SDRAM DIMMs EEPROM DEVICE SELECT CODE (The most significant bit (b7) is sent first) DEVICE TYPE IDENTIFIER b7 0 0 Memory Area Select Code (two arrays) Protection Register Select Code b6 1 1 b5 1 1 CHIP ENABLE b4 0 0 b3 E2 E2 b2 E1 E1 RW b1 E0 E0 b0 RW RW EEPROM OPERATING MODES (X = VIH or VIL) MODE Current Address Read Random Address Read WC1 X X X X VIL VIL RW BIT 1 0 1 1 0 0 Sequential Read Byte Write Page Write BYTES 1 1 1 1 16 INITIAL SEQUENCE START, Device Select, RW = 1 START, Device Select, RW = 0, Address reSTART, Device Select, RW = 1 Similar to Current or Random Address Read START, Device Select, RW = 0 START, Device Select, RW = 0 SPD EEPROM TIMING DIAGRAM tF t HIGH tR t LOW SCL t HD:STA t SU:STA t SU:DAT t HD:DAT t SU:STO SDA IN t DH t AA t BUF SDA OUT UNDEFINED SERIAL PRESENCE-DETECT EEPROM TIMING PARAMETERS SYMBOL tAA tBUF tDH MIN 4 4.7 MAX UNITS s s s MAX UNITS 0.3 4.7 300 3.5 s s ns 300 tSU:DAT 250 ns tSU:STA tSU:STO 4.7 4.7 s s tF tHD:DAT 0 ns s tHD:STA 4 s 16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs SD9C16_32X72G_A.p65 - Rev. 4/02 SYMBOL tHIGH tLOW tR MIN 19 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. 128MB / 256MB (x72) 168-PIN REGISTERED SDRAM DIMMs SERIAL PRESENCE-DETECT EEPROM DC OPERATING CONDITIONS (Note: 1) (VDD = +3.3V 0.3V) PARAMETER/CONDITION SYMBOL MIN MAX UNITS SUPPLY VOLTAGE VDD 3 3.6 V INPUT HIGH VOLTAGE: Logic 1; All inputs VIH INPUT LOW VOLTAGE: Logic 0; All inputs VIL -1 VDD x 0.3 OUTPUT LOW VOLTAGE: IOUT = 3mA VDD x 0.7 VDD + 0.5 V V VOL - 0.4 V INPUT LEAKAGE CURRENT: VIN = GND to VDD ILI - 10 A OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD ILO - 10 A STANDBY CURRENT: SCL = SDA = VDD - 0.3V; All other inputs = GND or 3.3V +10% ISB - 30 A POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz IDD - 2 mA NOTE: 1. All voltages referenced to VSS. SERIAL PRESENCE-DETECT EEPROM AC OPERATING CONDITIONS (Note: 1) (VDD = +3.3V 0.3V) PARAMETER/CONDITION SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA and SCL fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SDA and SCL rise time SCL clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time SYMBOL tAA tBUF tDH tF tHD:DAT tHD:STA tHIGH tI tLOW tR tSCL tSU:DAT tSU:STA tSU:STO tWRC MIN 0.3 4.7 300 MAX 3.5 300 0 4 4 100 4.7 1 100 250 4.7 4.7 10 UNITS s s ns ns s s s ns s s KHz ns s s ms NOTES 2 NOTE: 1. All voltages referenced to VSS. 2. Timing actually specified by tWR. 16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs SD9C16_32X72G_A.p65 - Rev. 4/02 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. 128MB / 256MB (x72) 168-PIN REGISTERED SDRAM DIMMs SERIAL PRESENCE-DETECT MATRIX BYTE 0 1 2 3 4 5 6 7 8 9 DESCRIPTION NUMBER OF BYTES USED BY MICRON TOTAL NUMBER OF SPD MEMORY BYTES MEMORY TYPE NUMBER OF ROW ADDRESSES NUMBER OF COLUMN ADDRESSES NUMBER OF BANKS MODULE DATA WIDTH MODULE DATA WIDTH (continued) MODULE VOLTAGE INTERFACE LEVELS SDRAM CYCLE TIME, tCK (CAS LATENCY = 3) (note 2) ENTRY (VERSION) 128 256 SDRAM 12 or 13 10 1 72 0 LVTTL 7 (-13E) 7.5 (-133) 8 (-10E) MT9LSDT1672 80 08 04 0C 0A 01 48 00 01 70 75 80 MT9LSDT3272 80 08 04 0D 0A 01 48 00 01 70 75 80 5.4 (-13E/-133) 6 (-10E) 54 60 54 60 10 SDRAM ACCESS FROM CLOCK, tAC (CAS LATENCY = 3) (note 2) 11 12 13 14 15 MODULE CONFIGURATION TYPE ECC REFRESH RATE/TYPE 15.6s/SELF (128MB), 7.81s/SELF (256MB) SDRAM WIDTH (PRIMARY SDRAM) 8 ERROR-CHECKING SDRAM DATA WIDTH 8 MIN. CLOCK DELAY FROM BACK-TO-BACK 1 RANDOM COLUMN ADDRESSES, tCCD 02 80 08 08 01 02 82 08 08 01 16 17 18 19 20 21 BURST LENGTHS SUPPORTED NUMBER OF BANKS ON SDRAM DEVICE CAS LATENCIES SUPPORTED CS LATENCY WE LATENCY SDRAM MODULE ATTRIBUTES 22 23 SDRAM DEVICE ATTRIBUTES: GENERAL SDRAM CYCLE TIME, tCK (CAS LATENCY = 2) (note 2) 1, 2, 4, 8, PAGE 4 2, 3 0 0 -13E/-133 -10E 0E 7.5 (-13E) 10 (-133/-10E) 8F 04 06 01 01 1F 1F 0E 75 A0 8F 04 06 01 01 1F 1F 0E 75 A0 24 SDRAM ACCESS FROM CLK, tAC (CAS LATENCY = 2) (note 2) 5.4 (-13E) 6 (-10E) 54 60 54 60 25 SDRAM CYCLE TIME, tCK (CAS LATENCY = 1) - 00 00 26 SDRAM ACCESS FROM CLK, tAC (CAS LATENCY = 1) - 00 00 27 MINIMUM ROW PRECHARGE TIME, tRP 28 MINIMUM ROW ACTIVE TO ROW ACTIVE, tRRD 29 MINIMUM RAS# TO CAS# DELAY, tRCD 15 (-13E) 20 (-133/-10E) 14 (-13E) 14 (-13E) 15 (-133) 20 (-10E) 15 (-13E) 20 (-133/-10E) 0F 14 0E 0E 0F 14 0F 14 0F 14 0E 0E 0F 14 0F 14 NOTE: 1. "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW." 2. Device latencies used for SPD values 16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs SD9C16_32X72G_A.p65 - Rev. 4/02 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. 128MB / 256MB (x72) 168-PIN REGISTERED SDRAM DIMMs SERIAL PRESENCE-DETECT MATRIX (continued) BYTE 30 31 32 DESCRIPTION MINIMUM RAS# PULSE WIDTH, (note 3) 34 MODULE BANK DENSITY COMMAND AND ADDRESS SETUP TIME, tAS, tCMS COMMAND AND ADDRESS HOLD TIME, tAH, tCMH DATA SIGNAL INPUT SETUP TIME, tDS 35 DATA SIGNAL INPUT HOLD TIME, tDH 33 36-61 62 63 RESERVED SPD REVISION CHECKSUM FOR BYTES 0-62 64 65-71 72 MANUFACTURER'S JEDEC ID CODE MANUFACTURER'S JEDEC ID CODE (CONT.) MANUFACTURING LOCATION 73-90 91 MODULE PART NUMBER (ASCII) PCB IDENTIFICATION CODE 92 93 94 95-98 99-125 126 127 IDENTIFICATION CODE (CONT.) YEAR OF MANUFACTURE IN BCD WEEK OF MANUFACTURE IN BCD MODULE SERIAL NUMBER MANUFACTURER-SPECIFIC DATA (RSVD) SYSTEM FREQUENCY SDRAM COMPONENT AND CLOCK DETAIL ENTRY (VERSION) 45 (-13E) 44 (-133) 50 (-10E) 128MB or 256MB 1.5 (-13E/-133) 2 (-10E) 0.8 (-13E/133) 1 (-10E) 1.5 (-13E/-133) 2 (-10E) 0.8 (-13E/-133) 1 (-10E) REV. 1.2 -13E -133 -10E MICRON 1 2 3 4 5 6 7 8 9 0 100/133 MHz MT9LSDT1672 2D 2C 32 20 15 20 08 10 15 20 08 10 00 12 99 DF 27 2C FF 01 02 03 04 05 06 07 08 09 MT9LSDT3272 2D 2C 32 40 15 20 08 10 15 20 08 10 00 12 BC 02 4A 2C FF 01 02 03 04 05 06 07 08 09 xx xx 01 02 03 04 05 06 07 08 09 00 01 02 03 04 05 06 07 08 09 00 xx xx xx xx xx xx - 64 8F - 64 8F NOTE: 1. "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW." 2. x = Variable Data. 3. The value of tRAS used for the -13E module is calculated from tRC - tRP. Actual device spec. value is 37ns. 16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs SD9C16_32X72G_A.p65 - Rev. 4/02 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. 128MB / 256MB (x72) 168-PIN REGISTERED SDRAM DIMMs 168-PIN DIMM STANDARD PCB .157(3.99) MAX FRONT VIEW 5.256 (133.50) 5.244 (133.20) .079 (2.00) R (2X) 1.505 (38.23) 1.495 (37.97) .118 (3.00) (2X) .700 (17.78) .118 (3.00) .250 (6.35) .118 (3.00) .039 (1.00) R(2X) PIN 1 .050 (1.27) .040 (1.02) PIN 84 4.550 (115.57) BACK VIEW .128 (3.25) (2X) .118 (3.00) 1.661 (42.18) 2.625 (66.68) PIN 168 PIN 85 NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted. MIN 16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs SD9C16_32X72G_A.p65 - Rev. 4/02 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc. 128MB / 256MB (x72) 168-PIN REGISTERED SDRAM DIMMs 168-PIN DIMM LOW PROFILE PCB FRONT VIEW .157 (3.99) MAX 5.256 (133.50) 5.244 (133.20) .079 (2.00) R (2X) 1.131 (28.73) 1.119(28.42) .118 (3.00) (2X) .700 (17.78) .118 (3.00) .250 (6.35) .118 (3.00) .039 (1.00) R(2X) PIN 1 .040 (1.02) .050 (1.27) PIN 84 4.550 (115.57) Back View .128 (3.25) (2X) .118 (3.00) 1.661 (42.18) 2.625 (66.68) PIN 168 PIN 85 NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted. MIN 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micronsemi.com, Internet: http://www.micronsemi.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark and the Micron logo are trademarks of Micron Technology, Inc. 16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs SD9C16_32X72G_A.p65 - Rev. 4/02 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.