MT9LSDT1672G-10E - Micron - Datasheet.Directory

16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

128MB / 256MB (x72)

168-PIN REGISTERED SDRAM DIMMs

DEVICE TIMING

Module PC100 PC133

Markings CL - tRCD - tRP CL - tRCD - tRP

-13E 2 - 2 - 2 2 - 2 - 2

-133 2 - 2 - 2 3 - 3 - 3

-10E 2 - 2 - 2 NA

NOTE: Symbols in parentheses are not used on these modules but may be used

for other modules in this product family. They are for reference only.

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

1VSS 43 VSS 85 VSS 127 VSS

2 DQ0 44 DNU 86 DQ32 128 CKE0

3 DQ1 45 S2# 87 DQ33 129 RFU

4 DQ2 46 DQMB2 88 DQ34 130 DQMB6

5 DQ3 47 DQMB3 89 DQ35 131 DQMB7

6VDD 48 D N U 90 VDD 132 N C

7 DQ4 49 VDD 91 DQ36 133 VDD

8 DQ5 50 N C 92 DQ37 134 N C

9 DQ6 51 N C 93 DQ38 135 N C

10 DQ7 52 CB2 94 DQ39 136 CB6

11 DQ8 53 CB3 95 DQ40 137 CB7

12 VSS 54 VSS 96 VSS 138 VSS

13 DQ9 55 DQ16 97 DQ41 139 DQ48

14 DQ10 56 DQ17 98 DQ42 140 DQ49

15 DQ11 57 DQ18 99 DQ43 141 DQ50

16 DQ12 58 DQ19 100 DQ44 142 DQ51

17 DQ13 59 VDD 101 DQ45 143 VDD

18 VDD 60 DQ20 102 VDD 144 DQ52

19 DQ14 61 N C 103 DQ46 145 N C

20 DQ15 62 N C 104 DQ47 146 N C

21 CB0 63 RFU 105 CB4 147 REGE

22 CB1 64 V SS 106 CB5 148 VSS

23 VSS 65 DQ21 107 VSS 149 DQ53

24 N C 66 DQ22 108 N C 150 DQ54

25 N C 67 DQ23 109 N C 151 DQ55

26 VDD 68 VSS 110 VDD 152 VSS

27 WE# 69 DQ24 111 CAS# 153 DQ56

28 DQMB0 70 DQ25 112 DQMB4 154 DQ57

29 DQMB1 71 DQ26 113 DQMB5 155 DQ58

30 S0# 72 DQ27 114 RFU 156 DQ59

31 D N U 73 VDD 115 RAS# 157 VDD

32 VSS 74 DQ28 116 VSS 158 DQ60

33 A0 75 DQ29 117 A1 159 DQ61

34 A2 76 DQ30 118 A3 160 DQ62

35 A4 77 DQ31 119 A5 161 DQ63

36 A6 78 V SS 120 A7 162 VSS

37 A8 79 CK2 121 A9 163 CK3

38 A10 80 N C 122 BA0 164 N C

39 BA1 81 WP 123 A11 165 SA0

40 VDD 82 SDA 124 VDD 166 SA1

41 VDD 83 SCL 125 CK1 167 SA2

42 CK0 84 VDD 126 RFU/A12* 168 VDD

PIN ASSIGNMENT (FRONT VIEW)

SYNCHRONOUS

DRAM MODULE

MT9LSDT1672 - 128MB

MT9LSDT3272 - 256MB

For the latest data sheet, please refer to the Micron Web

site: www.micron.com/datasheets

168-PIN DIMMS

FEATURES

• JEDEC-standard 168-pin, dual in-line memory

module (DIMM)

• PC133- and PC100-compliant

• Registered inputs with one-clock delay

• Phase-lock loop (PLL) clock driver to reduce loading

• ECC-optimized pinout

• 128MB (16 Meg x 72), 256MB (32 Meg x 72)

• Single +3.3V ±0.3V power supply

• Fully synchronous; all signals registered on

positive edge of PLL clock

• Internal pipelined operation; column address can

be changed every clock cycle

• Internal SDRAM banks for hiding row access/

precharge

• Programmable burst lengths: 1, 2, 4, 8, or full page

• Auto Precharge and Auto Refresh Modes

• Self Refresh Mode

• 64ms refresh (128MB - 4,096 cycles; 256MB - 8,192

cycles)

• LVTTL-compatible inputs and outputs

• Serial Presence-Detect (SPD)

OPTIONS MARKING

• Package

168-pin DIMM (gold) G

• Frequency/CAS Latency*

133 MHz/CL = 3 -13E

133 MHz/CL = 4 -133

100 MHz/CL = 3 -10E

• Standard or Low Profile PCB Contact Factory

*Module latency; extra clock cycle due to input register when in

registered mode.

Standard

Low Profile

*RFU on 128MB, A12 on 256MB

ADDRESS TABLE

128MB 256MB

Module Module

Refresh Count 4K 8K

Device Banks 4 (BA0, BA1) 4 (BA0, BA1)

Row Addressing 4K (A0–A11) 8K (A0–A12)

Column Addressing 1K (A0–A9) 1K (A0–A9)

Module Banks 1 (S0,S2) 1 (S0,S2)

16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

128MB / 256MB (x72)

168-PIN REGISTERED SDRAM DIMMs

GENERAL DESCRIPTION

The MT9LSDT1672 and MT9LSDT3272 are high-

speed CMOS, dynamic random-access, 128MB and

256MB memory modules organized in x72 configura-

tions. These modules use internally configured quad-

bank SDRAMs with a synchronous interface (all signals

are registered on the positive edge of clock signals CK0).

Read and write accesses to the SDRAM modules are

burst oriented; accesses start at a selected location and

continue for a programmed number of locations in a

programmed sequence. Accesses begin with the registra-

tion of an ACTIVE command, which is then followed

by a READ or WRITE command. The address bits regis-

tered coincident with the ACTIVE command are used to

select the device bank and row to be accessed (BA0, BA1

select the device bank; A0-A11 for 128MB/A0-A12 for

256MB, select the device row). The address bits registered

coincident with the READ or WRITE command are used

to select the starting column location for the burst access.

These modules provide for programmable READ or

WRITE burst lengths of 1, 2, 4, or 8 locations, or full

page, with a burst terminate option. An auto precharge

function may be enabled to provide a self-timed row

precharge that is initiated at the end of the burst se-

quence.

These modules use an internal pipelined architecture

to achieve high-speed operation. This architecture is

compatible with the 2n rule of prefetch architectures, but

it also allows the column address to be changed on every

PART NUMBERS

PART NUM BER CONFIGURATION SYSTEM BUS SPEED

MT9LSDT1672G-13E__ 16 Meg x 72 133 MHz

MT9LSDT1672G-133__ 16 Meg x 72 133 MHz

MT9LSDT1672G-10E__ 16 Meg x 72 100 MHz

MT9LSDT3272G-13E__ 32 Meg x 72 133 MHz

MT9LSDT3272G-133__ 32 Meg x 72 133 MHz

MT9LSDT3272G-10E__ 32 Meg x 72 100 MHz

NOTE: The designators for component and PCB revision are

the last two characters of each part number. Consult

factory for current revision codes. Example:

MT9LSDT1672G-133B1

clock cycle to achieve a high-speed, fully random access.

Precharging one bank while accessing one of the other

three banks will hide the PRECHARGE cycles and pro-

vide seamless, high-speed, random-access operation.

These modules are designed to operate in 3.3V, low-

power memory systems. An auto refresh mode is pro-

vided, along with a power-saving, power-down mode.

All inputs and outputs are LVTTL-compatible.

SDRAM modules offer substantial advances in DRAM

operating performance, including the ability to

synchronously burst data at a high data rate with

automatic column-address generation, the ability to

interleave between internal banks in order to hide

precharge time, and the capability to randomly change

column addresses on each clock cycle during a burst

access. For more information regarding SDRAM opera-

tion, refer to the 128Mb and 256Mb SDRAM data sheets.

PLL AND REGISTER OPERATION

These modules can be operated in either registered

mode (REGE pin HIGH), where the control/address

input signals are latched in the register on one rising

clock edge and sent to the SDRAM devices on the

following rising clock edge (data access is delayed by one

clock), or in buffered mode (REGE pin LOW) where the

input signals pass through the register/buffer to the

SDRAM devices on the same clock. A phase-lock loop

(PLL) on the modules is used to redrive the clock signals

to the SDRAM devices to minimize system clock loading

(CK0 is connected to the PLL, and CK1, CK2, and CK3 are

terminated).

SERIAL PRESENCE-DETECT OPERATION

These modules incorporate serial presence-detect

(SPD). The SPD function is implemented using a 2,048-

bit EEPROM. This nonvolatile storage device contains

256 bytes. The first 128 bytes can be programmed by

Micron to identify the module type and various SDRAM

organizations and timing parameters. The remaining

128 bytes of storage are available for use by the customer.

System READ/WRITE operations between the master

(system logic) and the slave EEPROM device (DIMM)

occur via a standard IIC bus using the DIMM’s SCL

(clock) and SDA (data) signals, together with SA(2:0),

which provide eight unique DIMM/EEPROM addresses.

16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

128MB / 256MB (x72)

168-PIN REGISTERED SDRAM DIMMs

FUNCTIONAL BLOCK DIAGRAM

STANDARD PCB LAYOUT

SA0

SPD

SDA

SA1

SA2

RAS#

CAS#

CKE0

WE#

A0-A12*

RRAS#: SDRAMs U1-4, U10-14

RCAS#: SDRAMs U1-4, U10-14

RCKE0: SDRAMs U1-4, U10-14

RWE#: SDRAMs U1-4, U10-14

RA0-RA11: SDRAMs U1-4, U10-14

RBA0: SDRAMs U1-4, U10-14

RBA1: SDRAMs U1-4, U10-14

RS0#, RS2#

RDQMB0-RDQMB7

BA0

BA1

S0#, S2#

DQMB0-DQMB7

PLL CLK

SDRAMs U1-4, U10-14

DQM CS#

U10

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

RDQMB7

DQM CS#

U11

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

RDQMB6

DQM CS#

U13

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

RDQMB5

DQM CS#

U14

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

RDQMB4

DQM CS#

U5, U7

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

RDQMB3

DQM CS#

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

RDQMB2

DQM CS#

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

RDQMB1

DQM CS#

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

RDQMB0

RS2#

RS0#

DQM CS#

U12

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

REGE

10K

PLL

SDRAM x 3

CK0

12pF

CK1-CK3

SCL

47K

U1-4, U10-14 = MT48LC16M8A2TG SDRAMs for 128MB

U1-4, U10-14 = MT48LC32M8A2TG SDRAMs for 256MB

NOTE: 1. All resistor values are 10 ohms unless otherwise specified.

*A12 for 256MB module, A11 for 128MB Module

16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

128MB / 256MB (x72)

168-PIN REGISTERED SDRAM DIMMs

FUNCTIONAL BLOCK DIAGRAM

LOW PROFILE PCB LAYOUT

SA0

SPD

SDA

SA1

SA2

RAS#

CAS#

CKE0

WE#

A0-A12*

RRAS#: SDRAMs U1-3, 5-6, 9-10, 13-14

RCAS#: SDRAMs U1-3, 5-6, 9-10, 13-14

RCKE0: SDRAMs U1-3, 5-6, 9-10, 13-14

RWE#: SDRAMs U1-3, 5-6, 9-10, 13-14

RA0-RA11: SDRAMs U1-3, 5-6, 9-10, 13-14

RBA0: SDRAMs U1-3, 5-6, 9-10, 13-14

RBA1: SDRAMs U1-3, 5-6, 9-10, 13-14

RS0#, RS2#

RDQMB0-RDQMB7

BA0

BA1

S0#, S2#

DQMB0-DQMB7

PLL CLK

SDRAMs U1-3, 5-6, 9-10, 13-14

DQM CS#

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

RDQMB7

DQM CS#

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

RDQMB6

DQM CS#

U13

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

RDQMB5

DQM CS#

U14

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

RDQMB4

DQM CS#

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

RDQMB3

DQM CS#

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

RDQMB2

DQM CS#

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

RDQMB1

DQM CS#

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

RDQMB0

RS2#

RS0#

DQM CS#

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

REGE

10K

PLL

SDRAM x 3

CK0

12pF

CK1-CK3

SCL

47K

U1-3, 5-6, 9-10, 13-14 = MT48LC16M8A2TG SDRAMs for 128MB

U1-3, 5-6, 9-10, 13-14 = MT48LC32M8A2TG SDRAMs for 256MB

NOTE: 1. All resistor values are 10 ohms unless otherwise specified.

U5 U10

U6 U9

U12, U11

*A12 for 256MB module, A11 for 128MB module.

16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

128MB / 256MB (x72)

168-PIN REGISTERED SDRAM DIMMs

PIN DESCRIPTIONS

PIN NUMBERS SYMBOL TYPE DESCRIPTION

27, 111, 115 WE#, CAS#, Input Command Inputs: WE#, RAS#, and CAS# (along with S0#,

RAS# S2#) define the command being entered.

42, 79, 125, 163 CK0-CK3 Input Clock: CK0 is distributed through an on-board PLL to all

devices. CK1-CK3 are terminated.

128 CKE0 Input Clock Enable: CKE0 activates (HIGH) and deactivates (LOW)

the CK0 signal. Deactivating the clock provides POWER-

DOWN and SELF REFRESH operation (all device banks idle)

or CLOCK SUSPEND operation (burst access in progress).

CKE0 is synchronous except after the device enters power-

down and self refresh modes, where CKE0 becomes asyn-

chronous until after exiting the same mode. The input

buffers, including CK0, are disabled during power-down and

self refresh modes, providing low standby power.

30, 45 S0#, S2# Input Chip Select: S0#, S2# enable (registered LOW) and disable

(registered HIGH) the command decoder. All commands are

masked when S0#, S2# are registered HIGH. S0#, S2# are

considered part of the command code.

28-29, 46-47, DQMB0- Input Input/Output Mask: DQMB is an input mask signal for write

112-113, 130-131 DQMB7 accesses and an output enable signal for read accesses. Input

data is masked when DQMB is sampled HIGH during a WRITE

cycle. The output buffers are placed in a High-Z state (two-

clock latency) when DQMB is sampled HIGH during a READ

cycle.

39, 122 BA0, BA1 Input Bank Address: BA0 and BA1 define to which device bank the

ACTIVE, READ, WRITE or PRECHARGE command is being

applied.

33, 34, 35, 36, 37, 38, 117, A0-A11, Input Address Inputs: A0-A11 are sampled during the ACTIVE

118, 119, 120, 121, 123 128MB; command (row-address A0-A11) and READ/WRITE command

A0-A12, (column-address A0-A9, with A10 defining auto precharge)

256MB to select one location out of the memory array in the

respective devicebank. A10 is sampled during a PRECHARGE

command to determine if both device banks are to be

precharged (A10 HIGH). The address inputs also provide the

op-code during a LOAD MODE REGISTER command.

126 RFU/A12 Input Reserved for future use on 128MB module; Address input

A12 on 256MB module.

81 WP Input Write Protect: Serial presence-detect hardware write protect.

83 SCL Input Serial Clock for Presence-Detect: SCL is used to synchronize

the presence-detect data transfer to and from the module.

165-167 SA0-SA2 Input Presence-Detect Address Inputs: These pins are used to

configure the presence-detect device.

147 REGE Input Register Enable.

16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

128MB / 256MB (x72)

168-PIN REGISTERED SDRAM DIMMs

PIN DESCRIPTIONS (continued)

PIN NUMBERS SYMBOL TYPE DESCRIPTION

2-5, 7-11, 13-17, 19-20, DQ0-DQ63 Input/ Data I/Os: Data bus.

55-58, 60, 65-67, 69-72, Output

74-77, 86-89, 91-95,

97-101, 103-104,

139-142, 144, 149-151,

153-156, 158-161

21-22, 52-53, 105-106, CB0-CB7 Input/ Check Bits.

136-137 Output

82 SDA Input/ Serial Presence-Detect Data: SDA is a bidirectional pin

Output used to transfer addresses and data into and data out of the

presence-detect portion of the module.

6, 18, 26, 40-41, 49, 59, VDD Supply Power Supply: +3.3V ±0.3V.

73, 84, 90, 102, 110, 124,

133, 143, 157, 168

1, 12, 23, 32, 43, 54, 64, VSS Supply Ground.

68, 78, 85, 96, 107, 116,

127, 138, 148, 152, 162

24, 25, 31, 44, 48, 50, NC –Not Connected: These pins are not connected on this

51, 61,62, 80, 108, 109, module but are assigned pins on the compatible DRAM

132, 134, 135,145, 146 version.

63 RFU –Reserved for Future Use: CKE1

114 RFU –Reserved for Future Use: S1#

129 RFU –Reserved for Future Use: S3#

16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

128MB / 256MB (x72)

168-PIN REGISTERED SDRAM DIMMs

SDRAM FUNCTIONAL DESCRIPTION

In general, the 128Mb and 256Mb SDRAM memory

devices used for these modules are quad-bank DRAMs,

that operate at 3.3V and include a synchronous inter-

face (all signals are registered on the positive edge of the

clock signal, CLK). The four banks of a x8, 128Mb device

are each configured as 4,096 bit-rows, by 1,024 bit-

columns, by 8 input/output bits. The four banks of a x8,

256Mb device are configured as 8,192 bit-rows by 1,024

bit columns, by 8 input/output bits.

Read and write accesses to the SDRAM are burst

oriented; accesses start at a selected location and con-

tinue for a programmed number of locations in a

programmed sequence. Accesses begin with the registra-

tion of an ACTIVE command, which is then followed

by a READ or WRITE command. The address bits

registered coincident with the ACTIVE command are

used to select the device bank and row to be accessed

BA0 and BA1 select the device bank, A0-A11 (for

128Mb), or A0-A12 (for 256Mb), select the device row.

The address bits A0-A9, registered coincident with the

READ or WRITE command are used to select the

starting device column location for the burst access.

Prior to normal operation, the SDRAM must be

initialized. The following sections provide detailed

information covering device initialization, register defi-

nition, command descriptions and device operation.

Initialization

SDRAMs must be powered up and initialized in a

predefined manner. Operational procedures other than

those specified may result in undefined operation.

Once power is applied to VDD and VDDQ (simulta-

neously) and the clock is stable (stable clock is defined

as a signal cycling within timing constraints specified

for the clock pin), the SDRAM requires a 100µs delay

prior to issuing any command other than a COM-

MAND INHIBIT or NOP. Starting at some point during

this 100µs period and continuing at least through the

end of this period, COMMAND INHIBIT or NOP

commands should be applied.

Once the 100µs delay has been satisfied with at least

one COMMAND INHIBIT or NOP command having

been applied, a PRECHARGE command should be

applied. All device banks must then be precharged,

thereby placing the device in the all banks idle state.

Once in the idle state, two AUTO REFRESH cycles

must be performed. After the AUTO REFRESH cycles are

complete, the SDRAM is ready for mode register pro-

gramming. Because the mode register will power up in

an unknown state, it should be loaded prior to apply-

ing any operational command.

Mode Register Definition

MODE REGISTER

The mode register is used to define the specific mode

of operation of the SDRAM. This definition includes

the selection of a burst length, a burst type, a CAS

latency, an operating mode and a write burst mode, as

shown in the Mode Register Definition Diagram (p. 9).

The mode register is programmed via the LOAD MODE

mation until it is programmed again or the device loses

power.

Mode register bits M0-M2 specify the burst length,

M3 specifies the type of burst (sequential or inter-

leaved), M4-M6 specify the CAS latency, M7 and M8

specify the operating mode, M9 specifies the write burst

mode, and M10 and M11 are reserved for future use.

The mode register must be loaded when all device

banks are idle, and the controller must wait the specified

time before initiating the subsequent operation. Violat-

ing either of these requirements will result in unspecified

operation.

Burst Length

Read and write accesses to the SDRAM are burst

oriented, with the burst length being programmable, as

shown in the Mode Register Definition Diagram (p. 9).

The burst length determines the maximum number of

column locations that can be accessed for a given READ

or WRITE command. Burst lengths of 1, 2, 4, or 8

locations are available for both the sequential and the

interleaved burst types, and a full-page burst is available

for the sequential type. The full-page burst is used in

conjunction with the BURST TERMINATE command

to generate arbitrary burst lengths.

Reserved states should not be used, as unknown

operation or incompatibility with future versions may

result.

When a READ or WRITE command is issued, a block

of columns equal to the burst length is effectively

selected. All accesses for that burst take place within this

block, meaning that the burst will wrap within the block

if a boundary is reached, as shown in the Burst Defini-

tion Table (p. 9). The block is uniquely selected by A1-

A9 when the burst length is set to two; A2-A9 when the

burst length is set to four; and by A3-A9 when the burst

length is set to eight. The remaining (least significant)

address bit(s) is (are) used to select the starting location

within the block. Full-page bursts wrap within the page

if the boundary is reached.

16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

128MB / 256MB (x72)

168-PIN REGISTERED SDRAM DIMMs

Operating Mode

The normal operating mode is selected by setting M7

and M8 to zero; the other combinations of values for

M7 and M8 are reserved for future use and/or test

modes. The programmed burst length applies to both

READ and WRITE bursts.

Test modes and reserved states should not be used

because unknown operation or incompatibility with

future versions may result.

Write Burst Mode

When M9 = 0, the burst length programmed via

M0-M2 applies to both READ and WRITE bursts; when

M9 = 1, the programmed burst length applies to

READ bursts, but write accesses are single-location

(nonburst) accesses.

CAS Latency

The CAS latency is the delay, in clock cycles, between

the registration of a READ command and the availabil-

ity of the first piece of output data. The latency can be

set to two or three clocks.

If a READ command is registered at clock edge n, and

the latency is m clocks, the data will be available by clock

edge n + m. The DQs will start driving as a result of the

clock edge one cycle earlier (n + m - 1), and provided that

the relevant access times are met, the data will be valid

by clock edge n + m. For example, assuming that the

clock cycle time is such that all relevant access times are

met, if a READ command is registered at T0 and the

latency is programmed to two clocks, the DQs will start

driving after T1 and the data will be valid by T2, as

shown in the CAS Latency Diagram. The CAS Latency

Table indicate the operating frequencies at which each

CAS latency setting can be used.

Reserved states should not be used as unknown

operation or incompatibility with future versions

may result.

CAS Latency Diagram

CLK

T2T1 T3T0

CAS Latency = 3

OUT

tOH

COMMAND

NOPREAD

tAC

NOP

DON’T CARE

UNDEFINED

CLK

T2T1 T3T0

CAS Latency = 2

OUT

tOH

COMMAND

NOPREAD

tAC

NOP

CAS Latency Table

ALLOWABLE OPERATING

FREQUENCY (MHz)

CAS CAS

SPEED LATENCY = 2* LATENCY = 3*

-13E ≤ 133 ≤ 143

-133 ≤ 100 ≤ 133

-10E ≤ 100 ≤ 125

* When in registered mode, input register will add one extra

clock.

16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

128MB / 256MB (x72)

168-PIN REGISTERED SDRAM DIMMs

NOTE: 1. For full-page accesses: y = 1,024

2. For a burst length of two, A1-A9 select the block

of two burst; A0 selects the starting column

within the block.

3. For a burst length of four, A2-A9 select the block

of four burst; A0-A1 select the starting column

within the block.

4. For a burst length of eight, A3-A9 select the block

of eight burst; A0-A2 select the starting column

within the block.

5. For a full-page burst, the full row is selected and

A0-A9 select the starting column.

6. Whenever a boundary of the block is reached

within a given sequence above, the following

access wraps within the block.

7. For a burst length of one, A0-A9 select the unique

column to be accessed, and Mode Register bit M3

is ignored.

Burst Definition Table

Burst Starting Column Order of Accesses Within a Burst

Length Address Type = Sequential Type = Interleaved

2 0 0-1 0-1

1 1-0 1-0

A1 A0

0 0 0-1-2-3 0-1-2-3

4 0 1 1-2-3-0 1-0-3-2

1 0 2-3-0-1 2-3-0-1

1 1 3-0-1-2 3-2-1-0

A2 A1 A0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7

0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6

0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4

1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3

1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2

1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1

1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Full n = A0-9 Cn, Cn+1, Cn+2

Page (location 0-y) Cn+3, Cn+4... Not supported

(y) …Cn-1,

Cn…

Mode Register Definition Diagram

Burst Type

Accesses within a given burst may be programmed to

be either sequential or interleaved; this is referred to as

the burst type and is selected via bit M3.

The ordering of accesses within a burst is determined

by the burst length, the burst type and the starting

column address, as shown in the Burst Definition Table.

M3 = 0

Reserved

Full Page

M3 = 1

Reserved

Operating Mode

Standard Operation

All other states reserved

Defined

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

Burst Length

Burst LengthCAS Latency BT

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Mode Register (Mx)

Address Bus

976543

8210

M6-M0

M8 M7

Op Mode

A10

A11

Reserved*

Write Burst Mode

Programmed Burst Length

Single Location Access

*Should program

M12, M11, M10 = 0, 0, 0

to ensure compatibility

with future devices.

A12

Reserved*

16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

128MB / 256MB (x72)

168-PIN REGISTERED SDRAM DIMMs

NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.

2. A0-A11, 128MB; and A0-A12, 256MB define the op-code written to the Mode Register.

3. A0-A11, 128MB; and A0-A12, 256MB provide row address, and BA0, BA1 determine which device bank is made active.

4. A0-A8/A9 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW

disables the auto precharge feature; BA0, BA1 determine which device bank is being read from or written to.

5. A10 LOW: BA0, BA1 determine which device bank is being precharged. A10 HIGH: all device banks are precharged and

BA0, BA1 are “Don’t Care.”

6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.

7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.

8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).

TRUTH TABLE – SDRAM COMMANDS AND DQMB OPERATION

(Note: 1; notes appear below table)

NAME (FUNCTION) CS# RAS# CAS# WE# DQMB ADDR DQs NOTES

COMMAND INHIBIT (NOP) H X X X X X X

NO OPERATION (NOP) L H H H X X X

ACTIVE (Select bank and activate row) L L H H X Bank/Row X 3

READ (Select bank and column, and start READ burst) L H L H L/H

Bank/Col X 4

WRITE (Select bank and column, and start WRITE burst) L H L L L/H

Bank/Col Valid 4

BURST TERMINATE L H H L X X Active

PRECHARGE (Deactivate row in bank or banks) L L H L X Code X 5

AUTO REFRESH or L L L H X X X 6, 7

SELF REFRESH (Enter self refresh mode)

LOAD MODE REGISTER L L L L X Op-Code X 2

Write Enable/Output Enable –––– L–Active 8

Write Inhibit/Output High-Z –––– H–High-Z 8

Commands

The Truth Table provides a quick reference of avail-

able commands. This is followed by a written descrip-

tion of each command. For a more detailed description

of commands and operations refer to the 128Mb or

256Mb SDRAM datasheets.

16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

128MB / 256MB (x72)

168-PIN REGISTERED SDRAM DIMMs

ABSOLUTE MAXIMUM RATINGS*

Voltage on VDD, VDDQ Supply

Relative to VSS ................................. -1V to +4.6V

Voltage on Inputs, NC or I/O Pins

Relative to VSS ................................. -1V to +4.6V

Operating Temperature, T

A............................

0°C to +70°C

Storage Temperature (plastic) ........... -55°C to +150°C

Power Dissipation ................................................... 9W

*Stresses greater than those listed under “Absolute

Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only, and functional

operation of the device at these or any other conditions

above those indicated in the operational sections of this

specification is not implied. Exposure to absolute maxi-

mum rating conditions for extended periods may affect

reliability.

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(Notes: 1, 5, 6; notes appear following parameter tables); (VDD, VDDQ = +3.3V ±0.3V)

PARAMETER/CONDITION SYMBOL MIN M A X UNITS NOTES

SUPPLY VOLTAGE VDD, VDDQ 3 3.6 V

INPUT HIGH VOLTAGE: Logic 1; All inputs VIH 2VDD + 0.3 V 22

INPUT LOW VOLTAGE: Logic 0; All inputs VIL -0.3 0.8 V 22

INPUT LEAKAGE CURRENT:

Any input 0V ≤ VIN ≤ VDD II-5 5 µA

(All other pins not under test = 0V)

OUTPUT LEAKAGE CURRENT: DQs are disabled; IOZ -5 5 µA

0V ≤ VOUT ≤ VDDQ

OUTPUT LEVELS: VOH 2.4 –V

Output High Voltage (IOUT = -4mA)

Output Low Voltage (IOUT = 4mA) VOL –0.4 V

16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

128MB / 256MB (x72)

168-PIN REGISTERED SDRAM DIMMs

MAX

IDD SPECIFICATIONS AND CONDITIONS*: 128MB MODULE

(Notes: 1, 5, 6, 11, 13; notes appear following the parameter tables);

(VDD, VDDQ = +3.3V ±0.3V)

PARAMETER/CONDITION SYMBOL -13E -133 -10E UNITS NOTES

OPERATING CURRENT: Active Mode; IDD11,215 1,125 1,125 mA 3, 18,

Burst = 2; READ or WRITE; tRC = tRC (MIN) 19, 30

STANDBY CURRENT: Power-Down Mode; IDD218 18 18 mA 30

All device banks idle; CKE = LOW

STANDBY CURRENT: Active Mode; IDD3 360 360 360 mA 3, 12,

CKE = HIGH; CS# = HIGH; All device banks active after tRCD met; 19, 30

No accesses in progress

OPERATING CURRENT: Burst Mode; Continuous burst; IDD41,215 1,215 1,215 mA 3, 18,

READ or WRITE; All device banks active 19, 30

AUTO REFRESH CURRENT tRFC = tRFC (MIN) IDD52,565 2,430 2,430 mA 3, 12,

CKE = HIGH; CS# = HIGH tRFC = 15.625µs IDD631.5 31.5 31.5 mA 18, 19,

30, 31

SELF REFRESH CURRENT: CKE ≤ 0.2V Standard IDD722.5 22.5 22.5 mA 4

*DRAM Components only. EEPROM, registers, and PLL not included in these calculations.

16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

128MB / 256MB (x72)

168-PIN REGISTERED SDRAM DIMMs

IDD SPECIFICATIONS AND CONDITIONS*: 256MB MODULE

(Notes: 1, 6, 11, 13; notes appear following parameter tables)

(VDD, VDDQ = +3.3V ±0.3V)

PARAMETER/CONDITION SYMBOL -13E -133 -10E UNITS NOTES

OPERATING CURRENT: Active Mode; IDD11530 1440 1350 mA 3, 18,

Burst = 2; READ or WRITE; tRC = tRC (MIN) 19, 30

STANDBY CURRENT: Power-Down Mode; IDD218 18 18 mA 30

All device banks idle; CKE = LOW

STANDBY CURRENT: Active Mode; IDD3540 540 495 mA 3, 12,

CKE = HIGH; CS# = HIGH; All device banks active after tRCD met; 19, 30

No accesses in progress

OPERATING CURRENT: Burst Mode; Continuous burst; IDD41440 1440 1350 mA 3, 18,

READ or WRITE; All device banks active 19, 30

AUTO REFRESH CURRENT tRFC = tRFC (MIN) IDD52700 2700 2700 mA 3, 12,

CS# = HIGH; CKE = HIGH tRFC = 7.81 µs IDD636 36 36 mA 18, 19,

30, 31

SELF REFRESH CURRENT: CKE ≤ 0.2V Standard IDD736 36 36 mA 4

MAX

*DRAM components only. EEPROM, registers, and PLL not included in thes calculations.

16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

128MB / 256MB (x72)

168-PIN REGISTERED SDRAM DIMMs

CAPACITANCE

(Note: 2; notes appear following parameter tables)

PARAMETER SYMBOL MIN MAX MIN MAX UNITS

Input Capacitance: A0-A12, BA0, BA1, RAS#, CI14646pF

CAS#, WE#

Input Capacitance: CK0 CI2-4-4pF

Input Capacitance: S0#-S2# CI34646pF

Input Capacitance: CKE0 CI44646pF

Input Capacitance: DQMB0-DQMB7 CI54646pF

Input/Output Capacitance: SCL, SA0-SA2 CI6–6–6pF

Input/Output Capacitance: DQ0-DQ63, SDA CIO 4 64 6 pF

128MB 256MB

16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

128MB / 256MB (x72)

168-PIN REGISTERED SDRAM DIMMs

ELECTRICAL CHARACTERISTICS AND RECOMMENDED SDRAM DEVICE

AC TIMING PARAMETERS*

(Notes: 5, 6, 8, 9, 11; notes appear following parameter tables)

AC CHARACTERISTICS -13E -133 -10E

PARAMETER

SYMBOL

MIN MAX MIN MAX MIN MAX UNITS NOTES

Access time from CLK (pos. edge) CL = 3 tAC (3) 5.4 5.4 6 ns 27

CL = 2 tAC (2) 5.4 6 6 ns

Address hold time tAH 0.8 0.8 1 ns

Address setup time tAS 1.5 1.5 2 ns

CLK high-level width tCH 2.5 2.5 3 ns

CLK low-level width tCL 2.5 2.5 3 ns

Clock cycle time CL = 3 tCK (3) 7 7.5 8 ns 23

CL = 2 tCK (2) 7.5 10 10 ns 23

CKE hold time tCKH 0.8 0.8 1 ns

CKE setup time tCKS 1.5 1.5 2 ns

CS#, RAS#, CAS#, WE#, DQM hold time tCMH 0.8 0.8 1 ns

CS#, RAS#, CAS#, WE#, DQM setup time tCMS 1.5 1.5 2 ns

Data-in hold time tDH 0.8 0.8 1 ns

Data-in setup time tDS 1.5 1.5 2 ns

Data-out high-impedance time CL = 3 tHZ (3) 5.4 5.4 6 ns 10

CL = 2 tHZ (2) 5.4 6 7 ns 10

Data-out low-impedance time tLZ111ns

Data-out hold time (load) tOH333ns

Data-out hold time (no load) tOHN1.8 1.8 1.8 ns 28

ACTIVE to PRECHARGE command tRAS 37 120,000 44 120,000 50 120,000 ns 29

ACTIVE to ACTIVE command period tRC 60 66 70 ns

ACTIVE to READ or WRITE delay tRCD 15 20 20 ns

Refresh period (4,096 rows) tREF 64 64 64 ms

AUTO REFRESH period tRFC 66 66 70 ns

PRECHARGE command period tRP 15 20 20 ns

ACTIVE bank a to ACTIVE bank b command tRRD 14 15 20 ns

Transition time tT 0.3 1.2 0.3 1.2 0.3 1.2 ns 7

WRITE recovery time tWR 1 CLK + 1 CLK + 1 CLK + –24

7ns 7.5ns 7ns

14 15 15 ns 25

Exit SELF REFRESH to ACTIVE command tXSR 67 75 80 ns 20

* Module AC timing parameters comply with PC133 SDRAM Registered DIMM Design Specs, based on component parameters.

16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

128MB / 256MB (x72)

168-PIN REGISTERED SDRAM DIMMs

AC FUNCTIONAL CHARACTERISTICS*

(Notes: 5, 6, 7, 8, 9, 11; notes appear following parameter tables)

PARAMETER

SYMBOL -13E -133 -10E UNITS NOTES

READ/WRITE command to READ/WRITE command tCCD 1 1 1 tCK 17

CKE to clock disable or power-down entry mode tCKED 1 1 1 tCK 14, 32

CKE to clock enable or power-down exit setup mode tPED 1 1 1 tCK 14, 32

DQM to input data delay tDQD 0 0 0 tCK 17, 32

DQM to data mask during WRITEs tDQM 0 0 0 tCK 17, 32

DQM to data high-impedance during READs tDQZ 2 2 2 tCK 17, 32

WRITE command to input data delay tDWD 0 0 0 tCK 17, 32

Data-in to ACTIVE command tDAL 4 5 4 tCK 15, 21,

Data-in to PRECHARGE command tDPL 2 2 2 tCK 16, 21,

Last data-in to burst STOP command tBDL 1 1 1 tCK 17, 32

Last data-in to new READ/WRITE command tCDL 1 1 1 tCK 17, 32

Last data-in to PRECHARGE command tRDL 2 2 2 tCK 16, 21,

LOAD MODE REGISTER command to ACTIVE or REFRESH command tMRD 2 2 2 tCK 26

Data-out to high-impedance from PRECHARGE command CL = 3 tROH(3) 3 3 3 tCK 17, 32

CL = 2 tROH(2) 2 2 2 tCK 17, 32

* Module AC timing parameters comply with PC133 SDRAM Registered DIMM Design Specs, based on component parameters.

16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

128MB / 256MB (x72)

168-PIN REGISTERED SDRAM DIMMs

14. Timing actually specified by tCKS; clock(s) specified

as a reference only at minimum cycle rate.

15. Timing actually specified by tWR plus tRP; clock(s)

specified as a reference only at minimum cycle rate.

16. Timing actually specified by tWR.

17. Required clocks are specified by JEDEC functional-

ity and are not dependent on any timing param-

eter.

18. The IDD current will increase or decrease propor-

tionally according to the amount of frequency

alteration for the test condition.

19. Address transitions average one transition every

two clocks.

20. CLK must be toggled a minimum of two times

during this period.

21. Based on tCK = 10ns for -10E, and tCK = 7.5ns for

-133 and -13E.

22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse

width ≤ 3ns, and the pulse width cannot be greater

than one third of the cycle rate. VIL undershoot: VIL

(MIN) = -2V for a pulse width ≤ 3ns.

23. The clock frequency must remain constant (stable

clock is defined as a signal cycling within timing

constraints specified for the clock pin) during access

or precharge states (READ, WRITE, including tWR,

and PRECHARGE commands). CKE may be used to

reduce the data rate.

24. Auto precharge mode only. The precharge timing

budget (tRP) begins 7ns for -13E; 7.5ns for -133 and

7ns for -10E after the first clock delay, after the last

WRITE is executed. May not exceed limit set for

precharge mode.

25. Precharge mode only.

26. JEDEC and PC100 specify three clocks.

27. tAC for -133/-13E at CL = 3 with no load is 4.6ns and

is guaranteed by design.

28. Parameter guaranteed by design.

29. The value of tRAS. use in -13E speed grade module

SPDs is calculated from tRC - tRP = 45ns.

30. For -10E, CL= 2 and tCK = 10ns; for -133, CL = 3 and

tCK = 7.5ns; for -13E, CL = 2 and tCK = 7.5ns.

31. CKE is HIGH during refresh command period

tRFC (MIN) else CKE is LOW. The IDD6 limit is

actually a nominal value and does not result in a fail

value.

32. This timing function will incur one extra clock cycle

due to the input register when in registered mode.

NOTES

1. All voltages referenced to VSS.

2. This parameter is sampled. VDD, VDDQ = +3.3V;

f = 1 MHz, TA = 25°C; pin under test biased at 1.4V.

3. IDD is dependent on output loading and cycle rates.

Specified values are obtained with minimum cycle

time and the outputs open.

4. Enables on-chip refresh and address counters.

5. The minimum specifications are used only to

indicate cycle time at which proper operation over

the full temperature range is ensured; (0°C ≤ TA ≤

+70°C).

6. An initial pause of 100µs is required after power-up,

followed by two AUTO REFRESH commands, be-

fore proper device operation is ensured. (VDD and

VDDQ must be powered up simultaneously. VSS and

VSSQ must be at same potential.) The two AUTO

REFRESH command wake-ups should be repeated

any time the tREF refresh requirement is exceeded.

7. AC characteristics assume tT = 1ns.

8. In addition to meeting the transition rate specifica-

tion, the clock and CKE must transit between VIH

and VIL (or between VIL and VIH) in a monotonic

manner.

9. Outputs measured at 1.5V with equivalent load:

50pF

10. tHZ defines the time at which the output achieves

the open circuit condition; it is not a reference to

VOH or VOL. The last valid data element will meet

tOH before going High-Z.

11. AC timing and IDD tests have VIL = 0V and VIH = 3V,

with timing referenced to 1.5V crossover point. If

the input transition time is longer than 1 ns, then

the timing is referenced at VIL (MAX) and VIH (MIN)

and no longer at the 1.5V crossover point.

12. Other input signals are allowed to transition no

more than once every two clocks and are otherwise

at valid VIH or VIL levels.

13. IDD specifications are tested after the device is prop-

erly initialized.

16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

128MB / 256MB (x72)

168-PIN REGISTERED SDRAM DIMMs

SPD CLOCK AND DATA CONVENTIONS

Data states on the SDA line can change only during

SCL LOW. SDA state changes during SCL HIGH are

reserved for indicating start and stop conditions (Fig-

ures 1 and 2).

SPD START CONDITION

All commands are preceded by the start condition,

which is a HIGH-to-LOW transition of SDA when SCL

is HIGH. The SPD device continuously monitors the

SDA and SCL lines for the start condition and will not

respond to any command until this condition has

been met.

SPD STOP CONDITION

All communications are terminated by a stop con-

dition, which is a LOW-to-HIGH transition of SDA

when SCL is HIGH. The stop condition is also used to

place the SPD device into standby power mode.

SPD ACKNOWLEDGE

Acknowledge is a software convention used to

indicate successful data transfers. The transmitting

device, either master or slave, will release the bus after

transmitting eight bits. During the ninth clock cycle,

the receiver will pull the SDA line LOW to acknowledge

that it received the eight bits of data (Figure 3).

The SPD device will always respond with an ac-

knowledge after recognition of a start condition and its

slave address. If both the device and a WRITE operation

have been selected, the SPD device will respond with an

acknowledge after the receipt of each subsequent eight-

bit word. In the read mode the SPD device will transmit

eight bits of data, release the SDA line and monitor the

line for an acknowledge. If an acknowledge is detected

and no stop condition is generated by the master, the

slave will continue to transmit data. If an acknowledge

is not detected, the slave will terminate further data

transmissions and await the stop condition to return to

standby power mode.

SCL

SDA

DATA STABLE DATA STABLEDATA

CHANGE

Figure 1

Data Validity

SCL

SDA

START

BIT

STOP

BIT

Figure 2

Definition of Start and Stop

SCL from Master

Data Output

from Transmitter

Data Output

from Receiver

Acknowledge

Figure 3

Acknowledge Response from Receiver

16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

128MB / 256MB (x72)

168-PIN REGISTERED SDRAM DIMMs

SCL

SDA IN

SDA OUT

tLOW

tSU:STA tHD:STA

tFtHIGH tR

tBUF

tDH

tAA

tSU:STO

tSU:DAT

tHD:DAT

UNDEFINED

SPD EEPROM TIMING DIAGRAM

SYMBOL MIN MAX UNITS

tAA 0.3 3.5 µs

tBUF 4.7 µs

tDH 300 ns

tF 300 ns

tHD:DAT 0 µs

tHD:STA 4 µs

SYMBOL MIN MAX UNITS

tHIGH 4 µs

tLOW 4.7 µs

tR1µs

tSU:DAT 250 ns

tSU:STA 4.7 µs

tSU:STO 4.7 µs

SERIAL PRESENCE-DETECT EEPROM TIMING PARAMETERS

EEPROM DEVICE SELECT CODE

(The most significant bit (b7) is sent first)

DEVICE TYPE IDENTIFIER CHIP ENABLE RW

b7 b6 b5 b4 b3 b2 b1 b0

Memory Area Select Code (two arrays) 0 1 1 0 E2 E1 E0 RW

Protection Register Select Code 0 1 1 0 E2 E1 E0 RW

EEPROM OPERATING MODES

(X = VIH or VIL)

MODE RW BIT WC1BYTES INITIAL SEQUENCE

Current Address Read 1 X 1 START, Device Select, RW = 1

Random Address Read 0 X 1 START, Device Select, RW = 0, Address

1 X reSTART, Device Select, RW = 1

Sequential Read 1 X ≥ 1 Similar to Current or Random Address Read

Byte Write 0 VIL 1 START, Device Select, RW = 0

Page Write 0 VIL ≤ 16 START, Device Select, RW = 0

16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

128MB / 256MB (x72)

168-PIN REGISTERED SDRAM DIMMs

SERIAL PRESENCE-DETECT EEPROM DC OPERATING CONDITIONS

(Note: 1) (VDD = +3.3V ±0.3V)

PARAMETER/CONDITION SYMBOL MIN MAX UNITS

SUPPLY VOLTAGE VDD 3 3.6 V

INPUT HIGH VOLTAGE: Logic 1; All inputs VIH VDD x 0.7 VDD + 0.5 V

INPUT LOW VOLTAGE: Logic 0; All inputs VIL -1 VDD x 0.3 V

OUTPUT LOW VOLTAGE: IOUT = 3mA VOL –0.4 V

INPUT LEAKAGE CURRENT: VIN = GND to VDD ILI –10 µA

OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD ILO –10 µA

STANDBY CURRENT: ISB –30 µA

SCL = SDA = VDD - 0.3V; All other inputs = GND or 3.3V +10%

POWER SUPPLY CURRENT: IDD –2mA

SCL clock frequency = 100 KHz

SERIAL PRESENCE-DETECT EEPROM AC OPERATING CONDITIONS

(Note: 1) (VDD = +3.3V ±0.3V)

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

SCL LOW to SDA data-out valid tAA 0.3 3.5 µs

Time the bus must be free before a new transition can start tBUF 4.7 µs

Data-out hold time tDH 300 ns

SDA and SCL fall time tF 300 ns

Data-in hold time tHD:DAT 0 µs

Start condition hold time tHD:STA 4 µs

Clock HIGH period tHIGH 4 µs

Noise suppression time constant at SCL, SDA inputs tI 100 ns

Clock LOW period tLOW 4.7 µs

SDA and SCL rise time tR1µs

SCL clock frequency tSCL 100 KHz

Data-in setup time tSU:DAT 250 ns

Start condition setup time tSU:STA 4.7 µs

Stop condition setup time tSU:STO 4.7 µs

WRITE cycle time tWRC 10 ms 2

NOTE: 1. All voltages referenced to VSS.

2. Timing actually specified by tWR.

NOTE: 1. All voltages referenced to VSS.

16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

128MB / 256MB (x72)

168-PIN REGISTERED SDRAM DIMMs

SERIAL PRESENCE-DETECT MATRIX

BYTE DESCRIPTION ENTRY (VERSION) MT9LSDT1672 MT9LSDT3272

0 NUMBER OF BYTES USED BY MICRON 128 80 80

1 TOTAL NUMBER OF SPD MEMORY BYTES 256 08 08

2 MEMORY TYPE SDRAM 04 04

3 NUMBER OF ROW ADDRESSES 12 or 13 0C 0D

4 NUMBER OF COLUMN ADDRESSES 10 0A 0A

5 NUMBER OF BANKS 1 01 01

6 MODULE DATA WIDTH 72 48 48

7 MODULE DATA WIDTH (continued) 0 00 00

8 MODULE VOLTAGE INTERFACE LEVELS LVTTL 01 01

9 SDRAM CYCLE TIME, tCK 7 (-13E) 70 70

(CAS LATENCY = 3) (note 2) 7.5 (-133) 75 75

8 (-10E) 80 80

10 SDRAM ACCESS FROM CLOCK, tAC 5.4 (-13E/-133) 54 54

(CAS LATENCY = 3) (note 2) 6 (-10E) 60 60

11 MODULE CONFIGURATION TYPE ECC 02 02

12 REFRESH RATE/TYPE 15.6µs/SELF (128MB), 7.81µs/SELF (256MB) 80 82

13 SDRAM WIDTH (PRIMARY SDRAM) 8 08 08

14 ERROR-CHECKING SDRAM DATA WIDTH 8 08 08

15 MIN. CLOCK DELAY FROM BACK-TO-BACK 1 01 01

RANDOM COLUMN ADDRESSES, tCCD

16 BURST LENGTHS SUPPORTED 1, 2, 4, 8, PAGE 8F 8F

17 NUMBER OF BANKS ON SDRAM DEVICE 4 04 04

18 CAS LATENCIES SUPPORTED 2, 3 06 06

19 CS LATENCY 0 01 01

20 WE LATENCY 0 01 01

21 SDRAM MODULE ATTRIBUTES -13E/-133 1F 1F

-10E 1F 1F

22 SDRAM DEVICE ATTRIBUTES: GENERAL 0E 0E 0E

23 SDRAM CYCLE TIME, tCK 7.5 (-13E) 75 75

(CAS LATENCY = 2) (note 2) 10 (-133/-10E) A0 A0

24 SDRAM ACCESS FROM CLK, tAC 5.4 (-13E) 54 54

(CAS LATENCY = 2) (note 2) 6 (-10E) 60 60

25 SDRAM CYCLE TIME, tCK –00 00

(CAS LATENCY = 1)

26 SDRAM ACCESS FROM CLK, tAC –00 00

(CAS LATENCY = 1)

27 MINIMUM ROW PRECHARGE TIME, tRP 15 (-13E) 0F 0F

20 (-133/-10E) 14 14

14 (-13E) 0E 0E

28 MINIMUM ROW ACTIVE TO ROW ACTIVE, 14 (-13E) 0E 0E

tRRD 15 (-133) 0F 0F

20 (-10E) 14 14

29 MINIMUM RAS# TO CAS# DELAY, tRCD 15 (-13E) 0F 0F

20 (-133/-10E) 14 14

NOTE: 1. “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW.”

2. Device latencies used for SPD values

16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

128MB / 256MB (x72)

168-PIN REGISTERED SDRAM DIMMs

SERIAL PRESENCE-DETECT MATRIX (continued)

BYTE DESCRIPTION ENTRY (VERSION) MT9LSDT1672 MT9LSDT3272

30 MINIMUM RAS# PULSE WIDTH, 45 (-13E) 2D 2D

(note 3) 44 (-133) 2C 2C

50 (-10E) 32 32

31 MODULE BANK DENSITY 128MB or 256MB 20 40

32 COMMAND AND ADDRESS SETUP TIME, 1.5 (-13E/-133) 15 15

tAS, t CMS 2 (-10E) 20 20

33 COMMAND AND ADDRESS HOLD TIME, 0.8 (-13E/133) 08 08

tAH, tCMH 1 (-10E) 10 10

34 DATA SIGNAL INPUT SETUP TIME, tDS 1.5 (-13E/-133) 15 15

2 (-10E) 20 20

35 DATA SIGNAL INPUT HOLD TIME, tDH 0.8 (-13E/-133) 08 08

1 (-10E) 10 10

36-61 RESERVED 00 00

62 SPD REVISION REV. 1.2 12 12

63 CHECKSUM FOR BYTES 0-62 -13E 99 BC

-133 DF 02

-10E 27 4A

64 MANUFACTURER’S JEDEC ID CODE MICRON 2C 2C

65-71 MANUFACTURER’S JEDEC ID CODE (CONT.) FF FF

72 MANUFACTURING LOCATION 01 01

02 02

03 03

04 04

05 05

06 06

07 07

08 08

09 09

73-90 MODULE PART NUMBER (ASCII) xx xx

91 PCB IDENTIFICATION CODE 1 01 01

20202

30303

40404

50505

60606

70707

80808

90909

92 IDENTIFICATION CODE (CONT.) 0 00 00

93 YEAR OF MANUFACTURE IN BCD xx xx

94 WEEK OF MANUFACTURE IN BCD xx xx

95-98 MODULE SERIAL NUMBER xx xx

99-125 MANUFACTURER-SPECIFIC DATA (RSVD) ––

126 SYSTEM FREQUENCY 100/133 MHz 64 64

127 SDRAM COMPONENT AND CLOCK DETAIL 8F 8F

NOTE: 1. “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW.”

2. x = Variable Data.

3. The value of tRAS used for the -13E module is calculated from tRC - tRP. Actual device spec. value is 37ns.

16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

128MB / 256MB (x72)

168-PIN REGISTERED SDRAM DIMMs

168-PIN DIMM

STANDARD PCB

NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted.

MIN

PIN 1

.700 (17.78)

.118 (3.00)

(2X)

.118 (3.00)

.250 (6.35)

4.550 (115.57)

.050 (1.27)

.118 (3.00) .040 (1.02)

.079 (2.00) R

(2X)

.039 (1.00) R(2X)

PIN 84

FRONT VIEW

.157(3.99)

MAX

.128 (3.25)

.118 (3.00) (2X)

BACK VIEW

PIN 168 PIN 85

2.625 (66.68)

1.661 (42.18)

1.505 (38.23)

1.495 (37.97)

5.256 (133.50)

5.244 (133.20)

16, 32 Meg x 72 PC133/PC100 Registered SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

128MB / 256MB (x72)

168-PIN REGISTERED SDRAM DIMMs

168-PIN DIMM

LOW PROFILE PCB

Back Vie w

FRONT VIEW

5.256 (133.50)

5.244 (133.20)

.157 (3.99)

MAX

.700 (17.78)

1.131 (28.73)

1.119(28.42)

PIN 1

.250 (6.35)

4.550 (115.57)

.050 (1.27)

.040 (1.02)

.039 (1.00) R(2X)

PIN 84

.118 (3.00)

.079 (2.00) R

(2X)

.118 (3.00)

(2X)

PIN 168 PIN 85

2.625 (66.68)

1.661 (42.18)

.128 (3.25)

.118 (3.00) (2X)

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micronsemi.com, Internet: http://www.micronsemi.com, Customer Comment Line: 800-932-4992

Micron is a registered trademark and the Micron logo are trademarks of Micron Technology, Inc.

NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted.

MIN