ee FAIRCHILD eee SEMICONDUCTOR? tr NC7ST86 February 1997 Revised March 1999 TinyLogic HST 2-Input Exclusive-OR Gate General Description The NG7ST86 is a single 2-Input high performance GMOS Exclusive-OR Gate, with TTL-compatible inputs. Advanced Silicon Gate GMOS fabrication assures high speed and low power circuit operation. ESD protection diodes inherently guard both inputs and outputs with respect to the Vor and GND rails. High gain circuitry offers high noise immunity and reduced sensitivity to input edge rate. The TTL-com- patible inputs facilitate TTL to NMOS/CMOQ8 interfacing. Device performance is similar to MM74HCT but with 2 the output current drive of HG/HCT. Features @ Space saving SOT23 or SC70 5-lead package @ High Speed; tap <8 ns typ, Veg =5V, C, = 15 pF @ Low Quiescent Power: Iog <1 HA typ, Voc = 5.5 @ Balanced Output Drive; 2 mA Ip, ,-2 MA Iny @ TTL-compatible inputs Ordering Code: Order Package Package . Package Description Supplied As Number Number Top Mark NG7ST86M5 MAG5B 8586 5-Lead SOT23, JEDEC MO-178, 1.6mm 250 Units on Tape and Reel NC7ST86M5xX MAQ5B 8586 5-Lead SOT23, JEDEC MO-178, 1.6mm 3k Units on Tape and Reel NC7STS6P5 MAAO5A TSs6 5-Lead SC70, EIAJ SC-88a, 1.25mm Wide |250 Units on Tape and Reel NC7STS6P5X MAAO5A Ts6 5-Lead $C70, ElAJ SC-88a, 1.25mm Wide |3k Units on Tape and Reel Logic Symbol Connection Diagram IEEEAEC a Pin Descriptions Pin Names Descriptions A,B Input Y Output TinyLogic is a trademark of Fairchild Semiconductor Corporation OD HO eso [3] | [ade (Top View) Function Table Y=A@B Inputs Output A B Y L L L L H H H L H H H L H = HIGH Logic Level L=LOW Logic Level 1999 Fairchild Semiconductor Corporation DSO12183.prf www faischildsemi.com a1B5 YO-saIsnjoxg indul-Z LSH wIIBoAULL 98LSZONNC7ST86 Absolute Maximum Ratingswte 1) Power Dissipation (P,}) @+85C SOT23-5 200 mW Supply Voltage (Vee) 0.5V to +7.0V 5C70-5 150 mW DC Input Diode Current {I)<) Vin <-0.5 20mA Recommended Operating Vin 2 Veco + 0.5 +20 mA Conditions DC Input Voltage (Vj) 0.5V to Veg +0.5V DC Output Diode Current (lox) Supply Voltage 4.5V-5.5V Vout <O.5V -20mA Input Voltage (Vin) OV-Voc Vout > Veco + 0.5V 420mA Output Voltage (Your) OV-Voc Output Voltage (Vour) -0.5 to Voc +0.5 Operating Temperature (Ta) 40C to +85C DC Output Source or Sink Input Rise and Fall Time (t,, ty) Current (lgu7) H2.5mA Voo =5.0V 0-500 ns DE Vee or Ground Current per Thermal Resistance (8) ,) Supply Pin {log oF lenin) 425 mA $0OT23-5 300C/W Storage Temperature (Tata) -65C to +150C $70-5 425C/W Junetion Temperature (T)) 150C Note 1: Absolute Maximum Ratings are those values beyond which dam- age to the device may occur The databock specifications should be met Lead Temperature 7); without exception to ensure that the system design Is reliable over its (Soldering, 10 seconds) zeorc fone spay eer ane aeaeree rom ames arn tions DC Electrical Characteristics Veco Ta = 725C Ta = 40C to +85C Symbol Parameter Units Conditions Vv) Min Typ Max Min Max Vin HIGH Level Input Voltage 45-55 20 20 Vi LOW Level Input Voltage 455.5 0.8 0.8 Vv Vou HIGH Level Gutput Voltage 45 44 45 44 Vo floH =-2OHA, Vin = Vib. 4.5 4.18 4.35 4.13 Vo VVin logy =-2 mA Vor LOW Level Output Voltage 45 a o1 o1 Vo flop =20 HA, Vin = VIL. 45 0.10 0.26 0.33 Vo [Viglop=2mA lin Input Leakage Current 5.5 +0.1 +1.0 pA |O= Vin = 5.5V loc Quiescent Supply Current 5.5 10 10.0 HA [Vin = Vog or GND loot log per Input 5.5 2.0 29 mA | One Input Vy =0.5V or 2.4, Other Input Veg or GND www fairchildsemi.comAC Electrical Characteristics Veo Ta = +25C Ta =40C to 485C Symbol Parameter Units Conditions Fig. No. () Min Typ Max Min Max IpLH. Propagation Delay 50 44 14 C_=15 pF Figure 1, x ns tpuL 7A 19 Figure 3 6.6 18 22 C_ = 50 pF 45 L pI 13.1 29 3B ns 5.6 16 20 5.5 12.5 28 32 iTLH, Output Transition Time 50 4 10 ns |C,=15pF Figure 1, TTL 45 an] 25 34 CL = 50 pF Figure 3 ns 55 10 21 26 Cw Input Capacitance Open 2 10 pF Cpp Power Dissipation Capacitance 5.0 8 pF | (Note 2} Figure 2 Note 2: Crap is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption leap) at no output loading and operating at 50% duty cycle (See Figure 2} Opp is related to leep dynamic operating current by expression leon = (Cpp) (Vice (ind + (Ice static) AC Loading and Waveforms OUTPLT G\ includes load and stray capacitance Input PRR = 1 OMHz t= 00 ns FIGURE 1. AC Test Circuit Input= AC Waveforms, PRA = Vanable, Duty Cycle = 50% FIGURE 2. Igep Test Circuit Sud of Phase G tery | 4 UT PUT tery Ir Phase QUT?UT FIGURE 3. AC Waveforms www-faicchildsemi.com 98LSZDNNC7ST86 Tape and Reel Specification TAPE FORMAT Package Tape Number Cavity Cover Tape Designator Section Cavities Status Status Leader (Start End) 125 (typ) Empty Sealed M5, P5 Carrier 250 Filled Sealed Trailer (Hub End} 75 (typ) Empty Sealed Leader (Start End) 125 (typ) Empty Sealed M5xX, P5X Carrier 3000 Filled Sealed Trailer (Hub End) 75 (typ) Empty Sealed TAPE DIMENSIONS inches (millimeters) , v itegap oe BP OTRO WF TP Ltd togde.05| | | 4 Tr? +_+ 2 TANGENT POINTS 1 eayity ual SMM GRECTION OF FIEC some ey rd) ocerrae Celaeal bie bate : of SFCTION R-B SECTION A-A BENG RADIUS NOT TO SCALE Package Tape Size DIM A DIM B DIM F DIM K, DIM P1 DIM W 0.093 0.096 0.138 + 0.004 | 0.053 + 0.004 0.157 0.3154 0.004 $0705 8mm (2.35) (2.45) (3.5+0.10) | (1.35+40.10) (4) (840.1) 0.130 0.130 0.138 + 0.002 | 0.055 + 0.004. 0.157 0.315+0.012 $07T23-5 8mm (3.3) (3.3) (3.5 + 0.05) (1440.11) (4) (8+ 0.3) www fairchildsemi.comREEL DIMENSIONS inches (millimeters) TA&PE SLOT o b ro LI | DETAIL X DETAIL X | LL. We SCALE: 3X | . Wo Tape A B c D N W1 W2 W3 Size 8 7.0 0.059 | 0.512 | 0.795 | 2.165 |0.331+0.059/-0.000 0.567 W1 +0.078/-0.039 mm (177.8) | 1.50) | (13.00) | (20.20) | (55.00) | (@.40+ 1.50/-0.00) (14.40) (W1 + 2.00/-1.00) www-faicchildsemi.com 98LSZDNNC7ST86 Physical Dimensions inches (millimeters) unless otherwise noted SiMM b pS eps 89 2.60 | mim 1.40 - =| O78 Fe LAND PATTERN FECOMMEMDATICN v7 SEE DETAIL A | & byt Qo ta = of a a a E El a NOTES: UNLESS OTHEWISE SPECIFIED 4) THIS PACLAGE COMFORMS TO JEDEC Mo-178, ISSUE B, VARIATIIIN 4a, GAGE PLANE DATED JaAHUarr 19a4. B) ALL DIMENSIONS ARE IM MILLIMETEPS. SEATING PLANE 5-Lead SOT23, JEDEC MO-178, 1.6mm Package Number MA05B www fairchildsemi.com 6Physical Dimensions inches (millimeters) unless otherwise noted (Continued) POLE, \ Cees GAGE PLANE a, \ , i i 7 4 i yay as . oat #_[. aan ye dk | ED RANienS Wil FLASH, 5-Lead SC70, ElAJ SC-38a, 1.25mm Wide Package Number MAAO5A LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www. fairchildsemi.com Fairchidd does not assume any responsibility for use of any circurtry described, no circurt patent licenses are impliedand Fairchild reserves the nght at any time without notice to charge sad circurtry and specifications a1B5 YO-saIsnjoxg indul-Z LSH wIIBoAULL 98LSZON