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Rev.1.00, Mar.12.2004, page 1 of 13
R1RP0416D Series
4M High Speed SRAM (256-kword × 16-bit)
REJ03C0108-0100Z
Rev. 1.00
Mar.12.2004
Description
The R1RP0416D Series is a 4-Mbit high speed static RAM organized 256-k word × 16-bit. It has realized
high speed access time by employing CMOS process (6-transistor memory cell) and high speed circuit
designing technology. It is most appropriate for the application which requires high speed, high density
memory and wide bit width configuration, such as cache and buffer memory in system. It is packaged in
400-mil 44-pin plastic SOJ and 400-mil 44-pin plastic TSOPII.
Features
• Single 5.0 V supply: 5.0 V ± 10%
• Access time: 12 ns (max)
• Completely static memory
No clock or timing strobe required
• Equal access and cycle times
• Directly TTL compatible
All inputs and outputs
• Operating current: 160 mA (max)
• TTL standby current: 40 mA (max)
• CMOS standby current : 5 mA (max)
: 1.0 mA (max) (L-version)
• Data retention current: 0.5 mA (max) (L-version)
• Data retention voltage: 2 V (min ) (L-version)
• Cente r VCC and VSS type pin out
Ordering Information
Type No. Access time Package
R1RP0416DGE-2PR 12 ns 400-mil 44-pin plastic SOJ (44P0K)
R1RP0416DGE-2LR 12 ns
R1RP0416DSB-2PR 12 ns 400-mil 44-pin plastic TSOPII (44P3W-H)
R1RP0416DSB-2LR 12 ns
R1RP0416D Series
Rev.1.00, Mar.12.2004, page 2 of 13
Pin Arrangement
A0
A1
A2
A3
A4
CS#
I/O1
I/O2
I/O3
I/O4
V
CC
V
SS
I/O5
I/O6
I/O7
I/O8
WE#
A5
A6
A7
A8
A9
(Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE#
UB#
LB#
I/O16
I/O15
I/O14
I/O13
V
SS
V
CC
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
44-pin SOJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A0
A1
A2
A3
A4
CS#
I/O1
I/O2
I/O3
I/O4
V
CC
V
SS
I/O5
I/O6
I/O7
I/O8
WE#
A5
A6
A7
A8
A9
A17
A16
A15
OE#
UB#
LB#
I/O16
I/O15
I/O14
I/O13
V
SS
V
CC
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
44-pin TSOP
(Top View)
Pin Description
Pin name Function
A0 to A17 Address input
I/O1 to I/O16 Data input/output
CS# Chip select
OE# Output enable
WE# Write enable
UB# Upper byte select
LB# Lower byte select
VCC Power supply
VSS Ground
NC No connection
R1RP0416D Series
Rev.1.00, Mar.12.2004, page 3 of 13
Block Diagram
1024-row × 32-column ×
8-block × 16-bit
(4,194,304 bits)
CS
VCC
VSS
A8 A9 A17 A15 A16 A0 A2 A4
Column I/O
Column decoder
I/O1
WE#
Input
data
control
Row
decoder
OE#
CS#
CS
CS
LB#
UB#
I/O16
I/O9
I/O8
.
.
.
.
.
.
A14
A13
A12
A5
A6
A7
A11
A10
A3
A1
(LSB)
(MSB)
Internal
voltage
generator
(LSB) (MSB)
R1RP0416D Series
Rev.1.00, Mar.12.2004, page 4 of 13
Operation Table
CS# OE# WE# LB# UB# Mode VCC current I/O1−
−−
−I/O8 I/O9−
−−
−I/O16 Ref. cycle
H × × × × Standby ISB, ISB1 High-Z High-Z
L H H × × Output disable ICC High-Z High-Z
L L H L L Read ICC Output Output Read cycle
L L H L H Lower byte read ICC Output High-Z Read cycle
L L H H L Upper byte read ICC High-Z Output Read cycle
L L H H H I
CC High-Z High-Z
L × L L L Write ICC Input Input Write cycle
L × L L H Lower byte write ICC Input High-Z Write cycle
L × L H L Upper byte write ICC High-Z Input Write cycle
L × L H H I
CC High-Z High-Z
Note: H: VIH, L: VIL, ×: VIH or VIL
Absolute Maximum Ratings
Parameter Symbol Value Unit
Supply voltage relative to VSS V
CC −0.5 to +7.0 V
Voltage on any pin relative to VSS V
T −0.5*1 to VCC + 0.5*2 V
Power dissipation PT 1.0 W
Operating temperature Topr 0 to +70 °C
Storage temperature Tstg −55 to +125 °C
Storage temperature under bias Tbias −10 to +85 °C
Notes: 1. VT (min) = −2.0 V for pulse width (under shoot) ≤ 6 ns.
2. VT (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 6 ns.
Recommended DC Operating Conditions
(Ta = 0 to +70°C)
Parameter Symbol Min Typ Max Unit
Supply voltage VCC*3 4.5 5.0 5.5 V
V
SS*4 0 0 0 V
Input voltage VIH 2.2 V
CC + 0.5*2 V
V
IL −0.5*1 0.8 V
Notes: 1. VIL (min) = −2.0 V for pulse width (under shoot) ≤ 6 ns.
2. VIH (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 6 ns.
3. The supply voltage with all VCC pins must be on the same level.
4. The supply voltage with all VSS pins must be on the same level.
R1RP0416D Series
Rev.1.00, Mar.12.2004, page 5 of 13
DC Characteristics
(Ta = 0 to +70°C, VCC = 5.0 V ± 10%, VSS = 0 V)
Parameter Symbol Min Max Unit Test conditions
Input leakage current |ILI| 2 µA VIN = VSS to VCC
Output leakage current |ILO| 2 µA VIN = VSS to VCC
Operation power supply current ICC 160 mA Min cycle
CS# = VIL, lOUT = 0 mA
Other inputs = VIH/VIL
Standby power supply current ISB 40 mA Min cycle, CS# = VIH,
Other inputs = VIH/VIL
I
SB1 5 mA f = 0 MHz
VCC ≥ CS# ≥ VCC − 0.2 V,
(1) 0 V ≤ VIN ≤ 0.2 V or
(2) VCC ≥ VIN ≥ VCC − 0.2 V
*1 1.0*1
Output voltage VOL 0.4 V IOL = 8 mA
V
OH 2.4 V IOH = −4 mA
Note: 1. This characteristics is guaranteed only for L-version.
Capacitance
(Ta = +25°C, f = 1.0 MHz)
Parameter Symbol Min Max Unit Test conditions
Input capacitance*1 C
IN 6 pF VIN = 0 V
Input/output capacitance*1 C
I/O 8 pF VI/O = 0 V
Note: 1. This parameter is sampled and not 100% tested.
R1RP0416D Series
Rev.1.00, Mar.12.2004, page 6 of 13
AC Characteristics
(Ta = 0 to +70°C, VCC = 5.0 V ± 10%, unless otherwise noted.)
Test Condit ions
• Input pulse levels: 3.0 V/0.0 V
• Input rise and fall time: 3 ns
• Input and output timing reference levels: 1.5 V
• Output load: See figures (Including scope and jig)
Output load (B)
(for t
CLZ
, t
OLZ
, t
BLZ
, t
CHZ
, t
OHZ
,
t
BHZ
, t
WHZ
, and t
OW
)
D
OUT
255 Ω
480 Ω
5 V
5 pF
1.5 V
30 pF
D
OUT
RL = 50 Ω
Output load (A)
Zo = 50 Ω
Read Cycle
R1RP0416D
-2
Parameter Symbol Min Max Unit Notes
Read cycle time tRC 12 ns
Address access time tAA 12 ns
Chip select access time tACS 12 ns
Output enable to output valid tOE 6 ns
Byte select to output valid tBA 6 ns
Output hold from address change tOH 3 ns
Chip select to output in low-Z tCLZ 3 ns 1
Output enable to output in low-Z tOLZ 0 ns 1
Byte select to output in low-Z tBLZ 0 ns 1
Chip deselect to output in high-Z tCHZ 6 ns 1
Output disable to output in high-Z tOHZ 6 ns 1
Byte deselect to output in high-Z tBHZ 6 ns 1
R1RP0416D Series
Rev.1.00, Mar.12.2004, page 7 of 13
Write Cycle
R1RP0416D
-2
Parameter Symbol Min Max Unit Notes
Write cycle time tWC 12 ns
Address valid to end of write tAW 8 ns
Chip select to end of write tCW 8 ns 8
Write pulse width tWP 8 ns 7
Byte select to end of write tBW 8 ns
Address setup time tAS 0 ns 5
Write recovery time tWR 0 ns 6
Data to write time overlap tDW 6 ns
Data hold from write time tDH 0 ns
Write disable to output in low-Z tOW 3 ns 1
Output disable to output in high-Z tOHZ 6 ns 1
Write enable to output in high-Z tWHZ 6 ns 1
Notes: 1. Transition is measured ±200 mV from steady voltage with output load (B). This parameter is
sampled and not 100% tested.
2. If the CS# or LB# or UB# low transition occurs simultaneously with the WE# low transition or
after the WE# transition, output remains a high impedance state.
3. WE# and/or CS# must be high during address transition time.
4. If CS#, OE#, LB# and UB# are low during this period, I/O pins are in the output state. Then the
data input signals of opposite phase to the outputs must not be applied to them.
5. tAS is measured from the latest address transition to the latest of CS#, WE#, LB# or UB# going
low.
6. tWR is measured from the earliest of CS#, WE#, LB# or UB# going high to the first address
transition.
7. A write occurs during the overlap of a low CS#, a low WE# and a low LB# or a low UB# (tWP). A
write begins at the latest transition among CS# going low, WE# going low and LB# going low or
UB# going low. A write ends at the earliest transition among CS# going high, WE# going high
and LB# going high or UB# going high.
8. tCW is measured from the later of CS# going low to the end of write.
R1RP0416D Series
Rev.1.00, Mar.12.2004, page 8 of 13
Timing Waveforms
Read Timing Waveform (1) (WE# = VIH)
t
AA
t
ACS
t
OE
t
BA
t
BLZ
t
OLZ
t
CLZ
t
OH
t
CHZ
t
OHZ
t
BHZ
t
RC
Address Valid address
Valid data
D
OUT
CS#
OE#
LB#, UB#
High impedance
*
1
*
1
*
1
*
1
*
1
*
1
*
4
*
4
R1RP0416D Series
Rev.1.00, Mar.12.2004, page 9 of 13
Read Timing Waveform (2) (WE# = VIH, LB# = VIL, UB# = VIL)
t
AA
t
ACS
t
RC
t
OE
t
CLZ
Valid data
Address
CS#
D
OUT
Valid address
High impedance
t
OHZ
OE#
t
OH
t
CHZ
t
OLZ
*
1
*
1
*
1
*
1
*
4
*
4
R1RP0416D Series
Rev.1.00, Mar.12.2004, page 10 of 13
Write Timing Waveform (1) (WE# Controlled)
Address
WE#*
3
t
WC
t
AW
t
AS
t
WR
t
WP
t
WHZ
t
OLZ
t
OW
t
OHZ
t
CW
t
BW
t
DH
t
DW
Valid address
Valid data
CS#*
3
OE#
LB#, UB#
D
OUT
D
IN
High impedance
*
2
R1RP0416D Series
Rev.1.00, Mar.12.2004, page 11 of 13
Write Timing Waveform (2) (CS# Controlled)
Address
CS# *
3
t
WC
t
AW
t
AS
t
WR
t
WP
t
WHZ
t
OLZ
t
OW
t
OHZ
t
CW
t
BW
t
DH
t
DW
Valid address
Valid data
WE# *
3
OE#
LB#, UB#
D
OUT
D
IN
High impedance
*
2
*
4
R1RP0416D Series
Rev.1.00, Mar.12.2004, page 12 of 13
Write Timing Waveform (3) (LB#, UB# Controlled, OE# = VIH)
Address
DIN-UB
(DIN-LB)
DIN-LB
(DIN-UB)
DOUT High impedance
Valid address
tDW tDH
tCW
tAS tBW
tWP
tWC
tWR
tAW
WE#*3
CS#*3
UB# (LB#)
LB# (UB#)
tBW
Valid data
tDW tDH
Valid data
R1RP0416D Series
Rev.1.00, Mar.12.2004, page 13 of 13
Low VCC Data Retention Characteristics
(Ta = 0 to +70°C)
This characteristics is guaranteed only for L-version.
Parameter Symbol Min Max Unit Test conditions
VCC for data retention VDR 2.0 V VCC ≥ CS# ≥ VCC − 0.2 V,
(1) 0 V ≤ VIN ≤ 0.2 V or
(2) VCC ≥ VIN ≥ VCC − 0.2 V
Data retention current ICCDR 500 µA VCC = 3 V
VCC ≥ CS# ≥ VCC − 0.2 V,
(1) 0 V ≤ VIN ≤ 0.2 V or
(2) VCC ≥ VIN ≥ VCC − 0.2 V
Chip deselect to data retention time tCDR 0 ns See retention waveform
Operation recovery time tR 5 ms
Low VCC Da ta Retention Timing Waveform
CC
V
2.2 V
4.5 V
0 V
CS#
t
CDR
t
R
DR
V
Data retention mode
V
CC
≥ CS# ≥ V
CC
− 0.2 V
Revision History R1RP0416D Series Data Sheet
Contents of Modification Rev. Date
Page Description
0.01 Sep. 30, 2003 Initial issue
1.00 Mar.12.2004 Deletion of Preliminary
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