© 2010 Semtech Corporation 1
SC417/SC427
10A EcoSpeedTM Integrated FET
Regulator with Programmable LDO
Features
Power system:
Input voltage — 3V to 28V
Integrated bootstrap switch
Programmable LDO output — 200mA
1% reference tolerance -40 to +85 °C
Selectable internal/external bias power supply
EcoSpeedTM architecture with pseudo-xed fre-
quency adaptive on-time control
Logic input/output control
Independent control EN for LDO and switcher
Programmable VIN UVLO threshold
Power good output
Selectable ultrasonic/power save methods
Protections
Over-voltage/under-voltage
TC compensated RDS(ON) sensed current limit
Thermal shutdown
Output capacitor types
High ESR — SP, POSCAP, OSCON
Ceramic capacitors
Package — 5x5mm, 32-pin MLPQ
Lead-free and halogen free
RoHS and WEEE compliant
Applications
Oce automation and computing
Networking and telecommunication equipment
Point-of-load power supplies and module replacement.
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Description
The SC417/SC427 is a stand-alone synchronous
EcoSpeedTM buck regulator which incorporates Semtech’s
advanced, patented adaptive on-time control architecture
to provide excellent light-load eciency and fast transient
response. It features integrated power MOSFETs, a boot-
strap switch, and a programmable LDO in a 5x5mm
package. The device is highly ecient and uses minimal
15x20mm PCB area for a total converter solution. Refer to
page 16 for information on the C-SIM simulation tool.
The SC417/SC427 supports using standard capacitor types
such as electrolytic or special polymer, in addition to
ceramic, at switching frequencies up to 1MHz. The pro-
grammable frequency, synchronous operation, and select-
able power-save provide high eciency operation over a
wide load range. In power-save mode, the minimum oper-
ating frequency for the SC417 is 25kHz whereas the SC427
has no minimum.
Additional features include internal soft-start, program-
mable cycle-by-cycle over-current limit protection, under
and over-voltage protections and soft shutdown. The
device also provides separate enable inputs for the PWM
controller and LDO as well as a power good output for the
PWM controller.
The wide input voltage range, programmable frequency,
and programmable LDO make the device extremely exible
and easy to use in a broad range of applications. Support is
provided for single cell or multi-cell battery systems in addi-
tion to traditional DC power supply applications.
May 20, 2010
POWER MANAGEMENT
SC417/SC427
V5V
BST
LX
PGOOD
ILIM
LXS
EN/PSV
TON
ENL
LXBST
RILIM
CBST
+
RFB1
RFB2
VOUT
COUT
1µF
L1
VEXT/LDO
CIN PGND
AGND
VIN
VIN
VOUT
FB
PGOOD
ENABLE LDO
ENABLE/PSAVE
RTON
Typical Application Circuit
US Patent: 7,714,547 B2
SC417/SC427
2
Pin Conguration Ordering Information
Marking Information
SC417
yyww
xxxxxx
xxxxxx
AGND
PAD 1
VIN
PAD 2
LX
PAD 3
ENL
32
TON
31
AGND
30
EN/PSV
29
LXS
28
ILIM
27
PGOOD
26
LX
25
24
LX
LX
23
PGND
22
PGND
21
PGND
20
PGND
19
PGND
18
PGND
17
PGND
16
PGND
15
DL
14
LXBST
13
DH
12
VIN
11
VIN
10
VIN
9
BST
8
VOUT
5
VLDO
7
VIN
6
V5V
3
AGND
4
FBL
2
FB
1
Top View
Notes:
1) Available in tape and reel only. A reel contains 3000 devices.
2) Pb-free, Halogen free, and RoHS/WEEE compliant
yyww = Date Code
xxxxxx = Semtech Lot Number
xxxxxx = Semtech Lot Number
SC417 and SC427
MLPQ-32; 5x5, 32 LEAD
SC427
yyww
xxxxxx
xxxxxx
yyww = Date Code
xxxxxx = Semtech Lot Number
xxxxxx = Semtech Lot Number
Device Package
SC417MLTRT(1)(2) MLPQ-32 5X5
SC427MLTRT(1)(2) MLPQ-32 5X5
SC417EVB Evaluation Board
SC427EVB Evaluation Board
SC417/SC427
3
Absolute Maximum Ratings
LX to PGND (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +30
LX to PGND (V) (transient — 100ns max.) . . . . . . -2 to +30
VIN to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +30
EN/PSV, PGOOD, ILIM, to GND (V) . . . . . . -0.3 to +(V5V + 0.3)
VOUT, VLDO, FB, FBL, to GND (V) . . . . . . . -0.3 to +(V5V + 0.3)
V5V to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6
TON to PGND (V) . . . . . . . . . . . . . . . . . . . . . -0.3 to +(V5V - 1.5)
ENL (V) ...................................... -0.3 to VIN
BST to LX (V) ..............................-0.3 to +6.0
BST to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +35
AGND to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +0.3
ESD Protection Level(1) (kV) ............................ 2
Recommended Operating Conditions
Input Voltage (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 to 28
V5V to PGND (V) .............................4.5 to 5.5
VOUT to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 to 5.5
Thermal Information
Storage Temperature (°C) . . . . . . . . . . . . . . . . . . . . -60 to +150
Maximum Junction Temperature (°C) . . . . . . . . . . . . . . . 1 5 0
Operating Junction Temperature (°C) . . . . . . -40 to +125
Thermal resistance, junction to ambient (2) (°C/W)
High-side MOSFET ............................... 25
Low-side MOSFET ............................... 20
PWM controller and LDO thermal resistance . . . . . . 50
Peak IR Reflow Temperature (°C) . . . . . . . . . . . . . . . . . . . . .260
Exceeding the above specications may result in permanent damage to the device or device malfunction. Operation outside of the parameters
specied in the Electrical Characteristics section is not recommended.
NOTES:
(1) Tested according to JEDEC standard JESD22-A114.
(2) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards.
Unless specied: VIN =12V, TA = +25°C for Typ, -40 to +85 °C for Min and Max, TJ < 125°C, V5V = +5V, Typical Application Circuit
Electrical Characteristics
Parameter Conditions Min Typ Max Units
Input Supplies
Input Supply Voltage 3 28 V
V5V Voltage 4.5 5.5 V
VIN UVLO Threshold(1)
Sensed at ENL pin, rising edge 2.40 2.60 2.95
V
Sensed at ENL pin, falling edge 2.23 2.40 2.57
VIN UVLO Hysteresis EN/PSV = High 0.2 V
V5V UVLO Threshold
Measured at V5V pin, rising edge 3.7 3.9 4.1
V
Measured at V5V pin, falling edge 3.5 3.6 3.75
V5V UVLO Hysteresis 0.3 V
VIN Supply Current
ENL , EN/PSV = 0V, VIN = 28V 8.5 20
μA
Standby mode; ENL=V5V, EN/PSV = 0V 130
SC417/SC427
4
Electrical Characteristics (continued)
Parameter Conditions Min Typ Max Units
Input Supplies (continued)
V5V Supply Current
ENL , EN/PSV = 0V 3 7 μA
SC417, EN/PSV = V5V, no load (fSW = 25kHz),
VFB > 500mV(2) 2
mA
SC427, EN/PSV = V5V, no load, VFB > 500mV(2) 0.7
fSW = 250kHz, EN/PSV = oating , no load(2) 10
FB On-Time Threshold
Static VIN and load, 0 to +85 °C 0.496 0.500 0.504 V
Static VIN and load, -40 to +85 °C 0.495 0.505 V
Frequency Range
Continuous mode operation 200 1000
kHz
Minimum fSW, (SC417 only), EN/PSV = V5V, no load 25
Bootstrap Switch Resistance 10 Ω
Timing
On-Time Continuous mode operation,
VIN = 15V, VOUT = 5V, fSW= 300kHz, RTON = 133kΩ 999 1110 1220 ns
Minimum On-Time (2) 80 ns
Minimum O-Time (2) 250 ns
Soft-Start
Soft-Start Ramp Time (2) 850 μs
Analog Inputs/Outputs
VOUT Input Resistance 500 kΩ
Current Sense
Zero-Crossing Detector Threshold LX - PGND -3 0 +3 mV
Power Good
Power Good Threshold
Upper limit, VFB > internal 500mV reference +20 %
Lower limit, VFB < internal 500mV reference -10 %
Start-Up Delay Time 2 ms
Fault (noise immunity) Delay Time(2) 5 µs
Leakage 1 µA
Power Good On-Resistance 10 Ω
SC417/SC427
5
Electrical Characteristics (continued)
Parameter Conditions Min Typ Max Units
Fault Protection
Valley Current Limit RILIM = 5.9k Ω 6 8 10 A
ILIM Source Current 10 μA
ILIM Comparator Oset With respect to AGND -10 0 +10 mV
Output Under-Voltage Fault VFB with respect to internal 500mV reference,
8 consecutive clocks -25 %
Smart Power-save Protection Threshold (2) VFB with respect to internal 500mV reference +10 %
Over-Voltage Protection Threshold VFB with respect to internal 500mV reference +20 %
Over-Voltage Fault Delay(2) 5 μs
Over-Temperature Shutdown(2) 10°C hysteresis 150 °C
Logic Inputs/Outputs
Logic Input High Voltage ENL 1.0 V
Logic Input Low Voltage ENL 0.4 V
EN/PSV Input for PSAVE Operation (2) V5V = 5V 2.2 5 V
EN/PSV Input for Forced Continuous Operation (2) 1 2 V
EN/PSV Input for Disabling Switcher (2) 0.4 V
EN/PSV Input Bias Current EN/PSV= V5V or AGND -10 +10 μA
ENL Input Bias Current VIN = 28V 11 18 μA
FBL, FB Input Bias Current FBL, FB = V5V or AGND -1 +1 μA
SC417/SC427
6
Electrical Characteristics (continued)
Parameter Conditions Min Typ Max Units
Linear Regulator (LDO)
FBL Accuracy VLDO load = 10mA 0.735 0.75 0.765 V
LDO Current Limit
Start-up and foldback, VIN = 12V 85
mA
Operating current limit, VIN = 12V 135 200
VLDO to VOUT Switch-over Threshold (3) -140 +140 mV
VLDO to VOUT Non-switch-over Threshold (3) -450 +450 mV
VLDO to VOUT Switch-over Resistance VOUT = +5V 2 Ω
LDO Drop Out Voltage (4) From VIN to VVLDO, VVLDO = +5V, IVLDO = 100mA 1.2 V
Notes:
(1) VIN UVLO is programmable using a resistor divider from VIN to ENL to AGND. The ENL voltage is compared to an internal reference.
(2) Guaranteed by design.
(3) The switch-over threshold is the maximum voltage dierential between the VLDO and VOUT pins which ensures that VLDO will internally
switch-over to VOUT. The non-switch-over threshold is the minimum voltage dierential between the VLDO and VOUT pins which ensures
that VLDO will not switch-over to VOUT.
(4) The LDO drop out voltage is the voltage at which the LDO output drops 2% below the nominal regulation point.
SC417/SC427
7
RTON
154KΩ
SC417/SC427
FB
1
FBL
2
V5V
3
AGND
4
VOUT
5
VIN
6
VLDO
7
BST
8
VIN
9
VIN
10
VIN
11
PGND
15
PGND
16
17
18
19
20
21
PGND 22
LX 23
LX 24
LX 25
PGOOD 26
ILIM 27
LXS 28
EN/PSV 29
AGND 30
TON 31
ENL 32
DL
14 LXBST
13 DH
12
VIN
PAD 2
AGND
PAD 1
LX PAD 3
RILIM
10KΩ
RLDO2
10KΩ
RLDO1
57.6KΩ
CIN
4 x 10µF
(see note)
RGND
0
1µF
CBST
1µF
VIN
+12V
Note:
V5V is tied to VLDO
PGND
PGND
PGND
PGND
PGND
+
10nF
CFF
100pF
RFB1
11KΩ
L1
0.88µH
RFB2
10KΩ
VOUT
1.05V @ 10A, 250kHz
COUT1
220µF
15mΩ
ENABLE/
PSAVE
ENABLE
LDO
+
COUT2
15mΩ
220µF
PGOOD
1µF
Component Value Manufacturer Part Number Web
CIN 4 x 10µF/25V Murata GRM32DR71E106KA12L www.murata.com
www.panasonic.comCOUT1,2 (option 1) 2 x 220µF/15mΩPanasonic EEFUE0J221R
Key Components
All other small signal components (resistors and capacitors) are standard SMT devices.
www.nec-tokin.comL1 (option 1) 0.88µH/2.3mΩNEC-Tokin
IHLP4040DZER1R0M11 www.vishay.comL1 (option 2) 1.0µH/2.3mΩVishay
MPC1040LR88C
COUT1,2 (option 2)
NOTE: The quantity of 10µF input capacitors required varies with the application requirements.
www.panasonic.com330µF/9mΩPanasonic EEF-SX0E331ER
Detailed Application Circuit
SC417/SC427
8
Typical Characteristics
SC417 Eciency/Power Loss vs. Load — PSAVE Mode
50
55
60
65
70
75
80
85
90
95
100
0 1 2 3 4 5 6 7 8 9 10
I
OUT
(A)
Efficiency (%)
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
Power Loss (W)
Internal biased: VLDO = 5V, V
OUT
= 1.05V
Efficiency
Power Loss
19V
IN
12V
IN
6V
IN
19V
IN
12V
IN
6V
IN
Characteristics in this section are based on using the Detailed Application Circuit on page 7 (SC417/SC427).
SC417 Eciency/Power Loss — PSAVE vs. FCM
External biased: V5V = 5V, V
IN
= 12v, V
OUT
= 1.05V
FCM
50
55
60
65
70
75
80
85
90
95
100
0 1 2 3 4 5 6 7 8 9 10
I
OUT
(A)
Efficiency (%)
-0.025
0.025
0.075
0.125
0.175
0.225
Delta Power Loss (W)
Power Loss FCM -PSM
PSM
Internal biased: VLDO = 5V, V
IN
= 12v, V
OUT
= 1.05V
50
55
60
65
70
75
80
85
90
95
100
0 1 2 3 4 5 6 78 9 10
I
OUT
(A)
Efficiency (%)
-0.025
0.025
0.075
0.125
0.175
0.225
Delta Power Loss (W)
PSM
FCM
Power Loss FCM -PSM
SC417 Eciency/Power Loss vs. Load — PSAVE Mode
External biased: V5V = 5V, VOUT = 1.05V
50
55
60
65
70
75
80
85
90
95
100
0 1 2 3 4 5 6 7 8 9 10
IOUT (A)
Efficiency (%)
0.00
0.50
1.00
1.50
2.00
2.50
Power Loss (W)
Power Loss
Efficiency
6VIN
12VIN
19VIN
19VIN 12VIN
6VIN
SC417 Eciency/Power Loss vs. Load — FCM SC417 Eciency/Power Loss — FCM
External biased: V5V = 5V, V
OUT
= 1.05V
50
55
60
65
70
75
80
85
90
95
100
0 1 2 3 4 5 6 7 8 9 10
I
OUT
(A)
Efficiency (%)
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
Power Loss (W)
12V
IN
Efficiency
6V
IN
19V
IN
Power Loss
19V
IN
12V
IN
6V
IN
V
IN
= 12v, V
OUT
= 1.05V
50
55
60
65
70
75
80
85
90
95
100
0 1 2 3 4 5 6 7 8 9 10
I
OUT
(A)
Efficiency (%)
0.04
0.06
0.08
0.10
0.12
0.14
Delta Power Loss (W)
Power Loss FCM -PSM
External Bias
Internal Bias
SC417 Eciency/Power Loss — PSAVE vs. FCM
SC417/SC427
9
Typical Characteristics (continued)
SC417 vs. SC427 Eciency/Power Loss — PSAVE Mode
External Biased: V5V = 5V, VOUT = 1.05V
IOUT (A)
0
10
20
30
40
50
60
70
80
90
100
0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 0.22
Efficiency (%)
-0.005
-0.002
0.001
0.004
0.007
0.010
0.013
0.016
0.019
0.022
0.025
Delta Power Loss (W)
SC427
SC417
Power Loss SC417 – SC427
Characteristics in this section are based on using the Detailed Application Circuit on page 7 (SC417/SC427).
SC417 Load Regulation —PSAVE Mode
External biased; V5V = 5V, V
OUT
= 1.05V
19V
1.03
1.04
1.05
1.06
1.07
1.08
0 2 4 6 8 10
I
OUT
(A)
Vout (V)
Note: Measured V
OUT
= 1.05V plus ½ of output ripple voltage
12V
6V
SC427 Eciency/Power Loss vs. Load — PSAVE Mode
External biased: V5V = 5V, V
OUT
= 1.05V
19V
IN
19V
IN
6V
IN
6V
IN
I
OUT
(A)
50
55
60
65
70
75
80
85
90
95
100
0 1 2 3 4 5 6 7 8 9 10
Efficiency (%)
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
Power Loss (W)
Power Loss
Efficiency
12V
IN
12V
IN
SC427 Eciency/Power Loss vs. Load — FCM
External biased: V5V = 5V, V
OUT
= 1.05V
19V
IN
I
OUT
(A)
6V
IN
50
55
60
65
70
75
80
85
90
95
100
0 1 2 3 4 5 6 7 8 9 10
Efficiency (%)
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
Power Loss (W)
Efficiency
Power Loss
12V
IN
19V
IN
12V
IN
6V
IN
SC427 Eciency/Power Loss — FCM
V
IN
= 12V, V
OUT
= 1.05V
I
OUT
(A)
50
55
60
65
70
75
80
85
90
95
100
01 2 3 4 5 6 7 8 9 10
Efficiency (%)
0.05
0.06
0.07
0.08
0.09
0.10
0.11
0.12
0.13
0.14
0.15
Delta Power Loss (W)
Power Loss: Internal-External Biased
External Bias
Internal Bias
SC427 Load Regulation —PSAVE Mode
External biased; V5V = 5V, VOUT = 1.05V
12V
IOUT(A)
VOUT (V)
19V
1.03
1.04
1.05
1.06
1.07
1.08
0 2 4 6 8 10
Note: Measured VOUT = 1.05V plus ½ of output ripple voltage
6V
SC417/SC427
10
Typical Characteristics (continued)
Characteristics in this section are based on using the Detailed Application Circuit on page 7 (SC417/SC427).
SC417 Load Regulation —FCM
SC417 Switching Freq. — FCM vs. PSAVE Mode
SC427 Load Regulation —FCM
SC417 VOUT Ripple —FCM vs. PSAVE Mode
SC427 VOUT Ripple —FCM vs. PSAVE Mode
External biased; V5V = 5V, VOUT = 1.05V, VIN = 12V
FCM
PSM
IOUT(A)
VOUT Ripple (V)
0.020
0.025
0.030
0.035
0.040
0 2 4 6 8 10
SC427 Switching Freq. — FCM vs. PSAVE Mode
SC417/SC427
11
Typical Characteristics (continued)
Ultrasonic Powersave Mode — No Load (SC417)
Time (10µs/div)s/div)/div)
(50mV/div)
(10V/div)
(10V/div)
(5V/div)
VIN = 12V, VOUT = 1.05V, IOUT = 0A, VLDO = V5V = EN/PSV= ENL = 5V
1.073V Δ V ~ 29mV
1.044V
f=26.22kHz
Time (400µs/div)s/div)/div)
Self-Biased Start-Up — Power Good True
(10V/div)
(2V/div)
(5V/div)
VIN = 0V to 12V step, VOUT = 1.05V, IOUT = 0A, VLDO = V5V = EN/PSV= ENL = 5V
1.05V
0V
ΔV/ΔT ~
1.4 V/ms
(500mV/div)
Time (100µs/div)s/div)/div)
Enabled Loaded Output — Full Scale
(50mV/div)
(10V/div)
(5V/div)
VIN = 12V, VOUT = 1.05V, IOUT = 1A, VLDO = V5V = ENL = 5V. EN/PSV= 5V
1.05V
0V
ΔV/ΔT ~
1.4V/ms
Forced Continuous Mode — No Load
Time (2µs/div)s/div)/div)
(50mV/div)
(10V/div)
(10V/div)
(5V/div)
VIN = 12V, VOUT = 1.05V, IOUT = 0A, VLDO = V5V = ENL = 5V, EN/PSV= oat
1.078V Δ V ~ 30mV
1.048V
f=227.4kHz
Enabled Loaded Output — Power Good True
(500mV/div)
(10V/div)
(5V/div)
VIN = 12V, VOUT = 1.05V, IOUT = 1A, VLDO = V5V = ENL = 5V. EN/PSV= 5V
Time (400µs/div)s/div)/div)
1.05V
0V
~2ms
Characteristics in this section are based on using the Detailed Application Circuit on page 7 (SC417/SC427).
SC417/SC427
12
Typical Characteristics (continued)
Transient Response — Load Rising (SC417)
Time (10µs/div)s/div)/div)
(50mV/div)
(10A/div)
(10V/div)
(5V/div)
VIN = 12V, VOUT = 1.05V, IOUT = 0A to 10A, VLDO = V5V = EN/PSV= ENL = 5V
1.063V
1.025V
Output Over-current Response — Normal Operation
Time (100µs/div)s/div)/div)
(500mV/div)
(10V/div)
(10A/div)
(5V/div)
VIN = 12V, VOUT = 1.05V, VLDO = V5V = ENL = 5V, EN/PSV= oating; IOUT ramped to trip point
1.05V
IOUT = 10.37A
0V
Transient Response — Load Falling (SC417)
Time (10µs/div)s/div)/div)
(50mV/div)
(10A/div)
(10V/div)
(5V/div)
VIN = 12V, VOUT = 1.05V, IOUT = 10A to 0A, VLDO = V5V = EN/PSV= ENL = 5V
1.101V
1.055V
Output Under-voltage Response — Normal Operation
Time (100µs/div)s/div)/div)
(500mV/div)
(10V/div)
(5V/div)
VIN = 12V, VOUT = 1.05V, IOUT = 0A, VLDO = V5V = ENL = 5V, oating EN/PSV
V2~710mV
Transient Response — Load Rising (SC427)
Time (10µs/div)s/div)/div)
(50mV/div)
(5A/div)
(10V/div)
(5V/div)
VIN = 12V, VOUT = 1.05V, IOUT = 0A to 10A, VLDO = V5V = EN/PSV= ENL = 5V
Transient Response — Load Falling (SC427)
Time (10µs/div)s/div)/div)
(50mV/div)
(5A/div)
(10V/div)
(5V/div)
VIN = 12V, VOUT = 1.05V, IOUT = 10A to 0A, VLDO = V5V = EN/PSV= ENL = 5V
Characteristics in this section are based on using the Detailed Application Circuit on page 7 (SC417/SC427).
SC417/SC427
13
Typical Characteristics (continued)
Shorted Output Response — Normal Operation
Time (40µs/div)s/div)/div)
(500mV/div)
(10V/div)
(10A/div)
(5V/div)
VIN = 12V, VOUT = 1.05V, IOUT = 0A, VLDO = V5V = EN/PSV= ENL = 5V
1.05V
0V
Shorted Output Response — Power-UP Operation
Time (400µs/div)s/div)/div)
(500mV/div)
(10V/div)
(10A/div)
(5V/div)
VIN = 12V, VOUT = 1.05V, IOUT = 0A, VLDO = V5V = EN/PSV= ENL = 5V
~1.7ms
Characteristics in this section are based on using the Detailed Application Circuit on page 7 (SC417/SC427).
SC417/SC427
14
Pin Descriptions
Pin # Pin Name Pin Function
1 FB Feedback input for switching regulator used to program the output voltage — connect to an external resis-
tor divider from VOUT to AGND.
2 FBL Feedback input for the LDO — connect to an external resistor divider from VLDO to AGND — used to pro-
gram the LDO output.
3 V5V 5V power input for internal analog circuits and gate drives — connect to external 5V supply or congure
the LDO for 5V and connect to VLDO.
4, 30, PAD 1 AGND Analog ground
5 VOUT Switcher output voltage sense pin — also the input to the internal switch-over between VOUT and VLDO.
The voltage at this pin must be less than or equal to the voltage at the V5V pin.
6, 9-11,
PAD 2 VIN Input supply voltage
7 VLDO LDO output — The voltage at this pin must be less than or equal to the voltage at the V5V pin.
8 BST Bootstrap pin — connect a capacitor of at least 100nF from BST to LX to develop the oating supply for the
high-side gate drive.
12 DH High-side gate drive — do not connect this pin
13 LXBST LX Boost — connect to the BST capacitor.
23-25, PAD 3 LX Switching (phase) node
14 DL Low-side gate drive — do not connect this pin
15-22 PGND Power ground
26 PGOOD Open-drain power good indicator — high impedance indicates power is good. An external pull-up
resistor is required.
27 ILIM Current limit sense pin — used to program the current limit by connecting a resistor from ILIM to LX.
28 LXS LX sense — connects to RILIM.
29 EN/PSV
Enable/power-save input for the switching regulator — connect to AGND to disable the switching regulator.
Float to operate in forced continuous mode (power-save disabled). SC417 — connect to V5V to operate with
ultra-sonic power-save mode enabled. SC427 — connect to V5V to operate with power-save mode enabled
with no minimum frequency.
31 TON On-time programming input — set the on-time by connecting through a resistor to AGND
32 ENL Enable input for the LDO — connect ENL to AGND to disable the LDO. Drive with logic to +3V for logic con-
trol, or program the VIN UVLO with a resistor divider between VIN, ENL, and AGND.
SC417/SC427
15
Block Diagram
Reference
Soft Start
FB
AGND
On- time
Generator
Control & Status
PGOOD
Gate Drive
Control
VIN
PGND
TON
VOUT
Zero Cross Detector
Valley Current Limit ILIM
ENL
FBL
VLDO Switchover MUX
A
Y
BLDO
VLDO
BST
FB Comparator
V5V
-
LX
EN/PSV
Bypass ComparatorBypass Comparator
DH
DL
A
12
8
27
14
32
2
7
5
31
1
3 26 29
A = connected to pins 6, 9-11, PAD 2
B = connected to pins 23-25, PAD 3
C = connected to pins 15-22
D = connect to pins 4, 30, PAD 1
B
C
D
V
IN
V5V
V5V
V5V
V
IN
Bootstrap
Switch
Lo-side
MOSFET
Hi-side
MOSFET
LXBST13
LXS28
DL
DL
SC417/SC427
16
Synchronous Buck Converter
The SC417/SC427 is a step down synchronous DC-DC buck
converter with integrated power MOSFETs and a program-
mable LDO. The device is capable of 10A operation at very
high eciency. A space saving 5x5 (mm) 32-pin package
is used. The programmable operating frequency range of
200kHz to 1MHz enables optimizing the conguration for
PCB area and eciency.
The buck controller uses a pseudo-xed frequency adap-
tive on-time control. This control method allows fast tran-
sient response which permits the use of smaller output
capacitors.
In addition to the following information, the user can
click on the applicable link to go to the SC417 online
C-SIM design and simulation tool or to go to the SC427
online C-SIM design and simulation tool, which will
lead the user through the design process.
Input Voltage Requirements
The SC417/SC427 requires two input supplies for normal
operation: VIN and V5V. VIN operates over the wide range
from 3V to 28V. V5V requires a 5V supply input that can be
an external source or the internal LDO configured to
supply 5V from VIN.
Power Up Sequence
When the SC417/SC427 uses an external power source at
the V5V pin, the switching regulator initiates the start-up
process when VIN, V5V, and EN/PSV are above their respec-
tive thresholds. When EN/PSV is at a logic high, V5V needs
to be applied after VIN rises. To start using the EN/PSV pin
when both V5V and VIN are above their respective thresh-
olds, apply EN/PSV to enable the start-up process. For
SC417/SC427 in self-biased mode, refer to the LDO section
for a full description.
Shutdown
The SC417/SC427 can be shutdown by pulling either V5V
or EN/PSV below its threshold. When V5V is active and
EN/PSV at low logic, the output voltage discharges
through an internal FET.
Psuedo-xed Frequency Adaptive On-time Control
The PWM control method used by the SC417/SC427 is
pseudo-xed frequency, adaptive on-time, as shown in
Figure 1. The ripple voltage generated at the output
capacitor ESR is used as a PWM ramp signal. This ripple is
used to trigger the on-time of the controller.
The adaptive on-time is determined by an internal one-
shot timer. When the one-shot is triggered by the output
ripple, the device sends a single on-time pulse to the high-
side MOSFET. The pulse period is determined by VOUT and
VIN; the period is proportional to output voltage and
inversely proportional to input voltage. With this adaptive
on-time arrangement, the device automatically antici-
pates the on-time needed to regulate VOUT for the present
VIN condition and at the selected frequency.
Q1
Q2
L
COUT
ESR
+
CIN
VOUT
FB Threshold
VFB
VLX
VLX
TON
FB
VIN
Figure 1 — PWM Control Method, VOUT Ripple
The advantages of adaptive on-time control are:
Predictable operating frequency compared to
other variable frequency methods.
Reduced component count by eliminating the
error amplier and compensation components.
Reduced component count by removing the
need to sense and control inductor current.
Fast transient response — the response time is
controlled by a fast comparator instead of a typi-
cally slow error amplier.
Reduced output capacitance due to fast tran-
sient response
One-Shot Timer and Operating Frequency
The one-shot timer operates as shown in Figure 2. The FB
Comparator output goes high when VFB is less than the
•
•
•
•
•
Applications Information
SC417/SC427
17
internal 500mV reference. This feeds into the gate drive
and turns on the high-side MOSFET, and also starts the
one-shot timer. The one-shot timer uses an internal com-
parator and a capacitor. One comparator input is con-
nected to VOUT, the other input is connected to the capacitor.
When the on-time begins, the internal capacitor charges
from zero volts through a current which is proportional to
VIN. When the capacitor voltage reaches VOUT, the on-time is
completed and the high-side MOSFET turns o.
Gate
Drives
FB Comparator
One-Shot
Timer
On-time = K x R
TON
x (V
OUT
/V
IN
)
V
OUT
V
IN
FB
500mV Q1
Q2
L
C
OUT
V
IN
ESR
+
V
OUT
V
LX
FB
DH
DL
R
TON
+
-
Figure 2 — On-Time Generation
This method automatically produces an on-time that is
proportional to VOUT and inversely proportional to VIN.
Under steady-state conditions, the switching frequency
can be determined from the on-time by the following
equation.
INON
OUT
SW VT
V
fu
The SC417/SC427 uses an external resistor to set the on-
time which indirectly sets the frequency. The on-time can
be programmed to provide operating frequency from
200kHz to 1MHz using a resistor between the TON pin and
ground. The resistor value is selected by the following
equation.
OUT
INON
TON VpF25
V)ns10T(
Ru
u
The maximum RTON value allowed is shown by the follow-
ing equation.
A15
V
RMIN_IN
MAX_TON P
VOUT Voltage Selection
The switcher output voltage is regulated by comparing
VOUT as seen through a resistor divider at the FB pin (see
Figure 3) to the internal 500mV reference voltage, see the
Detailed Application Circuit.
R
1
V
OUT
To FB pin
R
2
Figure 3 — Output Voltage Selection
Note that this control method regulates the valley of the
output ripple voltage, not the DC value. The DC output
voltage VOUT is oset by the output ripple according to the
following equation.
¸
¹
·
¨
©
§
¸
¸
¹
·
¨
¨
©
§u 2
V
R
R
15.0V RIPPLE
2
1
OUT
When a large capacitor is placed in parallel with R1 (CTOP)
VOUT is shown by the following equation.
2
TOP
12
12
2
TOP1RIPPLE
2
1
OUT
C
RR
RR
1
)CR(1
2
V
R
R
15.0V
¸
¸
¹
·
¨
¨
©
§Z
u
Z
u
¸
¹
·
¨
©
§
¸
¸
¹
·
¨
¨
©
§u
The switcher output voltage can be programmed higher
than 5V. The VOUT pin is not allowed to connect directly
to the switcher output due to its the maximum voltage
rating. An additional resistor divider network is required
to connect from the switcher output to the VOUT pin.
When SC417/SC427 operates in self-biased mode, the
minimum dierence between the voltages for the VOUT
and the VLDO pins should be ±500mV to avoid unwanted
switchover function due to resistor divider voltage drop.
For example, the voltage at the VOUT pin can be 4V if
VLDO is set for 5V. When the SC417/SC427 operates from
an external power source and the LDO is disabled, the
voltage at the VOUT pin can be as high as shown in
Recommended Operating Conditions. RTON is calculated
according to the voltage at the VOUT pin not the voltage
of the switcher output.
Enable and Power-save Input
The EN/PSV input is used to enable or disable the switch-
ing regulator. When EN/PSV is low (grounded), the switch-
ing regulator is o and in its lowest power state. When o,
Applications Information (continued)
SC417/SC427
18
the output of the switching regulator soft-discharges the
output into a 15Ω internal resistor via the VOUT pin. When
EN/PSV is allowed to oat, the pin voltage will oat to 33%
of the voltage at V5V. The switching regulator turns on
with power-save disabled and all switching is in forced
continuous mode.
When EN/PSV is high (above 44% of the voltage at V5V)
for SC417, the switching regulator turns on with ultra-
sonic power-save enabled. The SC417 ultra-sonic power-
save operation maintains a minimum switching frequency
of 25kHz, for applications with stringent audio
requirements.
When EN/PSV is high (above 44% of the voltage at V5V)
for SC427, the switching regulator turns on with power-
save enabled. The SC427 power-save operation is designed
to maximize eciency at light loads with no minimum
frequency limits. This makes the SC427 an excellent choice
for portable and battery-operated systems.
Forced Continuous Mode Operation
The SC417/SC427 operates the switcher in Forced
Continuous Mode (FCM) by oating the EN/PSV pin (see
Figure 4). In this mode one of the power MOSFETs is
always on, with no intentional dead time other than to
avoid cross-conduction. This feature results in uniform
frequency across the full load range with the trade-o
being poor eciency at light loads due to the high-fre-
quency switching of the MOSFETs.
FB Ripple
Voltage (VFB)FB threshold
DL
DH
Inductor
Current
DC Load Current
DH on-time is triggered when
VFB reaches the FB Threshold.
(500mV)
On-time
(TON)
DL drives high when on-time is completed.
DL remains high until VFB falls to the FB threshold.
Figure 4 — Forced Continuous Mode Operation
Ultra-sonic Power-save Operation (SC417)
The SC417 provides ultra-sonic power-save operation at
light loads, with the minimum operating frequency xed
at 25kHz. This is accomplished using an internal timer that
monitors the time between consecutive high-side gate
pulses. If the time exceeds 40µs, DL drives high to turn the
low-side MOSFET on. This draws current from VOUT through
the inductor, forcing both VOUT and VFB to fall. When VFB
drops to the 500mV threshold, the next DH on-time is trig-
gered. After the on-time is completed the high-side
MOSFET is turned o and the low-side MOSFET turns on.
The low-side MOSFET remains on until the inductor
current ramps down to zero, at which point the low-side
MOSFET is turned o.
Because the on-times are forced to occur at intervals no
greater than 40µs, the frequency will not fall below
~25kHz. Figure 5 shows ultra-sonic power-save
operation.
Applications Information (continued)
SC417/SC427
19
FB Ripple
Voltage (V
FB
)
FB threshold
(500mV)
Inductor
Current
DH
DL
(0A)
40µs time-out
minimum f
SW
~ 25kHz
After the 40µsec time-out, DL drives high if V
FB
has not reached the FB threshold.
DH On-time is triggered when
V
FB
reaches the FB Threshold
On-time
(T
ON
)
Figure 5 — Ultrasonic Power-save Operation
Power-save Mode Operation (SC427)
The SC427 provides power-save operation at light loads
with no minimum operating frequency. With power-save
enabled, the internal zero crossing comparator monitors
the inductor current via the voltage across the low-side
MOSFET during the o-time. If the inductor current falls to
zero for 8 consecutive switching cycles, the controller
enters power-save operation. It will turn o the low-side
MOSFET on each subsequent cycle provided that the
current crosses zero. At this time both MOSFETs remain
o until VFB drops to the 500mV threshold. Because the
MOSFETs are o, the load is supplied by the output capaci-
tor. If the inductor current does not reach zero on any
switching cycle, the controller immediately exits power-
save and returns to forced continuous mode. Figure 6
shows power-save operation at light loads.
FB Ripple
Voltage
(V
FB
)FB threshold
DL
DH
Inductor
Current
Zero (0A)
DH On-time is triggered when
V
FB
reaches the FB Threshold.
(500mV)
On-time (T
ON
)
DL drives high when on-time is completed.
DL remains high until inductor current reaches zero.
Dead time varies
according to load
Figure 6 — Power-save Operation
Smart Power-save Protection
Active loads may leak current from a higher voltage into
the switcher output. Under light load conditions with
power-save enabled, this can force VOUT to slowly rise and
reach the over-voltage threshold, resulting in a hard shut-
down. Smart power-save prevents this condition. When
the FB voltage exceeds 10% above nominal (exceeds
550mV), the device immediately disables power-save, and
DL drives high to turn on the low-side MOSFET. This draws
current from VOUT through the inductor and causes VOUT to
fall. When VFB drops back to the 500mV trip point, a normal
TON switching cycle begins. This method prevents a hard
OVP shutdown and also cycles energy from VOUT back to
VIN. It also minimizes operating power by avoiding forced
conduction mode operation. Figure 7 shows typical wave-
forms for the Smart Power-save feature.
SmartDriveTM
For each DH pulse the DH driver initially turns on the high-
side MOSFET at a lower speed, allowing a softer, smooth
turn-o of the low-side diode. Once the diode is o and
the LX voltage has risen 0.5V above PGND, the SmartDrive
circuit automatically drives the high-side MOSFET on at a
rapid rate. This technique reduces switching while main-
taining high eciency and also avoids the need for snub-
bers or series resistors in the gate drive.
Applications Information (continued)
SC417/SC427
20
FB
threshold
High-side
Drive (DH)
Low-side
Drive (DL)
V
OUT
drifts up to due to leakage
current flowing into C
OUT
DH and DL off
DL turns on when Smart
PSAVE threshold is reached
Smart Power Save
Threshold (550mV)
DL turns off when FB
threshold is reached
Single DH on-time pulse
after DL turn-off
V
OUT
discharges via inductor
and low-side MOSFET
Normal DL pulse after DH
on-time pulse
Normal V
OUT
ripple
Figure 7 — Smart Power-save
Current Limit Protection
The device features programmable current limiting, which
is accomplished by using the RDSON of the lower MOSFET
for current sensing. The current limit is set by RILIM resistor.
The RILIM resistor connects from the ILIM pin to the LX pin
which is also the drain of the low-side MOSFET. When the
low-side MOSFET is on, an internal ~10μA current flows
from the ILIM pin and through the RILIM resistor, creating a
voltage drop across the resistor. While the low-side MOSFET
is on, the inductor current ows through it and creates a
voltage across the RDSON. The voltage across the MOSFET is
negative with respect to ground. If this MOSFET voltage
drop exceeds the voltage across RILIM, the voltage at the ILIM
pin will be negative and current limit will activate. The
current limit then keeps the low-side MOSFET on and will
not allow another high-side on-time, until the current in the
low-side MOSFET reduces enough to bring the ILIM voltage
back up to zero. This method regulates the inductor valley
current at the level shown by ILIM in Figure 8.
Time
IPEAK
ILOAD
ILIM
Inductor Current
Figure 8 — Valley Current Limit
Setting the valley current limit to 10A results in a peak
inductor current of 10A plus peak ripple current. In this
situation, the average (load) current through the inductor
is 10A plus one-half the peak-to-peak ripple current.
The internal 10μA current source is temperature compen-
sated at 4100ppm in order to provide tracking with the
RDSON.
The RILIM value is calculated by the following equation.
RILIM = 735 x ILIM
When selecting a value for RILIM be sure not to exceed the
absolute maximum voltage value for the ILIM pin. Note
that because the low-side MOSFET with low RDSON is used
for current sensing, the PCB layout, solder connections,
and PCB connection to the LX node must be done care-
fully to obtain good results. RILIM should be connected
directly to LXS (pin 28).
Soft-Start of PWM Regulator
Soft-start is achieved in the PWM regulator by using an
internal voltage ramp as the reference for the FB
Comparator. The voltage ramp is generated using an
internal charge pump which drives the reference from
zero to 500mV in ~1.2mV increments, using an internal
~500kHz oscillator. When the ramp voltage reaches
500mV, the ramp is ignored and the FB comparator
switches over to a xed 500mV threshold. During soft-start
the output voltage tracks the internal ramp, which limits
the start-up inrush current and provides a controlled soft-
start prole for a wide range of applications. Typical soft-
start ramp time is 850μs.
Pre-Bias Startup
SC417/427 can start up into a pre-biased output voltage.
The start up time is approximately 850μs from enable to
regulation. The output voltage starts to ramp up when
the internal ramp meets the pre-charged FB voltage level.
Pre-bias startup is achieved by turning o the lower gate
when the inductor current falls below zero. This method
prevents output voltage discharge.
Applications Information (continued)
SC417/SC427
21
Power Good Output
The power good (PGOOD) output is an open-drain output
which requires a pull-up resistor. When the output voltage
is 10% below the nominal voltage, PGOOD is pulled low. It
is held low until the output voltage returns above -8% of
nominal. PGOOD is held low during start-up and will not
be allowed to transition high until soft-start is completed
(when VFB reaches 500mV) and typically 2ms has passed.
PGOOD will transition low if the VFB pin exceeds +20% of
nominal, which is also the over-voltage shutdown thresh-
old (600mV). PGOOD also pulls low if the EN/PSV pin is
low when V5V is present.
Output Over-Voltage Protection
Over-voltage protection becomes active as soon as the
device is enabled. The threshold is set at 500mV + 20%
(600mV). When VFB exceeds the OVP threshold, DL latches
high and the low-side MOSFET is turned on. DL remains
high and the controller remains o, until the EN/PSV input
is toggled or V5V is cycled. There is a 5μs delay built into
the OVP detector to prevent false transitions. PGOOD is
also low after an OVP event.
Output Under-Voltage Protection
When VFB falls 25% below its nominal voltage (falls to
375mV) for eight consecutive clock cycles, the switcher is
shut o and the DH and DL drives are pulled low to tri-
state the MOSFETs. The controller stays o until EN/PSV is
toggled or V5V is cycled.
V5V UVLO, and POR
Under-Voltage Lock-Out (UVLO) circuitry inhibits switching
and tri-states the DH/DL drivers until V5V rises above 3.9V.
An internal Power-On Reset (POR) occurs when V5V exceeds
3.9V, which resets the fault latch and soft-start counter to
prepare for soft-start. The SC417/SC427 then begins a soft-
start cycle. The PWM will shut o if V5V falls below 3.6V.
LDO Regulator
The LDO output is programmable from 0.75V to 5.25V
using external resistors. The feedback pin (FBL) for the
LDO is regulated to 750mV. There is also an enable pin
(ENL) for the LDO that provides independent control. The
LDO voltage can also be used to provide the bias voltage
for the switching regulator. When a separate source is
used as the bias supply, the LDO can be programmed to
provide a dierent voltage (see Figure 9).
VLDO To FBL pin
R
LDO2
R
LDO1
Figure 9 — LDO Start-Up
The LDO output voltage is set by the following equation.
¸
¸
¹
·
¨
¨
©
§u
2LDO
1LDO
R
R
1mV750VLDO
A minimum capacitance of 1μF referenced to AGND is
normally required at the output of the LDO for stability. If
the LDO is providing bias power to the device, then a
minimum 0.1μF capacitor referenced to AGND is required
along with a minimum 1.0μF capacitor referenced to
PGND to lter the gate drive pulses. Refer to the layout
guidelines section.
LDO ENL Functions
The ENL input is used to enable/disable the internal LDO.
When ENL is a logic low, the LDO is o. When ENL is a high
but below the VIN UVLO threshold (2.6V typical), then the
LDO is on and the switcher is o. When ENL is above the VIN
UVLO threshold, the LDO is enabled and the switcher is also
enabled if the EN/PSV pin is not grounded. The table below
summarizes the function of ENL and EN/PSV pins.
EN/PSV ENL LDO Switcher
Disabled Low, < 0.4V OFF OFF
Enabled Low, < 0.4V OFF ON
Disabled 1.0V < High < 2.6V ON OFF
Enabled 1.0V < High < 2.6V ON OFF
Disabled High, > 2.6V ON OFF
Enabled High, > 2.6V ON ON
The ENL pin also acts as the switcher under-voltage lockout
for the VIN supply. When SC417/SC427 is self-biased from
the LDO and runs from the VIN power source only, the VIN
UVLO feature can be used to prevent false UV faults for the
PWM output by programming with a resistor divider at the
VIN, ENL and AGND pins. When SC417/SC427 has an exter-
Applications Information (continued)
SC417/SC427
22
nal bias voltage at V5V and the ENL pin is used to program
the VIN UVLO feature, the voltage at FBL needs to be higher
than 750mV to force the LDO o.
Timing is important when driving ENL with logic and not
implementing VIN UVLO. The ENL pin must transition from
high to low within 2 switching cycles to avoid the PWM
output turning off. If ENL goes below the VIN UVLO
threshold and stays above 1V, then the switcher will turn
o but the LDO will remain on.
Additional protection logic is included in the SC417/SC427
to allow for maximum exibility of the IC and controlled
starting in self-biased mode. In self-biased mode where the
LDO and PWM are started at the same time, the PWM
output will not start until the LDO reaches 90% of it’s nal
value. This prevents overloading the current limited LDO
output during LDO start up. When using the LDO as an
independent output, it is desirable to be able to turn the
LDO on and o independent of the PWM output. This is
accomplished by checking the PWM PGOOD output during
start-up. If PGOOD is high when the LDO turns on then the
two outputs are assumed to be independent and the LDO
start-up will not eect the PWM. If the PGOOD output is
low then the part is assumed to be in self-biased mode and
the PWM turn-on is delayed until the LDO start-up is 90%
complete.
LDO Start-up
Before start-up, the LDO checks the status of the following
signals to ensure proper operation can be maintained.
ENL pin
VLDO output
VIN input voltage
When the ENL pin is high and VIN is above the UVLO point,
the LDO will begin start-up. During the initial phase, when
the LDO output voltage is near zero, the LDO initiates a
current-limited start-up (typically 85mA) to charge the output
capacitor. When VLDO has reached 90% of the nal value (as
sensed at the FBL pin), the LDO current limit is increased to
~200mA and the LDO output is quickly driven to the nominal
value by the internal LDO regulator (see Figure 10).
1.
2.
3.
V
VLDO
Final
90% of V
VLDO
Final
Constant current startup
Voltage regulating with
~200mA current limit
Figure 10 — LDO Start-Up
LDO Switch-Over Operation
The SC417/SC427 includes a switch-over function for the
LDO. The switch-over function is designed to increase
eciency by using the more ecient DC-DC converter to
power the LDO output, avoiding the less efficient LDO
regulator when possible. The switch-over function con-
nects the VLDO pin directly to the VOUT pin using an
internal switch. When the switch-over is complete the
LDO is turned o, which results in a power savings and
maximizes eciency. If the LDO output is used to bias the
SC417/SC427, then after switch-over the device is self-
powered from the switching regulator with the LDO
turned o.
The switch-over logic waits for 32 switching cycles before
it starts the switch-over. There are two methods that
determine the switch-over of VLDO to VOUT.
In the rst method, the LDO is already in regulation and
the DC-DC converter is later enabled. As soon as the
PGOOD output goes high, the 32 cycles are started. The
voltages at the VLDO and VOUT pins are then compared;
if the two voltages are within ±300mV of each other, the
VLDO pin connects to the VOUT pin using an internal
switch, and the LDO is turned o.
In the second method, the DC-DC converter is already
running and the LDO is enabled. In this case the 32 cycles
are started as soon as the LDO reaches 90% of its nal
value. At this time, the VLDO and VOUT pins are compared,
and if within ±300mV the switch-over occurs and the LDO
is turned o.
Switch-over Limitations on VOUT and VLDO
Because the internal switch-over circuit always compares
the VOUT and VLDO pins at start-up, there are limitations
on permissible combinations of these pins. Consider the
case where VOUT is programmed to 3.0V and VLDO is pro-
Applications Information (continued)
SC417/SC427
23
Applications Information (continued)
grammed to 3.3V. After start-up, the device would connect
VOUT to VLDO and disable the LDO, since the two volt-
ages are within the ±300mV switch-over window. To avoid
unwanted switch-over, the minimum dierence between
the voltages for VOUT and VLDO should be ±500mV.
It is not recommended to use the switch-over feature for
an output voltage less than 3V since this does not provide
sucient voltage for the gate-source drive to the internal
p-channel switch-over MOSFET.
Switch-over MOSFET Parasitic Diodes
The switch-over MOSFET contains parasitic diodes that
are inherent to its construction, as shown in Figure 11.
Switchover
MOSFET
Parasitic diode Parasitic diode
V5V
V
LDO
V
OUT
Switchover
control
Figure 11— Switch-over MOSFET Parasitic Diodes
There are some important design rules that must be fol-
lowed to prevent forward bias of these diodes. The fol-
lowing two conditions need to be satised in order for the
parasitic diodes to stay o.
V5V ≥ VLDO
V5V ≥ VOUT
If either VLDO or VOUT is higher than V5V, then the respective
diode will turn on and the SC417/SC427 operating current
will flow through this diode. This has the potential of
damaging the device.
Using the On-chip LDO to Bias the SC417/SC427
The following steps must be followed when using the on-
chip LDO to bias the device.
Connect V5V to VLDO before enabling the LDO.
The LDO has an initial current limit of 85mA at
start-up, therefore, do not connect any external
load to VLDO during start-up.
•
•
•
•
When VLDO reaches 90% of its nal value, the
LDO current limit increases to 200mA. At this
time the LDO may be used to supply the required
bias current to the device.
Attempting to operate in self-powered mode in any other
conguration can cause unpredictable results and may
damage the device.
Design Procedure
When designing a switch mode supply the input voltage
range, load current, switching frequency, and inductor
ripple current must be specied.
The maximum input voltage (VINMAX) is the highest speci-
ed input voltage. The minimum input voltage ( VINMIN) is
determined by the lowest input voltage after evaluating
the voltage drops due to connectors, fuses, switches, and
PCB traces.
The following parameters dene the design.
Nominal output voltage (VOUT)
Static or DC output tolerance
Transient response
Maximum load current (IOUT)
There are two values of load current to evaluate — con-
tinuous load current and peak load current. Continuous
load current relates to thermal stresses which drive the
selection of the inductor and input capacitors. Peak load
current determines instantaneous component stresses and
ltering requirements such as inductor saturation, output
capacitors, and design of the current limit circuit.
The following values are used in this design.
VIN = 12V + 10%
VOUT = 1.05V + 4%
fSW = 250kHz
Load = 10A maximum
Frequency Selection
Selection of the switching frequency requires making a
trade-o between the size and cost of the external lter
components (inductor and output capacitor) and the
power conversion eciency.
•
•
•
•
•
•
•
•
•
SC417/SC427
24
Applications Information (continued)
The desired switching frequency is 250kHz which results
from using components selected for optimum size and
cost.
A resistor (RTON) is used to program the on-time (indirectly
setting the frequency) using the following equation.
OUT
INON
TON VpF25
V)ns10T(
Ru
u
To select RTON, use the maximum value for VIN, and for TON
use the value associated with maximum VIN.
SWINMAX
OUT
ON fV
V
Tu
TON = 318 ns at 13.2VIN, 1.05VOUT, 250kHz
Substituting for RTON results in the following solution.
RTON = 154.9kΩ, use RTON = 154kΩ
Inductor Selection
In order to determine the inductance, the ripple current
must rst be dened. Low inductor values result in smaller
size but create higher ripple current which can reduce
eciency. Higher inductor values will reduce the ripple
current/voltage and for a given DC resistance are more
ecient. However, larger inductance translates directly
into larger packages and higher cost. Cost, size, output
ripple, and eciency are all used in the selection process.
The ripple current will also set the boundary for power-
save operation. The switching will typically enter power-
save mode when the load current decreases to 1/2 of the
ripple current. For example, if ripple current is 4A then
Power-save operation will typically start for loads less than
2A. If ripple current is set at 40% of maximum load current,
then power-save will start for loads less than 20% of
maximum current.
The inductor value is typically selected to provide a ripple
current that is between 25% to 50% of the maximum load
current. This provides an optimal trade-o between cost,
eciency, and transient performance.
During the DH on-time, voltage across the inductor is
(VIN - VOUT). The equation for determining inductance is
shown next.
RIPPLE
ONOUTIN
I
T)VV(
Lu
Example
In this example, the inductor ripple current is set equal to
50% of the maximum load current. Therefore ripple
current will be 50% x 10A or 5A. To nd the minimum
inductance needed, use the VIN and TON values that corre-
spond to VINMAX.
H77.0
A5
ns318)05.12.13(
LP
u
A slightly larger value of 0.88µH is selected. This will
decrease the maximum IRIPPLE to 4.4A.
Note that the inductor must be rated for the maximum DC
load current plus 1/2 of the ripple current.
The ripple current under minimum VIN conditions is also
checked using the following equations.
ns384ns10
V
VRpF25
T
INMIN
OUTTON
VINMIN_ON
uu
L
T)VV(
IONOUTIN
RIPPLE
u
A25.4
H088
ns384)05.18.10(
IVINMIN_RIPPLE
P
u
Output Capacitor Selection
The output capacitors are chosen based on required ESR
and capacitance. The maximum ESR requirement is con-
trolled by the output ripple requirement and the DC toler-
ance. The output voltage has a DC value that is equal to
the valley of the output ripple plus 1/2 of the peak-to-peak
ripple. Change in the output ripple voltage will lead to a
change in DC voltage at the output.
The design goal is that the output voltage regulation be
±4% under static conditions. The internal 500mV refer-
ence tolerance is 1%. Allowing 1% tolerance from the FB
resistor divider, this allows 2% tolerance due to VOUT ripple.
SC417/SC427
25
Applications Information (continued)
Since this 2% error comes from 1/2 of the ripple voltage,
the allowable ripple is 4%, or 42mV for a 1.05V output.
The maximum ripple current of 4.4A creates a ripple
voltage across the ESR. The maximum ESR value allowed
is shown by the following equations.
A4.4
mV42
I
V
ESR
RIPPLEMAX
RIPPLE
MAX
ESRMAX = 9.5 mΩ
The output capacitance is usually chosen to meet tran-
sient requirements. A worst-case load release, from
maximum load to no load at the exact moment when
inductor current is at the peak, determines the required
capacitance. If the load release is instantaneous (load
changes from maximum to zero in < 1µs), the output
capacitor must absorb all the inductor’s stored energy.
This will cause a peak voltage on the capacitor according
to the following equation.
2
OUT
2
PEAK
2
RIPPLEMAXOUT
MIN
VV
I
2
1
IL
COUT
¸
¹
·
¨
©
§u
Assuming a peak voltage VPEAK of 1.150 (100mV rise upon
load release), and a 10A load release, the required capaci-
tance is shown by the next equation.
22
2
MIN
05.115.1
4.4
2
1
10H88.0
COUT
¸
¹
·
¨
©
§uP
COUTMIN = 595µF
If the load release is relatively slow, the output capacitance
can be reduced. At heavy loads during normal switching,
when the FB pin is above the 500mV reference, the DL
output is high and the low-side MOSFET is on. During this
time, the voltage across the inductor is approximately
-VOUT. This causes a down-slope or falling di/dt in the
inductor. If the load di/dt is not much faster than the
-di/dt in the inductor, then the inductor current will tend
to track the falling load current. This will reduce the excess
inductive energy that must be absorbed by the output
capacitor, therefore a smaller capacitance can be used.
The following can be used to calculate the needed capaci-
tance for a given dILOAD/dt.
Peak inductor current is shown by the next equation.
ILPK = IMAX + 1/2 x IRIPPLEMAX
ILPK = 10 + 1/2 x 4.4 = 12.2A
dt
dl
CurrentLoadofchangeofRate LOAD
IMAX = maximum load release = 10A
OUTPK
LOAD
MAX
OUT
LPK
LPKOUT VV2
dt
dl
I
V
I
L
IC
uu
u
Example
s
A5.2
dt
dlLOAD
P
This would cause the output current to move from 10A to
0A in 4µs, giving the minimum output capacitance
requirement shown in the following equation.
05.115.12
s1
5.2
10
05.1
2.12
H88.0
2.12COUT
PuuP
u
COUT = 379 µF
Note that COUT is much smaller in this example, 379µF
compared to 595µF based on a worst-case load release. To
meet the two design criteria of minimum 379µF and
maximum 9mΩ ESR, select two capacitors rated at 220µF
and 15mΩ ESR.
It is recommended that an additional small capacitor be
placed in parallel with COUT in order to lter high frequency
switching noise.
Stability Considerations
Unstable operation is possible with adaptive on-time con-
trollers, and usually takes the form of double-pulsing or
ESR loop instability.
SC417/SC427
26
Applications Information (continued)
Double-pulsing occurs due to switching noise seen at the
FB input or because the FB ripple voltage is too low. This
causes the FB comparator to trigger prematurely after the
250ns minimum o-time has expired. In extreme cases
the noise can cause three or more successive on-times.
Double-pulsing will result in higher ripple voltage at the
output, but in most applications it will not aect opera-
tion. This form of instability can usually be avoided by
providing the FB pin with a smooth, clean ripple signal
that is at least 10mVp-p, which may dictate the need to
increase the ESR of the output capacitors. It is also impera-
tive to provide a proper PCB layout as discussed in the
Layout Guidelines section.
Another way to eliminate doubling-pulsing is to add a
small (~ 10pF) capacitor across the upper feedback resis-
tor, as shown in Figure 13. This capacitor should be left
unpopulated until it can be conrmed that double-pulsing
exists. Adding the CTOP capacitor will couple more ripple
into FB to help eliminate the problem. An optional con-
nection on the PCB should be available for this capacitor.
VOUT To FB pin
R2
R1
CTOP
Figure 13 — Capacitor Coupling to FB Pin
ESR loop instability is caused by insufficient ESR. The
details of this stability issue are discussed in the ESR
Requirements section. The best method for checking sta-
bility is to apply a zero-to-full load transient and observe
the output voltage ripple envelope for overshoot and
ringing. Ringing for more than one cycle after the initial
step is an indication that the ESR should be increased.
One simple way to solve this problem is to add trace resis-
tance in the high current output path. A side eect of
adding trace resistance is a decrease in load regulation.
ESR Requirements
A minimum ESR is required for two reasons. One reason is
to generate enough output ripple voltage to provide
10mVp-p at the FB pin (after the resistor divider) to avoid
double-pulsing.
The second reason is to prevent instability due to insu-
cient ESR. The on-time control regulates the valley of the
output ripple voltage. This ripple voltage is the sum of the
two voltages. One is the ripple generated by the ESR, the
other is the ripple due to capacitive charging and dis-
charging during the switching cycle. For most applica-
tions the minimum ESR ripple voltage is dominated by the
output capacitors, typically SP or POSCAP devices. For
stability the ESR zero of the output capacitor should be
lower than approximately one-third the switching fre-
quency. The formula for minimum ESR is shown by the
following equation.
swOUT
MIN fC2
3
SRE uuSu
Using Ceramic Output Capacitors
For applications using ceramic output capacitors, the ESR
is normally too small to meet the above ESR criteria. In
these applications it is necessary to add a small virtual ESR
network composed of two capacitors and one resistor, as
shown in Figure 14. This network creates a ramp voltage
across CL, analogous to the ramp voltage generated across
the ESR of a standard capacitor. This ramp is then capaci-
tively coupled into the FB pin via capacitor CC.
R1
R2
FB
pin
C
C
C
OUT
L
Low-
side
High-
side C
L
R
L
Figure 14 — Virtual ESR Ramp Current
SC417/SC427
27
Applications Information (continued)
The component values used in this circuit are calculated
using the following procedure.
Select CL (100nF) and RL to provide a 25mV ripple across
CL (VCL).
CL
OUTIN
LI
VV
R
where
ON
CLL
CL T
VC
I'u
and
SWIN
OUT
ON fV
V
Tu
Next choose a value for CC so that
EQ
ON
CR
T
C
where
21
21
EQ RR
RR
R
u
The resistor values (R1 and R2) in the voltage divider circuit
set the VOUT for the switcher.
Choosing Input Capacitors
Input capacitors bank is used to provide AC current to the
power stage when the high side FET turns on and espe-
cially during the output current step up. The ripple current
rating of the input capacitors must meet or exceed IRMS
ripple caused by the switching currents. The ripple current
generated is calculated using the following equation.
IN
OUTINOUT
OUTRMS V
)VV(V
II u
u
A83.2
12V
)V1.05V12(V1.05
A10IRMS
u
u
Because of their low ESR and ESL, ceramic capacitors are
typically used. High quality dielectric capacitors should
be used (for example X5R or X7R). The eective capaci-
tance of ceramic capacitors varies under DC bias and tem-
perature. Another factor of selecting the input capacitors
is its voltage rating which needs to be higher than the
maximum input voltage because the ringing on the LX
node. While a single capacitor is sucient to handle the
ripple current, additional ceramic capacitors or bulk
capacitors may be needed to provide local energy storage
and a low impedance input source to account for any PCB
or input connector impedances.
Dropout Performance
The output voltage adjust range for continuous-conduc-
tion operation is limited by the fixed 250ns (typical)
minimum o-time of the one-shot. When working with
low input voltages, the duty-factor limit must be calcu-
lated using worst-case values for on and o times.
The duty-factor limitation is shown by the next equation.
)MAX(OFF)MIN(ON
)MIN(ON
TT
T
DUTY
The inductor resistance and MOSFET on-state voltage
drops must be included when performing worst-case
dropout duty-factor calculations.
System DC Accuracy (VOUT Controller)
Three factors aect VOUT accuracy: the trip point of the FB
error comparator, the ripple voltage variation with line
and load, and the external resistor tolerance. The error
comparator oset is trimmed so that under static condi-
tions it trips when the feedback pin is 500mV, 1%.
The on-time pulse from the SC417/SC427 in the design
example is calculated to give a pseudo-xed frequency of
250kHz. Some frequency variation with line and load is
expected. This variation changes the output ripple
voltage. Because constant on-time converters regulate to
the valley of the output ripple, ½ of the output ripple
appears as a DC regulation error. For example, if the
output ripple is 50mV with VIN = 6 volts, then the measured
DC output will be 25mV above the comparator trip point.
If the ripple increases to 80mV with VIN = 25V, then the
measured DC output will be 40mV above the comparator
trip. The best way to minimize this eect is to minimize
the output ripple.
SC417/SC427
28
Applications Information (continued)
To compensate for valley regulation, it may be desirable to
use passive droop. Take the feedback directly from the
output side of the inductor and place a small amount of
trace resistance between the inductor and output capaci-
tor. This trace resistance should be optimized so that at
full load the output droops to near the lower regulation
limit. Passive droop minimizes the required output capaci-
tance because the voltage excursions due to load steps
are reduced as seen at the load.
The use of 1% feedback resistors may result in up to 1%
error. If tighter DC accuracy is required, 0.1% resistors
should be used.
The output inductor value may change with current. This
will change the output ripple and therefore will have a
minor eect on the DC output voltage. The output ESR
also aects the output ripple and thus has a minor eect
on the DC output voltage.
Switching Frequency Variations
The switching frequency will vary depending on line and
load conditions. The line variations are a result of xed
propagation delays in the on-time one-shot, as well as
unavoidable delays in the external MOSFET switching. As
VIN increases, these factors make the actual DH on-time
slightly longer than the ideal on-time. The net eect is
that frequency tends to falls slightly with increasing input
voltage.
The switching frequency also varies with load current as a
result of the power losses in the MOSFETs and the induc-
tor. For a conventional PWM constant-frequency con-
verter, as load increases the duty cycle also increases
slightly to compensate for IR and switching losses in the
MOSFETs and inductor. A constant on-time converter
must also compensate for the same losses by increasing
the effective duty cycle (more time is spent drawing
energy from VIN as losses increase). The on-time is essen-
tially constant for a given VOUT/VIN combination, to oset
the losses the o-time will tend to reduce slightly as load
increases. The net effect is that switching frequency
increases slightly with increasing load.
SC417/SC427
29
PCB Layout Guidelines
The optimum layout for the SC417/SC427 is shown in
Figure 15. This layout shows an integrated FET buck regu-
lator with a maximum current of 10A. The total PCB area is
approximately 20 x 25 mm.
Critical Layout Guidelines
The following critical layout guidelines must be followed
to ensure proper performance of the device.
IC Decoupling capacitors
PGND plane
AGND island
FB, VOUT, and other analog control signals
BST, ILIM, and LX
CIN and COUT placement and Current Loops
IC Decoupling Capacitors
A 0.1 μF capacitor must be located as close as
possible to the IC and directly connected to pins
3 (V5V) and 4 (AGND).
All other decoupling capacitors must be located
as close as possible to the IC.
•
•
•
•
•
•
•
•
PGND Plane
PGND requires its own copper plane with no
other signal traces routed on it.
Copper planes, multiple vias and wide traces are
needed to connect PGND to input capacitors,
output capacitors, and the PGND pins on the IC.
The PGND copper area between the input
capacitors, output capacitors and PGND pins
must be as tight and compact as possible to
reduce the area of the PCB that is exposed to
noise due to current ow on this node.
Connect PGND to AGND with a short trace or
0Ω resistor. This connection should be as close
to the IC as possible.
AGND Island
AGND should have its own island of copper with
no other signal traces routed on this layer that
connects the AGND pins and pad of the IC to the
analog control components.
All of the components for the analog control cir-
cuitry should be located so that the connections
•
•
•
•
•
•
Applications Information (continued)
VOUT Plane
on Top layer
L
CLDO
C
IN
CFF
RFB2RFB1
RILIM
CBST
RLDO2 RLDO1
LX plane on inner
or bottom layer
All components
shown Top Side
AGND plane on
inner layer
VIN plane on inner
or bottom layer
RGND — AGND connects to
PGND close to SC417/SC427
Pin 1 marking
SC417/SC427
with vias for LX,
AGND, VIN
C
OUT
PGND on inner
or bottom layer
PGND
PGND on
Top Layer
V5V Decoupling Capacitor
CV5V
Figure 15 — PCB Layout
SC417/SC427
30
Applications Information (continued)
to AGND are done by wide copper traces or vias
down to AGND.
Connect PGND to AGND with a short trace or 0Ω
resistor. This connection should be as close to
the IC as possible.
FB, VOUT, and Other Analog Control Signals
The connection from the VOUT power to the
analog control circuitry must be routed from the
output capacitors and located on a quiet layer.
The traces between Vout and the analog control
circuitry (VOUT, and FB pins) must be short and
routed away from noise sources, such as BST, LX,
VIN, and PGND between the input capacitors,
output capacitors, and the IC.
ILIM and TON nodes must be as short as possible
to ensure the best accuracy in current limit and
on time.
RILIM should be close to the IC and connected to
LX with a Kelvin trace to pin 28 on the IC. All of
the LX pins are connected to the LX PAD on the
IC, which should be a sucient connection and
will prevent the need to connect the resistor
further into the LX plane.
The feedback components for the switcher and
the LDO need to be as close to the FB and FBL
pins of the IC as possible to reduce the possibil-
ity of noise corrupting these analog signals.
•
•
•
•
•
•
BST, ILIM and LX
LX and BST are very noisy nodes and must be
routed to minimized the PCB area that is exposed
to these signals.
The connections for the boost capacitor
between the IC and LX must be short and directly
connected to the LXBST (pin 13).
The connections for the current limit resistor
between the ILIM pin and LX must be as short as
possible and directly connected to pin 28 (LXS).
The LX node between the IC and the inductor
should be wide enough to handle the inductor
current and short enough to eliminate the pos-
sibility of LX noise corrupting other signals.
Multiple vias should be used to provide a good
connection to LX between the IC and the
inductor.
Capacitors and Current Loops
The current loops between the input capacitors,
the IC, the inductor, and the output capacitors
must be as close as possible to each other to
reduce IR drop across the copper.
All bypass and output capacitors must be con-
nected as close as possible to the pin on the IC.
•
•
•
•
•
•
•
SC417/SC427
31
Outline Drawing — MLPQ-5x5-32
B
aaa C
C
SEATING
PLANE
1
2
N
bbb CAB
COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
NOTES:
2.
1.
A
PIN 1
INDICATOR
(LASER MARK)
D
E
A2
bxN
A
A1
e
LxN
E1
0.76
0.76
3.48
1.05
D1
1.66
1.49
PIN 1
IDENTIFICATION
R0.20
3.61
MILLIMETERS
0.50 BSC
.002
-0.00.000
A1
.193
.193
.135
.076
.012
.007
E1
aaa
bbb
N
e
L
A2
D1
D
E
b
.020 BSC
.137
.016
.003
.004
32
.197
(.008)
.078
.197
.010
-
3.43
.139
.020 0.30
.201
.201
.080
-
.012
4.90
4.90
1.92
-
0.18
.031
MIN
DIM
A
MAX
DIMENSIONS
INCHES
-
NOM
.039 0.80
MIN
-0.05
5.10
5.10
3.53
2.02
0.50
0.30
3.48
0.40
0.10
0.08
32
5.00
(0.20)
1.97
5.00
0.25
-
1.00
MAX
-
NOM
SC417/SC427
32
Land Pattern — MLPQ-5x5-32
1.74
3.48
H2
K
3.61
H1
K1
Y
H
(C) G
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
NOTES:
2.
DIM
X
Y
H
K
P
C
G
MILLIMETERSINCHES
(4.95)
.012
.030
.165
.020
.078
.137
(.195)
0.30
0.75
3.48
0.50
1.97
4.20
DIMENSIONS
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
5.70
.224
Z
FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR
FUNCTIONAL PERFORMANCE OF THE DEVICE.
SHALL BE CONNECTED TO A SYSTEM GROUND PLANE.
THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD
3.
4. SQUARE PACKAGE-DIMENSIONS APPLY IN BOTH X AND Y DIRECTIONS.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
1.
X
P
Z
H1 .059 1.49
H2 .065 1.66
K1 .041 1.05
1.74
SC417/SC427
33
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