LM46000PWP - NATIONAL SEMICONDUCTOR

EN 55022 Class B Limit

Frequency (MHz)

dBuV

Evaluation Board Emissions

1000100

Vertical Polarization

Horizontal Polarization

SWVIN

PGND

CBOOT

VCC

BIAS

SYNC

ENABLE

SS/TRK

AGND

LM46000

VIN COUT

CBOOT

CIN

CVCC

VOUT

CBIAS RFBT

RFBB

CFF

PGOOD

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM46000

SNVSA45B –JUNE 2014–REVISED MARCH 2018

LM46000 3.5-V to 60-V, 0.5-A Synchronous Step-Down Voltage Converter

1 Features

1• 24-µA Quiescent Current in Regulation

• High Efficiency at Light Load (DCM and PFM)

• Meets EN55022/CISPR 22 EMI standards

• Integrated Synchronous Rectification

• Adjustable Frequency Range: 200 kHz to 2.2 MHz

(500 kHz default)

• Frequency Synchronization to External Clock

• Internal Compensation

• Stable With Almost Any Combination of Ceramic,

Polymer, Tantalum, and Aluminum Capacitors

• Power-Good Flag

• Soft-Start into Prebiased Load

• Internal Soft Start: 4.1 ms

• Extendable Soft-Start Time by External Capacitor

• Output Voltage Tracking Capability

• Precision Enable to Program System UVLO

• Output Short-Circuit Protection With Hiccup Mode

• Overtemperature Thermal Shutdown Protection

• Create a Custom Design Using the LM46000 With

the WEBENCH®Power Designer

2 Applications

• Industrial Power Supplies

• Telecommunications Systems

• Sub-AM Band 12-V and 24-V Automotive

• Commercial Vehicle Power Supplies

• General Purpose Wide VIN Regulation

• High Efficiency Point-Of-Load Regulation

3 Description

The LM46000 regulator is an easy-to-use

synchronous step-down DC-DC converter capable of

driving up to 500 mA of load current from an input

voltage range of 3.5 V to 60 V. The LM46000

provides exceptional efficiency, output accuracy and

dropout voltage in a very small solution size. An

extended family is available in 1 A and 2 A load

current options in pin-to-pin compatible packages.

Peak current mode control is employed to achieve

simple control loop compensation and cycle-by-cycle

current limiting. Optional features such as

programmable switching frequency, synchronization,

power-good flag, precision enable, internal soft start,

extendable soft start, and tracking provide a flexible

and easy-to-use platform for a wide range of

applications. Discontinuous conduction and automatic

frequency modulation at light loads improve light load

efficiency. The family requires few external

components and pin arrangement allows simple,

optimum PCB layout. Protection features include

thermal shutdown, VCC undervoltage lockout, cycle-

by-cycle current limit, and output short-circuit

protection. The LM46000 device is available in the

16-pin leaded HTSSOP (PWP) package (6.6 mm ×

5.1 mm × 1.2 mm) with 0.65-mm lead pitch. Pin-to-

pin compatible with LM46001, LM46002, LM43603,

LM43602, LM43601, and LM43600.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

LM46000 HTSSOP (16) 6.60 mm × 5.10 mm

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

space

Simplified Schematic Radiated Emission Graph

VOUT = 3.3 V, VIN = 24 V, FS= 500 kHz, IOUT = 0.5 A

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings ............................................................ 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 5

6.6 Timing Requirements................................................ 6

6.7 Switching Characteristics.......................................... 7

6.8 Typical Characteristics.............................................. 8

7 Detailed Description............................................ 14

7.1 Overview................................................................. 14

7.2 Functional Block Diagram....................................... 14

7.3 Feature Description................................................. 15

7.4 Device Functional Modes........................................ 23

8 Applications and Implementation ...................... 25

8.1 Application Information............................................ 25

8.2 Typical Applications ................................................ 25

9 Power Supply Recommendations...................... 43

10 Layout................................................................... 43

10.1 Layout Guidelines ................................................. 43

10.2 Layout Example .................................................... 46

11 Device and Documentation Support................. 47

11.1 Device Support...................................................... 47

11.2 Receiving Notification of Documentation Updates 47

11.3 Community Resources.......................................... 47

11.4 Trademarks........................................................... 47

11.5 Electrostatic Discharge Caution............................ 47

11.6 Glossary................................................................ 47

12 Mechanical, Packaging, and Orderable

Information........................................................... 47

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (July 2014) to Revision B Page

• Added links for WEBENCH; bring to latest TI data sheet standard with editorial updates ................................................... 1

• Added TYPE column to Pin Functions .................................................................................................................................. 3

• Changed Handling Ratings to ESD Ratings .......................................................................................................................... 4

Changes from Original (June 2014) to Revision A Page

• Changed device from Product Preview to Production Data .................................................................................................. 1

VIN

PGND

CBOOT

VCC

BIAS

SYNC

PGOOD

SS/TRK

AGND

SW PGND

VIN

PAD

1 16

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(1) P = Power, G = Ground, A = Analog

5 Pin Configuration and Functions

PWP Package

16-Pin HTSSOP

Top View

Pin Functions

PIN TYPE(1) DESCRIPTION

NO. NAME

1,2 SW P Switching output of the regulator. Internally connected to both power MOSFETs. Connect to power

inductor.

3 CBOOT P Boot-strap capacitor connection for high-side driver. Connect a high-quality 470-nF capacitor from

CBOOT to SW.

4 VCC P Internal bias supply output for bypassing. Connect bypass capacitor from this pin to AGND. Do not

connect external load to this pin. Never short this pin to ground during operation.

5 BIAS P Optional internal LDO supply input. To improve efficiency, TI recommends tying this pin to VOUT when

3.3 V ≤VOUT ≤28 V, or tie to an external 3.3 V or 5 V rail if available. When used, place a bypass

capacitor (1 to 10 µF) from this pin to ground. Tie to ground when not in use (VOUT < 3.3 V). Do not

float.

6 SYNC A Clock input to synchronize switching action to an external clock. Use proper high speed termination to

prevent ringing. Connect to ground if not used. Do not float.

7 RT A Connect a resistor RTfrom this pin to AGND to program switching frequency. Leave floating for 500-

kHz default switching frequency.

8 PGOOD A Open-drain output for power-good flag. Use a 10-kΩto 100-kΩpullup resistor to logic rail or other DC

voltage no higher than 12 V.

9 FB A Feedback sense input pin. Connect to the midpoint of feedback divider to set VOUT. Do not short this

pin to ground during operation.

10 AGND G Analog ground pin. Ground reference for internal references and logic. Connect to system ground.

11 SS/TRK A Soft-start control pin. Leave floating for internal soft-start slew rate. Connect to a capacitor to extend

soft-start time. Connect to external voltage ramp for tracking.

12 EN A Enable input to the LM46000: High = ON and low = OFF. Connect to VIN, or to VIN through resistor

divider, or to an external voltage or logic source. Do not float.

13,14 VIN P Supply input pins to internal LDO and high side power FET. Connect to power supply and bypass

capacitors CIN. Path from VIN pin to high frequency bypass CIN and PGND must be as short as

possible.

15,16 PGND G Power ground pins, connected internally to the low side power FET. Connect to system ground, PAD,

AGND, ground pins of CIN and COUT. Path to CIN must be as short as possible.

17 PAD G Low impedance connection to AGND. Connect to PGND on PCB . Major heat dissipation path of the

die. Must be used for heat sinking to ground plane on PCB.

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6 Specifications

6.1 Absolute Maximum Ratings(1)

Over operating free-air temperature range (unless otherwise noted)

PARAMETER MIN MAX UNIT

Input voltages

VIN to PGND –0.3 65

EN to PGND –0.3 VIN + 0.3

FB, RT, SS/TRK to AGND –0.3 3.6

PGOOD to AGND –0.3 15

SYNC to AGND –0.3 5.5

BIAS to AGND –0.3 30

AGND to PGND –0.3 0.3

Output voltages

SW to PGND –0.3 VIN + 0.3

SW to PGND less than 10-ns transients –3.5 65

CBOOT to SW –0.3 5.5

VCC to AGND –0.3 3.6

Storage temperature, Tstg –65 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings VALUE UNIT

V(ESD) Electrostatic

discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V

Charged device model (CDM), per JEDEC specification JESD22-C101, all

pins(2) ±500

(1) Recommended Operating Ratings indicate conditions for which the device is intended to be functional, but do not ensure specific

performance limits. For ensured specifications, see Electrical Characteristics.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)(1)

PARAMETER MIN MAX UNIT

Input voltages

VIN to PGND 3.5 60

EN –0.3 VIN

FB –0.3 1.1

PGOOD –0.3 12

BIAS input not used –0.3 0.3

BIAS input used 3.3 28

AGND to PGND –0.1 0.1

Output voltage VOUT 1 28 V

Output current IOUT 0 0.5 A

Temperature Operating junction temperature range, TJ–40 125 °C

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(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) The package thermal impedance is calculated in accordance with JESD 51-7 standard with a 4-layer board and 1-W power dissipation.

(3) RθJA is highly related to PCB layout and heat sinking. See Figure 101 for measured RθJA vs PCB area from a 2-layer board and a 4-

layer board.

6.4 Thermal Information

THERMAL METRIC(1)(2) LM46000

UNITPWP (HTSSOP)

16 PINS

RθJA Junction-to-ambient thermal resistance 39.9(3) °C/W

RθJC(top) Junction-to-case (top) thermal resistance 26.9 °C/W

RθJB Junction-to-board thermal resistance 21.7 °C/W

ψJT Junction-to-top characterization parameter 0.8 °C/W

ψJB Junction-to-board characterization parameter 21.5 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance 2.3 °C/W

6.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (TJ) range of –40°C to 125°C, unless otherwise stated.

Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most

likely parametric norm at TJ= 25°C, and are provided for reference purposes only. Unless otherwise stated, the following

conditions apply: VIN = 24 V, VOUT = 3.3 V, FS= 500 kHz.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY VOLTAGE (VIN PINS)

VIN-MIN-ST Minimum input voltage for startup 3.8 V

ISHDN Shutdown quiescent current VEN = 0 V 2.3 5 µA

IQ-NONSW Operating quiescent current (non-

switching) from VIN

VEN = 3.3 V

VFB = 1.5 V

VBIAS = 3.4 V external 7 13 µA

IBIAS-NONSW Operating quiescent current (non-

switching) from external VBIAS

VEN = 3.3 V

VFB = 1.5 V

VBIAS = 3.4 V external 85 140 µA

IQ-SW Operating quiescent current (switching)

VEN = 3.3 V

IOUT = 0 A

RT= open

VBIAS = VOUT = 3.3 V

RFBT = 1 Meg

24 µA

ENABLE (EN PIN)

VEN-VCC-H Voltage level to enable the internal LDO

output VCC VENABLE high level 1.2 V

VEN-VCC-L Voltage level to disable the internal LDO

output VCC VENABLE low level 0.4 V

VEN-VOUT-H Precision enable level for switching and

regulator output: VOUT VENABLE high level 2 2.1 2.42 V

VEN-VOUT-HYS Hysteresis voltage between VOUT

precision enable and disable thresholds VENABLE hysteresis –305 mV

ILKG-EN Enable input leakage current VEN = 3.3 V 0.8 1.75 µA

INTERNAL LDO (VCC PIN AND BIAS PIN)

VCC Internal LDO output voltage VCC VIN ≥3.8 V 3.3 V

VCC-UVLO Undervoltage lockout (UVLO) thresholds

for VCC

VCC rising threshold 3.14 V

Hysteresis voltage between rising and

falling thresholds –567 mV

VBIAS-ON Internal LDO input change over

threshold to BIAS

VBIAS rising threshold 2.96 3.2 V

Hysteresis voltage between rising and

falling thresholds –71 mV

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Electrical Characteristics (continued)

Limits apply over the recommended operating junction temperature (TJ) range of –40°C to 125°C, unless otherwise stated.

Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most

likely parametric norm at TJ= 25°C, and are provided for reference purposes only. Unless otherwise stated, the following

conditions apply: VIN = 24 V, VOUT = 3.3 V, FS= 500 kHz.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(1) Ensured by design.

(2) Measured at package pins.

VOLTAGE REFERENCE (FB PIN)

VFB Feedback voltage TJ= 25ºC 1.009 1.016 1.023 VTJ= –40ºC to 85ºC 0.999 1.016 1.031

TJ= –40ºC to 125ºC 0.999 1.016 1.039

ILKG-FB Input leakage current at FB pin FB = 1.016 V 0.2 65 nA

THERMAL SHUTDOWN

TSD (1) Thermal shutdown Shutdown threshold 160 ºC

Recovery threshold 150 ºC

CURRENT LIMIT AND HICCUP

IHS-LIMIT Peak inductor current limit 1.05 1.35 1.56 A

ILS-LIMIT Valley inductor current limit 0.46 0.6 0.75 A

SOFT START (SS/TRK PIN)

ISSC Soft-start charge current 1.17 2.2 2.85 µA

RSSD Soft-start discharge resistance UVLO, TSD, OCP, or EN = 0 V 16 kΩ

POWER GOOD (PGOOD PIN)

VPGOOD-HIGH Power-good flag overvoltage tripping

threshold % of FB voltage 110% 113%

VPGOOD-LOW Power-good flag undervoltage tripping

threshold % of FB voltage 83% 90%

VPGOOD-HYS Power-good flag recovery hysteresis % of FB voltage 6%

RPGOOD PGOOD pin pulldown resistance when

power bad VEN = 3.3 V 40 125 Ω

VEN = 0 V 60 150

MOSFETS(2)

RDS-ON-HS High-side MOSFET ON-resistance IOUT = 0.5 A

VBIAS = VOUT = 3.3 V 419 mΩ

RDS-ON-LS Low-side MOSFET ON-resistance IOUT = 0.5 A

VBIAS = VOUT = 3.3 V 231 mΩ

6.6 Timing Requirements

Typical values represent the most likely parametric norm at TJ= 25°C. MIN NOM MAX UNIT

CURRENT LIMIT AND HICCUP

NOC Hiccup wait cycles when LS current limit tripped 32 Cycles

TOC Hiccup retry delay time 5.5 ms

SOFT START (SS/TRK PIN)

TSS Internal soft-start time when SS pin open circuit 4.1 ms

POWER GOOD (PGOOD PIN)

TPGOOD-RISE Power-good flag rising transition deglitch delay 220 µs

TPGOOD-FALL Power-good flag falling transition deglitch delay 220 µs

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(1) Ensured by design.

6.7 Switching Characteristics

Limits apply over the recommended operating junction temperature (TJ) range of –40°C to 125°C, unless otherwise stated.

Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most

likely parametric norm at TJ= 25°C, and are provided for reference purposes only. Unless otherwise stated, the following

conditions apply: VIN = 24 V, VOUT = 3.3 V, FS= 500 kHz.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SW (SW PIN)

tON-MIN(1) Minimum high side MOSFET ON-

time 125 165 ns

tOFF-MIN(1) Minimum high side MOSFET OFF-

time 200 250 ns

OSCILLATOR (SW PINS AND SYNC PIN)

FOSC-

DEFAULT Oscillator default frequency RT pin open circuit 445 500 570 kHz

FADJ

Minimum adjustable frequency With 1% resistors at RT pin 200 kHz

Maximum adjustable frequency 2200 kHz

Frequency adjust accuracy 10%

VSYNC-HIGH Sync clock high level threshold 2 V

VSYNC-LOW Sync clock low level threshold 0.4 V

DSYNC-MAX Sync clock maximum duty cycle 90%

DSYNC-MIN Sync clock minimum duty cycle 10%

TSYNC-MIN Mininum sync clock ON- and OFF-

time 80 ns

100

0.001 0.01 0.1

Efficiency (%)

Load Current (A)

VIN = 24V

VIN = 28V

VIN = 36V

VIN = 42V

VIN = 48V

VIN = 60V

C007

100

0.001 0.01 0.1

Efficiency (%)

Load Current (A)

VIN = 36V

VIN = 42V

VIN = 48V

VIN = 60V

C008

100

0.001 0.01 0.1

Efficiency (%)

Load Current (A)

VIN = 12V

VIN = 18V

VIN = 24V

VIN = 28V

C005

100

0.001 0.01 0.1

Efficiency (%)

Load Current (A)

VIN = 12V

VIN = 18V

VIN = 24V

VIN = 28V

VIN = 36V

VIN = 42V

C003

100

0.001 0.01 0.1

Efficiency (%)

Load Current (A)

VIN = 8V

VIN = 12V

VIN = 18V

VIN = 24V

VIN = 28V

VIN = 36V

C002

100

0.001 0.01 0.1

Efficiency (%)

Load Current (A)

VIN = 8V

VIN = 12V

VIN = 18V

VIN = 24V

VIN = 28V

VIN = 36V

VIN = 42V

VIN = 48V

VIN = 60V

C004

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6.8 Typical Characteristics

Unless otherwise specified, VIN = 24 V, VOUT = 3.3 V, FS= 500 kHz, L = 27 µH, COUT = 100 µF, CFF = 33 pF. See Application

Performance Curves for Bill of Materials (BOM) for other VOUT and FScombinations.

VOUT = 3.3 V FS= 500 kHz

Figure 1. Efficiency

VOUT = 5 V FS= 200 kHz

Figure 2. Efficiency

VOUT = 5 V FS= 500 kHz

Figure 3. Efficiency

VOUT = 5 V FS= 1 MHz

Figure 4. Efficiency

VOUT = 12 V FS= 500 kHz

Figure 5. Efficiency

VOUT = 24 V FS= 500 kHz

Figure 6. Efficiency

11.5

11.6

11.7

11.8

11.9

12.0

12.1

12.2

12.3

12.4

12.5

0.001 0.01 0.1

Vout (V)

Load Current (A)

VIN = 24V VIN = 28V

VIN = 36V VIN = 42V

VIN = 48V VIN = 60V

C017

23.0

23.2

23.4

23.6

23.8

24.0

24.2

24.4

24.6

24.8

25.0

0.001 0.01 0.1

Vout (V)

Load Current (A)

VIN = 36V

VIN = 42V

VIN = 48V

VIN = 60V

C018

4.80

4.85

4.90

4.95

5.00

5.05

5.10

5.15

5.20

0.001 0.01 0.1

Vout (V)

Load Current (A)

VIN = 12V VIN = 18V

VIN = 24V VIN = 28V

VIN = 36V VIN = 42V

C013

4.80

4.85

4.90

4.95

5.00

5.05

5.10

5.15

5.20

0.001 0.01 0.1

Vout (V)

Load Current (A)

VIN = 12V

VIN = 18V

VIN = 24V

VIN = 28V

C015

3.20

3.22

3.24

3.26

3.28

3.30

3.32

3.34

3.36

3.38

3.40

0.001 0.01 0.1

Vout (V)

Load Current (A)

VIN = 8V VIN = 12V

VIN = 18V VIN = 24V

VIN = 28V VIN = 36V

C012

4.80

4.85

4.90

4.95

5.00

5.05

5.10

5.15

0.001 0.01 0.1

Vout (V)

Load Current (A)

VIN = 8V VIN = 12V VIN = 18V

VIN = 24V VIN = 28V VIN = 36V

VIN = 42V VIN = 48V VIN = 60V

C014

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Typical Characteristics (continued)

Unless otherwise specified, VIN = 24 V, VOUT = 3.3 V, FS= 500 kHz, L = 27 µH, COUT = 100 µF, CFF = 33 pF. See Application

Performance Curves for Bill of Materials (BOM) for other VOUT and FScombinations.

VOUT = 3.3 V FS= 500 kHz

Figure 7. VOUT Regulation

VOUT = 5 V FS= 200 kHz

Figure 8. VOUT Regulation

VOUT = 5 V FS= 500 kHz

Figure 9. VOUT Regulation

VOUT = 5 V FS= 1 MHz

Figure 10. VOUT Regulation

VOUT = 12 V FS= 500 kHz

Figure 11. VOUT Regulation

VOUT = 24 V FS= 500 kHz

Figure 12. VOUT Regulation

11.0

11.2

11.4

11.6

11.8

12.0

12.2

12.4

12.0 12.5 13.0 13.5 14.0

VOUT (V)

VIN (V)

Load = 0.2A

Load = 0.3A

Load = 0.4A

Load = 0.5A

C027

22.0

22.5

23.0

23.5

24.0

24.5

24.0 24.5 25.0 25.5 26.0

VOUT (V)

VIN (V)

Load = 0.2A

Load = 0.3A

Load = 0.4A

Load = 0.5A

C028

4.0

4.2

4.4

4.6

4.8

5.0

5.2

5.0 5.2 5.4 5.6 5.8 6.0

VOUT (V)

VIN (V)

Load = 0.2A

Load = 0.3A

Load = 0.4A

Load = 0.5A

C023

4.0

4.2

4.4

4.6

4.8

5.0

5.2

5.0 5.2 5.4 5.6 5.8 6.0

VOUT (V)

VIN (V)

Load = 0.2A

Load = 0.3A

Load = 0.4A

Load = 0.5A

C025

2.5

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

3.5 3.7 3.9 4.1 4.3 4.5

VOUT (V)

VIN (V)

Load = 0.2A

Load = 0.3A

Load = 0.4A

Load = 0.5A

C022

4.0

4.2

4.4

4.6

4.8

5.0

5.2

5.0 5.2 5.4 5.6 5.8 6.0

VOUT (V)

VIN (V)

Load = 0.2A

Load = 0.3A

Load = 0.4A

Load = 0.5A

C024

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Typical Characteristics (continued)

Unless otherwise specified, VIN = 24 V, VOUT = 3.3 V, FS= 500 kHz, L = 27 µH, COUT = 100 µF, CFF = 33 pF. See Application

Performance Curves for Bill of Materials (BOM) for other VOUT and FScombinations.

VOUT = 3.3 V FS= 500 kHz

Figure 13. Dropout Curve

VOUT = 5 V FS= 200 kHz

Figure 14. Dropout Curve

VOUT = 5 V FS= 500 kHz

Figure 15. Dropout Curve

VOUT = 5 V FS= 1 MHz

Figure 16. Dropout Curve

VOUT = 12 V FS= 500 kHz

Figure 17. Dropout Curve

VOUT = 24 V FS= 500 kHz

Figure 18. Dropout Curve

Quasi Peak Limit

Average Limit

Frequency (MHz)

dBuV

100

0.15 1 10 30

Measured Peak Emissions

Quasi Peak Limit

Average Limit

Frequency (MHz)

dBuV

100

0.15 1 10 30

Measured Peak Emissions

EN 55022 Class B Limit

Frequency (MHz)

dBuV

Evaluation Board Emissions

1000100

Vertical Polarization

Horizontal Polarization

EN 55022 Class B Limit

Frequency (MHz)

dBuV

Evaluation Board Emissions

1000100

Vertical Polarization

Horizontal Polarization

10000

100000

1000000

3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

Frequency (Hz)

VIN (V)

Load = 0.01 A

Load = 0.1 A

Load = 0.5 A

C001

10000

100000

1000000

5.0 5.2 5.4 5.6 5.8 6.0 6.2 6.4 6.6 6.8 7.0

Frequency (Hz)

VIN (V)

Load = 0.01 A

Load = 0.1 A

Load = 0.5 A

C001

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Typical Characteristics (continued)

Unless otherwise specified, VIN = 24 V, VOUT = 3.3 V, FS= 500 kHz, L = 27 µH, COUT = 100 µF, CFF = 33 pF. See Application

Performance Curves for Bill of Materials (BOM) for other VOUT and FScombinations.

VOUT = 3.3 V FS= 500 kHz

Figure 19. Switching Frequency vs VIN in Dropout Operation

VOUT = 5 V FS= 1 MHz

Figure 20. Switching Frequency vs VIN in Dropout Operation

VOUT = 3.3 V FS= 500 kHz IOUT = 0.5 A

Measured on the LM46000PWPEVM with default BOM. No input

filter used.

Figure 21. Radiated EMI Curve

VOUT = 5 V FS= 500 kHz IOUT = 0.5 A

Measured on the LM46000PWPEVM with L = 44 µH, COUT = 66

µF, CFF = 33 pF. No input filter used.

Figure 22. Radiated EMI Curve

VOUT = 3.3 V FS= 500 kHz IOUT = 0.5 A

Measured on the LM46000PWPEVM with default BOM. EVM input

filter: Lin = 1 µH Cd= 47 µF CIN4 = 68 µF

Figure 23. Conducted EMI Curve

VOUT = 5 V FS= 500 kHz IOUT = 0.5 A

Measured on the LM46000PWPEVM with L = 44 µH, COUT = 66

µF, CFF = 33 pF. EVM input filter Lin = 1 µH Cd= 47 µF CIN4 = 68

µF

Figure 24. Conducted EMI Curve

75%

80%

85%

90%

95%

100%

105%

110%

115%

120%

-50 0 50 100 150

PGOOD Threshold / VOUT (%)

Temperature (ƒC)

OVP Trip Level

OVP Recover Level

UVP Recover Level

UVP Trip Level

C001

0.990

0.995

1.000

1.005

1.010

1.015

1.020

1.025

1.030

-50 0 50 100 150

VFB (V)

Temperature (ƒC)

VIN = 12V

VIN = 24V

C001

0.5

1.5

2.5

-50 0 50 100 150

Enable Threshold (V)

Temperature (ƒC)

EN-VOUT Rising TH

EN-VOUT Falling TH

EN-VCC Rising TH

EN-VCC Falling TH

C001

0.2

0.4

0.6

0.8

1.2

1.4

-50 0 50 100 150

EN Leakage Current (A)

Temperature (ƒC)

VEN = 3.3V

C001

100

200

300

400

500

600

700

800

-50 0 50 100 150

Rdson (mohm)

Temperature (ƒC)

C001

0.5

1.5

2.5

3.5

-50 0 50 100 150

Shutdown Current (A)

Temperature (ƒC)

VIN = 12V

VIN = 24V

C001

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Typical Characteristics (continued)

Unless otherwise specified, VIN = 24 V, VOUT = 3.3 V, FS= 500 kHz, L = 27 µH, COUT = 100 µF, CFF = 33 pF. See Application

Performance Curves for Bill of Materials (BOM) for other VOUT and FScombinations.

Figure 25. High-Side and Low-side On-Resistance vs

Junction Temperature Figure 26. Shutdown Current vs Junction Temperature

Figure 27. Enable Threshold vs Junction Temperature Figure 28. Enable Leakage Current vs

Junction Temperature

Figure 29. PGOOD Threshold vs Junction Temperature Figure 30. Feedback Voltage vs Junction Temperature

0 10 20 30 40 50 60

IQ (A)

VIN (V)

C001

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

-50 0 50 100 150

Current (A)

Temperature (ƒC)

IL Peak Limit

IL Valley Limit

C001

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Typical Characteristics (continued)

Unless otherwise specified, VIN = 24 V, VOUT = 3.3 V, FS= 500 kHz, L = 27 µH, COUT = 100 µF, CFF = 33 pF. See Application

Performance Curves for Bill of Materials (BOM) for other VOUT and FScombinations.

VIN = 24 V VOUT = 3.3 V FS= 500 kHz

Figure 31. Peak and Valley Current Limits vs Junction

Temperature

VOUT = 3.3 V FS= 500 kHz IOUT = 0 A

Figure 32. Operating IQvs VIN With BIAS Connected to VOUT

Precision

Enable

VCC

Enable

Slope

Comp

LDO

HICCUP

Detector

PFM

Detector

TSD

Oscillator

PWM CONTROL LOGIC

Freq

Foldback Zero

Cross

UVLO

CBOOT

VIN

BIAS

PGOOD

ENABLE

AGND

PGNDSYNC

VCC

HS I Sense

ISSC

LS I Sense

PGood

SS/TRK

OV/UV

Detector

REF EA

Internal

+±

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7 Detailed Description

7.1 Overview

The LM46000 regulator is an easy-to-use synchronous step-down DC/DC converter that operates from 3.5-V to

60-V supply voltage. The device is capable of delivering up to 0.5-A DC load current with exceptional efficiency

and thermal performance in a very small solution size. An extended family is available in 1-A and 2-A load

options in pin-to-pin compatible packages.

The LM46000 employs fixed-frequency, peak-current-mode control with discontinuous conduction mode (DCM)

and pulse frequency modulation (PFM) mode at light load to achieve high efficiency across the load range. The

device is internally compensated, which reduces design time and requires fewer external components. The

switching frequency is programmable from 200 kHz to 2.2 MHz by an external resistor, RT. The device defaults at

500 kHz without RT. The LM46000 is also capable of synchronization to an external clock within the 200-kHz to

2.2-MHz frequency range. The wide switching frequency range allows the device to be optimized to fit small

board space at higher frequency, or high efficient power conversion at lower frequency.

Optional features are included for more comprehensive system requirements, including power-good (PGOOD)

flag, precision enable, synchronization to external clock, extendable soft-start time, and output voltage tracking.

These features provide a flexible and easy-to-use platform for a wide range of applications. Protection features

include over temperature shutdown, VCC undervoltage lockout (UVLO), cycle-by-cycle current limit, and short-

circuit protection with hiccup mode.

The family requires few external components and the pin arrangement was designed for simple, optimum PCB

layout. The LM46000 device is available in the 16-pin leaded HTSSOP / PWP package (6.6 mm × 5.1 mm × 1.2

mm) with 0.65-mm lead pitch.

7.2 Functional Block Diagram

VIN

-VD1

tON

Inductor Current

D = tON / TSW

VSW

tOFF

TSW

SW Voltage

ûiL

IOUT

ILPK

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7.3 Feature Description

7.3.1 Fixed-Frequency, Peak-Current-Mode Controlled Step-Down Regulator

The following operating description of the LM46000 refers to the Functional Block Diagram and to the waveforms

in Figure 33. The LM46000 is a step-down buck regulator with both high-side (HS) switch and low-side (LS)

switch (synchronous rectifier) integrated. The LM46000 supplies a regulated output voltage by turning on the HS

and LS NMOS switches with controlled ON-time. During the HS switch ON-time, the SW pin voltage VSW swings

up to approximately VIN, and the inductor current ILincreases with a linear slope (VIN – VOUT) / L. When the HS

switch is turned off by the control logic, the LS switch is turned on after a anti-shoot-through dead time. Inductor

current discharges through the LS switch with a slope of –VOUT / L. The control parameter of buck converters are

defined as duty cycle D = tON / TSW, where tON is the HS switch ON-time and TSW is the switching period. The

regulator control loop maintains a constant output voltage by adjusting the duty cycle D. In an ideal buck

converter, where losses are ignored, D is proportional to the output voltage and inversely proportional to the input

voltage: D = VOUT / VIN.

Figure 33. SW Node and Inductor Current Waveforms in Continuous Conduction Mode

The LM46000 synchronous buck converter employs peak current mode control topology. A voltage feedback

loop is used to get accurate DC voltage regulation by adjusting the peak-current command based on voltage

offset. The peak inductor current is sensed from the HS switch and compared to the peak current to control the

ON-time of the HS switch. The voltage feedback loop is internally compensated, which allows for fewer external

components, makes it easy to design, and provides stable operation with almost any combination of output

capacitors. The regulator operates with fixed switching frequency in continuous conduction mode (CCM) and

discontinuous conduction mode (DCM). At very light load, the LM46000 operates in PFM to maintain high

efficiency, and the switching frequency decreases with reduced load current.

7.3.2 Light Load Operation

DCM operation is employed in the LM46000 when the inductor current valley reaches zero. The LM46000 is in

DCM when load current is less than half of the peak-to-peak inductor current ripple in CCM. In DCM, the LS

switch is turned off when the inductor current reaches zero. Switching loss is reduced by turning off the LS FET

at zero current, and the conduction loss is lowered by not allowing negative current conduction. Power

conversion efficiency is higher in DCM than CCM under the same conditions.

In DCM, the HS switch ON time reduces with lower load current. When either the minimum HS switch ON-time

(TON-MIN) or the minimum peak inductor current (IPEAK-MIN) is reached, the switching frequency decreases to

maintain regulation. At this point, the LM46000 operates in PFM. In PFM, switching frequency is decreased by

the control loop when load current reduces to maintain output voltage regulation. Switching loss is further

reduced in PFM operation due to less frequent switching actions. Figure 34 shows an example of switching

frequency decreases with decreased load current.

FBB FBT

OUT FB

R R

V V



RFBT

RFBB

VOUT

10000

100000

1000000

0.001 0.01 0.1

Frequency (Hz)

Load (A)

VIN = 8 V

VIN = 12 V

VIN = 18 V

VIN = 24 V

VIN = 36 V

C001

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Feature Description (continued)

Figure 34. Switching Frequency Decreases with Lower Load Current in PFM Operation

VOUT =5VFS= 1 MHz

In PFM operation, a small positive DC offset is required at the output voltage to activate the PFM detector. The

lower the frequency in PFM, the more DC offset is needed at VOUT. See Typical Characteristics for typical DC

offset at very light load. If the DC offset on VOUT is not acceptable for a given application, TI recommends a static

load at output to reduce or eliminate the offset. Lowering values of the feedback divider RFBT and RFBB can also

serve as a static load. In conditions with low VIN and/or high frequency, the LM46000 may not enter PFM mode if

the output voltage cannot be charged up to provide the trigger to activate the PFM detector. Once the LM46000

is operating in PFM mode at higher VIN, the device remains in PFM operation when VIN is reduced.

7.3.3 Adjustable Output Voltage

The voltage regulation loop in the LM46000 regulates output voltage by maintaining the voltage on FB pin ( VFB)

to be the same as the internal REF voltage (VREF). A resistor divider pair is needed to program the ratio from

output voltage VOUT to VFB. The resistor divider is connected from the VOUT of the LM46000 to ground with the

mid-point connecting to the FB pin.

Figure 35. Output Voltage Setting

The voltage reference system produces a precise voltage reference over temperature. The internal REF voltage

is 1.016 V typically. To program the output voltage of the LM46000 to be a certain value VOUT, RFBB can be

calculated with a selected RFBT by

(1)

The choice of the RFBT depends on the application. TI recommends RFBT in the range from 10 kΩto 100 kΩfor

most applications. A lower RFBT value can be used if static loading is desired to reduce VOUT offset in PFM

operation. Lower RFBT reduces efficiency at very light load. Less static current goes through a larger RFBT and

might be more desirable when light load efficiency is critical. But RFBT larger than 1 MΩis not recommended

because it makes the feedback path more susceptible to noise. Larger RFBT value requires more carefully

designed feedback path on the PCB. The tolerance and temperature variation of the resistor dividers affect the

output voltage regulation. TI recommends using divider resistors with 1% tolerance or better and temperature

coefficient of 100 ppm or lower.

VIN

ENABLE

RENT

RENB

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Feature Description (continued)

If the resistor divider is not connected properly, output voltage cannot be regulated because the feedback loop is

broken. If the FB pin is shorted to ground, the output voltage is driven close to VIN, since the regulator detects

very low voltage on the FB pin and tries to regulate it up. The load connected to the output could be damaged

under such a condition. Do not short FB pin to ground when the LM46000 is enabled. It is important to route the

feedback trace away from the noisy area of the PCB. For more layout recommendations, see Layout .

7.3.4 Enable (EN)

Voltage on the EN pin (VEN) controls the ON or OFF functionality of the LM46000. Applying a voltage less than

0.4 V to the EN input shuts down the operation of the LM46000. In shutdown mode the quiescent current drops

to typically 2.3 µA at VIN = 24 V.

The internal LDO output voltage VCC is turned on when VEN is higher than 1.2 V. The LM46000 switching action

and output regulation are enabled when VEN is greater than 2.1 V (typical). The LM46000 supplies regulated

output voltage when enabled and output current up to 0.5 A.

The EN pin is an input and cannot be open circuit or floating. The simplest way to enable the operation of the

LM46000 is to connect the EN pin to VIN pins directly. This allows self-start-up of the LM46000 when VIN is

within the operation range.

Many applications benefit from the employment of an enable divider RENT and RENB in Figure 36 to establish a

precision system UVLO level for the stage. System UVLO can be used for supplies operating from utility power

as well as battery power. It can be used for sequencing, ensuring reliable operation, or supply protection, such

as a battery discharge voltage level. An external logic signal can also be used to drive EN input for system

sequencing and protection.

Figure 36. System UVLO By Enable Dividers

7.3.5 VCC, UVLO, and BIAS

The LM46000 integrates an internal LDO to generate VCC for control circuitry and MOSFET drivers. The nominal

voltage for VCC is 3.3 V. The VCC pin is the output of the LDO and must be properly bypassed. Place a high-

quality ceramic capacitor with 2.2-µF to 10-µF capacitance and 6.3-V or higher rated voltage as close as possible

to VCC, grounded to the exposed PAD and ground pins. The VCC output pin must not be loaded, left floating,

connected to any external supply, or shorted to ground during operation. Shorting VCC to ground during

operation may cause damage to the LM46000.

Undervoltage lockout (UVLO) prevents the LM46000 from operating until the VCC voltage exceeds 3.14 V

(typical). The VCC UVLO threshold has 567 mV of hysteresis (typically) to prevent undesired shutting down due

to temporary VIN droops.

The internal LDO has two inputs: primary from VIN and secondary from BIAS input. The BIAS input powers the

LDO when VBIAS is higher than the change-over threshold. Power loss of an LDO is calculated by ILDO × (VIN-

LDO – VOUT-LDO). The higher the difference between the input and output voltages of the LDO, the more power

loss occur to supply the same output current. The BIAS input is designed to reduce the difference of the input

and output voltages of the LDO to reduce power loss and improve LM46000 efficiency, especially at light load. TI

recommends tying the BIAS pin to VOUT when VOUT ≥3.3 V. Ground the BIAS pin in applications with VOUT less

than 3.3 V. BIAS input can also come from an external voltage source, if available, to reduce power loss. When

used, TI recommends a 1-µF to 10-µF high-quality ceramic capacitor to bypass the BIAS pin to ground.

Enable

Internal SS Ramp

Ext Tracking Signal to SS pin

VOUT

SS/TRK

RTRT

RTRB

EXT RAMP

SS SSC SS

C I t u

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Feature Description (continued)

7.3.6 Soft Start and Voltage Tracking (SS/TRK)

The LM46000 has a flexible and easy-to-use start-up rate control pin: SS/TRK. The soft-start feature is there to

prevent inrush current impacting the LM46000 and its supply when power is first applied. Soft-start is achieved

by slowly ramping up the target regulation voltage when the device is first enabled or powered up.

The simplest way to use the device is to leave the SS/TRK pin open circuit or floating. The LM46000 employs

the internal soft-start control ramp and starts up to the regulated output voltage in 4.1 ms typically.

In applications with a large amount of output capacitors, or higher VOUT, or other special requirements, the soft-

start time can be extended by connecting an external capacitor CSS from SS/TRK pin to AGND. Extended soft-

start time further reduces the supply current required to charge up output capacitors and supply any output

loading. An internal current source (ISSC = 2.2 µA) charges CSS and generates a ramp from 0 V to VFB to control

the ramp-up rate of the output voltage. VFB value is typically 1 V, and therefore it is not mentioned in the

Equation 2. For a desired soft-start time tSS, the capacitance for CSS can be found by:

(2)

The soft-start capacitor CSS is discharged by an internal FET when VOUT is shut down by hiccup protection due to

excessive load, temperature shutdown due to overheating or ENABLE = logic low. A large CSS capacitor takes a

long time to discharge when EN is toggled low. If EN is toggled high again before the CSS is completely

discharged, then the next resulting soft-start ramp follows the internal soft-start ramp. Only when the soft-start

voltage reaches the leftover voltage on CSS, does the output follow the ramp programmed by CSS. This behavior

looks as if there are two slopes at start-up. If this is not acceptable by a certain application, a R-C low-pass filter

can be added to EN to slow down the shutting down of VCC, which allows more time to discharge CSS.

The LM46001 is capable of start-up into prebiased output conditions. When the inductor current reaches zero,

the LS switch is turned off to avoid negative current conduction. This operation mode is also called diode

emulation mode. It is built-in by the DCM operation at light loads. With a prebiased output voltage, the LM46001

waits until the soft-start ramp allows regulation above the prebiased voltage. It then follows the soft-start ramp to

the regulation level.

When an external voltage ramp is applied to the SS/TRK pin, the LM46001 FB voltage follows the external ramp

if the ramp magnitude is lower than the internal soft-start ramp. A resistor divider pair can be used on the

external control ramp to the SS/TRK pin to program the tracking rate of the output voltage. The final external

ramp voltage applied at the SS/TRK pin must be above 1.2 V to avoid abnormal operation.

Figure 37. Soft Start Tracking External Ramp

VOUT tracked to an external voltage ramp has the option of ramping up slower or faster than the internal voltage

ramp. VFB always follows the lower potential of the internal voltage ramp and the voltage on the SS/TRK pin.

Figure 38 shows the case when VOUT ramps slower than the internal ramp, while Figure 39 shows when VOUT

ramps faster than the internal ramp. Faster start up time may result in inductor current tripping current protection

during start-up. Use with special care.

Figure 38. Tracking with Longer Start-up Time Than The Internal Ramp

100

150

200

250

0 500 1000 1500 2000 2500

RT Resistance (kŸ)

Switching Frequency (kHz)

C008

Enable

Internal SS Ramp

Ext Tracking Signal to SS pin

VOUT

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Feature Description (continued)

Figure 39. Tracking With Shorter Start-up Time Than the Internal Ramp

7.3.7 Switching Frequency (RT) and Synchronization (SYNC)

The switching frequency of the LM46000 can be programmed by the impedance RTfrom the RT pin to ground.

The frequency is inversely proportional to the RTresistance. The RT pin can be left floating and the LM46000

operates at 500-kHz default switching frequency. The RT pin is not designed to be shorted to ground.

For a desired frequency, typical RTresistance can be found by Equation 3.

RT(kΩ) = 40200 / Freq (kHz) – 0.6 (3)

Figure 40 shows RTresistance vs switching frequency FScurve.

Figure 40. RTResistance vs Switching Frequency

SYNC

RTERM

EXT CLOCK

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Feature Description (continued)

Table 1 provides typical RTvalues for a given FS.

Table 1. Typical Frequency Setting RTResistance

FS(kHz) RT(kΩ)

200 200

350 115

500 80.6

750 53.6

1000 39.2

1500 26.1

2000 19.6

2200 17.8

The LM46000 switching action can also be synchronized to an external clock from 200 kHz to 2.2 MHz. Connect

an external clock to the SYNC pin, with proper high speed termination, to avoid ringing. Ground the SYNC pin if

not used.

Figure 41. Frequency Synchronization

The recommendations for the external clock include high level no lower than 2 V, low level no higher than 0.4 V,

duty cycle between 10% and 90% and both positive and negative pulse width no shorter than 80 ns. When the

external clock fails at logic high or low, the LM46000 switches at the frequency programmed by the RTresistor

after a time-out period. TI recommends connecting a resistor RTto the RT pin such that the internal oscillator

frequency is the same as the target clock frequency when the LM46000 is synchronized to an external clock.

This allows the regulator to continue operating at approximately the same switching frequency if the external

clock fails.

The choice of switching frequency is usually a compromise between conversion efficiency and the size of the

circuit. Lower switching frequency implies reduced switching losses (including gate charge losses, switch

transition losses, etc.) and usually results in higher overall efficiency. However, higher switching frequency allows

use of smaller LC output filters and hence a more compact design. Lower inductance also helps transient

response (higher large signal slew rate of inductor current), and reduces the DCR loss. The optimal switching

frequency is usually a trade-off in a given application and thus needs to be determined on a case-by-case basis.

It is related to the input voltage, output voltage, most frequent load current level(s), external component choices,

and circuit size requirement. The choice of switching frequency may also be limited if an operating condition

triggers TON-MIN or TOFF-MIN.

7.3.8 Minimum ON-Time, Minimum OFF-Time and Frequency Foldback at Dropout Conditions

Minimum ON-time, TON-MIN, is the smallest duration of time that the HS switch can be on. TON-MIN is typically 125

ns in the LM46000. Minimum OFF-time, TOFF-MIN, is the smallest duration that the HS switch can be off. TOFF-MIN

is typically 200 ns in the LM46000.

In CCM operation, TON-MIN and TOFF-MIN limits the voltage conversion range given a selected switching frequency.

The minimum duty cycle allowed is

DMIN = TON-MIN × FS(4)

And the maximum duty cycle allowed is

DMAX = 1 – TOFF-MIN × FS(5)

RFBT

RFBB

CFF

VOUT

10000

100000

1000000

5.0 5.2 5.4 5.6 5.8 6.0 6.2 6.4 6.6 6.8 7.0

Frequency (Hz)

VIN (V)

Load = 0.01 A

Load = 0.1 A

Load = 0.5 A

C001

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Feature Description (continued)

Given fixed TON-MIN and TOFF-MIN, the higher the switching frequency the narrower the range of the allowed duty

cycle. In the LM46000, frequency foldback scheme is employed to extend the maximum duty cycle when TOFF-MIN

is reached. The switching frequency decreases once longer duty cycle is needed under low VIN conditions. The

switching frequency can be decreased to approximately 1/10 of the programmed frequency by RTor the

synchronization clock. Such wide range of frequency foldback allows the LM46000 output voltage to stay in

regulation with a much lower supply voltage VIN. This leads to a lower effective dropout voltage. See Typical

Characteristics for more details.

Given an output voltage, the choice of the switching frequency affects the allowed input voltage range, solution

size and efficiency. The maximum operatable supply voltage can be found by

VIN-MAX = VOUT / (FS× TON-MIN ) (6)

At lower supply voltage, the switching frequency decreases once TOFF-MIN is tripped. The minimum VIN without

frequency foldback can be approximated by

VIN-MIN = VOUT / (1 – FS× TOFF-MIN ) (7)

Taking considerations of power losses in the system with heavy load operation, VIN-MIN is higher than the result

calculated in Equation 7 . With frequency foldback, VIN-MIN is lowered by decreased FS.Figure 42 gives an

example of how FSdecreases with decreasing supply voltage VIN at drop-out operation.

Figure 42. Switching Frequency Decreases in Dropout Operation

VOUT =5VFS= 1 MHz

7.3.9 Internal Compensation and CFF

The LM46000 is internally compensated with RC= 400 kΩand CC= 50 pF as shown in Functional Block

Diagram. The internal compensation is designed such that the loop response is stable over the entire operating

frequency and output voltage range. Depending on the output voltage, the compensation loop phase margin can

be low with all ceramic capacitors. An external feed-forward cap CFF is recommended to be placed in parallel

with the top resistor divider RFBT for optimum transient performance.

Figure 43. Feed-Forward Capacitor for Loop Compensation

The feed-forward capacitor CFF in parallel with RFBT places an additional zero before the cross over frequency of

the control loop to boost phase margin. The zero frequency can be found by

fZ-CFF = 1 / ( 2π× RFBT × CFF ) (8)

An additional pole is also introduced with CFF at the frequency of

fP-CFF = 1 / ( 2π× CFF × ( RFBT // RFBB )) (9)

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Feature Description (continued)

Select the CFF so that the bandwidth of the control loop without the CFF is centered between fZ-CFF and fP-CFF. The

zero fZ-CFF adds phase boost at the crossover frequency and improves transient response. The pole fP-CFF helps

maintaining proper gain margin at frequency beyond the crossover.

Designs with different combinations of output capacitors need different CFF. Different types of capacitors have

different equivalent series resistance (ESR). Ceramic capacitors have the smallest ESR and need the most CFF.

Electrolytic capacitors have much larger ESR and the ESR zero frequency low enough to boost the phase up

around the crossover frequency. Designs using mostly electrolytic capacitors at the output may not need any

CFF:fZ-ESR = 1 / ( 2π× ESR × COUT) (10)

The CFF creates a time constant with RFBT that couples in the attenuated output voltage ripple to the FB node. If

the CFF value is too large, it can couple too much ripple to the FB and affect VOUT regulation. It could also couple

too much transient voltage deviation and falsely trip PGOOD thresholds. Therefore, calculate CFF based on

output capacitors used in the system. At cold temperatures, the value of CFF might change based on the

tolerance of the chosen component. This may reduce its impedance and ease noise coupling on the FB node. To

avoid this, more capacitance can be added to the output or the value of CFF can be reduced. See Detailed

Design Procedure for the calculation of CFF.

7.3.10 Bootstrap Voltage (CBOOT)

The driver of the HS switch requires a bias voltage higher than VIN when the HS switch is ON. The capacitor

connected between CBOOT and SW pins works as a charge pump to boost voltage on the CBOOT pin to (VSW +

VCC). The boot diode is integrated on the LM46000 die to minimize the bill of material (BOM). A synchronous

switch is also integrated in parallel with the boot diode to reduce voltage drop on CBOOT. A high-quality ceramic,

0.47-µF, 6.3-V or higher capacitor is recommended for CBOOT.

7.3.11 Power Good (PGOOD)

The LM46000 has a built-in power-good flag shown on PGOOD pin to indicate whether the output voltage is

within its regulation level. The PGOOD signal can be used for start-up sequencing of multiple rails or fault

protection. The PGOOD pin is an open-drain output that requires a pullup resistor to an appropriate DC voltage.

Voltage detected by the PGOOD pin should never exceed 12 V. A resistor divider pair can be used to divide the

voltage down from a higher potential. A typical range of pullup resistor value is 10 kΩto 100 kΩ.

When the FB voltage is within the power-good band, +4% above and –4% below the internal reference VREF

typically, the PGOOD switch is turned off, and the PGOOD voltage is pulled up to the voltage level defined by

the pullup resistor or divider. When the FB voltage is outside of the tolerance band, +10% above or –10% below

VREF typically, the PGOOD switch is turned on and the PGOOD pin voltage is pulled low to indicate power bad.

Both rising and falling edges of the power-good flag have a built-in 220-µs (typical) deglitch delay.

7.3.12 Overcurrent and Short-Circuit Protection

The LM46000 is protected from overcurrent conditions by cycle-by-cycle current limiting on both peak and valley

of the inductor current. Hiccup mode is activated to prevent overheating if a fault condition persists.

High-side MOSFET overcurrent protection is implemented by the nature of the peak-current-mode control. The

HS switch current is sensed when the HS is turned on after a set blanking time. The HS switch current is

compared to the output of the error amplifier (EA) minus slope compensation every switching cycle. See

Functional Block Diagram for more details. The peak current of the HS switch is limited by the maximum EA

output voltage minus the slope compensation at every switching cycle. The slope compensation magnitude at the

peak current is proportional to the duty cycle.

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Feature Description (continued)

When the LS switch is turned on, the current going through it is also sensed and monitored. The LS switch is not

turned OFF at the end of a switching cycle if its current is above the LS current limit ILS-LIMIT. The LS switch is

kept ON so that inductor current keeps ramping down, until the inductor current ramps below ILS-LIMIT. Then the

LS switch is turned OFF, and the HS switch is turned on after a dead time. If the current of the LS switch is

higher than the LS current limit for 32 consecutive cycles and the power-good flag is low, hiccup current-

protection mode is activated. In hiccup mode, the regulator is shut down and kept off for 5.5 ms typically before

the LM46000 tries to start again. If overcurrent or short-circuit fault condition still exists, hiccup repeats until the

fault condition is removed. Hiccup mode reduces power dissipation under severe overcurrent conditions,

prevents overheating and potential damage to the device.

Hiccup is only activated when power-good flag is low. Under non-severe overcurrent conditions when VOUT has

not fallen outside of the PGOOD tolerance band, the LM46000 reduces the switching frequency and keeps the

inductor current valley clamped at the LS current limit level. This operation mode allows slight over current

operation during load transients without tripping hiccup. If the power-good flag becomes low, hiccup operation

starts after LS current limit is tripped 32 consecutive cycles.

7.3.13 Thermal Shutdown

Thermal shutdown is a built-in self protection to limit junction temperature and prevent damages due to over

heating. Thermal shutdown turns off the device when the junction temperature exceeds 160°C typically to

prevent further power dissipation and temperature rise. Junction temperature reduces after thermal shutdown.

The LM46000 attempt sto restart when the junction temperature drops to 150°C.

7.4 Device Functional Modes

7.4.1 Shutdown Mode

The EN pin provides electrical ON and OFF control for the LM46000. When VEN is below 0.4 V, the device is in

shutdown mode. Both the internal LDO and the switching regulator are off. In shutdown mode the quiescent

current drops to 2.3 µA typically with VIN = 24 V. The LM46000 also employs UVLO protection. If VCC voltage is

below the UVLO level, the output of the regulator is turned off.

7.4.2 Standby Mode

The internal LDO has a lower enable threshold than the regulator. When ENABLE voltage is above 1.2 V and

below the precision enable falling threshold (1.8 V typically), the internal LDO regulates the VCC voltage at 3.3 V.

The precision enable circuitry is turned on once VCC is above the UVLO threshold. The switching action and

voltage regulation are not enabled unless VEN rises above the precision enable threshold (2.1 V typically).

7.4.3 Active Mode

The LM46000 is in active mode when VEN is above the precision enable threshold and VCC is above its UVLO

level. The simplest way to enable the LM46000 is to connect the EN pin to VIN. This allows self start-up of the

LM46000 when the input voltage is in the operation range: 3.5 V to 60 V.see to Enable (EN) and VCC, UVLO,

and BIAS for details on setting these operating levels.

In active mode, depending on the load current, the LM46000 is in one of four modes:

1. Continuous conduction mode (CCM) with fixed switching frequency when load current is above half of the

peak-to-peak inductor current ripple;

2. Discontinuous conduction mode (DCM) with fixed switching frequency when load current is lower than half of

the peak-to-peak inductor current ripple in CCM operation;

3. Pulse frequency modulation (PFM) when switching frequency is decreased at very light load;

4. Foldback mode when switching frequency is decreased to maintain output regulation at lower supply voltage

VIN.

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Device Functional Modes (continued)

7.4.4 CCM Mode

CCM operation is employed in the LM46000 when the load current is higher than half of the peak-to-peak

inductor current. In CCM operation, the frequency of operation is fixed unless the minimum HS switch ON-time

(TON_MIN), the minimum HS switch OFF-time (TOFF_MIN) or LS current limit is exceeded. Output voltage ripple is at

a minimum in this mode, and the maximum output current of 0.5 A can be supplied by the LM46000.

7.4.5 Light Load Operation

When the load current is lower than half of the peak-to-peak inductor current in CCM, the LM46000 operates in

DCM , also known as diode emulation mode (DEM). In DCM operation, the LS FET is turned off when the

inductor current drops to 0 A to improve efficiency. Both switching losses and conduction losses are reduced in

DCM, comparing to forced PWM operation at light load.

At even lighter current loads, PFM is activated to maintain high efficiency operation. When the HS switch ON-

time reduces to TON-MIN or peak inductor current reduces to its minimum IPEAK-MIN, the switching frequency reduce

sto maintain proper regulation. Efficiency is greatly improved by reducing switching and gate drive losses.

7.4.6 Self-Bias Mode

For highest efficiency of operation, TI recommends that the BIAS pin be connected directly to VOUT when VOUT ≥

3.3 V. In this self-bias mode of operation, the difference between the input and output voltages of the internal

LDO are reduced, and therefore the total efficiency of the LM46000 is improved. These efficiency gains are more

evident during light load operation. During this mode of operation, the LM46000 operates with a minimum

quiescent current of 24 µA (typical). See VCC, UVLO, and BIAS for more details.

SWVIN

PGND

CBOOT

VCC

BIAS

SYNC

ENABLE

SS/TRK

AGND

LM46000

VIN COUT

CBOOT

CIN

CVCC

VOUT

CBIAS RFBT

RFBB

CFF

PGOOD

SWVIN

PGND

CBOOT

VCC

BIAS

SYNC

ENABLE

SS/TRK

AGND

LM46000

VIN COUT

CBOOT

CIN

CVCC

VOUT

RFBT

RFBB

CFF

PGOOD

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8 Applications and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LM46000 is a step-down DC-to-DC regulator. It is typically used to convert a higher DC voltage to a lower

DC voltage with a maximum output current of 0.5 A. The following design procedure can be used to select

components for the LM46000. Alternately, the WEBENCH® software may be used to generate complete

designs. When generating a design, the WEBENCH software utilizes iterative design procedure and accesses

comprehensive databases of components. See Custom Design With WEBENCH® Tools and ti.com for more

details.

8.2 Typical Applications

The LM46000 only requires a few external components to convert from a wide range of supply voltage to output

voltage. Figure 44 shows a basic schematic when BIAS is connected to VOUT . This is recommended for VOUT ≥

3.3 V. For VOUT < 3.3 V, connect BIAS to ground, as shown in Figure 45.

Figure 44. LM46000 Basic Schematic for

VOUT ≥3.3 V, Tie BIAS to VOUT

Figure 45. LM46000 Basic Schematic for

VOUT < 3.3 V, Tie BIAS to Ground

The LM46000 also integrates a full list of optional features to aid system design requirements, such as precision

enable, VCC UVLO, programmable soft start, output voltage tracking, programmable switching frequency, clock

synchronization and power-good indication. Each application can select the features for a more comprehensive

design. A schematic with all features utilized is shown in Figure 46.

SWVIN

PGND

CBOOT

VCC

BIAS

SYNC

PGOOD

ENABLE

SS/TRK

AGND

LM46000

VIN

COUT

CBOOT

CIN

CVCC

CBIAS

RFBT

RFBB

CFF

CSS

RSYNC

VOUT

Tie BIAS to PGND

when VOUT < 3.3 V

RENT

RENB

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Typical Applications (continued)

Figure 46. LM46000 Schematic With All Features

The external components must fulfill the needs of the application, but also the stability criteria of the device

control loop. The LM46000 is optimized to work within a range of external components. Inductance and

capacitance of the LC output filter must be considered in conjunction, creating a double pole, responsible for the

corner frequency of the converter. Table 2 can be used to simplify the output filter component selection.

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Typical Applications (continued)

(1) Inductor values are calculated based on typical VIN = 24 V. For VOUT of 24 V, VIN = 48 V

(2) All the COUT values are after derating. Add more when using ceramics.

(3) RFBT = 0 Ωfor VOUT = 1 V. RFBT = 1 MΩfor all other VOUT settings.

(4) For designs with RFBT other than 1 MΩ, adjust CFF such that (CFF × RFBT) is unchanged and adjust RFBB such that (RFBT / RFBB) is

unchanged.

(5) High ESR COUT givse enough phase boost, and CFF not needed.

Table 2. L, COUT and CFF Typical Values

FS(kHz) L (µH)(1) COUT (µF)(2) CFF (pF)(3)(4) RT(kΩ) RFBB (kΩ)(3)(4)

VOUT = 1 V

200 22 500 none 200 100

500 10 330 none 80.6 or open 100

1000 4.8 180 none 39.2 100

2200 2.2 100 none 17.8 100

VOUT = 3.3 V

200 68 220 44 200 442

500 27 100 33 80.6 or open 442

1000 15 47 18 39.2 442

2200 6.8 27 12 17.8 442

VOUT = 5 V

200 100 150 66 200 249

500 44 66 33 80.6 or open 249

1000 22 33 22 39.2 249

2200 10 22 18 17.8 249

VOUT = 12 V

200 150 33 see note (5) 200 93.1

500 56 22 47 80.6 or open 93.1

1000 27 15 33 39.2 93.1

VOUT = 24 V

200 270 22 see note (5) 200 44.2

500 120 15 see note (5) 80.6 or open 44.2

1000 56 10 see note (5) 39.2 44.2

FBB FBT

OUT FB

R R

V V



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8.2.1 Design Requirements

A detailed design procedure is described based on a design example. For this design example, use the

parameters listed in Table 3 as the input parameters.

Table 3. Design Example Parameters

DESIGN PARAMETER VALUE

Input voltage VIN 24 V typical, range from 3.8 V to 60 V

Output voltage VOUT 3.3 V

Input ripple voltage 400 mV

Output ripple voltage 30 mV

Output current rating 0.5 A

Operating frequency 500 kHz

Soft-start time 10 ms

8.2.2 Detailed Design Procedure

8.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM46000 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.2.2 Output Voltage Setpoint

The output voltage of the LM46000 device is externally adjustable using a resistor divider network. The divider

network is comprised of top feedback resistor RFBT and bottom feedback resistor RFBB. Use Equation 11 to

determine the output voltage of the converter:

(11)

Choose the value of the RFBT to be 1 MΩto minimize quiescent current to improve light load efficiency in this

application. With the desired output voltage set to be 3.3 V and the VFB = 1.016 V, the RFBB value can then be

calculated using Equation 11. The formula yields a value of 444.83 kΩ. Choose the closest available value of 442

kΩfor the RFBB. Please refer to Adjustable Output Voltage for more details.

8.2.2.3 Switching Frequency

The default switching frequency of the LM46000 device is set at 500 kHz when RT pin is open circuit. The

switching frequency is selected to be 500 kHz in this application for one less passive components. If other

frequency is desired, use Equation 12 to calculate the required value for RT.

RT(kΩ) = 40200 / Freq (kHz) – 0.6 (12)

For 500 kHz, the calculated RTis 79.8 kΩ, and standard value 80.6 kΩcan also be used to set the switching

frequency at 500 kHz.

OUT

 

 u  u

d d

u u u u

IN OUT IN OUT

S L MAX S L MAX

(V V ) D (V V ) D

0.4 F I 0.2 F I

 u

IN OUT

(V V ) D

iL F

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8.2.2.4 Input Capacitors

The LM46000 device requires high frequency input decoupling capacitor(s) and a bulk input capacitor, depending

on the application. The typical recommended value for the high frequency decoupling capacitor is 4.7 µF to 10

µF. TI recommends a high-quality ceramic type X5R or X7R with sufficient voltage rating. The voltage rating

must be greater than the maximum input voltage. To compensate the derating of ceramic capacitor, a voltage

rating of twice the maximum input voltage is recommended. Additionally, some bulk capacitance may be

required, especially if the LM46000 circuit is not located within approximately 5 cm from the input voltage source.

The bulk input capacitor is used to provide damping to the voltage spiking due to the lead inductance of the

cable or trace. The value for this capacitor is not critical but must be rated to handle the maximum input voltage

including ripple.

For this design, a 10-µF, X7R dielectric capacitor rated for 100 V is used for the input decoupling capacitor. The

ESR is approximately 3 mΩ, and the current-rating is 3 A. Include a capacitor with a value of 0.1 µF for high-

frequency filtering and place it as close as possible to the device pins.

NOTE

DC Bias effect: High capacitance ceramic capacitors have a DC bias effect, which will

have a strong influence on the final effective capacitance. Therefore the right capacitor

value has to be chosen carefully. Package size and voltage rating in combination with

dielectric material are responsible for differences between the rated capacitor value and

the effective capacitance.

8.2.2.5 Inductor Selection

The first criterion for selecting an output inductor is the inductance itself. In most buck converters, this value is

based on the desired peak-to-peak ripple current, ΔiL, that flows in the inductor along with the DC load current.

As with switching frequency, the selection of the inductor is a tradeoff between size and cost. Higher inductance

gives lower ripple current and hence lower output voltage ripple with the same output capacitors. Lower

inductance could result in smaller, less expensive component. An inductance that gives a ripple current of 20% to

40% of the 0.5 A at the typical supply voltage is a good starting point. ΔiL= (1/5 to 2/5) x IOUT. The peak-to-peak

inductor current ripple can be found by Equation 13 and the range of inductance can be found by Equation 14

with the typical input voltage used as VIN.

(13)

(14)

D is the duty cycle of the converter which in a buck converter it can be approximated as D = VOUT / VIN, assuming

no loss power conversion. By calculating in terms of amperes, volts, and megahertz, the inductance value will

come out in micro Henries. The inductor ripple current ratio is defined by:

(15)

The second criterion is the inductor saturation current rating. The inductor must be rated to handle the maximum

load current plus the ripple current:

IL-PEAK = ILOAD-MAX +ΔiL(16)

The LM46000 has both valley current limit and peak current limit. During an instantaneous short, the peak

inductor current can be high due to a momentary increase in duty cycle. The inductor current rating must be

higher than the HS current limit. Select an inductor with a larger core saturation margin and preferably a softer

roll-off of the inductance value over load current.

 u 

S OUT

D 1

ESR ( 0.5)

F C r

 

ª º

§ ·

c c

! u u   u 

« »

¨ ¸

u u ' « »

¬ ¼

OUT S OUT OUT

1 r

C (1 D ) D (1 r)

(F r V /I ) 12

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In general, choosing lower inductance is preferred in switching power supplies, because it usually corresponds to

faster transient response, smaller DCR, and reduced size for more compact designs. But too low of an

inductance can generate too large of an inductor current ripple such that over current protection at the full load

could be falsely triggered. It also generates more conduction loss, since the RMS current is slightly higher

relative that with lower current ripple at the same DC current. Larger inductor current ripple also implies larger

output voltage ripple with the same output capacitors. With peak current mode control, it is not recommended to

have too small of an inductor current ripple. Enough inductor current ripple improves signal-to-noise ratio on the

current comparator and makes the control loop more immune to noise.

Once the inductance is determined, the type of inductor must be selected. Ferrite designs have very low core

losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and

preventing saturation. Ferrite core material saturates hard, which means that inductance collapses abruptly when

the peak design current is exceeded. The ‘hard’ saturation results in an abrupt increase in inductor ripple current

and consequent output voltage ripple. Do not allow the core to saturate!

For the design example, a standard 27-μH inductor from Wurth, Coiltronics, or Vishay can be used for the 3.3-V

output with plenty of current rating margin.

8.2.2.6 Output Capacitor Selection

The device is designed to be used with a wide variety of LC filters. It is generally desired to use as little output

capacitance as possible to keep cost and size down. Choose the output capacitor (s), COUT, with care because it

directly affects the steady-state output voltage ripple, loop stability and the voltage over/undershoot during load

current transients.

The output voltage ripple is essentially composed of two parts. One is caused by the inductor current ripple going

through the ESR of the output capacitors:

ΔVOUT-ESR =ΔiL× ESR (17)

The other is caused by the inductor current ripple charging and discharging the output capacitors:

ΔVOUT-C =ΔiL/ ( 8 × FS× COUT ) (18)

The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the

sum of the two peaks.

Output capacitance is usually limited by transient performance specifications if the system requires tight voltage

regulation in the presence of large current steps and fast slew rates. When a fast large load transient happens,

output capacitors provide the required charge before the inductor current can slew to the appropriate level. The

initial output voltage step is equal to the load current step multiplied by the ESR. VOUT continues to droop until

the control loop response increases or decreases the inductor current to supply the load. To maintain a small

over- or under-shoot during a transient, small ESR and large capacitance are desired. But these also come with

higher cost and size. Thus, the motivation is to seek a fast control loop response to reduce the output voltage

deviation.

For a given input and output requirement, Equation 19 gives an approximation for an absolute minimum output

capacitor required:

(19)

Along with this for the same requirement, calculate the maximum ESR per Equation 20

where

• r = Ripple ratio of the inductor ripple current (ΔIL/ IOUT)

•ΔVOUT = target output voltage undershoot

• D’ = 1 – duty cycle

• FS= switching frequency

• IOUT = load current (20)

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A general guideline for COUT range is that COUT should be larger than the minimum required output capacitance

calculated by Equation 19, and smaller than 10 times the minimum required output capacitance or 1 mF. In

applications with VOUT less than 3.3 V, it is critical that low ESR output capacitors are selected. This limits

potential output voltage overshoots as the input voltage falls below the device normal operating range. To

optimize the transient behavior a feed-forward capacitor could be added in parallel with the upper feedback

resistor. For this design example, two 47-µF,10-V, X7R ceramic capacitors are used in parallel.

SS SSC SS

C I t u

FF xFBT FBT FBB

1 1

C2 f R (R / /R )

xOUT OUT

1.5

fV C

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8.2.2.7 Feed-Forward Capacitor

The LM46000 is internally compensated and the internal R-C values are 400 kΩand 50 pF, respectively.

Depending on the VOUT and frequency FS, if the output capacitor COUT is dominated by low ESR (ceramic types)

capacitors, it could result in low phase margin. To improve the phase boost an external feed-forward capacitor

CFF can be added in parallel with RFBT. Choose CFF so that phase margin is boosted at the crossover frequency

without CFF. A simple estimation for the crossover frequency without CFF (fx) is shown in Equation 21, assuming

COUT has very small ESR.

(21)

Equation 22 was tested for CFF:

(22)

Equation 22 indicates that the crossover frequency is geometrically centered on the zero and pole frequencies

caused by the CFF capacitor.

For designs with higher ESR, CFF is not required when COUT has very high ESR and CFF calculated from

Equation 22 should be reduced with medium ESR.Table 2 can be used as a quick starting point.

For the application in this design example, a 33-pF COG capacitor is selected.

8.2.2.8 Bootstrap Capacitors

Every LM46000 design requires a bootstrap capacitor, CBOOT. The recommended bootstrap capacitor is 0.47 μF

and rated at 6.3 V or higher. The bootstrap capacitor is located between the SW pin and the CBOOT pin. The

bootstrap capacitor must be a high-quality ceramic type with X7R or X5R grade dielectric for temperature

stability.

8.2.2.9 VCC Capacitor

The VCC pin is the output of an internal LDO for LM46000. The input for this LDO comes from either VIN or

BIAS (see Functional Block Diagram for LM46000). To insure stability of the part, place a minimum of 2.2-µF, 10-

V capacitor from this pin to ground.

8.2.2.10 BIAS Capacitors

For an output voltage of 3.3 V and greater, the BIAS pin can be connected to the output in order to increase light

load efficiency. This pin is an input for the VCC LDO. When BIAS is not connected, the input for the VCC LDO is

internally connected into VIN. Because this is an LDO, the voltage differences between the input and output

affects the efficiency of the LDO. If necessary, a capacitor with a value of 1 μF can be added close to the BIAS

pin as an input capacitor for the LDO.

8.2.2.11 Soft-Start Capacitors

The user can leave the SS/TRK pin floating, and the LM46000 implement a soft-start time of 4.1 ms typically. In

order to use an external soft-start capacitor, size the capacitor so that the soft-start time is longer than 4.1 ms.

Use Equation 23 to calculate the soft-start capacitor value:

where

• CSS = Soft-start capacitor value (µF)

• ISS = Soft-start charging current (µA)

• tSS = Desired soft-start time (s) (23)

For the desired soft start time of 10 ms and soft-start charging current of 2.2 µA, Equation 23 yields a soft-start

capacitor value of 0.022 µF.

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8.2.2.12 Undervoltage Lockout Setpoint

The UVLO is adjusted using the external voltage divider network of RENT and RENB. RENT is connected between

VIN and the EN pin of the LM46000 device. RENB is connected between the EN pin and the GND pin. The UVLO

has two thresholds, one for power up when the input voltage is rising and one for power down or brownouts

when the input voltage is falling. Equation 24 can be used to determine the rising VIN (UVLO) level:

VIN-UVLO-RISING = VENH × (RENB + RENT) / RENB (24)

The EN rising threshold for LM46000 is set to be 2.1 V. Choose the value of RENB to be 1 MΩto minimize input

current going into the converter. If the desired VIN (UVLO) level is at 5 V, then the value of RENT can be

calculated using Equation 25:

RENT = (VIN-UVLO-RISING / VENH - 1) × RENB (25)

Equation 25 yields a value of 1.37 MΩ. The resulting falling UVLO threshold can be calculated as follows:

VIN-UVLO-FALLING = 1.8 × (RENB + RENT) / RENB (26)

8.2.2.13 PGOOD

A typical pullup resistor value is 10 kΩto 100 kΩfrom the PGOOD pin to a voltage no higher than 12 V. If it is

desired to pull up the PGOOD pin to a voltage higher than 12 V, a resistor can be added from the PGOOD pin to

ground to divide the voltage detected by the PGOOD pin to a value no higher than 12 V.

Time (200 µs/DIV)

VDROP_ON_0.75Ÿ_LOAD

(375 mV/DIV)

VOUT (200 mV/DIV)

IL (500 mA/DIV)

0.1

0.2

0.3

0.4

0.5

0.6

50 60 70 80 90 100 110 120

Current (A)

Temperature (ƒC)

R,JA = 10 ƒC/W

R,JA = 20 ƒC/W

R,JA = 30 ƒC/W

C001

3.20

3.22

3.24

3.26

3.28

3.30

3.32

3.34

3.36

3.38

3.40

0.001 0.01 0.1

Vout (V)

Load Current (A)

VIN = 8V VIN = 12V

VIN = 18V VIN = 24V

VIN = 28V VIN = 36V

C012

2.5

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

3.5 3.7 3.9 4.1 4.3 4.5

VOUT (V)

VIN (V)

Load = 0.2A

Load = 0.3A

Load = 0.4A

Load = 0.5A

C022

100

0.001 0.01 0.1

Efficiency (%)

Load Current (A)

VIN = 8V

VIN = 12V

VIN = 18V

VIN = 24V

VIN = 28V

VIN = 36V

C002

CBOOT

VCC

BIAS

LM46000 VOUT

RFBT

RFBB

CBIAS

2.2 µF 1 µF

0.47 µF

L=27 µH

100 µF

33 pF 1 MŸ

432

kŸ

CFF

COUT

CBOOT

CVCC

VOUT = 3.3 V FS = 500 kHz

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8.2.3 Application Performance Curves

See Table 2 for bill of materials for each VOUT and FScombination. Unless otherwise stated, application performance curves

were taken at TA= 25°C.

VOUT = 3.3 V FS= 500 kHz VIN = 24 V

Figure 47. BOM for VOUT = 3.3 V FS= 500 kHz

VOUT = 3.3 V FS= 500 kHz

Figure 48. Efficiency

VOUT = 3.3 V FS= 500 kHz

Figure 49. Output Voltage Regulation

VOUT = 3.3 V FS= 500 kHz

Figure 50. Dropout Curve

VOUT = 3.3 V FS= 500 kHz VIN = 24 V

Figure 51. Load Transient Between 0.05 A and 0.5 A

VOUT = 3.3 V FS= 500 kHz VIN = 24 V

Figure 52. Derating Curve

Time (200 µs/DIV)

VDROP_ON_0.50Ÿ_LOAD

(200 mV/DIV)

VOUT (200 mV/DIV)

IL (500 mA/DIV)

0.1

0.2

0.3

0.4

0.5

0.6

50 60 70 80 90 100 110 120

Current (A)

Temperature (ƒC)

R,JA = 10 ƒC/W

R,JA = 20 ƒC/W

R,JA = 30 ƒC/W

C001

4.80

4.85

4.90

4.95

5.00

5.05

5.10

5.15

5.20

0.001 0.01 0.1

Vout (V)

Load Current (A)

VIN = 12V VIN = 18V

VIN = 24V VIN = 28V

VIN = 36V VIN = 42V

C013

4.0

4.2

4.4

4.6

4.8

5.0

5.2

5.0 5.2 5.4 5.6 5.8 6.0

VOUT (V)

VIN (V)

Load = 0.2A

Load = 0.3A

Load = 0.4A

Load = 0.5A

C023

100

0.001 0.01 0.1

Efficiency (%)

Load Current (A)

VIN = 12V

VIN = 18V

VIN = 24V

VIN = 28V

VIN = 36V

VIN = 42V

C003

CBOOT

VCC

BIAS

LM46000

VOUT

RFBT

RFBB

CBIAS

2.2 µF 1 µF

0.47 µF

L=44 µH

66 µF

33 pF 1 MŸ

249

kŸ

CFF

COUT

CBOOT

CVCC

VOUT = 5 V FS = 500 kHz

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See Table 2 for bill of materials for each VOUT and FScombination. Unless otherwise stated, application performance curves

were taken at TA= 25°C.

VOUT = 5 V FS= 500 kHz VIN = 24 V

Figure 53. BOM for VOUT = 5 V, FS= 500 kHz

VOUT = 5 V FS= 500 kHz

Figure 54. Efficiency

VOUT = 5 V FS= 500 kHz

Figure 55. Output Voltage Regulation

VOUT = 5 V FS= 500 kHz

Figure 56. Dropout Curve

VOUT = 5 V FS= 500 kHz VIN = 24 V

Figure 57. Load Transient Between 0.05 A and 0.5 A

VOUT = 5 V FS= 500 kHz VIN = 24 V

Figure 58. Derating Curve

Time (200 µs/DIV)

VDROP_ON_0.75Ÿ_LOAD

(500 mV/DIV)

VOUT (200 mV/DIV)

IL (500 mA/DIV)

0.1

0.2

0.3

0.4

0.5

0.6

50 60 70 80 90 100 110 120

Current (A)

Temperature (ƒC)

R,JA = 10 ƒC/W

R,JA = 20 ƒC/W

R,JA = 30 ƒC/W

C001

4.80

4.85

4.90

4.95

5.00

5.05

5.10

5.15

0.001 0.01 0.1

Vout (V)

Load Current (A)

VIN = 8V VIN = 12V VIN = 18V

VIN = 24V VIN = 28V VIN = 36V

VIN = 42V VIN = 48V VIN = 60V

C014

4.0

4.2

4.4

4.6

4.8

5.0

5.2

5.0 5.2 5.4 5.6 5.8 6.0

VOUT (V)

VIN (V)

Load = 0.2A

Load = 0.3A

Load = 0.4A

Load = 0.5A

C024

100

0.001 0.01 0.1

Efficiency (%)

Load Current (A)

VIN = 8V

VIN = 12V

VIN = 18V

VIN = 24V

VIN = 28V

VIN = 36V

VIN = 42V

VIN = 48V

VIN = 60V

C004

CBOOT

VCC

BIAS

LM46000 VOUT

RFBT

RFBB

CBIAS

2.2 µF 1 µF

0.47 µF

L=100 µH

150 µF

68 pF 1 MŸ

249

kŸ

CFF

COUT

CBOOT

CVCC

200

kŸ

VOUT = 5 V FS = 200 kHz

LM46000

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See Table 2 for bill of materials for each VOUT and FScombination. Unless otherwise stated, application performance curves

were taken at TA= 25°C.

VOUT = 5 V FS= 200 kHz VIN = 24 V

Figure 59. BOM for VOUT = 5 V, FS= 200 kHz

VOUT = 5 V FS= 200 kHz

Figure 60. Efficiency

VOUT = 5 V FS= 200 kHz

Figure 61. Output Voltage Regulation

VOUT = 5 V FS= 200 kHz

Figure 62. Dropout Curve

VOUT = 5 V FS= 200 kHz VIN = 24 V

Figure 63. Load Transient Between 0.05 A and 0.5A

VOUT = 5 V FS= 200 kHz VIN = 24 V

Figure 64. Derating Curve

Time (200 µs/DIV)

VDROP_ON_0.75Ÿ_LOAD

(375 mV/DIV)

VOUT (200 mV/DIV)

IL (500 mA/DIV)

0.1

0.2

0.3

0.4

0.5

0.6

50 60 70 80 90 100 110 120

Current (A)

Temperature (ƒC)

R,JA = 10 ƒC/W

R,JA = 20 ƒC/W

R,JA = 30 ƒC/W

C001

4.80

4.85

4.90

4.95

5.00

5.05

5.10

5.15

5.20

0.001 0.01 0.1

Vout (V)

Load Current (A)

VIN = 12V

VIN = 18V

VIN = 24V

VIN = 28V

C015

4.0

4.2

4.4

4.6

4.8

5.0

5.2

5.0 5.2 5.4 5.6 5.8 6.0

VOUT (V)

VIN (V)

Load = 0.2A

Load = 0.3A

Load = 0.4A

Load = 0.5A

C025

100

0.001 0.01 0.1

Efficiency (%)

Load Current (A)

VIN = 12V

VIN = 18V

VIN = 24V

VIN = 28V

C005

CBOOT

VCC

BIAS

LM46000 VOUT

RFBT

RFBB

CBIAS

2.2 µF 1 µF

0.47 µF

L=22 µH

33 µF

22 pF 1 MŸ

249

kŸ

CFF

COUT

CBOOT

CVCC

39.2

kŸ

VOUT = 5 V FS = 1 MHz

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See Table 2 for bill of materials for each VOUT and FScombination. Unless otherwise stated, application performance curves

were taken at TA= 25°C.

VOUT = 5 V FS= 1 MHz VIN = 24 V

Figure 65. BOM for VOUT = 5 V, FS= 1 MHz

VOUT = 5 V FS= 1 MHz VIN = 24 V

Figure 66. Efficiency

VOUT = 5 V FS= 1 MHz

Figure 67. Output Voltage Regulation

VOUT = 5 V FS= 1 MHz

Figure 68. Dropout Curve

VOUT = 5 V FS= 1 MHz VIN = 24 V

Figure 69. Load Transient Between 0.05 A and 0.5 A

VOUT = 5 V FS= 1 MHz VIN = 24 V

Figure 70. Derating Curve

Time (200 µs/DIV)

ILOAD (500 mA/DIV)

VOUT (500 mV/DIV)

IL (500 mA/DIV)

0.1

0.2

0.3

0.4

0.5

0.6

50 60 70 80 90 100 110 120

Current (A)

Temperature (ƒC)

R,JA = 10 ƒC/W

R,JA = 20 ƒC/W

R,JA = 30 ƒC/W

C001

11.5

11.6

11.7

11.8

11.9

12.0

12.1

12.2

12.3

12.4

12.5

0.001 0.01 0.1

Vout (V)

Load Current (A)

VIN = 24V VIN = 28V

VIN = 36V VIN = 42V

VIN = 48V VIN = 60V

C017

11.0

11.2

11.4

11.6

11.8

12.0

12.2

12.4

12.0 12.5 13.0 13.5 14.0

VOUT (V)

VIN (V)

Load = 0.2A

Load = 0.3A

Load = 0.4A

Load = 0.5A

C027

100

0.001 0.01 0.1

Efficiency (%)

Load Current (A)

VIN = 24V

VIN = 28V

VIN = 36V

VIN = 42V

VIN = 48V

VIN = 60V

C007

CBOOT

VCC

BIAS

LM46000

VOUT

RFBT

RFBB

CBIAS

2.2 µF 1 µF

0.47 µF

L=56 µH

22 µF

47 pF 1 MŸ

90.9

kŸ

CFF

COUT

CBOOT

CVCC

VOUT = 12 V FS = 500 kHz

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See Table 2 for bill of materials for each VOUT and FScombination. Unless otherwise stated, application performance curves

were taken at TA= 25°C.

VOUT = 12 V FS= 500 kHz VIN = 24 V

Figure 71. BOM for VOUT = 12 V, FS= 500 kHz

VOUT = 12 V FS= 500 kHz

Figure 72. Efficiency

VOUT = 12 V FS= 500 kHz

Figure 73. Output Voltage Regulation

VOUT = 12 V FS= 500 kHz

Figure 74. Dropout Curve

VOUT = 12 V FS= 500 kHz VIN = 24 V

Figure 75. Load Transient Between 0.05 A and 0.5 A

VOUT = 12 V FS= 500 kHz VIN = 24 V

Figure 76. Derating Curve

Time (200 µs/DIV)

ILOAD (500 mA/DIV)

VOUT (1 V/DIV)

IL (500 mA/DIV)

0.1

0.2

0.3

0.4

0.5

0.6

50 60 70 80 90 100 110 120

Current (A)

Temperature (ƒC)

R,JA = 10 ƒC/W

R,JA = 20 ƒC/W

C001

23.0

23.2

23.4

23.6

23.8

24.0

24.2

24.4

24.6

24.8

25.0

0.001 0.01 0.1

Vout (V)

Load Current (A)

VIN = 36V

VIN = 42V

VIN = 48V

VIN = 60V

C018

22.0

22.5

23.0

23.5

24.0

24.5

24.0 24.5 25.0 25.5 26.0

VOUT (V)

VIN (V)

Load = 0.2A

Load = 0.3A

Load = 0.4A

Load = 0.5A

C028

100

0.001 0.01 0.1

Efficiency (%)

Load Current (A)

VIN = 36V

VIN = 42V

VIN = 48V

VIN = 60V

C008

CBOOT

VCC

BIAS

LM46000

VOUT

RFBT

RFBB

CBIAS

2.2 µF 1 µF

0.47 µF

L=120 µH

15 µF

1 MŸ

43.2

kŸ

COUT

CBOOT

CVCC

VOUT = 24 V FS = 500 kHz

82 pF

CFF

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See Table 2 for bill of materials for each VOUT and FScombination. Unless otherwise stated, application performance curves

were taken at TA= 25°C.

VOUT = 24 V FS= 500 kHz VIN = 48 V

Figure 77. BOM for VOUT = 24 V, FS= 500 kHz

VOUT = 24 V FS= 500 kHz

Figure 78. Efficiency

VOUT = 24 V FS= 500 kHz

Figure 79. Output Voltage Regulation

VOUT = 24 V FS= 500 kHz

Figure 80. Dropout Curve

VOUT = 24 V FS= 500 kHz VIN = 48 V

Figure 81. Load Transient Between 0.05 A and 0.5 A

VOUT = 24 V FS= 500 kHz VIN = 48 V

Figure 82. Derating Curve

1.E+03

1.E+04

1.E+05

1.E+06

0.001 0.010 0.100 1.000

Switching Frequency (Hz)

LOAD CURRENT (A)

VIN = 8V

VIN = 12V

VIN = 24V

C006

1.E+03

1.E+04

1.E+05

1.E+06

0.001 0.010 0.100 1.000

Switching Frequency (Hz)

LOAD CURRENT (A)

VIN = 12V

VIN = 24V

VIN = 36V

C007

0.1

0.2

0.3

0.4

0.5

0.6

50 60 70 80 90 100 110 120

Current (A)

Temperature (ƒC)

Vin = 12V

Vin = 24V

Vin = 36V

C001

0.1

0.2

0.3

0.4

0.5

0.6

50 60 70 80 90 100 110 120

Current (A)

Temperature (ƒC)

Vin = 12V

Vin = 24V

Vin = 36V

C001

0.1

0.2

0.3

0.4

0.5

0.6

50 60 70 80 90 100 110 120

Current (A)

Temperature (ƒC)

Vin = 12V

Vin = 24V

Vin = 36V

C001

0.1

0.2

0.3

0.4

0.5

0.6

50 60 70 80 90 100 110 120

Current (A)

Temperature (ƒC)

Vin = 12V

Vin = 24V

Vin = 36V

C001

LM46000

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Product Folder Links: LM46000

See Table 2 for bill of materials for each VOUT and FScombination. Unless otherwise stated, application performance curves

were taken at TA= 25°C.

VOUT = 3.3 V FS= 500 kHz RθJA = 20°C/W

Figure 83. Derating Curve With RθJA = 20°C/W

VOUT = 5 V FS= 500 kHz RθJA = 20°C/W

Figure 84. Derating Curve With RθJA = 20°C/W

VOUT = 5 V FS= 200 kHz RθJA = 20°C/W

Figure 85. Derating Curve With RθJA = 20°C/W

VOUT = 5 V FS= 1 MHz RθJA = 20°C/W

Figure 86. Derating Curve With RθJA = 20°C/W

VOUT = 3.3 V FS= 500 kHz

Figure 87. Switching Frequency vs IOUT in PFM Operation

VOUT = 5 V FS= 1 MHz

Figure 88. Switching Frequency vs IOUT in PFM Operation

PGOOD (2 V/DIV)

VOUT (2 V/DIV)

IL (250 mA/DIV)

Time (2 ms/DIV)

PGOOD (2 V/DIV)

VOUT (2 V/DIV)

IL (100 mA/DIV)

Time (2 ms/DIV)

SW (10 V/DIV)

VOUT (5 mV/DIV)

IL (500 mA/DIV)

Time (500 µs/DIV)

PGOOD (2 V/DIV)

VOUT (2 V/DIV)

IL (500 mA/DIV)

Time (2 ms/DIV)

SW (10 V/DIV)

VOUT (5 mV/DIV)

IL (500 mA/DIV)

Time (2 µs/DIV)

SW (10 V/DIV)

VOUT (5 mV/DIV)

IL (500 mA/DIV)

Time (2 µs/DIV)

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See Table 2 for bill of materials for each VOUT and FScombination. Unless otherwise stated, application performance curves

were taken at TA= 25°C.

VOUT = 3.3 V FS= 500 kHz IOUT = 0.5A

Figure 89. Switching Waveform in CCM Operation

VOUT = 3.3 V FS= 500 kHz IOUT = 40 mA

Figure 90. Switching Waveform in DCM Operation

VOUT = 3.3 V FS= 500 kHz IOUT = 0 mA

Figure 91. Switching Waveform in PFM Operation

VIN = 24 V VOUT = 3.3 V RLOAD = 6.6 Ω

Figure 92. Start-up Into Full Load With Internal Soft-Start

Rate

VIN = 24 V VOUT = 3.3 V RLOAD = 13.2 Ω

Figure 93. Start-up Into Half Load With Internal Soft-Start

Rate

VIN = 24 V VOUT = 3.3 V RLOAD = 33 Ω

Figure 94. Start-up Into 100 mA With Internal Soft-Start

Rate

PGOOD (5 V/DIV)

VOUT (2 V/DIV)

IL (500 mA/DIV)

Time (10 ms/DIV)

VIN (20 V/DIV)

VOUT (50 mV/DIV)

IL (500 mA/DIV)

Time (2 ms/DIV)

VIN (20 V/DIV)

VOUT (50 mV/DIV)

IL (500 mA/DIV)

Time (2 ms/DIV)

PGOOD (2 V/DIV)

VOUT (1 V/DIV)

IL (500 mA/DIV)

Time (2 ms/DIV)

PGOOD (10 V/DIV)

VOUT (10 V/DIV)

IL (500 mA/DIV)

Time (5 ms/DIV)

LM46000

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Product Folder Links: LM46000

See Table 2 for bill of materials for each VOUT and FScombination. Unless otherwise stated, application performance curves

were taken at TA= 25°C.

VIN = 24 V VOUT = 3.3 V RLOAD = Open

Figure 95. Start-up Into 1.0 V Pre-biased Voltage

VIN = 24 V VOUT = 12 V RLOAD = 24 Ω

Figure 96. Start-up With External Capacitor CSS = 33 nF

VOUT = 3.3 V FS= 500 kHz IOUT = 0.5A

Figure 97. Line Transient: VIN Transitions Between 12 V

and 48 V

VOUT = 3.3 V FS= 500 kHz IOUT = 0.25 A

Figure 98. Line Transient: VIN Transitions Between 12 V

and 48 V

VOUT = 3.3 V FS= 500 kHz VIN = 24 V

Figure 99. Short-Circuit Protection and Recover

VIN

PGND

CIN

VIN

COUT

VOUT

High di/dt

current

BUCK

CONVERTER

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9 Power Supply Recommendations

The LM46000 is designed to operate from an input voltage supply range between 3.5 V and 60 V. This input

supply must be able to withstand the maximum input current and maintain a voltage above 3.5 V. The resistance

of the input supply rail must be low enough that an input current transient does not cause a high enough drop at

the LM46000 supply voltage that can cause a false UVLO fault triggering and system reset.

If the input supply is located more than a few inches from the LM46000 additional bulk capacitance may be

required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, but a 47-µF

or 100-µF electrolytic capacitor is a typical choice.

10 Layout

The performance of any switching converter depends as much upon the layout of the PCB as the component

selection. The following guidelines will help users design a PCB the best power conversion performance, thermal

performance, and minimized generation of unwanted EMI.

10.1 Layout Guidelines

1. Place ceramic high frequency bypass CIN as close as possible to the LM46000 VIN and PGND pins.

Grounding for both the input and output capacitors must consist of localized top side planes that connect to

the PGND pins and PAD.

2. Place bypass capacitors for VCC and BIAS close to the pins and ground the bypass capacitors to device

ground.

3. Minimize trace length to the FB pin. Locate both feedback resistors, RFBT and RFBB close to the FB pin. Place

CFF directly in parallel with RFBT. If VOUT accuracy at the load is important, make sure VOUT sense is made at

the load. Route VOUT sense path away from noisy nodes and preferably through a layer on the other side of

a shielding layer.

4. Use ground plane in one of the middle layers as noise shielding and heat dissipation path.

5. Have a single point ground connection to the plane. Route he ground connections for the feedback, soft

start, and enable components to the ground plane. This prevents any switched or load currents from flowing

in the analog ground traces. If not properly handled, poor grounding can result in degraded load regulation or

erratic output voltage ripple behavior.

6. Make VIN, VOUT and ground bus connections as wide as possible. This reduces any voltage drops on the

input or output paths of the converter and maximizes efficiency.

7. Provide adequate device heat-sinking. Use an array of heat-sinking vias to connect the exposed pad to the

ground plane on the bottom PCB layer. If the PCB has multiple copper layers, these thermal vias can also be

connected to inner layer heat-spreading ground planes. Ensure enough copper area is used for heat-sinking

to keep the junction temperature below 125°C.

10.1.1 Compact Layout for EMI Reduction

Radiated EMI is generated by the high di/dt components in pulsing currents in switching converters. The larger

area covered by the path of a pulsing current, the more electromagnetic emission is generated. The key to

minimize radiated EMI is to identify the pulsing current path and minimize the area of the path. In Buck

converters, the pulsing current path is from the VIN side of the input capacitors to HS switch, to the LS switch,

and then return to the ground of the input capacitors, as shown in Figure 100.

Figure 100. Buck Converter High di / dt Path

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Layout Guidelines (continued)

High-frequency ceramic bypass capacitors at the input side provide primary path for the high di/dt components of

the pulsing current. Placing ceramic bypass capacitor(s) as close as possible to the VIN and PGND pins is the

key to EMI reduction.

The SW pin connecting to the inductor must be as short as possible and just wide enough to carry the load

current without excessive heating. Use short, thick traces or copper pours (shapes) for high current condution

path to minimize parasitic resistance. Place the output capacitors close to the VOUT end of the inductor and

closely grounded to PGND pin and exposed PAD.

Place he bypass capacitors on VCC and BIAS pins as close as possible to the pins respectively and closely

grounded to PGND and the exposed PAD.

10.1.2 Ground Plane and Thermal Considerations

TI recommends using one of the middle layers as a solid ground plane. Ground plane provides shielding for

sensitive circuits and traces. It also provides a quiet reference potential for the control circuitry. Connect the

AGND and PGND pins to the ground plane using vias right next to the bypass capacitors. PGND pins are

connected to the source of the internal LS switch. They must be connected directly to the grounds of the input

and output capacitors. The PGND net contains noise at the switching frequency and may bounce due to load

variations. The PGND trace, as well as PVIN and SW traces, must be constrained to one side of the ground

plane. The other side of the ground plane contains much less noise and should be used for sensitive routes.

TI recommends providing adequate device heat sinking by utilizing the PAD of the IC as the primary thermal

path. Use a minimum 4 by 4 array of 10 mil thermal vias to connect the PAD to the system ground plane for heat

sinking. Evenly distribute the vias under the PAD. Use as much copper as possible for system ground plane on

the top and bottom layers for the best heat dissipation. It is recommended to use a four-layer board with the

copper thickness, for the four layers, starting from the top one, 2 oz / 1 oz / 1 oz / 2 oz. Four-layer boards with

enough copper thickness and proper layout provides low current conduction impedance, proper shielding and

lower thermal resistance.

The thermal characteristics of the LM46000 are specified using the parameter RθJA, which characterize the

junction temperature of the silicon to the ambient temperature in a specific system. Although the value of RθJA is

dependant on many variables, it still can be used to approximate the operating junction temperature of the

device. To obtain an estimate of the device junction temperature, one may use the following relationship:

TJ= PD× RθJA + TA

where

• TJ= junction temperature in °C

• PD= VIN x IIN x (1 −efficiency) −1.1 x IOUT x DCR

• DCR = inductor DC parasitic resistance in Ω

• RθJA = junction-to-ambient thermal resistance of the device in °C/W

• TA= 1mbient temperature in °C. (27)

The maximum operating junction temperature of the LM46000 is 125°C. RθJA is highly related to PCB size and

layout, as well as enviromental factors such as heat sinking and air flow. Figure 101 shows measured results of

RθJA with different copper area on a 2-layer board and a 4-layer board.

20.0

25.0

30.0

35.0

40.0

45.0

50.0

20mm x 20mm 30mm x 30mm 40mm x 40mm 50mm x 50mm

R,JA (ƒC/W)

Copper Area

1W @ 0fpm - 2 layer

2W @ 0fpm - 2 layer

1W @ 0fpm - 4 layer

2W @ 0fpm - 4 layer

C030

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Layout Guidelines (continued)

Figure 101. Measured RθJA vs PCB Copper Area on a 2-layer Board and a 4-layer Board

10.1.3 Feedback Resistors

To reduce noise sensitivity of the output voltage feedback path, it is important to place the resistor divider and

CFF close to the FB pin, rather than close to the load. The FB pin is the input to the error amplifier, so it is a high

impedance node and very sensitive to noise. Placing the resistor divider and CFF closer to the FB pin reduces the

trace length of FB signal and reduces noise coupling. The output node is a low impedance node, so the trace

from VOUT to the resistor divider can be long if short path is not available.

If voltage accuracy at the load is important, make sure voltage sense is made at the load. Doing so corrects for

voltage drops along the traces and provide the best output accuracy. The voltage sense trace from the load to

the feedback resistor divider should be routed away from the SW node path, the inductor and VIN path to avoid

contaminating the feedback signal with switch noise, while also minimizing the trace length. This is most

important when high value resistors are used to set the output voltage. It is recommended to route the voltage

sense trace on a different layer than the inductor, SW node and VIN path, such that there is a ground plane in

between the feedback trace and inductor / SW node / VIN polygon. This provides further shielding for the voltage

feedback path from switching noises.

VIN

PGND

CBOOT

VCC

BIAS

SYNC

PGOOD

SS/TRK

AGND

SW PGND

VIN

PAD

(17)

116

VIN

COUT

CBOOT

CIN

CVCC

VOUT

CBIAS

RFBT

RFBB

CFF

GND

Route VOUT

sense trace

away from SW

and VIN

nodes.

Preferably

shielded in an

alternative

layer

GND Plane

VOUT sense point

is away from

inductor and

past COUT

Thermal Vias under DAP

As much copper area as possible, for better thermal performance

Place

bypass caps

close to

terminals

As much copper area as possible, for

better thermal performance

VOUT distribution

point is away

from inductor

and past COUT

TO LOAD

Ground

bypass caps

to DAP

Place ceramic

bypass caps close

to VIN and PGND

terminals

LM46000

SNVSA45B –JUNE 2014–REVISED MARCH 2018

www.ti.com

Product Folder Links: LM46000

10.2 Layout Example

Figure 102. LM46000 PCB Layout Example

LM46000

www.ti.com

SNVSA45B –JUNE 2014–REVISED MARCH 2018

Product Folder Links: LM46000

11 Device and Documentation Support

11.1 Device Support

11.1.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM46000 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.4 Trademarks

E2E is a trademark of Texas Instruments.

WEBENCH is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.6 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LM46000PWP ACTIVE HTSSOP PWP 16 90 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 LM46000

LM46000PWPR ACTIVE HTSSOP PWP 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 LM46000

LM46000PWPT ACTIVE HTSSOP PWP 16 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 LM46000

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF LM46000 :

•Automotive: LM46000-Q1

NOTE: Qualified Version Definitions:

•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LM46000PWPR HTSSOP PWP 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

LM46000PWPT HTSSOP PWP 16 250 180.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 11-Jul-2019

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LM46000PWPR HTSSOP PWP 16 2000 350.0 350.0 43.0

LM46000PWPT HTSSOP PWP 16 250 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 11-Jul-2019

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

TYP

6.6

6.2

1.2 MAX

14X 0.65

16X 0.30

0.19

4.55

TYP

0.18

0.12

0 - 8

0.15

0.05

2.41

1.77

3.29

2.71

2X 0.56 MAX

NOTE 6

(1)

0.25

GAGE PLANE

0.75

0.50

NOTE 3

5.1

4.9

NOTE 4

4.5

4.3

2X 0.24 MAX

NOTE 6

4218975/B 01/2016

PowerPAD TSSOP - 1.2 mm max heightPWP0016G

PLASTIC SMALL OUTLINE

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153.

6. Features may not present.

PowerPAD is a trademark of Texas Instruments.

116

0.1 C A B

PIN 1 ID

AREA

SEATING PLANE

0.1 C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 2.400

THERMAL

PAD

www.ti.com

EXAMPLE BOARD LAYOUT

(5.8)

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

16X (1.5)

16X (0.45)

14X (0.65)

(3.4)

NOTE 10

(5)

(2.41)

(3.29)

SOLDER MASK

OPENING

( ) TYP

VIA

0.2

(0.95) TYP

(0.95)

TYP

4218975/B 01/2016

PowerPAD TSSOP - 1.2 mm max heightPWP0016G

PLASTIC SMALL OUTLINE

SYMM

SEE DETAILS

LAND PATTERN EXAMPLE

SCALE:10X

SOLDER MASK

OPENING

METAL COVERED

BY SOLDER MASK

SOLDER MASK

DEFINED PAD

NOTES: (continued)

7. Publication IPC-7351 may have alternate designs.

8. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

9. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

10. Size of metal pad may vary due to creepage requirement.

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

PADS 1-16

SOLDER MASK

DEFINED

SOLDER MASK

METAL UNDER SOLDER MASK

OPENING

www.ti.com

EXAMPLE STENCIL DESIGN

16X (1.5)

16X (0.45)

(2.41)

(3.29)

BASED ON

0.127 THICK

STENCIL

(5.8)

14X (0.65)

(R )0.05

4218975/B 01/2016

PowerPAD TSSOP - 1.2 mm max heightPWP0016G

PLASTIC SMALL OUTLINE

2.04 X 2.780.178

2.20 X 3.000.152

2.41 X 3.29 (SHOWN)0.127

2.69 X 3.680.1

SOLDER STENCIL

OPENING

STENCIL

THICKNESS

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

12. Board assembly site may have different recommendations for stencil design.

SYMM

BASED ON

0.127 THICK

STENCIL

BY SOLDER MASK

METAL COVERED

SEE TABLE FOR

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

SOLDER PASTE EXAMPLE

EXPOSED PAD

100% PRINTED SOLDER COVERAGE BY AREA

SCALE:10X

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

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